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(MINI-LFR) WFP_MS 0.1.49...
pellion -
r513:cb7d6dc9cf10 (MINI-LFR) WFP_MS-0-1-49 (LFR-EM) WFP_MS-1-1-49 JC
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@@ -42,7 +42,7 USE lpp.lpp_lfr_pkg.ALL; -- contains lp
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
@@ -250,7 +250,7 BEGIN -- beh
250 250 -------------------------------------------------------------------------------
251 251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 252 -------------------------------------------------------------------------------
253 apb_lfr_time_management_1 : apb_lfr_time_management
253 apb_lfr_management_1 : apb_lfr_management
254 254 GENERIC MAP (
255 255 pindex => 6,
256 256 paddr => 6,
@@ -264,6 +264,11 BEGIN -- beh
264 264 grspw_tick => swno.tickout,
265 265 apbi => apbi_ext,
266 266 apbo => apbo_ext(6),
267
268 HK_sample => sample_s(8),
269 HK_val => sample_val,
270 HK_sel => HK_SEL,
271
267 272 coarse_time => coarse_time,
268 273 fine_time => fine_time,
269 274 LFR_soft_rstn => LFR_soft_rstn
@@ -374,7 +379,7 BEGIN -- beh
374 379 pirq_ms => 6,
375 380 pirq_wfp => 14,
376 381 hindex => 2,
377 top_lfr_version => X"01012F") -- aa.bb.cc version
382 top_lfr_version => X"010131") -- aa.bb.cc version
378 383 -- AA : BOARD NUMBER
379 384 -- 0 => MINI_LFR
380 385 -- 1 => EM
@@ -435,20 +440,4 BEGIN -- beh
435 440 -----------------------------------------------------------------------------
436 441 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
437 442
438 lpp_lfr_hk_1: lpp_lfr_hk
439 GENERIC MAP (
440 pindex => 7,
441 paddr => 7,
442 pmask => 16#fff#)
443 PORT MAP (
444 clk => clk_25,
445 rstn => rstn,
446
447 apbi => apbi_ext,
448 apbo => apbo_ext(7),
449
450 sample_val => sample_val,
451 sample => sample_s(8),
452 HK_SEL => HK_SEL);
453
454 443 END beh;
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@@ -42,7 +42,7 USE lpp.lpp_lfr_pkg.ALL; -- contains lp
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
@@ -385,9 +385,9 BEGIN -- beh
385 385
386 386 SRAM_CE <= SRAM_CE_s(0);
387 387 -------------------------------------------------------------------------------
388 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 389 -------------------------------------------------------------------------------
390 apb_lfr_time_management_1 : apb_lfr_time_management
390 apb_lfr_management_1 : apb_lfr_management
391 391 GENERIC MAP (
392 392 pindex => 6,
393 393 paddr => 6,
@@ -401,6 +401,9 BEGIN -- beh
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 HK_sample => sample_hk,
405 HK_val => sample_val,
406 HK_sel => HK_SEL,
404 407 coarse_time => coarse_time,
405 408 fine_time => fine_time,
406 409 LFR_soft_rstn => LFR_soft_rstn
@@ -515,7 +518,7 BEGIN -- beh
515 518 pirq_ms => 6,
516 519 pirq_wfp => 14,
517 520 hindex => 2,
518 top_lfr_version => X"00012E") -- aa.bb.cc version
521 top_lfr_version => X"000131") -- aa.bb.cc version
519 522 PORT MAP (
520 523 clk => clk_25,
521 524 rstn => LFR_rstn,
@@ -578,22 +581,6 BEGIN -- beh
578 581 ADC_CLK <= ADC_CLK_sig;
579 582 ADC_SDO_sig <= ADC_SDO;
580 583
581 lpp_lfr_hk_1: lpp_lfr_hk
582 GENERIC MAP (
583 pindex => 7,
584 paddr => 7,
585 pmask => 16#fff#)
586 PORT MAP (
587 clk => clk_25,
588 rstn => rstn_25,
589
590 apbi => apbi_ext,
591 apbo => apbo_ext(7),
592
593 sample_val => sample_val,
594 sample => sample_hk,
595 HK_SEL => HK_SEL);
596
597 584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
598 585 "0010001000100010" WHEN HK_SEL = "10" ELSE
599 586 "0100010001000100" WHEN HK_SEL = "10" ELSE
@@ -727,7 +714,7 BEGIN -- beh
727 714 --
728 715 -----------------------------------------------------------------------------
729 716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
730 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE
717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
731 718 apbo_ext(I) <= apb_none;
732 719 END GENERATE apbo_ext_not_used;
733 720 END GENERATE all_apbo_ext;
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@@ -11,7 +11,7
11 11 ./dsp/lpp_fft_rtax
12 12 ./lpp_memory
13 13 ./dsp/lpp_fft
14 ./lfr_time_management
14 ./lfr_management
15 15 ./lpp_ad_Conv
16 16 ./lpp_bootloader
17 17 ./lpp_cna
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@@ -27,11 +27,11 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
30 USE lpp.lpp_lfr_management.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 32
33 33
34 ENTITY apb_lfr_time_management IS
34 ENTITY apb_lfr_management IS
35 35
36 36 GENERIC(
37 37 pindex : INTEGER := 0; --! APB slave index
@@ -50,16 +50,20 ENTITY apb_lfr_time_management IS
50 50
51 51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 52 apbo : OUT apb_slv_out_type; --! APB slave output signals
53
53 ---------------------------------------------------------------------------
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 ---------------------------------------------------------------------------
54 58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
55 59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
56 60 ---------------------------------------------------------------------------
57 61 LFR_soft_rstn : OUT STD_LOGIC
58 62 );
59 63
60 END apb_lfr_time_management;
64 END apb_lfr_management;
61 65
62 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
66 ARCHITECTURE Behavioral OF apb_lfr_management IS
63 67
64 68 CONSTANT REVISION : INTEGER := 1;
65 69 CONSTANT pconfig : apb_config_type := (
@@ -74,6 +78,9 ARCHITECTURE Behavioral OF apb_lfr_time_
74 78 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 79 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
76 80 LFR_soft_reset : STD_LOGIC;
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
77 84 END RECORD;
78 85 SIGNAL r : apb_lfr_time_management_Reg;
79 86
@@ -108,6 +115,10 ARCHITECTURE Behavioral OF apb_lfr_time_
108 115 SIGNAL soft_reset : STD_LOGIC;
109 116 SIGNAL soft_reset_sync : STD_LOGIC;
110 117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0);
111 122
112 123 SIGNAL rstn_LFR_TM : STD_LOGIC;
113 124
@@ -153,11 +164,11 BEGIN
153 164 --APB Write OP
154 165 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
155 166 CASE apbi.paddr(7 DOWNTO 2) IS
156 WHEN ADDR_LFR_TM_CONTROL =>
167 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
157 168 r.ctrl <= apbi.pwdata(0);
158 169 r.soft_reset <= apbi.pwdata(1);
159 170 r.LFR_soft_reset <= apbi.pwdata(2);
160 WHEN ADDR_LFR_TM_TIME_LOAD =>
171 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
161 172 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
162 173 coarsetime_reg_updated <= '1';
163 174 WHEN OTHERS =>
@@ -175,18 +186,27 BEGIN
175 186 --APB READ OP
176 187 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
177 188 CASE apbi.paddr(7 DOWNTO 2) IS
178 WHEN ADDR_LFR_TM_CONTROL =>
189 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
179 190 Rdata(0) <= r.ctrl;
180 191 Rdata(1) <= r.soft_reset;
181 192 Rdata(2) <= r.LFR_soft_reset;
182 193 Rdata(31 DOWNTO 3) <= (others => '0');
183 WHEN ADDR_LFR_TM_TIME_LOAD =>
194 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
184 195 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
185 WHEN ADDR_LFR_TM_TIME_COARSE =>
196 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
186 197 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
187 WHEN ADDR_LFR_TM_TIME_FINE =>
198 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
188 199 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
189 200 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
201 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
202 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
203 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
204 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
205 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
206 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
207 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
208 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
209 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
190 210 WHEN OTHERS =>
191 211 Rdata(31 DOWNTO 0) <= (others => '0');
192 212 END CASE;
@@ -326,4 +346,35 BEGIN
326 346 coarse_time => coarse_time_49,
327 347 coarse_time_new => coarse_time_new_49);
328 348
329 END Behavioral;
349 -----------------------------------------------------------------------------
350 -- HK
351 -----------------------------------------------------------------------------
352
353 PROCESS (clk25MHz, resetn)
354 BEGIN -- PROCESS
355 IF resetn = '0' THEN -- asynchronous reset (active low)
356
357 r.HK_temp_0 <= (OTHERS => '0');
358 r.HK_temp_1 <= (OTHERS => '0');
359 r.HK_temp_2 <= (OTHERS => '0');
360
361 HK_sel_s <= "00";
362
363 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
364
365 IF HK_val = '1' THEN
366 CASE HK_sel_s IS
367 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
368 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
369 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
370 WHEN OTHERS => NULL;
371 END CASE;
372
373 END IF;
374
375 END IF;
376 END PROCESS;
377
378 HK_sel <= HK_sel_s;
379
380 END Behavioral; No newline at end of file
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1 NO CONTENT: file renamed from lib/lpp/lfr_time_management/coarse_time_counter.vhd to lib/lpp/lfr_management/coarse_time_counter.vhd
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1 NO CONTENT: file renamed from lib/lpp/lfr_time_management/fine_time_counter.vhd to lib/lpp/lfr_management/fine_time_counter.vhd
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@@ -21,7 +21,7 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 USE lpp.lpp_lfr_time_management.ALL;
24 USE lpp.lpp_lfr_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
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@@ -24,29 +24,31 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 PACKAGE lpp_lfr_time_management IS
27 PACKAGE lpp_lfr_management IS
28 28
29 29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_MANAGEMENT
31 31
32 COMPONENT apb_lfr_time_management IS
33 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 FIRST_DIVISION : INTEGER;
38 NB_SECOND_DESYNC : INTEGER);
32 COMPONENT apb_lfr_management
33 GENERIC (
34 pindex : INTEGER;
35 paddr : INTEGER;
36 pmask : INTEGER;
37 FIRST_DIVISION : INTEGER;
38 NB_SECOND_DESYNC : INTEGER);
39 39 PORT (
40 clk25MHz : IN STD_LOGIC; --! Clock
41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
42 resetn : IN STD_LOGIC; --! Reset
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 apbi : IN apb_slv_in_type; --! APB slave input signals
45 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
48 LFR_soft_rstn : OUT STD_LOGIC
49 );
40 clk25MHz : IN STD_LOGIC;
41 clk24_576MHz : IN STD_LOGIC;
42 resetn : IN STD_LOGIC;
43 grspw_tick : IN STD_LOGIC;
44 apbi : IN apb_slv_in_type;
45 apbo : OUT apb_slv_out_type;
46 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
47 HK_val : IN STD_LOGIC;
48 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
51 LFR_soft_rstn : OUT STD_LOGIC);
50 52 END COMPONENT;
51 53
52 54 COMPONENT lfr_time_management
@@ -99,5 +101,5 PACKAGE lpp_lfr_time_management IS
99 101 END COMPONENT;
100 102
101 103
102 END lpp_lfr_time_management;
104 END lpp_lfr_management;
103 105
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@@ -2,11 +2,14 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 PACKAGE lpp_lfr_time_management_apbreg_pkg IS
5 PACKAGE lpp_lfr_management_apbreg_pkg IS
6 6
7 CONSTANT ADDR_LFR_TM_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8 CONSTANT ADDR_LFR_TM_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9 CONSTANT ADDR_LFR_TM_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10 CONSTANT ADDR_LFR_TM_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
7 CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8 CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9 CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10 CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
11 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
12 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
13 CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
11 14
12 END lpp_lfr_time_management_apbreg_pkg;
15 END lpp_lfr_management_apbreg_pkg;
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@@ -1,6 +1,6
1 lpp_lfr_time_management.vhd
2 lpp_lfr_time_management_apbreg_pkg.vhd
3 apb_lfr_time_management.vhd
1 lpp_lfr_management.vhd
2 lpp_lfr_management_apbreg_pkg.vhd
3 apb_lfr_management.vhd
4 4 lfr_time_management.vhd
5 5 fine_time_counter.vhd
6 6 coarse_time_counter.vhd
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@@ -39,7 +39,6 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 42 USE lpp.lpp_leon3_soc_pkg.ALL;
44 43 LIBRARY iap;
45 44 USE iap.memctrl.all;
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This diff has been collapsed as it changes many lines, (975 lines changed) Show them Hide them
@@ -1,488 +1,487
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44
45 ENTITY leon3ft_soc IS
46 GENERIC (
47 fabtech : INTEGER := apa3e;
48 memtech : INTEGER := apa3e;
49 padtech : INTEGER := inferred;
50 clktech : INTEGER := inferred;
51 disas : INTEGER := 0; -- Enable disassembly to console
52 dbguart : INTEGER := 0; -- Print UART on console
53 pclow : INTEGER := 2;
54 --
55 clk_freq : INTEGER := 25000; --kHz
56 --
57 NB_CPU : INTEGER := 1;
58 ENABLE_FPU : INTEGER := 1;
59 FPU_NETLIST : INTEGER := 1;
60 ENABLE_DSU : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
65 --
66 NB_AHB_MASTER : INTEGER := 11;
67 NB_AHB_SLAVE : INTEGER := 1;
68 NB_APB_SLAVE : INTEGER := 2
69 );
70 PORT (
71 clk : IN STD_ULOGIC;
72 reset : IN STD_ULOGIC;
73
74 errorn : OUT STD_ULOGIC;
75
76 -- UART AHB ---------------------------------------------------------------
77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79
80 -- UART APB ---------------------------------------------------------------
81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83
84 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 nSRAM_BE0 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
89 nSRAM_BE2 : OUT STD_LOGIC;
90 nSRAM_BE3 : OUT STD_LOGIC;
91 nSRAM_WE : OUT STD_LOGIC;
92 nSRAM_CE : OUT STD_LOGIC;
93 nSRAM_OE : OUT STD_LOGIC;
94
95 -- APB --------------------------------------------------------------------
96 apbi_ext : OUT apb_slv_in_type;
97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 -- AHB_Slave --------------------------------------------------------------
99 ahbi_s_ext : OUT ahb_slv_in_type;
100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 -- AHB_Master -------------------------------------------------------------
102 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104
105 );
106 END;
107
108 ARCHITECTURE Behavioral OF leon3ft_soc IS
109
110 -----------------------------------------------------------------------------
111 -- CONFIG -------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
114 -- Clock generator
115 CONSTANT CFG_CLKMUL : INTEGER := (1);
116 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
117 CONSTANT CFG_OCLKDIV : INTEGER := (1);
118 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
119 -- LEON3 processor core
120 CONSTANT CFG_LEON3 : INTEGER := 1;
121 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
122 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
123 CONSTANT CFG_V8 : INTEGER := 0;
124 CONSTANT CFG_MAC : INTEGER := 0;
125 CONSTANT CFG_SVT : INTEGER := 0;
126 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
127 CONSTANT CFG_LDDEL : INTEGER := (1);
128 CONSTANT CFG_NWP : INTEGER := (0);
129 CONSTANT CFG_PWD : INTEGER := 1*2;
130 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 -- 1*(8 + 16 * 0) => grfpu-light
132 -- 1*(8 + 16 * 1) => netlist
133 -- 0*(8 + 16 * 0) => No FPU
134 -- 0*(8 + 16 * 1) => No FPU;
135 CONSTANT CFG_ICEN : INTEGER := 1;
136 CONSTANT CFG_ISETS : INTEGER := 1;
137 CONSTANT CFG_ISETSZ : INTEGER := 4;
138 CONSTANT CFG_ILINE : INTEGER := 4;
139 CONSTANT CFG_IREPL : INTEGER := 0;
140 CONSTANT CFG_ILOCK : INTEGER := 0;
141 CONSTANT CFG_ILRAMEN : INTEGER := 0;
142 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
143 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
144 CONSTANT CFG_DCEN : INTEGER := 1;
145 CONSTANT CFG_DSETS : INTEGER := 1;
146 CONSTANT CFG_DSETSZ : INTEGER := 4;
147 CONSTANT CFG_DLINE : INTEGER := 4;
148 CONSTANT CFG_DREPL : INTEGER := 0;
149 CONSTANT CFG_DLOCK : INTEGER := 0;
150 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
151 CONSTANT CFG_DLRAMEN : INTEGER := 0;
152 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
153 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
154 CONSTANT CFG_MMUEN : INTEGER := 0;
155 CONSTANT CFG_ITLBNUM : INTEGER := 2;
156 CONSTANT CFG_DTLBNUM : INTEGER := 2;
157 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
158 CONSTANT CFG_TLB_REP : INTEGER := 1;
159
160 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
161 CONSTANT CFG_ITBSZ : INTEGER := 0;
162 CONSTANT CFG_ATBSZ : INTEGER := 0;
163
164 -- AMBA settings
165 CONSTANT CFG_DEFMST : INTEGER := (0);
166 CONSTANT CFG_RROBIN : INTEGER := 1;
167 CONSTANT CFG_SPLIT : INTEGER := 0;
168 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
169 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
170
171 -- DSU UART
172 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
173
174 -- LEON2 memory controller
175 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
176
177 -- UART 1
178 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
179 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
180
181 -- LEON3 interrupt controller
182 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
183
184 -- Modular timer
185 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
186 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
187 CONSTANT CFG_GPT_SW : INTEGER := (8);
188 CONSTANT CFG_GPT_TW : INTEGER := (32);
189 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
190 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
191 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
192 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
193 -----------------------------------------------------------------------------
194
195 -----------------------------------------------------------------------------
196 -- SIGNALs
197 -----------------------------------------------------------------------------
198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 -- CLK & RST --
200 SIGNAL clk2x : STD_ULOGIC;
201 SIGNAL clkmn : STD_ULOGIC;
202 SIGNAL clkm : STD_ULOGIC;
203 SIGNAL rstn : STD_ULOGIC;
204 SIGNAL rstraw : STD_ULOGIC;
205 SIGNAL pciclk : STD_ULOGIC;
206 SIGNAL sdclkl : STD_ULOGIC;
207 SIGNAL cgi : clkgen_in_type;
208 SIGNAL cgo : clkgen_out_type;
209 --- AHB / APB
210 SIGNAL apbi : apb_slv_in_type;
211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 SIGNAL ahbsi : ahb_slv_in_type;
213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 SIGNAL ahbmi : ahb_mst_in_type;
215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 --UART
217 SIGNAL ahbuarti : uart_in_type;
218 SIGNAL ahbuarto : uart_out_type;
219 SIGNAL apbuarti : uart_in_type;
220 SIGNAL apbuarto : uart_out_type;
221 --MEM CTRLR
222 SIGNAL memi : memory_in_type;
223 SIGNAL memo : memory_out_type;
224 SIGNAL wpo : wprot_out_type;
225 SIGNAL sdo : sdram_out_type;
226 --IRQ
227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 --Timer
230 SIGNAL gpti : gptimer_in_type;
231 SIGNAL gpto : gptimer_out_type;
232 --DSU
233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 SIGNAL dsui : dsu_in_type;
236 SIGNAL dsuo : dsu_out_type;
237 -----------------------------------------------------------------------------
238
239 SIGNAL nSRAM_CE_s : STD_LOGIC;
240 BEGIN
241
242
243 ----------------------------------------------------------------------
244 --- Reset and Clock generation -------------------------------------
245 ----------------------------------------------------------------------
246
247 cgi.pllctrl <= "00";
248 cgi.pllrst <= rstraw;
249
250 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
251
252 clkgen0 : clkgen -- clock generator
253 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
254 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
255 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
256
257 ----------------------------------------------------------------------
258 --- LEON3 processor / DSU / IRQ ------------------------------------
259 ----------------------------------------------------------------------
260
261 l3 : IF CFG_LEON3 = 1 GENERATE
262 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
263 u0 : leon3ft
264 GENERIC MAP (
265 hindex => i, --: integer;
266 fabtech => fabtech,
267 memtech => memtech,
268 nwindows => CFG_NWIN,
269 dsu => CFG_DSU,
270 fpu => CFG_FPU,
271 v8 => CFG_V8,
272 cp => 0,
273 mac => CFG_MAC,
274 pclow => pclow,
275 notag => 0,
276 nwp => CFG_NWP,
277 icen => CFG_ICEN,
278 irepl => CFG_IREPL,
279 isets => CFG_ISETS,
280 ilinesize => CFG_ILINE,
281 isetsize => CFG_ISETSZ,
282 isetlock => CFG_ILOCK,
283 dcen => CFG_DCEN,
284 drepl => CFG_DREPL,
285 dsets => CFG_DSETS,
286 dlinesize => CFG_DLINE,
287 dsetsize => CFG_DSETSZ,
288 dsetlock => CFG_DLOCK,
289 dsnoop => CFG_DSNOOP,
290 ilram => CFG_ILRAMEN,
291 ilramsize => CFG_ILRAMSZ,
292 ilramstart => CFG_ILRAMADDR,
293 dlram => CFG_DLRAMEN,
294 dlramsize => CFG_DLRAMSZ,
295 dlramstart => CFG_DLRAMADDR,
296 mmuen => CFG_MMUEN,
297 itlbnum => CFG_ITLBNUM,
298 dtlbnum => CFG_DTLBNUM,
299 tlb_type => CFG_TLB_TYPE,
300 tlb_rep => CFG_TLB_REP,
301 lddel => CFG_LDDEL,
302 disas => disas,
303 tbuf => CFG_ITBSZ,
304 pwd => CFG_PWD,
305 svt => CFG_SVT,
306 rstaddr => CFG_RSTADDR,
307 smp => CFG_NCPU-1,
308 iuft => 2, --: integer range 0 to 4;
309 fpft => 1, --: integer range 0 to 4;
310 cmft => 1, --: integer range 0 to 1;
311 iuinj => 0, --: integer;
312 ceinj => 0, --: integer range 0 to 3;
313 cached => 0, --: integer;
314 netlist => 0, --: integer;
315 scantest => 0, --: integer;
316 mmupgsz => 0, --: integer range 0 to 5;
317 bp => 1) --: integer);
318 PORT MAP (
319 clk => clkm,
320 rstn => rstn,
321 ahbi => ahbmi,
322 ahbo => ahbmo(i),
323 ahbsi => ahbsi,
324 ahbso => ahbso,
325 irqi => irqi(i),
326 irqo => irqo(i),
327 dbgi => dbgi(i),
328 dbgo => dbgo(i),
329 gclk => clkm
330 );
331
332 END GENERATE;
333
334
335 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
336
337 dsugen : IF CFG_DSU = 1 GENERATE
338 dsu0 : dsu3 -- LEON3 Debug Support Unit
339 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
340 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
341 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
342 dsui.enable <= '1';
343 dsui.break <= '0';
344 END GENERATE;
345 END GENERATE;
346
347 nodsu : IF CFG_DSU = 0 GENERATE
348 ahbso(2) <= ahbs_none;
349 dsuo.tstop <= '0';
350 dsuo.active <= '0';
351 END GENERATE;
352
353 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
354 irqctrl0 : irqmp -- interrupt controller
355 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
356 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
357 END GENERATE;
358 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
359 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
360 irqi(i).irl <= "0000";
361 END GENERATE;
362 apbo(2) <= apb_none;
363 END GENERATE;
364
365 ----------------------------------------------------------------------
366 --- Memory controllers ---------------------------------------------
367 ----------------------------------------------------------------------
368 memctrlr : mctrl GENERIC MAP (
369 hindex => 0,
370 pindex => 0,
371 paddr => 0,
372 srbanks => 1
373 )
374 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
375
376 memi.brdyn <= '1';
377 memi.bexcn <= '1';
378 memi.writen <= '1';
379 memi.wrn <= "1111";
380 memi.bwidth <= "10";
381
382 bdr : FOR i IN 0 TO 3 GENERATE
383 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
384 PORT MAP (
385 data(31-i*8 DOWNTO 24-i*8),
386 memo.data(31-i*8 DOWNTO 24-i*8),
387 memo.bdrive(i),
388 memi.data(31-i*8 DOWNTO 24-i*8));
389 END GENERATE;
390
391 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
392 PORT MAP (address, memo.address(21 DOWNTO 2));
393 nSRAM_CE_s <= NOT(memo.ramsn(0));
394 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
395 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
396 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
397 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
398 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
399 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
400 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
401
402 ----------------------------------------------------------------------
403 --- AHB CONTROLLER -------------------------------------------------
404 ----------------------------------------------------------------------
405 ahb0 : ahbctrl -- AHB arbiter/multiplexer
406 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
407 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
408 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
409 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
410
411 ----------------------------------------------------------------------
412 --- AHB UART -------------------------------------------------------
413 ----------------------------------------------------------------------
414 dcomgen : IF CFG_AHB_UART = 1 GENERATE
415 dcom0 : ahbuart
416 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
417 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
418 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
419 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
420 END GENERATE;
421 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
422
423 ----------------------------------------------------------------------
424 --- APB Bridge -----------------------------------------------------
425 ----------------------------------------------------------------------
426 apb0 : apbctrl -- AHB/APB bridge
427 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
428 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
429
430 ----------------------------------------------------------------------
431 --- GPT Timer ------------------------------------------------------
432 ----------------------------------------------------------------------
433 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
434 timer0 : gptimer -- timer unit
435 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
436 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
437 nbits => CFG_GPT_TW)
438 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
439 gpti.dhalt <= dsuo.tstop;
440 gpti.extclk <= '0';
441 END GENERATE;
442 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
443
444
445 ----------------------------------------------------------------------
446 --- APB UART -------------------------------------------------------
447 ----------------------------------------------------------------------
448 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
449 uart1 : apbuart -- UART 1
450 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
451 fifosize => CFG_UART1_FIFO)
452 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
453 apbuarti.rxd <= urxd1;
454 apbuarti.extclk <= '0';
455 utxd1 <= apbuarto.txd;
456 apbuarti.ctsn <= '0';
457 END GENERATE;
458 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
459
460 -------------------------------------------------------------------------------
461 -- AMBA BUS -------------------------------------------------------------------
462 -------------------------------------------------------------------------------
463
464 -- APB --------------------------------------------------------------------
465 apbi_ext <= apbi;
466 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
467 max_16_apb : IF I + 5 < 16 GENERATE
468 apbo(I+5) <= apbo_ext(I+5);
469 END GENERATE max_16_apb;
470 END GENERATE all_apb;
471 -- AHB_Slave --------------------------------------------------------------
472 ahbi_s_ext <= ahbsi;
473 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
474 max_16_ahbs : IF I + 3 < 16 GENERATE
475 ahbso(I+3) <= ahbo_s_ext(I+3);
476 END GENERATE max_16_ahbs;
477 END GENERATE all_ahbs;
478 -- AHB_Master -------------------------------------------------------------
479 ahbi_m_ext <= ahbmi;
480 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
481 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
482 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
483 END GENERATE max_16_ahbm;
484 END GENERATE all_ahbm;
485
486
487
488 END Behavioral;
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43
44 ENTITY leon3ft_soc IS
45 GENERIC (
46 fabtech : INTEGER := apa3e;
47 memtech : INTEGER := apa3e;
48 padtech : INTEGER := inferred;
49 clktech : INTEGER := inferred;
50 disas : INTEGER := 0; -- Enable disassembly to console
51 dbguart : INTEGER := 0; -- Print UART on console
52 pclow : INTEGER := 2;
53 --
54 clk_freq : INTEGER := 25000; --kHz
55 --
56 NB_CPU : INTEGER := 1;
57 ENABLE_FPU : INTEGER := 1;
58 FPU_NETLIST : INTEGER := 1;
59 ENABLE_DSU : INTEGER := 1;
60 ENABLE_AHB_UART : INTEGER := 1;
61 ENABLE_APB_UART : INTEGER := 1;
62 ENABLE_IRQMP : INTEGER := 1;
63 ENABLE_GPT : INTEGER := 1;
64 --
65 NB_AHB_MASTER : INTEGER := 11;
66 NB_AHB_SLAVE : INTEGER := 1;
67 NB_APB_SLAVE : INTEGER := 2
68 );
69 PORT (
70 clk : IN STD_ULOGIC;
71 reset : IN STD_ULOGIC;
72
73 errorn : OUT STD_ULOGIC;
74
75 -- UART AHB ---------------------------------------------------------------
76 ahbrxd : IN STD_ULOGIC; -- DSU rx data
77 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
78
79 -- UART APB ---------------------------------------------------------------
80 urxd1 : IN STD_ULOGIC; -- UART1 rx data
81 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
82
83 -- RAM --------------------------------------------------------------------
84 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
85 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 nSRAM_BE0 : OUT STD_LOGIC;
87 nSRAM_BE1 : OUT STD_LOGIC;
88 nSRAM_BE2 : OUT STD_LOGIC;
89 nSRAM_BE3 : OUT STD_LOGIC;
90 nSRAM_WE : OUT STD_LOGIC;
91 nSRAM_CE : OUT STD_LOGIC;
92 nSRAM_OE : OUT STD_LOGIC;
93
94 -- APB --------------------------------------------------------------------
95 apbi_ext : OUT apb_slv_in_type;
96 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
97 -- AHB_Slave --------------------------------------------------------------
98 ahbi_s_ext : OUT ahb_slv_in_type;
99 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
100 -- AHB_Master -------------------------------------------------------------
101 ahbi_m_ext : OUT AHB_Mst_In_Type;
102 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
103
104 );
105 END;
106
107 ARCHITECTURE Behavioral OF leon3ft_soc IS
108
109 -----------------------------------------------------------------------------
110 -- CONFIG -------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112
113 -- Clock generator
114 CONSTANT CFG_CLKMUL : INTEGER := (1);
115 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
116 CONSTANT CFG_OCLKDIV : INTEGER := (1);
117 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
118 -- LEON3 processor core
119 CONSTANT CFG_LEON3 : INTEGER := 1;
120 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
121 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
122 CONSTANT CFG_V8 : INTEGER := 0;
123 CONSTANT CFG_MAC : INTEGER := 0;
124 CONSTANT CFG_SVT : INTEGER := 0;
125 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
126 CONSTANT CFG_LDDEL : INTEGER := (1);
127 CONSTANT CFG_NWP : INTEGER := (0);
128 CONSTANT CFG_PWD : INTEGER := 1*2;
129 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
130 -- 1*(8 + 16 * 0) => grfpu-light
131 -- 1*(8 + 16 * 1) => netlist
132 -- 0*(8 + 16 * 0) => No FPU
133 -- 0*(8 + 16 * 1) => No FPU;
134 CONSTANT CFG_ICEN : INTEGER := 1;
135 CONSTANT CFG_ISETS : INTEGER := 1;
136 CONSTANT CFG_ISETSZ : INTEGER := 4;
137 CONSTANT CFG_ILINE : INTEGER := 4;
138 CONSTANT CFG_IREPL : INTEGER := 0;
139 CONSTANT CFG_ILOCK : INTEGER := 0;
140 CONSTANT CFG_ILRAMEN : INTEGER := 0;
141 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
142 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
143 CONSTANT CFG_DCEN : INTEGER := 1;
144 CONSTANT CFG_DSETS : INTEGER := 1;
145 CONSTANT CFG_DSETSZ : INTEGER := 4;
146 CONSTANT CFG_DLINE : INTEGER := 4;
147 CONSTANT CFG_DREPL : INTEGER := 0;
148 CONSTANT CFG_DLOCK : INTEGER := 0;
149 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
150 CONSTANT CFG_DLRAMEN : INTEGER := 0;
151 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
152 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
153 CONSTANT CFG_MMUEN : INTEGER := 0;
154 CONSTANT CFG_ITLBNUM : INTEGER := 2;
155 CONSTANT CFG_DTLBNUM : INTEGER := 2;
156 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
157 CONSTANT CFG_TLB_REP : INTEGER := 1;
158
159 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
160 CONSTANT CFG_ITBSZ : INTEGER := 0;
161 CONSTANT CFG_ATBSZ : INTEGER := 0;
162
163 -- AMBA settings
164 CONSTANT CFG_DEFMST : INTEGER := (0);
165 CONSTANT CFG_RROBIN : INTEGER := 1;
166 CONSTANT CFG_SPLIT : INTEGER := 0;
167 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
168 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
169
170 -- DSU UART
171 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
172
173 -- LEON2 memory controller
174 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
175
176 -- UART 1
177 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
178 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
179
180 -- LEON3 interrupt controller
181 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
182
183 -- Modular timer
184 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
185 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
186 CONSTANT CFG_GPT_SW : INTEGER := (8);
187 CONSTANT CFG_GPT_TW : INTEGER := (32);
188 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
189 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
190 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
191 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
192 -----------------------------------------------------------------------------
193
194 -----------------------------------------------------------------------------
195 -- SIGNALs
196 -----------------------------------------------------------------------------
197 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
198 -- CLK & RST --
199 SIGNAL clk2x : STD_ULOGIC;
200 SIGNAL clkmn : STD_ULOGIC;
201 SIGNAL clkm : STD_ULOGIC;
202 SIGNAL rstn : STD_ULOGIC;
203 SIGNAL rstraw : STD_ULOGIC;
204 SIGNAL pciclk : STD_ULOGIC;
205 SIGNAL sdclkl : STD_ULOGIC;
206 SIGNAL cgi : clkgen_in_type;
207 SIGNAL cgo : clkgen_out_type;
208 --- AHB / APB
209 SIGNAL apbi : apb_slv_in_type;
210 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
211 SIGNAL ahbsi : ahb_slv_in_type;
212 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
213 SIGNAL ahbmi : ahb_mst_in_type;
214 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
215 --UART
216 SIGNAL ahbuarti : uart_in_type;
217 SIGNAL ahbuarto : uart_out_type;
218 SIGNAL apbuarti : uart_in_type;
219 SIGNAL apbuarto : uart_out_type;
220 --MEM CTRLR
221 SIGNAL memi : memory_in_type;
222 SIGNAL memo : memory_out_type;
223 SIGNAL wpo : wprot_out_type;
224 SIGNAL sdo : sdram_out_type;
225 --IRQ
226 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
227 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
228 --Timer
229 SIGNAL gpti : gptimer_in_type;
230 SIGNAL gpto : gptimer_out_type;
231 --DSU
232 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
233 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
234 SIGNAL dsui : dsu_in_type;
235 SIGNAL dsuo : dsu_out_type;
236 -----------------------------------------------------------------------------
237
238 SIGNAL nSRAM_CE_s : STD_LOGIC;
239 BEGIN
240
241
242 ----------------------------------------------------------------------
243 --- Reset and Clock generation -------------------------------------
244 ----------------------------------------------------------------------
245
246 cgi.pllctrl <= "00";
247 cgi.pllrst <= rstraw;
248
249 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
250
251 clkgen0 : clkgen -- clock generator
252 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
253 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
254 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
255
256 ----------------------------------------------------------------------
257 --- LEON3 processor / DSU / IRQ ------------------------------------
258 ----------------------------------------------------------------------
259
260 l3 : IF CFG_LEON3 = 1 GENERATE
261 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
262 u0 : leon3ft
263 GENERIC MAP (
264 hindex => i, --: integer;
265 fabtech => fabtech,
266 memtech => memtech,
267 nwindows => CFG_NWIN,
268 dsu => CFG_DSU,
269 fpu => CFG_FPU,
270 v8 => CFG_V8,
271 cp => 0,
272 mac => CFG_MAC,
273 pclow => pclow,
274 notag => 0,
275 nwp => CFG_NWP,
276 icen => CFG_ICEN,
277 irepl => CFG_IREPL,
278 isets => CFG_ISETS,
279 ilinesize => CFG_ILINE,
280 isetsize => CFG_ISETSZ,
281 isetlock => CFG_ILOCK,
282 dcen => CFG_DCEN,
283 drepl => CFG_DREPL,
284 dsets => CFG_DSETS,
285 dlinesize => CFG_DLINE,
286 dsetsize => CFG_DSETSZ,
287 dsetlock => CFG_DLOCK,
288 dsnoop => CFG_DSNOOP,
289 ilram => CFG_ILRAMEN,
290 ilramsize => CFG_ILRAMSZ,
291 ilramstart => CFG_ILRAMADDR,
292 dlram => CFG_DLRAMEN,
293 dlramsize => CFG_DLRAMSZ,
294 dlramstart => CFG_DLRAMADDR,
295 mmuen => CFG_MMUEN,
296 itlbnum => CFG_ITLBNUM,
297 dtlbnum => CFG_DTLBNUM,
298 tlb_type => CFG_TLB_TYPE,
299 tlb_rep => CFG_TLB_REP,
300 lddel => CFG_LDDEL,
301 disas => disas,
302 tbuf => CFG_ITBSZ,
303 pwd => CFG_PWD,
304 svt => CFG_SVT,
305 rstaddr => CFG_RSTADDR,
306 smp => CFG_NCPU-1,
307 iuft => 2, --: integer range 0 to 4;
308 fpft => 1, --: integer range 0 to 4;
309 cmft => 1, --: integer range 0 to 1;
310 iuinj => 0, --: integer;
311 ceinj => 0, --: integer range 0 to 3;
312 cached => 0, --: integer;
313 netlist => 0, --: integer;
314 scantest => 0, --: integer;
315 mmupgsz => 0, --: integer range 0 to 5;
316 bp => 1) --: integer);
317 PORT MAP (
318 clk => clkm,
319 rstn => rstn,
320 ahbi => ahbmi,
321 ahbo => ahbmo(i),
322 ahbsi => ahbsi,
323 ahbso => ahbso,
324 irqi => irqi(i),
325 irqo => irqo(i),
326 dbgi => dbgi(i),
327 dbgo => dbgo(i),
328 gclk => clkm
329 );
330
331 END GENERATE;
332
333
334 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
335
336 dsugen : IF CFG_DSU = 1 GENERATE
337 dsu0 : dsu3 -- LEON3 Debug Support Unit
338 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
339 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
340 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
341 dsui.enable <= '1';
342 dsui.break <= '0';
343 END GENERATE;
344 END GENERATE;
345
346 nodsu : IF CFG_DSU = 0 GENERATE
347 ahbso(2) <= ahbs_none;
348 dsuo.tstop <= '0';
349 dsuo.active <= '0';
350 END GENERATE;
351
352 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
353 irqctrl0 : irqmp -- interrupt controller
354 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
355 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
356 END GENERATE;
357 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
358 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
359 irqi(i).irl <= "0000";
360 END GENERATE;
361 apbo(2) <= apb_none;
362 END GENERATE;
363
364 ----------------------------------------------------------------------
365 --- Memory controllers ---------------------------------------------
366 ----------------------------------------------------------------------
367 memctrlr : mctrl GENERIC MAP (
368 hindex => 0,
369 pindex => 0,
370 paddr => 0,
371 srbanks => 1
372 )
373 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
374
375 memi.brdyn <= '1';
376 memi.bexcn <= '1';
377 memi.writen <= '1';
378 memi.wrn <= "1111";
379 memi.bwidth <= "10";
380
381 bdr : FOR i IN 0 TO 3 GENERATE
382 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
383 PORT MAP (
384 data(31-i*8 DOWNTO 24-i*8),
385 memo.data(31-i*8 DOWNTO 24-i*8),
386 memo.bdrive(i),
387 memi.data(31-i*8 DOWNTO 24-i*8));
388 END GENERATE;
389
390 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
391 PORT MAP (address, memo.address(21 DOWNTO 2));
392 nSRAM_CE_s <= NOT(memo.ramsn(0));
393 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
394 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
395 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
396 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
397 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
398 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
399 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
400
401 ----------------------------------------------------------------------
402 --- AHB CONTROLLER -------------------------------------------------
403 ----------------------------------------------------------------------
404 ahb0 : ahbctrl -- AHB arbiter/multiplexer
405 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
406 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
407 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
408 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
409
410 ----------------------------------------------------------------------
411 --- AHB UART -------------------------------------------------------
412 ----------------------------------------------------------------------
413 dcomgen : IF CFG_AHB_UART = 1 GENERATE
414 dcom0 : ahbuart
415 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
416 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
417 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
418 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
419 END GENERATE;
420 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
421
422 ----------------------------------------------------------------------
423 --- APB Bridge -----------------------------------------------------
424 ----------------------------------------------------------------------
425 apb0 : apbctrl -- AHB/APB bridge
426 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
427 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
428
429 ----------------------------------------------------------------------
430 --- GPT Timer ------------------------------------------------------
431 ----------------------------------------------------------------------
432 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
433 timer0 : gptimer -- timer unit
434 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
435 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
436 nbits => CFG_GPT_TW)
437 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
438 gpti.dhalt <= dsuo.tstop;
439 gpti.extclk <= '0';
440 END GENERATE;
441 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
442
443
444 ----------------------------------------------------------------------
445 --- APB UART -------------------------------------------------------
446 ----------------------------------------------------------------------
447 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
448 uart1 : apbuart -- UART 1
449 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
450 fifosize => CFG_UART1_FIFO)
451 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
452 apbuarti.rxd <= urxd1;
453 apbuarti.extclk <= '0';
454 utxd1 <= apbuarto.txd;
455 apbuarti.ctsn <= '0';
456 END GENERATE;
457 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
458
459 -------------------------------------------------------------------------------
460 -- AMBA BUS -------------------------------------------------------------------
461 -------------------------------------------------------------------------------
462
463 -- APB --------------------------------------------------------------------
464 apbi_ext <= apbi;
465 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
466 max_16_apb : IF I + 5 < 16 GENERATE
467 apbo(I+5) <= apbo_ext(I+5);
468 END GENERATE max_16_apb;
469 END GENERATE all_apb;
470 -- AHB_Slave --------------------------------------------------------------
471 ahbi_s_ext <= ahbsi;
472 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
473 max_16_ahbs : IF I + 3 < 16 GENERATE
474 ahbso(I+3) <= ahbo_s_ext(I+3);
475 END GENERATE max_16_ahbs;
476 END GENERATE all_ahbs;
477 -- AHB_Master -------------------------------------------------------------
478 ahbi_m_ext <= ahbmi;
479 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
480 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
481 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
482 END GENERATE max_16_ahbm;
483 END GENERATE all_ahbm;
484
485
486
487 END Behavioral; No newline at end of file
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