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1 | 1 | ----------------------------------------------------------------------------- |
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2 | 2 | -- LEON3 Demonstration design |
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3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 2 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | 19 | |
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20 | 20 | |
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21 | 21 | library ieee; |
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22 | 22 | use ieee.std_logic_1164.all; |
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23 | 23 | library grlib; |
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24 | 24 | use grlib.amba.all; |
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25 | 25 | use grlib.stdlib.all; |
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26 | 26 | library techmap; |
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27 | 27 | use techmap.gencomp.all; |
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28 | 28 | library gaisler; |
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29 | 29 | use gaisler.memctrl.all; |
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30 | 30 | use gaisler.leon3.all; |
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31 | 31 | use gaisler.uart.all; |
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32 | 32 | use gaisler.misc.all; |
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33 | 33 | library esa; |
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34 | 34 | use esa.memoryctrl.all; |
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35 | 35 | use work.config.all; |
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36 | 36 | library lpp; |
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37 | 37 | use lpp.lpp_amba.all; |
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38 | 38 | use lpp.lpp_memory.all; |
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39 | 39 | --use lpp.lpp_uart.all; |
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40 | 40 | --use lpp.lpp_matrix.all; |
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41 | 41 | --use lpp.lpp_usb.all; |
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42 | 42 | |
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43 | 43 | entity leon3mp is |
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44 | 44 | generic ( |
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45 | 45 | fabtech : integer := CFG_FABTECH; |
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46 | 46 | memtech : integer := CFG_MEMTECH; |
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47 | 47 | padtech : integer := CFG_PADTECH; |
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48 | 48 | clktech : integer := CFG_CLKTECH; |
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49 | 49 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
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50 | 50 | dbguart : integer := CFG_DUART; -- Print UART on console |
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51 | 51 | pclow : integer := CFG_PCLOW |
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52 | 52 | ); |
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53 | 53 | port ( |
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54 | 54 | clk50MHz : in std_ulogic; |
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55 | 55 | reset : in std_ulogic; |
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56 | 56 | ramclk : out std_logic; |
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57 | 57 | |
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58 | 58 | ahbrxd : in std_ulogic; -- DSU rx data |
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59 | 59 | ahbtxd : out std_ulogic; -- DSU tx data |
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60 | 60 | dsubre : in std_ulogic; |
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61 | 61 | dsuact : out std_ulogic; |
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62 | 62 | urxd1 : in std_ulogic; -- UART1 rx data |
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63 | 63 | utxd1 : out std_ulogic; -- UART1 tx data |
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64 | 64 | errorn : out std_ulogic; |
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65 | 65 | |
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66 | 66 | address : out std_logic_vector(18 downto 0); |
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67 | 67 | data : inout std_logic_vector(31 downto 0); |
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68 | 68 | |
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69 | 69 | nBWa : out std_logic; |
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70 | 70 | nBWb : out std_logic; |
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71 | 71 | nBWc : out std_logic; |
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72 | 72 | nBWd : out std_logic; |
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73 | 73 | nBWE : out std_logic; |
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74 | 74 | nADSC : out std_logic; |
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75 | 75 | nADSP : out std_logic; |
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76 | 76 | nADV : out std_logic; |
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77 | 77 | nGW : out std_logic; |
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78 | 78 | nCE1 : out std_logic; |
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79 | 79 | CE2 : out std_logic; |
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80 | 80 | nCE3 : out std_logic; |
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81 | 81 | nOE : out std_logic; |
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82 | 82 | MODE : out std_logic; |
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83 | 83 | SSRAM_CLK : out std_logic; |
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84 | 84 | ZZ : out std_logic; |
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85 | 85 | led : out std_logic_vector(1 downto 0) |
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86 | 86 | ); |
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87 | 87 | end; |
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88 | 88 | |
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89 | 89 | architecture Behavioral of leon3mp is |
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90 | 90 | |
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91 | 91 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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92 | 92 | CFG_GRETH+CFG_AHB_JTAG; |
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93 | 93 | constant maxahbm : integer := maxahbmsp; |
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94 | 94 | |
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95 | 95 | --Clk & Rst gοΏ½nοΏ½ |
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96 | 96 | signal vcc : std_logic_vector(4 downto 0); |
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97 | 97 | signal gnd : std_logic_vector(4 downto 0); |
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98 | 98 | signal resetnl : std_ulogic; |
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99 | 99 | signal clk2x : std_ulogic; |
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100 | 100 | signal lclk : std_ulogic; |
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101 | 101 | signal lclk2x : std_ulogic; |
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102 | 102 | signal clkm : std_ulogic; |
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103 | 103 | signal rstn : std_ulogic; |
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104 | 104 | signal rstraw : std_ulogic; |
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105 | 105 | signal pciclk : std_ulogic; |
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106 | 106 | signal sdclkl : std_ulogic; |
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107 | 107 | signal cgi : clkgen_in_type; |
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108 | 108 | signal cgo : clkgen_out_type; |
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109 | 109 | --- AHB / APB |
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110 | 110 | signal apbi : apb_slv_in_type; |
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111 | 111 | signal apbo : apb_slv_out_vector := (others => apb_none); |
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112 | 112 | signal ahbsi : ahb_slv_in_type; |
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113 | 113 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
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114 | 114 | signal ahbmi : ahb_mst_in_type; |
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115 | 115 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
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116 | 116 | --UART |
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117 | 117 | signal ahbuarti : uart_in_type; |
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118 | 118 | signal ahbuarto : uart_out_type; |
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119 | 119 | signal apbuarti : uart_in_type; |
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120 | 120 | signal apbuarto : uart_out_type; |
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121 | 121 | --MEM CTRLR |
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122 | 122 | signal memi : memory_in_type; |
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123 | 123 | signal memo : memory_out_type; |
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124 | 124 | signal wpo : wprot_out_type; |
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125 | 125 | signal sdo : sdram_out_type; |
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126 | 126 | --IRQ |
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127 | 127 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
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128 | 128 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
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129 | 129 | --Timer |
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130 | 130 | signal gpti : gptimer_in_type; |
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131 | 131 | signal gpto : gptimer_out_type; |
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132 | 132 | --GPIO |
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133 | 133 | signal gpioi : gpio_in_type; |
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134 | 134 | signal gpioo : gpio_out_type; |
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135 | 135 | --DSU |
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136 | 136 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
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137 | 137 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
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138 | 138 | signal dsui : dsu_in_type; |
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139 | 139 | signal dsuo : dsu_out_type; |
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140 | 140 | ---------------------------------------------------------------------- |
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141 | 141 | --- AJOUT TEST ------------------------Signaux---------------------- |
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142 | 142 | ---------------------------------------------------------------------- |
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143 | 143 | -- TEST USB |
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144 | 144 | --signal USB_Read : std_logic; |
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145 | 145 | --signal USB_Write : std_logic; |
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146 | 146 | |
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147 | 147 | -- MATRICE SPECTRALE |
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148 | 148 | --signal Matrix_Write : std_logic; |
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149 | 149 | --signal Matrix_Read : std_logic_vector(1 downto 0); |
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150 | 150 | --signal Matrix_Full : std_logic_vector(1 downto 0); |
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151 | 151 | --signal Matrix_Empty : std_logic_vector(1 downto 0); |
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152 | 152 | --signal Matrix_Data1 : std_logic_vector(15 downto 0); |
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153 | 153 | --signal Matrix_Data2 : std_logic_vector(15 downto 0); |
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154 | 154 | --signal Matrix_Result : std_logic_vector(31 downto 0); |
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155 | 155 | |
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156 | 156 | --------------------------------------------------------------------- |
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157 | 157 | constant IOAEN : integer := CFG_CAN; |
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158 | 158 | constant boardfreq : integer := 50000; |
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159 | 159 | |
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160 | 160 | begin |
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161 | 161 | |
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162 | 162 | ---------------------------------------------------------------------- |
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163 | 163 | --- Reset and Clock generation ------------------------------------- |
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164 | 164 | ---------------------------------------------------------------------- |
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165 | 165 | |
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166 | 166 | vcc <= (others => '1'); gnd <= (others => '0'); |
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167 | 167 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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168 | 168 | |
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169 | 169 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
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170 | 170 | |
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171 | 171 | |
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172 | 172 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
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173 | 173 | |
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174 | 174 | clkgen0 : clkgen -- clock generator |
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175 | 175 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
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176 | 176 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
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177 | 177 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
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178 | 178 | |
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179 | 179 | ramclk <= clkm; |
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180 | 180 | process(lclk2x) |
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181 | 181 | begin |
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182 | 182 | if lclk2x'event and lclk2x = '1' then |
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183 | 183 | lclk <= not lclk; |
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184 | 184 | end if; |
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185 | 185 | end process; |
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186 | 186 | |
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187 | 187 | ---------------------------------------------------------------------- |
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188 | 188 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
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189 | 189 | ---------------------------------------------------------------------- |
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190 | 190 | |
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191 | 191 | l3 : if CFG_LEON3 = 1 generate |
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192 | 192 | cpu : for i in 0 to CFG_NCPU-1 generate |
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193 | 193 | u0 : leon3s -- LEON3 processor |
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194 | 194 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
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195 | 195 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
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196 | 196 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
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197 | 197 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
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198 | 198 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
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199 | 199 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
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200 | 200 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
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201 | 201 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
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202 | 202 | end generate; |
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203 | 203 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
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204 | 204 | |
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205 | 205 | dsugen : if CFG_DSU = 1 generate |
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206 | 206 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
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207 | 207 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
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208 | 208 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
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209 | 209 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
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210 | 210 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
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211 | 211 | dsui.enable <= '1'; |
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212 | 212 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
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213 | 213 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
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214 | 214 | end generate; |
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215 | 215 | end generate; |
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216 | 216 | |
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217 | 217 | nodsu : if CFG_DSU = 0 generate |
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218 | 218 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
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219 | 219 | end generate; |
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220 | 220 | |
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221 | 221 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
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222 | 222 | irqctrl0 : irqmp -- interrupt controller |
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223 | 223 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
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224 | 224 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
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225 | 225 | end generate; |
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226 | 226 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
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227 | 227 | x : for i in 0 to CFG_NCPU-1 generate |
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228 | 228 | irqi(i).irl <= "0000"; |
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229 | 229 | end generate; |
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230 | 230 | apbo(2) <= apb_none; |
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231 | 231 | end generate; |
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232 | 232 | |
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233 | 233 | ---------------------------------------------------------------------- |
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234 | 234 | --- Memory controllers --------------------------------------------- |
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235 | 235 | ---------------------------------------------------------------------- |
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236 | 236 | |
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237 | 237 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
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238 | 238 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
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239 | 239 | |
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240 | 240 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
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241 | 241 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
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242 | 242 | |
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243 | 243 | bdr : for i in 0 to 3 generate |
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244 | 244 | data_pad : iopadv generic map (tech => padtech, width => 8) |
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245 | 245 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
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246 | 246 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
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247 | 247 | end generate; |
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248 | 248 | |
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249 | 249 | |
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250 | 250 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
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251 | 251 | port map (address, memo.address(20 downto 2)); |
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252 | 252 | |
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253 | 253 | |
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254 | 254 | --SSRAM_0:entity ssram_plugin |
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255 | 255 | --generic map (tech => padtech) |
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256 | 256 | --port map |
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257 | 257 | --(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
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258 | 258 | |
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259 |
SSRAM_0:entity |
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259 | SSRAM_0:entity ssram_plugin | |
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260 | 260 | generic map (tech => padtech) |
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261 | 261 | port map |
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262 | 262 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
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263 | 263 | |
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264 | 264 | ---------------------------------------------------------------------- |
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265 | 265 | --- AHB CONTROLLER ------------------------------------------------- |
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266 | 266 | ---------------------------------------------------------------------- |
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267 | 267 | |
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268 | 268 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
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269 | 269 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
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270 | 270 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
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271 | 271 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
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272 | 272 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
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273 | 273 | |
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274 | 274 | ---------------------------------------------------------------------- |
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275 | 275 | --- AHB UART ------------------------------------------------------- |
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276 | 276 | ---------------------------------------------------------------------- |
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277 | 277 | dcomgen : if CFG_AHB_UART = 1 generate |
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278 | 278 | dcom0: ahbuart -- Debug UART |
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279 | 279 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
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280 | 280 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
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281 | 281 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
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282 | 282 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
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283 | 283 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
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284 | 284 | end generate; |
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285 | 285 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
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286 | 286 | |
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287 | 287 | ---------------------------------------------------------------------- |
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288 | 288 | --- APB Bridge ----------------------------------------------------- |
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289 | 289 | ---------------------------------------------------------------------- |
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290 | 290 | |
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291 | 291 | apb0 : apbctrl -- AHB/APB bridge |
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292 | 292 | generic map (hindex => 1, haddr => CFG_APBADDR) |
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293 | 293 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
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294 | 294 | |
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295 | 295 | ---------------------------------------------------------------------- |
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296 | 296 | --- GPT Timer ------------------------------------------------------ |
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297 | 297 | ---------------------------------------------------------------------- |
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298 | 298 | |
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299 | 299 | gpt : if CFG_GPT_ENABLE /= 0 generate |
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300 | 300 | timer0 : gptimer -- timer unit |
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301 | 301 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
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302 | 302 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
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303 | 303 | nbits => CFG_GPT_TW) |
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304 | 304 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
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305 | 305 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
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306 | 306 | -- led(4) <= gpto.wdog; |
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307 | 307 | end generate; |
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308 | 308 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
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309 | 309 | |
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310 | 310 | |
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311 | 311 | ---------------------------------------------------------------------- |
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312 | 312 | --- APB UART ------------------------------------------------------- |
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313 | 313 | ---------------------------------------------------------------------- |
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314 | 314 | |
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315 | 315 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
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316 | 316 | uart1 : apbuart -- UART 1 |
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317 | 317 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
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318 | 318 | fifosize => CFG_UART1_FIFO) |
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319 | 319 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
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320 | 320 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
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321 | 321 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
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322 | 322 | led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
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323 | 323 | end generate; |
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324 | 324 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
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325 | 325 | |
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326 | 326 | --------------------------------------------------------------------- |
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327 | 327 | --- AJOUT TEST -------------------------------------IPs------------ |
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328 | 328 | --------------------------------------------------------------------- |
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329 | 329 | |
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330 | 330 | |
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331 | 331 | end Behavioral; No newline at end of file |
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