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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | -- jean-christophe.pellion@easii-ic.com |
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22 | 22 | ---------------------------------------------------------------------------- |
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23 | 23 | LIBRARY ieee; |
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24 | 24 | USE ieee.std_logic_1164.ALL; |
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25 | 25 | USE ieee.numeric_std.ALL; |
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26 | 26 | LIBRARY grlib; |
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27 | 27 | USE grlib.amba.ALL; |
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28 | 28 | USE grlib.stdlib.ALL; |
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29 | 29 | USE grlib.devices.ALL; |
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30 | 30 | LIBRARY lpp; |
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31 | 31 | USE lpp.lpp_amba.ALL; |
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32 | 32 | USE lpp.apb_devices_list.ALL; |
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33 | 33 | USE lpp.lpp_memory.ALL; |
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34 | 34 | LIBRARY techmap; |
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35 | 35 | USE techmap.gencomp.ALL; |
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36 | 36 | |
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37 | 37 | ENTITY lpp_dma_apbreg IS |
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38 | 38 | GENERIC ( |
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39 | 39 | pindex : INTEGER := 4; |
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40 | 40 | paddr : INTEGER := 4; |
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41 | 41 | pmask : INTEGER := 16#fff#; |
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42 | 42 | pirq : INTEGER := 0); |
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43 | 43 | PORT ( |
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44 | 44 | -- AMBA AHB system signals |
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45 | 45 | HCLK : IN STD_ULOGIC; |
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46 | 46 | HRESETn : IN STD_ULOGIC; |
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47 | 47 | |
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48 | 48 | -- AMBA APB Slave Interface |
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49 | 49 | apbi : IN apb_slv_in_type; |
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50 | 50 | apbo : OUT apb_slv_out_type; |
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51 | 51 | |
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52 | 52 | -- IN |
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53 | 53 | ready_matrix_f0_0 : IN STD_LOGIC; |
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54 | 54 | ready_matrix_f0_1 : IN STD_LOGIC; |
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55 | 55 | ready_matrix_f1 : IN STD_LOGIC; |
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56 | 56 | ready_matrix_f2 : IN STD_LOGIC; |
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57 | 57 | error_anticipating_empty_fifo : IN STD_LOGIC; |
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58 | 58 | error_bad_component_error : IN STD_LOGIC; |
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59 | 59 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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60 | 60 | |
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61 | 61 | -- OUT |
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62 | 62 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
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63 | 63 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
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64 | 64 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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65 | 65 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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66 | 66 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
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67 | 67 | status_error_bad_component_error : OUT STD_LOGIC; |
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68 | 68 | |
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69 | 69 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
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70 | 70 | config_active_interruption_onError : OUT STD_LOGIC; |
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71 | 71 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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72 | 72 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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73 | 73 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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74 | 74 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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75 | 75 | ); |
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76 | 76 | |
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77 | 77 | END lpp_dma_apbreg; |
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78 | 78 | |
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79 | 79 | ARCHITECTURE beh OF lpp_dma_apbreg IS |
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80 | 80 | |
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81 | 81 | CONSTANT REVISION : INTEGER := 1; |
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82 | 82 | |
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83 | 83 | CONSTANT pconfig : apb_config_type := ( |
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84 | 84 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), |
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85 | 85 | 1 => apb_iobar(paddr, pmask)); |
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86 | 86 | |
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87 | 87 | TYPE lpp_dma_regs IS RECORD |
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88 | 88 | config_active_interruption_onNewMatrix : STD_LOGIC; |
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89 | 89 | config_active_interruption_onError : STD_LOGIC; |
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90 | 90 | status_ready_matrix_f0_0 : STD_LOGIC; |
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91 | 91 | status_ready_matrix_f0_1 : STD_LOGIC; |
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92 | 92 | status_ready_matrix_f1 : STD_LOGIC; |
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93 | 93 | status_ready_matrix_f2 : STD_LOGIC; |
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94 | 94 | status_error_anticipating_empty_fifo : STD_LOGIC; |
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95 | 95 | status_error_bad_component_error : STD_LOGIC; |
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96 | 96 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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97 | 97 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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98 | 98 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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99 | 99 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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100 | 100 | END RECORD; |
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101 | 101 | |
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102 | 102 | SIGNAL reg : lpp_dma_regs; |
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103 | 103 | |
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104 | 104 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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105 | 105 | |
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106 | 106 | BEGIN -- beh |
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107 | 107 | |
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108 | 108 | status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; |
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109 | 109 | status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; |
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110 | 110 | status_ready_matrix_f1 <= reg.status_ready_matrix_f1; |
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111 | 111 | status_ready_matrix_f2 <= reg.status_ready_matrix_f2; |
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112 | 112 | status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; |
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113 | 113 | status_error_bad_component_error <= reg.status_error_bad_component_error; |
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114 | 114 | |
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115 | 115 | config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; |
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116 | 116 | config_active_interruption_onError <= reg.config_active_interruption_onError; |
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117 | 117 | addr_matrix_f0_0 <= reg.addr_matrix_f0_0; |
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118 | 118 | addr_matrix_f0_1 <= reg.addr_matrix_f0_1; |
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119 | 119 | addr_matrix_f1 <= reg.addr_matrix_f1; |
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120 | 120 | addr_matrix_f2 <= reg.addr_matrix_f2; |
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121 | 121 | |
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122 | 122 | lpp_dma_apbreg : PROCESS (HCLK, HRESETn) |
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123 | 123 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
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124 | 124 | BEGIN -- PROCESS lpp_dma_top |
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125 | 125 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
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126 | 126 | reg.config_active_interruption_onNewMatrix <= '0'; |
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127 | 127 | reg.config_active_interruption_onError <= '0'; |
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128 | 128 | reg.status_ready_matrix_f0_0 <= '0'; |
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129 | 129 | reg.status_ready_matrix_f0_1 <= '0'; |
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130 | 130 | reg.status_ready_matrix_f1 <= '0'; |
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131 | 131 | reg.status_ready_matrix_f2 <= '0'; |
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132 | 132 | reg.status_error_anticipating_empty_fifo <= '0'; |
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133 | 133 | reg.status_error_bad_component_error <= '0'; |
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134 | 134 | reg.addr_matrix_f0_0 <= (OTHERS => '0'); |
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135 | 135 | reg.addr_matrix_f0_1 <= (OTHERS => '0'); |
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136 | 136 | reg.addr_matrix_f1 <= (OTHERS => '0'); |
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137 | 137 | reg.addr_matrix_f2 <= (OTHERS => '0'); |
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138 | 138 | prdata <= (OTHERS => '0'); |
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139 | 139 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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140 | 140 | |
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141 | 141 | reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
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142 | 142 | reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
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143 | 143 | reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; |
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144 | 144 | reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; |
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145 | 145 | |
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146 | 146 | reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; |
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147 | 147 | reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; |
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148 | 148 | |
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149 | 149 | paddr := "000000"; |
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150 | 150 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
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151 | 151 | prdata <= (OTHERS => '0'); |
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152 | 152 | IF apbi.psel(pindex) = '1' THEN |
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153 | 153 | -- APB DMA READ -- |
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154 | 154 | CASE paddr(7 DOWNTO 2) IS |
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155 | 155 | WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; |
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156 | 156 | prdata(1) <= reg.config_active_interruption_onError; |
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157 | 157 | WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; |
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158 | 158 | prdata(1) <= reg.status_ready_matrix_f0_1; |
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159 | 159 | prdata(2) <= reg.status_ready_matrix_f1; |
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160 | 160 | prdata(3) <= reg.status_ready_matrix_f2; |
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161 | 161 | prdata(4) <= reg.status_error_anticipating_empty_fifo; |
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162 | 162 | prdata(5) <= reg.status_error_bad_component_error; |
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163 | 163 | WHEN "000010" => prdata <= reg.addr_matrix_f0_0; |
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164 | 164 | WHEN "000011" => prdata <= reg.addr_matrix_f0_1; |
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165 | 165 | WHEN "000100" => prdata <= reg.addr_matrix_f1; |
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166 | 166 | WHEN "000101" => prdata <= reg.addr_matrix_f2; |
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167 | 167 | WHEN "000110" => prdata <= debug_reg; |
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168 | 168 | WHEN OTHERS => NULL; |
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169 | 169 | END CASE; |
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170 | 170 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
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171 | 171 | -- APB DMA WRITE -- |
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172 | 172 | CASE paddr(7 DOWNTO 2) IS |
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173 | 173 | WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
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174 | 174 | reg.config_active_interruption_onError <= apbi.pwdata(1); |
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175 | 175 | WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
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176 | 176 | reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); |
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177 | 177 | reg.status_ready_matrix_f1 <= apbi.pwdata(2); |
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178 | 178 | reg.status_ready_matrix_f2 <= apbi.pwdata(3); |
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179 | 179 | reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); |
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180 | 180 | reg.status_error_bad_component_error <= apbi.pwdata(5); |
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181 | 181 | WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; |
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182 | 182 | WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; |
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183 | 183 | WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; |
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184 | 184 | WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; |
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185 | 185 | WHEN OTHERS => NULL; |
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186 | 186 | END CASE; |
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187 | 187 | END IF; |
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188 | 188 | END IF; |
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189 | 189 | END IF; |
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190 | 190 | END PROCESS lpp_dma_apbreg; |
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191 | 191 | |
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192 | apbo.pirq <= (OTHERS => '0'); | |
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192 | apbo.pirq <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |
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193 | ready_matrix_f0_1 OR | |
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194 | ready_matrix_f1 OR | |
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195 | ready_matrix_f2) | |
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196 | ) | |
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197 | OR | |
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198 | (reg.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |
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199 | error_bad_component_error) | |
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200 | ); | |
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201 | ||
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202 | ||
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203 | ||
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204 | ||
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205 | ||
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193 | 206 |
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194 | 207 | apbo.pconfig <= pconfig; |
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195 | 208 | apbo.prdata <= prdata; |
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196 | 209 | |
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197 | 210 | |
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198 | 211 | END beh; |
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