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add HK debug
pellion -
r533:c48ab309a6b7 (LFR-EM) WFP_MS_1-1-60 JC
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@@ -391,7 +391,7 BEGIN -- beh
391 pirq_ms => 6,
391 pirq_ms => 6,
392 pirq_wfp => 14,
392 pirq_wfp => 14,
393 hindex => 2,
393 hindex => 2,
394 top_lfr_version => X"01013B") -- aa.bb.cc version
394 top_lfr_version => X"01013C") -- aa.bb.cc version
395 -- AA : BOARD NUMBER
395 -- AA : BOARD NUMBER
396 -- 0 => MINI_LFR
396 -- 0 => MINI_LFR
397 -- 1 => EM
397 -- 1 => EM
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@@ -59,10 +59,10 ENTITY apb_lfr_management IS
59 HK_val : IN STD_LOGIC;
59 HK_val : IN STD_LOGIC;
60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 DAC_SDO : OUT STD_LOGIC;
62 DAC_SDO : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
66 ---------------------------------------------------------------------------
66 ---------------------------------------------------------------------------
67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
@@ -127,18 +127,18 ARCHITECTURE Behavioral OF apb_lfr_manag
127 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128
128
129 SIGNAL previous_fine_time_bit : STD_LOGIC;
129 SIGNAL previous_fine_time_bit : STD_LOGIC;
130
130
131 SIGNAL rstn_LFR_TM : STD_LOGIC;
131 SIGNAL rstn_LFR_TM : STD_LOGIC;
132
132
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 -- DAC
134 -- DAC
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136 CONSTANT PRESZ : INTEGER := 8;
136 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT CPTSZ : INTEGER := 16;
137 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT datawidth : INTEGER := 18;
138 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT dacresolution : INTEGER := 12;
139 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT abits : INTEGER := 8;
140 CONSTANT abits : INTEGER := 8;
141
141
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL Reload : STD_LOGIC;
144 SIGNAL Reload : STD_LOGIC;
@@ -151,6 +151,9 ARCHITECTURE Behavioral OF apb_lfr_manag
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153
153
154 SIGNAL HK_debug_mode : STD_LOGIC;
155 SIGNAL HK_sel_debug : STD_LOGIC_VECTOR(1 DOWNTO 0);
156
154 BEGIN
157 BEGIN
155
158
156 LFR_soft_rstn <= NOT r.LFR_soft_reset;
159 LFR_soft_rstn <= NOT r.LFR_soft_reset;
@@ -172,17 +175,17 BEGIN
172
175
173 coarsetime_reg_updated <= '0';
176 coarsetime_reg_updated <= '0';
174 --DAC
177 --DAC
175 pre <= (OTHERS => '1');
178 pre <= (OTHERS => '1');
176 N <= (OTHERS => '1');
179 N <= (OTHERS => '1');
177 Reload <= '1';
180 Reload <= '1';
178 DATA_IN <= (OTHERS => '0');
181 DATA_IN <= (OTHERS => '0');
179 WEN <= '1';
182 WEN <= '1';
180 LOAD_ADDRESSN <= '1';
183 LOAD_ADDRESSN <= '1';
181 ADDRESS_IN <= (OTHERS => '1');
184 ADDRESS_IN <= (OTHERS => '1');
182 INTERLEAVED <= '0';
185 INTERLEAVED <= '0';
183 DAC_CFG <= (OTHERS => '0');
186 DAC_CFG <= (OTHERS => '0');
184 --
187 --
185 DAC_CAL_EN_s <= '0';
188 DAC_CAL_EN_s <= '0';
186 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
189 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
187 coarsetime_reg_updated <= '0';
190 coarsetime_reg_updated <= '0';
188
191
@@ -214,7 +217,9 BEGIN
214 Rdata(0) <= r.ctrl;
217 Rdata(0) <= r.ctrl;
215 Rdata(1) <= r.soft_reset;
218 Rdata(1) <= r.soft_reset;
216 Rdata(2) <= r.LFR_soft_reset;
219 Rdata(2) <= r.LFR_soft_reset;
217 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
220 Rdata(3) <= HK_debug_mode;
221 Rdata(5 DOWNTO 4) <= HK_sel_debug;
222 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
218 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
223 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
219 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
224 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
220 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
225 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
@@ -252,7 +257,7 BEGIN
252 WHEN OTHERS =>
257 WHEN OTHERS =>
253 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
258 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
254 END CASE;
259 END CASE;
255
260
256 --APB Write OP
261 --APB Write OP
257 IF (apbi.pwrite AND apbi.penable) = '1' THEN
262 IF (apbi.pwrite AND apbi.penable) = '1' THEN
258 CASE paddr(7 DOWNTO 2) IS
263 CASE paddr(7 DOWNTO 2) IS
@@ -260,24 +265,26 BEGIN
260 r.ctrl <= apbi.pwdata(0);
265 r.ctrl <= apbi.pwdata(0);
261 r.soft_reset <= apbi.pwdata(1);
266 r.soft_reset <= apbi.pwdata(1);
262 r.LFR_soft_reset <= apbi.pwdata(2);
267 r.LFR_soft_reset <= apbi.pwdata(2);
268 HK_debug_mode <= apbi.pwdata(3);
269 HK_sel_debug <= apbi.pwdata(5 DOWNTO 4);
263 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
270 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
264 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
271 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
265 coarsetime_reg_updated <= '1';
272 coarsetime_reg_updated <= '1';
266 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
273 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
267 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
274 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
268 Reload <= apbi.pwdata(4);
275 Reload <= apbi.pwdata(4);
269 INTERLEAVED <= apbi.pwdata(5);
276 INTERLEAVED <= apbi.pwdata(5);
270 DAC_CAL_EN_s <= apbi.pwdata(6);
277 DAC_CAL_EN_s <= apbi.pwdata(6);
271 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
278 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
272 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
279 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
273 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
280 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
274 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
281 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
275 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
282 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
276 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
283 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
277 LOAD_ADDRESSN <= '0';
284 LOAD_ADDRESSN <= '0';
278 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
285 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
279 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
286 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
280 WEN <= '0';
287 WEN <= '0';
281
288
282 WHEN OTHERS =>
289 WHEN OTHERS =>
283 NULL;
290 NULL;
@@ -440,7 +447,6 BEGIN
440 -- for 14, the update frequency is
447 -- for 14, the update frequency is
441 -- 4Hz and update for each
448 -- 4Hz and update for each
442 -- HK is 1.33Hz
449 -- HK is 1.33Hz
443
444 BEGIN -- PROCESS
450 BEGIN -- PROCESS
445 IF resetn = '0' THEN -- asynchronous reset (active low)
451 IF resetn = '0' THEN -- asynchronous reset (active low)
446
452
@@ -458,9 +464,27 BEGIN
458 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
464 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
459 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
465 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
460 CASE HK_sel_s IS
466 CASE HK_sel_s IS
461 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
467 WHEN "00" =>
462 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
468 r.HK_temp_0 <= HK_sample;
463 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
469 IF HK_debug_mode = '1' THEN
470 HK_sel_s <= HK_sel_debug;
471 ELSE
472 HK_sel_s <= "01";
473 END IF;
474 WHEN "01" =>
475 r.HK_temp_1 <= HK_sample;
476 IF HK_debug_mode = '1' THEN
477 HK_sel_s <= HK_sel_debug;
478 ELSE
479 HK_sel_s <= "10";
480 END IF;
481 WHEN "10" =>
482 r.HK_temp_2 <= HK_sample;
483 IF HK_debug_mode = '1' THEN
484 HK_sel_s <= HK_sel_debug;
485 ELSE
486 HK_sel_s <= "00";
487 END IF;
464 WHEN OTHERS => NULL;
488 WHEN OTHERS => NULL;
465 END CASE;
489 END CASE;
466 END IF;
490 END IF;
@@ -483,9 +507,9 BEGIN
483 abits => abits
507 abits => abits
484 )
508 )
485 PORT MAP(
509 PORT MAP(
486 clk => clk25MHz,
510 clk => clk25MHz,
487 rstn => resetn,
511 rstn => resetn,
488
512
489 pre => pre,
513 pre => pre,
490 N => N,
514 N => N,
491 Reload => Reload,
515 Reload => Reload,
@@ -496,12 +520,12 BEGIN
496 ADDRESS_OUT => ADDRESS_OUT,
520 ADDRESS_OUT => ADDRESS_OUT,
497 INTERLEAVED => INTERLEAVED,
521 INTERLEAVED => INTERLEAVED,
498 DAC_CFG => DAC_CFG,
522 DAC_CFG => DAC_CFG,
499
523
500 SYNC => DAC_SYNC,
524 SYNC => DAC_SYNC,
501 DOUT => DAC_SDO,
525 DOUT => DAC_SDO,
502 SCLK => DAC_SCK,
526 SCLK => DAC_SCK,
503 SMPCLK => OPEN --DAC_SMPCLK
527 SMPCLK => OPEN --DAC_SMPCLK
504 );
528 );
505
529
506 DAC_CAL_EN <= DAC_CAL_EN_s;
530 DAC_CAL_EN <= DAC_CAL_EN_s;
507 END Behavioral; No newline at end of file
531 END Behavioral;
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