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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY LFR_em IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk100MHz : IN STD_ULOGIC; |
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52 | 52 | clk49_152MHz : IN STD_ULOGIC; |
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53 | 53 | reset : IN STD_ULOGIC; |
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54 | 54 | |
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55 | 55 | -- TAG -------------------------------------------------------------------- |
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56 | 56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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57 | 57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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58 | 58 | -- UART APB --------------------------------------------------------------- |
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59 | 59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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60 | 60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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61 | 61 | -- RAM -------------------------------------------------------------------- |
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62 | 62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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63 | 63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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64 | 64 | nSRAM_BE0 : OUT STD_LOGIC; |
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65 | 65 | nSRAM_BE1 : OUT STD_LOGIC; |
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66 | 66 | nSRAM_BE2 : OUT STD_LOGIC; |
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67 | 67 | nSRAM_BE3 : OUT STD_LOGIC; |
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68 | 68 | nSRAM_WE : OUT STD_LOGIC; |
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69 | 69 | nSRAM_CE : OUT STD_LOGIC; |
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70 | 70 | nSRAM_OE : OUT STD_LOGIC; |
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71 | 71 | -- SPW -------------------------------------------------------------------- |
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72 | 72 | spw1_din : IN STD_LOGIC; |
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73 | 73 | spw1_sin : IN STD_LOGIC; |
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74 | 74 | spw1_dout : OUT STD_LOGIC; |
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75 | 75 | spw1_sout : OUT STD_LOGIC; |
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76 | 76 | spw2_din : IN STD_LOGIC; |
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77 | 77 | spw2_sin : IN STD_LOGIC; |
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78 | 78 | spw2_dout : OUT STD_LOGIC; |
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79 | 79 | spw2_sout : OUT STD_LOGIC; |
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80 | 80 | -- ADC -------------------------------------------------------------------- |
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81 | 81 | bias_fail_sw : OUT STD_LOGIC; |
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82 | 82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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83 | 83 | ADC_smpclk : OUT STD_LOGIC; |
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84 | 84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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85 | 85 | -- DAC -------------------------------------------------------------------- |
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86 | 86 | DAC_SDO : OUT STD_LOGIC; |
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87 | 87 | DAC_SCK : OUT STD_LOGIC; |
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88 | 88 | DAC_SYNC : OUT STD_LOGIC; |
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89 | 89 | DAC_CAL_EN : OUT STD_LOGIC; |
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90 | 90 | -- HK --------------------------------------------------------------------- |
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91 | 91 | HK_smpclk : OUT STD_LOGIC; |
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92 | 92 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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93 | 93 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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94 | 94 | --------------------------------------------------------------------------- |
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95 |
TAG8 : |
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95 | TAG8 : IN STD_LOGIC; | |
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96 | 96 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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97 | 97 | ); |
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98 | 98 | |
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99 | 99 | END LFR_em; |
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100 | 100 | |
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101 | 101 | |
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102 | 102 | ARCHITECTURE beh OF LFR_em IS |
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103 | ||
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104 | --========================================================================== | |
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105 | -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board | |
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106 | -- when enabled, chip enable polarity should be reversed and bank size also | |
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107 | -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 | |
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108 | -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 | |
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109 | --========================================================================== | |
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110 | CONSTANT USE_IAP_MEMCTRL : integer := 1; | |
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111 | --========================================================================== | |
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112 | ||
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103 | 113 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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104 | 114 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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105 | 115 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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106 | 116 | ----------------------------------------------------------------------------- |
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107 | 117 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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108 | 118 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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109 | 119 | |
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110 | 120 | -- CONSTANTS |
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111 | 121 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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112 | 122 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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113 | 123 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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114 | 124 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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115 | 125 | |
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116 | 126 | SIGNAL apbi_ext : apb_slv_in_type; |
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117 | 127 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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118 | 128 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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119 | 129 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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120 | 130 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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121 | 131 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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122 | 132 | |
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123 | 133 | -- Spacewire signals |
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124 | 134 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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125 | 135 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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126 | 136 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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127 | 137 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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128 | 138 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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129 | 139 | SIGNAL spw_clk : STD_LOGIC; |
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130 | 140 | SIGNAL swni : grspw_in_type; |
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131 | 141 | SIGNAL swno : grspw_out_type; |
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132 | 142 | |
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133 | 143 | --GPIO |
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134 | 144 | SIGNAL gpioi : gpio_in_type; |
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135 | 145 | SIGNAL gpioo : gpio_out_type; |
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136 | 146 | |
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137 | 147 | -- AD Converter ADS7886 |
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138 | 148 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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139 | 149 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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140 | 150 | SIGNAL sample_val : STD_LOGIC; |
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141 | 151 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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142 | 152 | |
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143 | 153 | ----------------------------------------------------------------------------- |
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144 | 154 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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145 | 155 | |
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146 | 156 | ----------------------------------------------------------------------------- |
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147 | 157 | SIGNAL rstn_25 : STD_LOGIC; |
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148 | 158 | SIGNAL rstn_24 : STD_LOGIC; |
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149 | 159 | |
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150 | 160 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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151 | 161 | SIGNAL LFR_rstn : STD_LOGIC; |
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152 | 162 | |
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153 | 163 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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154 | 164 | ---------------------------------------------------------------------------- |
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155 | 165 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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166 | SIGNAL nSRAM_READY : STD_LOGIC; | |
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156 | 167 | |
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157 | 168 | BEGIN -- beh |
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158 | 169 | |
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159 | 170 | ----------------------------------------------------------------------------- |
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160 | 171 | -- CLK |
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161 | 172 | ----------------------------------------------------------------------------- |
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162 | 173 | rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); |
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163 | 174 | rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); |
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164 | 175 | |
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165 | 176 | PROCESS(clk100MHz) |
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166 | 177 | BEGIN |
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167 | 178 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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168 | 179 | clk_50_s <= NOT clk_50_s; |
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169 | 180 | END IF; |
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170 | 181 | END PROCESS; |
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171 | 182 | |
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172 | 183 | PROCESS(clk_50_s) |
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173 | 184 | BEGIN |
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174 | 185 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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175 | 186 | clk_25 <= NOT clk_25; |
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176 | 187 | END IF; |
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177 | 188 | END PROCESS; |
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178 | 189 | |
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179 | 190 | PROCESS(clk49_152MHz) |
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180 | 191 | BEGIN |
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181 | 192 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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182 | 193 | clk_24 <= NOT clk_24; |
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183 | 194 | END IF; |
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184 | 195 | END PROCESS; |
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185 | 196 | |
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186 | 197 | ----------------------------------------------------------------------------- |
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187 | 198 | |
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188 | 199 | PROCESS (clk_25, rstn_25) |
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189 | 200 | BEGIN -- PROCESS |
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190 | 201 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
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191 | 202 | led(0) <= '0'; |
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192 | 203 | led(1) <= '0'; |
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193 | 204 | led(2) <= '0'; |
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194 | 205 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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195 | 206 | led(0) <= '0'; |
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196 | 207 | led(1) <= '1'; |
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197 | 208 | led(2) <= '1'; |
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198 | 209 | END IF; |
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199 | 210 | END PROCESS; |
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200 | 211 | |
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201 | 212 | -- |
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202 | 213 | leon3_soc_1 : leon3_soc |
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203 | 214 | GENERIC MAP ( |
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204 | 215 | fabtech => apa3e, |
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205 | 216 | memtech => apa3e, |
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206 | 217 | padtech => inferred, |
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207 | 218 | clktech => inferred, |
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208 | 219 | disas => 0, |
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209 | 220 | dbguart => 0, |
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210 | 221 | pclow => 2, |
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211 | 222 | clk_freq => 25000, |
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212 | 223 | IS_RADHARD => 0, |
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213 | 224 | NB_CPU => 1, |
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214 | 225 | ENABLE_FPU => 1, |
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215 | 226 | FPU_NETLIST => 0, |
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216 | 227 | ENABLE_DSU => 1, |
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217 | 228 | ENABLE_AHB_UART => 1, |
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218 | 229 | ENABLE_APB_UART => 1, |
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219 | 230 | ENABLE_IRQMP => 1, |
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220 | 231 | ENABLE_GPT => 1, |
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221 | 232 | NB_AHB_MASTER => NB_AHB_MASTER, |
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222 | 233 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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223 | 234 | NB_APB_SLAVE => NB_APB_SLAVE, |
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224 | 235 | ADDRESS_SIZE => 20, |
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225 |
USES_IAP_MEMCTRLR => |
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236 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, | |
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237 | BYPASS_EDAC_MEMCTRLR => '0', | |
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238 | SRBANKSZ => 8) | |
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226 | 239 | PORT MAP ( |
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227 | 240 | clk => clk_25, |
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228 | 241 | reset => rstn_25, |
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229 | 242 | errorn => OPEN, |
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230 | 243 | |
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231 | 244 | ahbrxd => TAG1, |
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232 | 245 | ahbtxd => TAG3, |
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233 | 246 | urxd1 => TAG2, |
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234 | 247 | utxd1 => TAG4, |
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235 | 248 | |
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236 | 249 | address => address, |
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237 | 250 | data => data, |
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238 | 251 | nSRAM_BE0 => nSRAM_BE0, |
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239 | 252 | nSRAM_BE1 => nSRAM_BE1, |
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240 | 253 | nSRAM_BE2 => nSRAM_BE2, |
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241 | 254 | nSRAM_BE3 => nSRAM_BE3, |
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242 | 255 | nSRAM_WE => nSRAM_WE, |
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243 | 256 | nSRAM_CE => nSRAM_CE_s, |
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244 | 257 | nSRAM_OE => nSRAM_OE, |
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245 |
nSRAM_READY => |
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258 | nSRAM_READY => nSRAM_READY, | |
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246 | 259 | SRAM_MBE => OPEN, |
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247 | 260 | |
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248 | 261 | apbi_ext => apbi_ext, |
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249 | 262 | apbo_ext => apbo_ext, |
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250 | 263 | ahbi_s_ext => ahbi_s_ext, |
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251 | 264 | ahbo_s_ext => ahbo_s_ext, |
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252 | 265 | ahbi_m_ext => ahbi_m_ext, |
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253 | 266 | ahbo_m_ext => ahbo_m_ext); |
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254 | 267 | |
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268 | PROCESS (clk_25, rstn_25) | |
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269 | BEGIN -- PROCESS | |
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270 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
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271 | nSRAM_READY <= '1'; | |
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272 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
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273 | nSRAM_READY <= '1'; | |
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274 | IF TAG8 = '1' THEN | |
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275 | nSRAM_READY <= '0'; | |
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276 | END IF; | |
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277 | END IF; | |
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278 | END PROCESS; | |
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255 | 279 | |
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280 | IAP:if USE_IAP_MEMCTRL = 1 GENERATE | |
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281 | nSRAM_CE <= not nSRAM_CE_s(0); | |
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282 | END GENERATE; | |
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283 | ||
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284 | NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE | |
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256 | 285 | nSRAM_CE <= nSRAM_CE_s(0); |
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286 | END GENERATE; | |
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257 | 287 | |
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258 | 288 | ------------------------------------------------------------------------------- |
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259 | 289 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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260 | 290 | ------------------------------------------------------------------------------- |
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261 | 291 | apb_lfr_management_1 : apb_lfr_management |
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262 | 292 | GENERIC MAP ( |
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263 | 293 | tech => apa3e, |
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264 | 294 | pindex => 6, |
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265 | 295 | paddr => 6, |
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266 | 296 | pmask => 16#fff#, |
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267 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
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297 | -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
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268 | 298 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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269 | 299 | PORT MAP ( |
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270 | 300 | clk25MHz => clk_25, |
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271 | 301 | resetn_25MHz => rstn_25, -- TODO |
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272 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
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273 | resetn_24_576MHz => rstn_24, -- TODO | |
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302 | -- clk24_576MHz => clk_24, -- 49.152MHz/2 | |
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303 | -- resetn_24_576MHz => rstn_24, -- TODO | |
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274 | 304 | |
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275 | 305 | grspw_tick => swno.tickout, |
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276 | 306 | apbi => apbi_ext, |
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277 | 307 | apbo => apbo_ext(6), |
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278 | 308 | |
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279 | 309 | HK_sample => sample_s(8), |
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280 | 310 | HK_val => sample_val, |
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281 | 311 | HK_sel => HK_SEL, |
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282 | 312 | |
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283 | 313 | DAC_SDO => DAC_SDO, |
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284 | 314 | DAC_SCK => DAC_SCK, |
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285 | 315 | DAC_SYNC => DAC_SYNC, |
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286 | 316 | DAC_CAL_EN => DAC_CAL_EN, |
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287 | 317 | |
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288 | 318 | coarse_time => coarse_time, |
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289 | 319 | fine_time => fine_time, |
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290 | 320 | LFR_soft_rstn => LFR_soft_rstn |
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291 | 321 | ); |
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292 | 322 | |
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293 | 323 | ----------------------------------------------------------------------- |
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294 | 324 | --- SpaceWire -------------------------------------------------------- |
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295 | 325 | ----------------------------------------------------------------------- |
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296 | 326 | |
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297 | 327 | -- SPW_EN <= '1'; |
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298 | 328 | |
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299 | 329 | spw_clk <= clk_50_s; |
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300 | 330 | spw_rxtxclk <= spw_clk; |
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301 | 331 | spw_rxclkn <= NOT spw_rxtxclk; |
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302 | 332 | |
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303 | 333 | -- PADS for SPW1 |
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304 | 334 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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305 | 335 | PORT MAP (spw1_din, dtmp(0)); |
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306 | 336 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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307 | 337 | PORT MAP (spw1_sin, stmp(0)); |
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308 | 338 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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309 | 339 | PORT MAP (spw1_dout, swno.d(0)); |
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310 | 340 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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311 | 341 | PORT MAP (spw1_sout, swno.s(0)); |
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312 | 342 | -- PADS FOR SPW2 |
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313 | 343 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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314 | 344 | PORT MAP (spw2_din, dtmp(1)); |
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315 | 345 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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316 | 346 | PORT MAP (spw2_sin, stmp(1)); |
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317 | 347 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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318 | 348 | PORT MAP (spw2_dout, swno.d(1)); |
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319 | 349 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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320 | 350 | PORT MAP (spw2_sout, swno.s(1)); |
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321 | 351 | |
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322 | 352 | -- GRSPW PHY |
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323 | 353 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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324 | 354 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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325 | 355 | spw_phy0 : grspw_phy |
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326 | 356 | GENERIC MAP( |
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327 | 357 | tech => apa3e, |
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328 | 358 | rxclkbuftype => 1, |
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329 | 359 | scantest => 0) |
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330 | 360 | PORT MAP( |
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331 | 361 | rxrst => swno.rxrst, |
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332 | 362 | di => dtmp(j), |
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333 | 363 | si => stmp(j), |
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334 | 364 | rxclko => spw_rxclk(j), |
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335 | 365 | do => swni.d(j), |
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336 | 366 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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337 | 367 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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338 | 368 | END GENERATE spw_inputloop; |
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339 | 369 | |
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340 | 370 | -- SPW core |
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341 | 371 | sw0 : grspwm GENERIC MAP( |
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342 | 372 | tech => apa3e, |
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343 | 373 | hindex => 1, |
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344 | 374 | pindex => 5, |
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345 | 375 | paddr => 5, |
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346 | 376 | pirq => 11, |
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347 | 377 | sysfreq => 25000, -- CPU_FREQ |
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348 | 378 | rmap => 1, |
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349 | 379 | rmapcrc => 1, |
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350 | 380 | fifosize1 => 16, |
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351 | 381 | fifosize2 => 16, |
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352 | 382 | rxclkbuftype => 1, |
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353 | 383 | rxunaligned => 0, |
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354 | 384 | rmapbufs => 4, |
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355 | 385 | ft => 0, |
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356 | 386 | netlist => 0, |
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357 | 387 | ports => 2, |
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358 | 388 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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359 | 389 | memtech => apa3e, |
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360 | 390 | destkey => 2, |
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361 | 391 | spwcore => 1 |
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362 | 392 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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363 | 393 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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364 | 394 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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365 | 395 | ) |
|
366 | 396 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
367 | 397 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
368 | 398 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
369 | 399 | swni, swno); |
|
370 | 400 | |
|
371 | 401 | swni.tickin <= '0'; |
|
372 | 402 | swni.rmapen <= '1'; |
|
373 | 403 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
374 | 404 | swni.tickinraw <= '0'; |
|
375 | 405 | swni.timein <= (OTHERS => '0'); |
|
376 | 406 | swni.dcrstval <= (OTHERS => '0'); |
|
377 | 407 | swni.timerrstval <= (OTHERS => '0'); |
|
378 | 408 | |
|
379 | 409 | ------------------------------------------------------------------------------- |
|
380 | 410 | -- LFR ------------------------------------------------------------------------ |
|
381 | 411 | ------------------------------------------------------------------------------- |
|
382 | 412 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
383 | 413 | |
|
384 | 414 | lpp_lfr_1 : lpp_lfr |
|
385 | 415 | GENERIC MAP ( |
|
386 | 416 | Mem_use => use_RAM, |
|
417 | tech => inferred, | |
|
387 | 418 | nb_data_by_buffer_size => 32, |
|
388 | 419 | --nb_word_by_buffer_size => 30, |
|
389 | 420 | nb_snapshot_param_size => 32, |
|
390 | 421 | delta_vector_size => 32, |
|
391 | 422 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
392 | 423 | pindex => 15, |
|
393 | 424 | paddr => 15, |
|
394 | 425 | pmask => 16#fff#, |
|
395 | 426 | pirq_ms => 6, |
|
396 | 427 | pirq_wfp => 14, |
|
397 | 428 | hindex => 2, |
|
398 |
top_lfr_version => X"0101 |
|
|
429 | top_lfr_version => X"010153") -- aa.bb.cc version | |
|
399 | 430 | -- AA : BOARD NUMBER |
|
400 | 431 | -- 0 => MINI_LFR |
|
401 | 432 | -- 1 => EM |
|
402 | 433 | PORT MAP ( |
|
403 | 434 | clk => clk_25, |
|
404 | 435 | rstn => LFR_rstn, |
|
405 | 436 | sample_B => sample_s(2 DOWNTO 0), |
|
406 | 437 | sample_E => sample_s(7 DOWNTO 3), |
|
407 | 438 | sample_val => sample_val, |
|
408 | 439 | apbi => apbi_ext, |
|
409 | 440 | apbo => apbo_ext(15), |
|
410 | 441 | ahbi => ahbi_m_ext, |
|
411 | 442 | ahbo => ahbo_m_ext(2), |
|
412 | 443 | coarse_time => coarse_time, |
|
413 | 444 | fine_time => fine_time, |
|
414 | 445 | data_shaping_BW => bias_fail_sw, |
|
415 | 446 | debug_vector => OPEN, |
|
416 | 447 | debug_vector_ms => OPEN); --, |
|
417 | 448 | --observation_vector_0 => OPEN, |
|
418 | 449 | --observation_vector_1 => OPEN, |
|
419 | 450 | --observation_reg => observation_reg); |
|
420 | 451 | |
|
421 | 452 | |
|
422 | 453 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
423 | 454 | sample_s(I) <= sample(I) & '0' & '0'; |
|
424 | 455 | END GENERATE all_sample; |
|
425 | 456 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
426 | 457 | |
|
427 | 458 | ----------------------------------------------------------------------------- |
|
428 | 459 | -- |
|
429 | 460 | ----------------------------------------------------------------------------- |
|
430 | 461 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
431 | 462 | GENERIC MAP ( |
|
432 | 463 | ChanelCount => 9, |
|
433 |
ncycle_cnv_high => 1 |
|
|
464 | ncycle_cnv_high => 12, | |
|
434 | 465 | ncycle_cnv => 25, |
|
435 | 466 | FILTER_ENABLED => 16#FF#) |
|
436 | 467 | PORT MAP ( |
|
437 | 468 | cnv_clk => clk_24, |
|
438 | 469 | cnv_rstn => rstn_24, |
|
439 | 470 | cnv => ADC_smpclk_s, |
|
440 | 471 | clk => clk_25, |
|
441 | 472 | rstn => rstn_25, |
|
442 | 473 | ADC_data => ADC_data, |
|
443 | 474 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
444 | 475 | sample => sample, |
|
445 | 476 | sample_val => sample_val); |
|
446 | 477 | |
|
447 | 478 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
448 | 479 | |
|
449 | 480 | ADC_smpclk <= ADC_smpclk_s; |
|
450 | 481 | HK_smpclk <= ADC_smpclk_s; |
|
451 | 482 | |
|
452 | TAG8 <= ADC_smpclk_s; | |
|
483 | -- TAG8 <= ADC_smpclk_s; | |
|
453 | 484 | |
|
454 | 485 | ----------------------------------------------------------------------------- |
|
455 | 486 | -- HK |
|
456 | 487 | ----------------------------------------------------------------------------- |
|
457 | 488 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
458 | 489 | |
|
459 |
END beh; |
|
|
490 | END beh; No newline at end of file |
@@ -1,153 +1,118 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | 26 | USE ieee.numeric_std.ALL; |
|
27 | 27 | |
|
28 | 28 | LIBRARY lpp; |
|
29 | 29 | USE lpp.general_purpose.ALL; |
|
30 | 30 | USE lpp.window_function_pkg.ALL; |
|
31 | USE lpp.data_type_pkg.ALL; | |
|
31 | 32 | |
|
32 | 33 | ENTITY window_function IS |
|
33 | 34 | GENERIC ( |
|
34 | 35 | DATA_SIZE : INTEGER := 16; |
|
35 | PARAM_SIZE : INTEGER := 10 | |
|
36 | PARAM_SIZE : INTEGER := 10; | |
|
37 | WINDOWS_PARAM : array_std_logic_vector_16b(0 TO 255) | |
|
36 | 38 | ); |
|
37 | 39 | |
|
38 | 40 | PORT ( |
|
39 | 41 | clk : IN STD_LOGIC; |
|
40 | 42 | rstn : IN STD_LOGIC; |
|
41 | 43 | |
|
42 | 44 | restart_window : IN STD_LOGIC; |
|
43 | 45 | |
|
44 | 46 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
45 | 47 | data_in_valid : IN STD_LOGIC; |
|
46 | 48 | |
|
47 | 49 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
48 | 50 | data_out_valid : OUT STD_LOGIC |
|
49 | 51 | ); |
|
50 | 52 | |
|
51 | 53 | END window_function; |
|
52 | 54 | |
|
53 | 55 | ARCHITECTURE beh OF window_function IS |
|
54 | ||
|
55 | SUBTYPE RANGE_NB_BIT_BY_WINDOW_PARAM IS INTEGER RANGE 1 TO DATA_SIZE; | |
|
56 | CONSTANT NB_BIT_BY_WINDOW_PARAM : RANGE_NB_BIT_BY_WINDOW_PARAM := 16; | |
|
57 | 56 | CONSTANT NB_POINT_BY_WINDOW : INTEGER := 256; |
|
58 | 57 | |
|
59 | TYPE WINDOWS_PARAM_TYPE IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
60 | CONSTANT windows_param_lfr_sigmoide : WINDOWS_PARAM_TYPE(0 TO 32) := | |
|
61 | ( X"0000",X"0012",X"002E",X"005B", X"00A2",X"0113",X"01C7",X"02E0", --0 - 7 | |
|
62 | X"0498",X"073A",X"0B37",X"110D", X"193C",X"240F",X"3147",X"3FF7", --8 - 15 | |
|
63 | X"4EA7",X"5BDF",X"66B2",X"6EE1", X"74B7",X"78B4",X"7B56",X"7D0E", --16 - 23 | |
|
64 | X"7E27",X"7EDB",X"7F4C",X"7F93", X"7FC0",X"7FDC",X"7FEE",X"7FF9", --24 - 31 | |
|
65 | X"7FFF" ); --32 | |
|
66 | CONSTANT windows_param_lfr_rampe : WINDOWS_PARAM_TYPE(0 TO 32) := | |
|
67 | ( X"0000",X"03E1",X"07C2",X"0BA3", X"0F84",X"1365",X"1746",X"1B27", | |
|
68 | X"1F08",X"22E8",X"26C9",X"2AAA", X"2E8B",X"326C",X"364D",X"3A2E", | |
|
69 | X"3E0F",X"41F0",X"45D1",X"49B2", X"4D93",X"5174",X"5555",X"5936", | |
|
70 | X"5D17",X"60F7",X"64D8",X"68B9", X"6C9A",X"707B",X"745C",X"783D", | |
|
71 | X"7FFF" ); | |
|
72 | CONSTANT windows_param_lfr_echelon : WINDOWS_PARAM_TYPE(0 TO 32) := | |
|
73 | ( X"0000",X"0000",X"0000",X"0000", X"0000",X"0000",X"0000",X"0000", | |
|
74 | X"0000",X"0000",X"0000",X"0000", X"0000",X"0000",X"0000",X"0000", | |
|
75 | X"FFFF",X"FFFF",X"FFFF",X"FFFF", X"FFFF",X"FFFF",X"FFFF",X"FFFF", | |
|
76 | X"FFFF",X"FFFF",X"FFFF",X"FFFF", X"FFFF",X"FFFF",X"FFFF",X"FFFF", | |
|
77 | X"FFFF"); | |
|
78 | ||
|
79 | CONSTANT windows_param_lfr : WINDOWS_PARAM_TYPE(0 TO 32) := windows_param_lfr_sigmoide; | |
|
80 | ||
|
81 | SIGNAL windows_param : WINDOWS_PARAM_TYPE(0 TO NB_POINT_BY_WINDOW-1); | |
|
82 | ||
|
83 | 58 | SIGNAL param_counter : INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1; |
|
84 | 59 | |
|
85 | 60 | SIGNAL data_x_param : STD_LOGIC_VECTOR(DATA_SIZE + PARAM_SIZE - 1 DOWNTO 0); |
|
86 | 61 | |
|
87 | 62 | SIGNAL windows_param_selected_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
88 | 63 | SIGNAL windows_param_selected : STD_LOGIC_VECTOR(PARAM_SIZE-1 DOWNTO 0); |
|
89 | 64 | SIGNAL data_in_valid_s : STD_LOGIC; |
|
90 | 65 | SIGNAL data_in_s : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
91 | 66 | |
|
92 | 67 | BEGIN |
|
93 | 68 | |
|
94 | all_windows_param_0: FOR I IN 0 TO 31 GENERATE | |
|
95 | windows_param(I) <= windows_param_lfr(I); | |
|
96 | END GENERATE all_windows_param_0; | |
|
97 | all_windows_param_1: FOR I IN 32 TO 223 GENERATE | |
|
98 | windows_param(I) <= windows_param_lfr(32); | |
|
99 | END GENERATE all_windows_param_1; | |
|
100 | all_windows_param_2: FOR I IN 224 TO 255 GENERATE | |
|
101 | windows_param(I) <= windows_param_lfr(255-I); | |
|
102 | END GENERATE all_windows_param_2; | |
|
103 | ||
|
104 | 69 | PROCESS (clk, rstn) |
|
105 | 70 | BEGIN -- PROCESS |
|
106 | 71 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
107 | 72 | param_counter <= 0; |
|
108 | 73 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
109 | 74 | IF restart_window = '1' THEN |
|
110 | 75 | param_counter <= 0; |
|
111 | 76 | ELSE |
|
112 | 77 | IF data_in_valid = '1' THEN |
|
113 | 78 | IF param_counter < 255 THEN |
|
114 | 79 | param_counter <= param_counter + 1; |
|
115 | 80 | ELSE |
|
116 | 81 | param_counter <= 0; |
|
117 | 82 | END IF; |
|
118 | 83 | END IF; |
|
119 | 84 | END IF; |
|
120 | 85 | END IF; |
|
121 | 86 | END PROCESS; |
|
122 | 87 | |
|
123 | 88 | data_in_valid_s <= data_in_valid; |
|
124 | 89 | data_in_s <= data_in; |
|
125 |
windows_param_selected_s <= |
|
|
90 | windows_param_selected_s <= WINDOWS_PARAM(param_counter); | |
|
126 | 91 | windows_param_selected <= windows_param_selected_s(15 DOWNTO 16 - PARAM_SIZE); |
|
127 | 92 | |
|
128 | 93 | WINDOWS_Multiplier : Multiplier |
|
129 | 94 | GENERIC MAP ( |
|
130 | 95 | Input_SZ_A => DATA_SIZE, |
|
131 | 96 | Input_SZ_B => PARAM_SIZE) |
|
132 | 97 | PORT MAP ( |
|
133 | 98 | clk => clk, |
|
134 | 99 | reset => rstn, |
|
135 | 100 | |
|
136 | 101 | mult => data_in_valid_s, |
|
137 | 102 | OP1 => data_in_s, |
|
138 | 103 | OP2 => windows_param_selected, |
|
139 | 104 | |
|
140 | 105 | RES => data_x_param); |
|
141 | 106 | |
|
142 | 107 | data_out <= data_x_param(DATA_SIZE + PARAM_SIZE-1 DOWNTO PARAM_SIZE); |
|
143 | 108 | |
|
144 | 109 | PROCESS (clk, rstn) |
|
145 | 110 | BEGIN -- PROCESS |
|
146 | 111 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
147 | 112 | data_out_valid <= '0'; |
|
148 | 113 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
149 | 114 | data_out_valid <= data_in_valid_s; |
|
150 | 115 | END IF; |
|
151 | 116 | END PROCESS; |
|
152 | 117 | |
|
153 | END beh; No newline at end of file | |
|
118 | END beh; |
@@ -1,44 +1,49 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
|
26 | 26 | |
|
27 | LIBRARY lpp; | |
|
28 | USE lpp.data_type_pkg.ALL; | |
|
29 | ||
|
27 | 30 | PACKAGE window_function_pkg IS |
|
28 | 31 | |
|
29 | 32 | COMPONENT window_function |
|
30 | 33 | GENERIC ( |
|
31 | 34 | DATA_SIZE : INTEGER; |
|
32 |
PARAM_SIZE : INTEGER |
|
|
35 | PARAM_SIZE : INTEGER; | |
|
36 | WINDOWS_PARAM : array_std_logic_vector_16b(0 TO 255) | |
|
37 | ); | |
|
33 | 38 | PORT ( |
|
34 | 39 | clk : IN STD_LOGIC; |
|
35 | 40 | rstn : IN STD_LOGIC; |
|
36 | 41 | restart_window : IN STD_LOGIC; |
|
37 | 42 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
38 | 43 | data_in_valid : IN STD_LOGIC; |
|
39 | 44 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
40 | 45 | data_out_valid : OUT STD_LOGIC); |
|
41 | 46 | END COMPONENT; |
|
42 | 47 | |
|
43 | 48 | |
|
44 | 49 | END window_function_pkg; |
@@ -1,35 +1,55 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ------------------------------------------------------------------------------- |
|
23 | 23 | |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
|
26 | 27 | |
|
27 | 28 | PACKAGE data_type_pkg IS |
|
28 | 29 | |
|
29 | 30 | TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
|
30 | 31 | TYPE array_real IS ARRAY (NATURAL RANGE <>) OF REAL; |
|
31 | 32 | TYPE array_std_logic_vector_16b IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
32 | 33 | |
|
33 | 34 | TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
34 | 35 | |
|
36 | FUNCTION to_array_std_logic_vector_16b ( | |
|
37 | array_in : array_real) | |
|
38 | RETURN array_std_logic_vector_16b; | |
|
39 | ||
|
35 | 40 | END data_type_pkg; |
|
41 | ||
|
42 | PACKAGE BODY data_type_pkg IS | |
|
43 | ||
|
44 | FUNCTION to_array_std_logic_vector_16b ( | |
|
45 | array_in : array_real) | |
|
46 | RETURN array_std_logic_vector_16b IS | |
|
47 | VARIABLE array_out : array_std_logic_vector_16b(array_in'RANGE); | |
|
48 | BEGIN | |
|
49 | all_value: FOR I IN array_in'RANGE LOOP | |
|
50 | array_out(I) := STD_LOGIC_VECTOR(to_signed(INTEGER(array_in(I) * 2.0**15),16)); | |
|
51 | END LOOP all_value; | |
|
52 | RETURN array_out; | |
|
53 | END to_array_std_logic_vector_16b; | |
|
54 | ||
|
55 | END data_type_pkg; |
@@ -1,115 +1,116 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | USE ieee.math_real.ALL; |
|
27 | 27 | |
|
28 | 28 | LIBRARY std; |
|
29 | 29 | USE std.textio.ALL; |
|
30 | 30 | |
|
31 | 31 | LIBRARY lpp; |
|
32 | 32 | USE lpp.data_type_pkg.ALL; |
|
33 | 33 | |
|
34 | 34 | PACKAGE reader_pkg IS |
|
35 | 35 | |
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36 | 36 | CONSTANT CHARACTER_COMMENT : CHARACTER := '#'; |
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37 | 37 | |
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38 | FUNCTION get_array_real ( | |
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39 |
file_ |
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40 | nb_data_read : INTEGER) | |
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38 | IMPURE FUNCTION get_array_real ( | |
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39 | file_name : STRING; | |
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40 | nb_data_to_read : INTEGER) | |
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41 | 41 | RETURN array_real; |
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42 | 42 | |
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43 | FUNCTION get_array_integer ( | |
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44 |
file_ |
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45 | nb_data_read : INTEGER) | |
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43 | IMPURE FUNCTION get_array_integer ( | |
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44 | file_name : STRING; | |
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45 | nb_data_to_read : INTEGER) | |
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46 | 46 | RETURN array_integer; |
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47 | 47 | |
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48 | 48 | |
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49 | 49 | END reader_pkg; |
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50 | 50 | |
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51 | 51 | PACKAGE BODY reader_pkg IS |
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52 | 52 | |
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53 | FUNCTION get_array_real ( | |
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53 | IMPURE FUNCTION get_array_real ( | |
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54 | 54 | file_name : STRING; |
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55 | 55 | nb_data_to_read : INTEGER) |
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56 | 56 | RETURN array_real |
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57 | 57 | IS |
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58 | ||
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58 | 59 |
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59 | 60 | VARIABLE array_real_v : array_real(0 TO nb_data_to_read-1); |
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60 | 61 | VARIABLE real_p : REAL; |
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61 | 62 | VARIABLE nb_data_read : INTEGER := 0; |
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62 | 63 | FILE file_p : TEXT; |
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63 | 64 | VARIABLE line_p : LINE; |
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64 | 65 | BEGIN |
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65 | 66 | GOOD := false; |
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66 | 67 | file_open(file_p, file_name, read_mode); |
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67 | 68 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP |
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68 | 69 | readline(file_p, line_p); |
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69 | 70 | read(line_p, real_p, GOOD); |
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70 | 71 | IF GOOD THEN |
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71 | 72 | array_real_v(nb_data_read) := real_p; |
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72 | 73 | nb_data_read := nb_data_read + 1; |
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73 | 74 | END IF; |
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74 | 75 | END LOOP; |
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75 | 76 | IF nb_data_read < nb_data_to_read THEN |
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76 | 77 | GOOD := false; |
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77 | 78 | ELSE |
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78 | 79 | GOOD := true; |
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79 | 80 | END IF; |
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80 | 81 | RETURN array_real_v; |
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81 | 82 | END get_array_real; |
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82 | 83 | |
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83 | FUNCTION get_array_integer ( | |
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84 | IMPURE FUNCTION get_array_integer ( | |
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84 | 85 | file_name : STRING; |
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85 | 86 | nb_data_to_read : INTEGER) |
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86 | 87 | RETURN array_integer |
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87 | 88 | IS |
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88 | 89 | VARIABLE GOOD : BOOLEAN; |
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89 | 90 | VARIABLE array_integer_v : array_integer(0 TO nb_data_to_read-1); |
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90 | 91 | VARIABLE integer_p : INTEGER; |
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91 | 92 | VARIABLE nb_data_read : INTEGER := 0; |
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92 | 93 | FILE file_p : TEXT; |
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93 | 94 | VARIABLE line_p : LINE; |
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94 | 95 | BEGIN |
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95 | 96 | GOOD := false; |
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96 | 97 | file_open(file_p, file_name, read_mode); |
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97 | 98 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP |
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98 | 99 | readline(file_p, line_p); |
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99 | 100 | read(line_p, integer_p, GOOD); |
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100 | 101 | IF GOOD THEN |
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101 | 102 | array_integer_v(nb_data_read) := integer_p; |
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102 | 103 | nb_data_read := nb_data_read + 1; |
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103 | 104 | END IF; |
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104 | 105 | END LOOP; |
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105 | 106 | IF nb_data_read < nb_data_to_read THEN |
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106 | 107 | GOOD := false; |
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107 | 108 | ELSE |
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108 | 109 | GOOD := true; |
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109 | 110 | END IF; |
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110 | 111 | RETURN array_integer_v; |
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111 | 112 | END get_array_integer; |
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112 | 113 | |
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113 | 114 | |
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114 | 115 | |
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115 | END reader_pkg; No newline at end of file | |
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116 | END reader_pkg; |
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