@@ -1,459 +1,490 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_management.ALL; |
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45 | USE lpp.lpp_lfr_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY LFR_em IS |
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48 | ENTITY LFR_em IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk100MHz : IN STD_ULOGIC; |
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51 | clk100MHz : IN STD_ULOGIC; | |
52 | clk49_152MHz : IN STD_ULOGIC; |
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52 | clk49_152MHz : IN STD_ULOGIC; | |
53 | reset : IN STD_ULOGIC; |
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53 | reset : IN STD_ULOGIC; | |
54 |
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54 | |||
55 | -- TAG -------------------------------------------------------------------- |
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55 | -- TAG -------------------------------------------------------------------- | |
56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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56 | TAG1 : IN STD_ULOGIC; -- DSU rx data | |
57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
58 | -- UART APB --------------------------------------------------------------- |
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58 | -- UART APB --------------------------------------------------------------- | |
59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
61 | -- RAM -------------------------------------------------------------------- |
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61 | -- RAM -------------------------------------------------------------------- | |
62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | nSRAM_BE0 : OUT STD_LOGIC; |
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64 | nSRAM_BE0 : OUT STD_LOGIC; | |
65 | nSRAM_BE1 : OUT STD_LOGIC; |
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65 | nSRAM_BE1 : OUT STD_LOGIC; | |
66 | nSRAM_BE2 : OUT STD_LOGIC; |
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66 | nSRAM_BE2 : OUT STD_LOGIC; | |
67 | nSRAM_BE3 : OUT STD_LOGIC; |
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67 | nSRAM_BE3 : OUT STD_LOGIC; | |
68 | nSRAM_WE : OUT STD_LOGIC; |
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68 | nSRAM_WE : OUT STD_LOGIC; | |
69 | nSRAM_CE : OUT STD_LOGIC; |
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69 | nSRAM_CE : OUT STD_LOGIC; | |
70 | nSRAM_OE : OUT STD_LOGIC; |
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70 | nSRAM_OE : OUT STD_LOGIC; | |
71 | -- SPW -------------------------------------------------------------------- |
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71 | -- SPW -------------------------------------------------------------------- | |
72 | spw1_din : IN STD_LOGIC; |
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72 | spw1_din : IN STD_LOGIC; | |
73 | spw1_sin : IN STD_LOGIC; |
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73 | spw1_sin : IN STD_LOGIC; | |
74 | spw1_dout : OUT STD_LOGIC; |
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74 | spw1_dout : OUT STD_LOGIC; | |
75 | spw1_sout : OUT STD_LOGIC; |
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75 | spw1_sout : OUT STD_LOGIC; | |
76 | spw2_din : IN STD_LOGIC; |
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76 | spw2_din : IN STD_LOGIC; | |
77 | spw2_sin : IN STD_LOGIC; |
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77 | spw2_sin : IN STD_LOGIC; | |
78 | spw2_dout : OUT STD_LOGIC; |
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78 | spw2_dout : OUT STD_LOGIC; | |
79 | spw2_sout : OUT STD_LOGIC; |
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79 | spw2_sout : OUT STD_LOGIC; | |
80 | -- ADC -------------------------------------------------------------------- |
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80 | -- ADC -------------------------------------------------------------------- | |
81 | bias_fail_sw : OUT STD_LOGIC; |
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81 | bias_fail_sw : OUT STD_LOGIC; | |
82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
83 | ADC_smpclk : OUT STD_LOGIC; |
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83 | ADC_smpclk : OUT STD_LOGIC; | |
84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
85 | -- DAC -------------------------------------------------------------------- |
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85 | -- DAC -------------------------------------------------------------------- | |
86 | DAC_SDO : OUT STD_LOGIC; |
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86 | DAC_SDO : OUT STD_LOGIC; | |
87 | DAC_SCK : OUT STD_LOGIC; |
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87 | DAC_SCK : OUT STD_LOGIC; | |
88 | DAC_SYNC : OUT STD_LOGIC; |
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88 | DAC_SYNC : OUT STD_LOGIC; | |
89 | DAC_CAL_EN : OUT STD_LOGIC; |
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89 | DAC_CAL_EN : OUT STD_LOGIC; | |
90 | -- HK --------------------------------------------------------------------- |
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90 | -- HK --------------------------------------------------------------------- | |
91 | HK_smpclk : OUT STD_LOGIC; |
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91 | HK_smpclk : OUT STD_LOGIC; | |
92 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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92 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |
93 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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93 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
94 | --------------------------------------------------------------------------- |
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94 | --------------------------------------------------------------------------- | |
95 |
TAG8 : |
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95 | TAG8 : IN STD_LOGIC; | |
96 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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96 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) | |
97 | ); |
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97 | ); | |
98 |
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98 | |||
99 | END LFR_em; |
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99 | END LFR_em; | |
100 |
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100 | |||
101 |
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101 | |||
102 | ARCHITECTURE beh OF LFR_em IS |
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102 | ARCHITECTURE beh OF LFR_em IS | |
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103 | ||||
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104 | --========================================================================== | |||
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105 | -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board | |||
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106 | -- when enabled, chip enable polarity should be reversed and bank size also | |||
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107 | -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 | |||
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108 | -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 | |||
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109 | --========================================================================== | |||
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110 | CONSTANT USE_IAP_MEMCTRL : integer := 1; | |||
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111 | --========================================================================== | |||
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112 | ||||
103 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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113 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
104 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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114 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
105 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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115 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
106 | ----------------------------------------------------------------------------- |
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116 | ----------------------------------------------------------------------------- | |
107 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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117 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
108 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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118 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
109 |
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119 | |||
110 | -- CONSTANTS |
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120 | -- CONSTANTS | |
111 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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121 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
112 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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122 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
113 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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123 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
114 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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124 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
115 |
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125 | |||
116 | SIGNAL apbi_ext : apb_slv_in_type; |
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126 | SIGNAL apbi_ext : apb_slv_in_type; | |
117 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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127 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
118 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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128 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
119 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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129 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
120 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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130 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
121 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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131 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
122 |
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132 | |||
123 | -- Spacewire signals |
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133 | -- Spacewire signals | |
124 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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134 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
125 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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135 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
126 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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136 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
127 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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137 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
128 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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138 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
129 | SIGNAL spw_clk : STD_LOGIC; |
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139 | SIGNAL spw_clk : STD_LOGIC; | |
130 | SIGNAL swni : grspw_in_type; |
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140 | SIGNAL swni : grspw_in_type; | |
131 | SIGNAL swno : grspw_out_type; |
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141 | SIGNAL swno : grspw_out_type; | |
132 |
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142 | |||
133 | --GPIO |
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143 | --GPIO | |
134 | SIGNAL gpioi : gpio_in_type; |
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144 | SIGNAL gpioi : gpio_in_type; | |
135 | SIGNAL gpioo : gpio_out_type; |
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145 | SIGNAL gpioo : gpio_out_type; | |
136 |
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146 | |||
137 | -- AD Converter ADS7886 |
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147 | -- AD Converter ADS7886 | |
138 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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148 | SIGNAL sample : Samples14v(8 DOWNTO 0); | |
139 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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149 | SIGNAL sample_s : Samples(8 DOWNTO 0); | |
140 | SIGNAL sample_val : STD_LOGIC; |
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150 | SIGNAL sample_val : STD_LOGIC; | |
141 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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151 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); | |
142 |
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152 | |||
143 | ----------------------------------------------------------------------------- |
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153 | ----------------------------------------------------------------------------- | |
144 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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154 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
145 |
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155 | |||
146 | ----------------------------------------------------------------------------- |
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156 | ----------------------------------------------------------------------------- | |
147 | SIGNAL rstn_25 : STD_LOGIC; |
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157 | SIGNAL rstn_25 : STD_LOGIC; | |
148 | SIGNAL rstn_24 : STD_LOGIC; |
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158 | SIGNAL rstn_24 : STD_LOGIC; | |
149 |
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159 | |||
150 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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160 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
151 | SIGNAL LFR_rstn : STD_LOGIC; |
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161 | SIGNAL LFR_rstn : STD_LOGIC; | |
152 |
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162 | |||
153 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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163 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
154 | ---------------------------------------------------------------------------- |
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164 | ---------------------------------------------------------------------------- | |
155 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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165 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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166 | SIGNAL nSRAM_READY : STD_LOGIC; | |||
156 |
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167 | |||
157 | BEGIN -- beh |
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168 | BEGIN -- beh | |
158 |
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169 | |||
159 | ----------------------------------------------------------------------------- |
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170 | ----------------------------------------------------------------------------- | |
160 | -- CLK |
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171 | -- CLK | |
161 | ----------------------------------------------------------------------------- |
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172 | ----------------------------------------------------------------------------- | |
162 | rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); |
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173 | rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); | |
163 | rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); |
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174 | rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); | |
164 |
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175 | |||
165 | PROCESS(clk100MHz) |
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176 | PROCESS(clk100MHz) | |
166 | BEGIN |
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177 | BEGIN | |
167 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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178 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN | |
168 | clk_50_s <= NOT clk_50_s; |
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179 | clk_50_s <= NOT clk_50_s; | |
169 | END IF; |
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180 | END IF; | |
170 | END PROCESS; |
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181 | END PROCESS; | |
171 |
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182 | |||
172 | PROCESS(clk_50_s) |
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183 | PROCESS(clk_50_s) | |
173 | BEGIN |
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184 | BEGIN | |
174 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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185 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
175 | clk_25 <= NOT clk_25; |
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186 | clk_25 <= NOT clk_25; | |
176 | END IF; |
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187 | END IF; | |
177 | END PROCESS; |
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188 | END PROCESS; | |
178 |
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189 | |||
179 | PROCESS(clk49_152MHz) |
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190 | PROCESS(clk49_152MHz) | |
180 | BEGIN |
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191 | BEGIN | |
181 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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192 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN | |
182 | clk_24 <= NOT clk_24; |
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193 | clk_24 <= NOT clk_24; | |
183 | END IF; |
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194 | END IF; | |
184 | END PROCESS; |
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195 | END PROCESS; | |
185 |
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196 | |||
186 | ----------------------------------------------------------------------------- |
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197 | ----------------------------------------------------------------------------- | |
187 |
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198 | |||
188 | PROCESS (clk_25, rstn_25) |
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199 | PROCESS (clk_25, rstn_25) | |
189 | BEGIN -- PROCESS |
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200 | BEGIN -- PROCESS | |
190 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
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201 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
191 | led(0) <= '0'; |
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202 | led(0) <= '0'; | |
192 | led(1) <= '0'; |
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203 | led(1) <= '0'; | |
193 | led(2) <= '0'; |
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204 | led(2) <= '0'; | |
194 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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205 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
195 | led(0) <= '0'; |
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206 | led(0) <= '0'; | |
196 | led(1) <= '1'; |
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207 | led(1) <= '1'; | |
197 | led(2) <= '1'; |
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208 | led(2) <= '1'; | |
198 | END IF; |
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209 | END IF; | |
199 | END PROCESS; |
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210 | END PROCESS; | |
200 |
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211 | |||
201 | -- |
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212 | -- | |
202 | leon3_soc_1 : leon3_soc |
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213 | leon3_soc_1 : leon3_soc | |
203 | GENERIC MAP ( |
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214 | GENERIC MAP ( | |
204 | fabtech => apa3e, |
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215 | fabtech => apa3e, | |
205 | memtech => apa3e, |
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216 | memtech => apa3e, | |
206 | padtech => inferred, |
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217 | padtech => inferred, | |
207 | clktech => inferred, |
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218 | clktech => inferred, | |
208 | disas => 0, |
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219 | disas => 0, | |
209 | dbguart => 0, |
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220 | dbguart => 0, | |
210 | pclow => 2, |
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221 | pclow => 2, | |
211 | clk_freq => 25000, |
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222 | clk_freq => 25000, | |
212 | IS_RADHARD => 0, |
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223 | IS_RADHARD => 0, | |
213 | NB_CPU => 1, |
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224 | NB_CPU => 1, | |
214 | ENABLE_FPU => 1, |
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225 | ENABLE_FPU => 1, | |
215 | FPU_NETLIST => 0, |
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226 | FPU_NETLIST => 0, | |
216 | ENABLE_DSU => 1, |
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227 | ENABLE_DSU => 1, | |
217 | ENABLE_AHB_UART => 1, |
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228 | ENABLE_AHB_UART => 1, | |
218 | ENABLE_APB_UART => 1, |
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229 | ENABLE_APB_UART => 1, | |
219 | ENABLE_IRQMP => 1, |
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230 | ENABLE_IRQMP => 1, | |
220 | ENABLE_GPT => 1, |
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231 | ENABLE_GPT => 1, | |
221 | NB_AHB_MASTER => NB_AHB_MASTER, |
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232 | NB_AHB_MASTER => NB_AHB_MASTER, | |
222 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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233 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
223 | NB_APB_SLAVE => NB_APB_SLAVE, |
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234 | NB_APB_SLAVE => NB_APB_SLAVE, | |
224 | ADDRESS_SIZE => 20, |
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235 | ADDRESS_SIZE => 20, | |
225 |
USES_IAP_MEMCTRLR => |
|
236 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, | |
|
237 | BYPASS_EDAC_MEMCTRLR => '0', | |||
|
238 | SRBANKSZ => 8) | |||
226 | PORT MAP ( |
|
239 | PORT MAP ( | |
227 | clk => clk_25, |
|
240 | clk => clk_25, | |
228 | reset => rstn_25, |
|
241 | reset => rstn_25, | |
229 | errorn => OPEN, |
|
242 | errorn => OPEN, | |
230 |
|
243 | |||
231 | ahbrxd => TAG1, |
|
244 | ahbrxd => TAG1, | |
232 | ahbtxd => TAG3, |
|
245 | ahbtxd => TAG3, | |
233 | urxd1 => TAG2, |
|
246 | urxd1 => TAG2, | |
234 | utxd1 => TAG4, |
|
247 | utxd1 => TAG4, | |
235 |
|
248 | |||
236 | address => address, |
|
249 | address => address, | |
237 | data => data, |
|
250 | data => data, | |
238 | nSRAM_BE0 => nSRAM_BE0, |
|
251 | nSRAM_BE0 => nSRAM_BE0, | |
239 | nSRAM_BE1 => nSRAM_BE1, |
|
252 | nSRAM_BE1 => nSRAM_BE1, | |
240 | nSRAM_BE2 => nSRAM_BE2, |
|
253 | nSRAM_BE2 => nSRAM_BE2, | |
241 | nSRAM_BE3 => nSRAM_BE3, |
|
254 | nSRAM_BE3 => nSRAM_BE3, | |
242 | nSRAM_WE => nSRAM_WE, |
|
255 | nSRAM_WE => nSRAM_WE, | |
243 | nSRAM_CE => nSRAM_CE_s, |
|
256 | nSRAM_CE => nSRAM_CE_s, | |
244 | nSRAM_OE => nSRAM_OE, |
|
257 | nSRAM_OE => nSRAM_OE, | |
245 |
nSRAM_READY => |
|
258 | nSRAM_READY => nSRAM_READY, | |
246 | SRAM_MBE => OPEN, |
|
259 | SRAM_MBE => OPEN, | |
247 |
|
260 | |||
248 | apbi_ext => apbi_ext, |
|
261 | apbi_ext => apbi_ext, | |
249 | apbo_ext => apbo_ext, |
|
262 | apbo_ext => apbo_ext, | |
250 | ahbi_s_ext => ahbi_s_ext, |
|
263 | ahbi_s_ext => ahbi_s_ext, | |
251 | ahbo_s_ext => ahbo_s_ext, |
|
264 | ahbo_s_ext => ahbo_s_ext, | |
252 | ahbi_m_ext => ahbi_m_ext, |
|
265 | ahbi_m_ext => ahbi_m_ext, | |
253 | ahbo_m_ext => ahbo_m_ext); |
|
266 | ahbo_m_ext => ahbo_m_ext); | |
254 |
|
267 | |||
|
268 | PROCESS (clk_25, rstn_25) | |||
|
269 | BEGIN -- PROCESS | |||
|
270 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |||
|
271 | nSRAM_READY <= '1'; | |||
|
272 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |||
|
273 | nSRAM_READY <= '1'; | |||
|
274 | IF TAG8 = '1' THEN | |||
|
275 | nSRAM_READY <= '0'; | |||
|
276 | END IF; | |||
|
277 | END IF; | |||
|
278 | END PROCESS; | |||
255 |
|
279 | |||
256 | nSRAM_CE <= nSRAM_CE_s(0); |
|
280 | IAP:if USE_IAP_MEMCTRL = 1 GENERATE | |
|
281 | nSRAM_CE <= not nSRAM_CE_s(0); | |||
|
282 | END GENERATE; | |||
|
283 | ||||
|
284 | NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE | |||
|
285 | nSRAM_CE <= nSRAM_CE_s(0); | |||
|
286 | END GENERATE; | |||
257 |
|
287 | |||
258 | ------------------------------------------------------------------------------- |
|
288 | ------------------------------------------------------------------------------- | |
259 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
289 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
260 | ------------------------------------------------------------------------------- |
|
290 | ------------------------------------------------------------------------------- | |
261 | apb_lfr_management_1 : apb_lfr_management |
|
291 | apb_lfr_management_1 : apb_lfr_management | |
262 | GENERIC MAP ( |
|
292 | GENERIC MAP ( | |
263 | tech => apa3e, |
|
293 | tech => apa3e, | |
264 | pindex => 6, |
|
294 | pindex => 6, | |
265 | paddr => 6, |
|
295 | paddr => 6, | |
266 | pmask => 16#fff#, |
|
296 | pmask => 16#fff#, | |
267 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
297 | -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
268 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
298 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
269 | PORT MAP ( |
|
299 | PORT MAP ( | |
270 | clk25MHz => clk_25, |
|
300 | clk25MHz => clk_25, | |
271 | resetn_25MHz => rstn_25, -- TODO |
|
301 | resetn_25MHz => rstn_25, -- TODO | |
272 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
302 | -- clk24_576MHz => clk_24, -- 49.152MHz/2 | |
273 | resetn_24_576MHz => rstn_24, -- TODO |
|
303 | -- resetn_24_576MHz => rstn_24, -- TODO | |
274 |
|
304 | |||
275 | grspw_tick => swno.tickout, |
|
305 | grspw_tick => swno.tickout, | |
276 | apbi => apbi_ext, |
|
306 | apbi => apbi_ext, | |
277 | apbo => apbo_ext(6), |
|
307 | apbo => apbo_ext(6), | |
278 |
|
308 | |||
279 | HK_sample => sample_s(8), |
|
309 | HK_sample => sample_s(8), | |
280 | HK_val => sample_val, |
|
310 | HK_val => sample_val, | |
281 | HK_sel => HK_SEL, |
|
311 | HK_sel => HK_SEL, | |
282 |
|
312 | |||
283 | DAC_SDO => DAC_SDO, |
|
313 | DAC_SDO => DAC_SDO, | |
284 | DAC_SCK => DAC_SCK, |
|
314 | DAC_SCK => DAC_SCK, | |
285 | DAC_SYNC => DAC_SYNC, |
|
315 | DAC_SYNC => DAC_SYNC, | |
286 | DAC_CAL_EN => DAC_CAL_EN, |
|
316 | DAC_CAL_EN => DAC_CAL_EN, | |
287 |
|
317 | |||
288 | coarse_time => coarse_time, |
|
318 | coarse_time => coarse_time, | |
289 | fine_time => fine_time, |
|
319 | fine_time => fine_time, | |
290 | LFR_soft_rstn => LFR_soft_rstn |
|
320 | LFR_soft_rstn => LFR_soft_rstn | |
291 | ); |
|
321 | ); | |
292 |
|
322 | |||
293 | ----------------------------------------------------------------------- |
|
323 | ----------------------------------------------------------------------- | |
294 | --- SpaceWire -------------------------------------------------------- |
|
324 | --- SpaceWire -------------------------------------------------------- | |
295 | ----------------------------------------------------------------------- |
|
325 | ----------------------------------------------------------------------- | |
296 |
|
326 | |||
297 | -- SPW_EN <= '1'; |
|
327 | -- SPW_EN <= '1'; | |
298 |
|
328 | |||
299 | spw_clk <= clk_50_s; |
|
329 | spw_clk <= clk_50_s; | |
300 | spw_rxtxclk <= spw_clk; |
|
330 | spw_rxtxclk <= spw_clk; | |
301 | spw_rxclkn <= NOT spw_rxtxclk; |
|
331 | spw_rxclkn <= NOT spw_rxtxclk; | |
302 |
|
332 | |||
303 | -- PADS for SPW1 |
|
333 | -- PADS for SPW1 | |
304 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
334 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
305 | PORT MAP (spw1_din, dtmp(0)); |
|
335 | PORT MAP (spw1_din, dtmp(0)); | |
306 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
336 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
307 | PORT MAP (spw1_sin, stmp(0)); |
|
337 | PORT MAP (spw1_sin, stmp(0)); | |
308 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
338 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
309 | PORT MAP (spw1_dout, swno.d(0)); |
|
339 | PORT MAP (spw1_dout, swno.d(0)); | |
310 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
340 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
311 | PORT MAP (spw1_sout, swno.s(0)); |
|
341 | PORT MAP (spw1_sout, swno.s(0)); | |
312 | -- PADS FOR SPW2 |
|
342 | -- PADS FOR SPW2 | |
313 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
343 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
314 | PORT MAP (spw2_din, dtmp(1)); |
|
344 | PORT MAP (spw2_din, dtmp(1)); | |
315 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
345 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
316 | PORT MAP (spw2_sin, stmp(1)); |
|
346 | PORT MAP (spw2_sin, stmp(1)); | |
317 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
347 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
318 | PORT MAP (spw2_dout, swno.d(1)); |
|
348 | PORT MAP (spw2_dout, swno.d(1)); | |
319 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
349 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
320 | PORT MAP (spw2_sout, swno.s(1)); |
|
350 | PORT MAP (spw2_sout, swno.s(1)); | |
321 |
|
351 | |||
322 | -- GRSPW PHY |
|
352 | -- GRSPW PHY | |
323 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
353 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
324 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
354 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
325 | spw_phy0 : grspw_phy |
|
355 | spw_phy0 : grspw_phy | |
326 | GENERIC MAP( |
|
356 | GENERIC MAP( | |
327 | tech => apa3e, |
|
357 | tech => apa3e, | |
328 | rxclkbuftype => 1, |
|
358 | rxclkbuftype => 1, | |
329 | scantest => 0) |
|
359 | scantest => 0) | |
330 | PORT MAP( |
|
360 | PORT MAP( | |
331 | rxrst => swno.rxrst, |
|
361 | rxrst => swno.rxrst, | |
332 | di => dtmp(j), |
|
362 | di => dtmp(j), | |
333 | si => stmp(j), |
|
363 | si => stmp(j), | |
334 | rxclko => spw_rxclk(j), |
|
364 | rxclko => spw_rxclk(j), | |
335 | do => swni.d(j), |
|
365 | do => swni.d(j), | |
336 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
366 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
337 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
367 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
338 | END GENERATE spw_inputloop; |
|
368 | END GENERATE spw_inputloop; | |
339 |
|
369 | |||
340 | -- SPW core |
|
370 | -- SPW core | |
341 | sw0 : grspwm GENERIC MAP( |
|
371 | sw0 : grspwm GENERIC MAP( | |
342 | tech => apa3e, |
|
372 | tech => apa3e, | |
343 | hindex => 1, |
|
373 | hindex => 1, | |
344 | pindex => 5, |
|
374 | pindex => 5, | |
345 | paddr => 5, |
|
375 | paddr => 5, | |
346 | pirq => 11, |
|
376 | pirq => 11, | |
347 | sysfreq => 25000, -- CPU_FREQ |
|
377 | sysfreq => 25000, -- CPU_FREQ | |
348 | rmap => 1, |
|
378 | rmap => 1, | |
349 | rmapcrc => 1, |
|
379 | rmapcrc => 1, | |
350 | fifosize1 => 16, |
|
380 | fifosize1 => 16, | |
351 | fifosize2 => 16, |
|
381 | fifosize2 => 16, | |
352 | rxclkbuftype => 1, |
|
382 | rxclkbuftype => 1, | |
353 | rxunaligned => 0, |
|
383 | rxunaligned => 0, | |
354 | rmapbufs => 4, |
|
384 | rmapbufs => 4, | |
355 | ft => 0, |
|
385 | ft => 0, | |
356 | netlist => 0, |
|
386 | netlist => 0, | |
357 | ports => 2, |
|
387 | ports => 2, | |
358 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
388 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
359 | memtech => apa3e, |
|
389 | memtech => apa3e, | |
360 | destkey => 2, |
|
390 | destkey => 2, | |
361 | spwcore => 1 |
|
391 | spwcore => 1 | |
362 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
392 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
363 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
393 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
364 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
394 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
365 | ) |
|
395 | ) | |
366 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
396 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
367 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
397 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
368 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
398 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
369 | swni, swno); |
|
399 | swni, swno); | |
370 |
|
400 | |||
371 | swni.tickin <= '0'; |
|
401 | swni.tickin <= '0'; | |
372 | swni.rmapen <= '1'; |
|
402 | swni.rmapen <= '1'; | |
373 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
403 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
374 | swni.tickinraw <= '0'; |
|
404 | swni.tickinraw <= '0'; | |
375 | swni.timein <= (OTHERS => '0'); |
|
405 | swni.timein <= (OTHERS => '0'); | |
376 | swni.dcrstval <= (OTHERS => '0'); |
|
406 | swni.dcrstval <= (OTHERS => '0'); | |
377 | swni.timerrstval <= (OTHERS => '0'); |
|
407 | swni.timerrstval <= (OTHERS => '0'); | |
378 |
|
408 | |||
379 | ------------------------------------------------------------------------------- |
|
409 | ------------------------------------------------------------------------------- | |
380 | -- LFR ------------------------------------------------------------------------ |
|
410 | -- LFR ------------------------------------------------------------------------ | |
381 | ------------------------------------------------------------------------------- |
|
411 | ------------------------------------------------------------------------------- | |
382 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
412 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
383 |
|
413 | |||
384 | lpp_lfr_1 : lpp_lfr |
|
414 | lpp_lfr_1 : lpp_lfr | |
385 | GENERIC MAP ( |
|
415 | GENERIC MAP ( | |
386 | Mem_use => use_RAM, |
|
416 | Mem_use => use_RAM, | |
|
417 | tech => inferred, | |||
387 | nb_data_by_buffer_size => 32, |
|
418 | nb_data_by_buffer_size => 32, | |
388 | --nb_word_by_buffer_size => 30, |
|
419 | --nb_word_by_buffer_size => 30, | |
389 | nb_snapshot_param_size => 32, |
|
420 | nb_snapshot_param_size => 32, | |
390 | delta_vector_size => 32, |
|
421 | delta_vector_size => 32, | |
391 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | delta_vector_size_f0_2 => 7, -- log2(96) | |
392 | pindex => 15, |
|
423 | pindex => 15, | |
393 | paddr => 15, |
|
424 | paddr => 15, | |
394 | pmask => 16#fff#, |
|
425 | pmask => 16#fff#, | |
395 | pirq_ms => 6, |
|
426 | pirq_ms => 6, | |
396 | pirq_wfp => 14, |
|
427 | pirq_wfp => 14, | |
397 | hindex => 2, |
|
428 | hindex => 2, | |
398 |
top_lfr_version => X"0101 |
|
429 | top_lfr_version => X"010153") -- aa.bb.cc version | |
399 | -- AA : BOARD NUMBER |
|
430 | -- AA : BOARD NUMBER | |
400 | -- 0 => MINI_LFR |
|
431 | -- 0 => MINI_LFR | |
401 | -- 1 => EM |
|
432 | -- 1 => EM | |
402 | PORT MAP ( |
|
433 | PORT MAP ( | |
403 | clk => clk_25, |
|
434 | clk => clk_25, | |
404 | rstn => LFR_rstn, |
|
435 | rstn => LFR_rstn, | |
405 | sample_B => sample_s(2 DOWNTO 0), |
|
436 | sample_B => sample_s(2 DOWNTO 0), | |
406 | sample_E => sample_s(7 DOWNTO 3), |
|
437 | sample_E => sample_s(7 DOWNTO 3), | |
407 | sample_val => sample_val, |
|
438 | sample_val => sample_val, | |
408 | apbi => apbi_ext, |
|
439 | apbi => apbi_ext, | |
409 | apbo => apbo_ext(15), |
|
440 | apbo => apbo_ext(15), | |
410 | ahbi => ahbi_m_ext, |
|
441 | ahbi => ahbi_m_ext, | |
411 | ahbo => ahbo_m_ext(2), |
|
442 | ahbo => ahbo_m_ext(2), | |
412 | coarse_time => coarse_time, |
|
443 | coarse_time => coarse_time, | |
413 | fine_time => fine_time, |
|
444 | fine_time => fine_time, | |
414 | data_shaping_BW => bias_fail_sw, |
|
445 | data_shaping_BW => bias_fail_sw, | |
415 | debug_vector => OPEN, |
|
446 | debug_vector => OPEN, | |
416 | debug_vector_ms => OPEN); --, |
|
447 | debug_vector_ms => OPEN); --, | |
417 | --observation_vector_0 => OPEN, |
|
448 | --observation_vector_0 => OPEN, | |
418 | --observation_vector_1 => OPEN, |
|
449 | --observation_vector_1 => OPEN, | |
419 | --observation_reg => observation_reg); |
|
450 | --observation_reg => observation_reg); | |
420 |
|
451 | |||
421 |
|
452 | |||
422 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
453 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
423 | sample_s(I) <= sample(I) & '0' & '0'; |
|
454 | sample_s(I) <= sample(I) & '0' & '0'; | |
424 | END GENERATE all_sample; |
|
455 | END GENERATE all_sample; | |
425 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
456 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); | |
426 |
|
457 | |||
427 | ----------------------------------------------------------------------------- |
|
458 | ----------------------------------------------------------------------------- | |
428 | -- |
|
459 | -- | |
429 | ----------------------------------------------------------------------------- |
|
460 | ----------------------------------------------------------------------------- | |
430 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
461 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
431 | GENERIC MAP ( |
|
462 | GENERIC MAP ( | |
432 | ChanelCount => 9, |
|
463 | ChanelCount => 9, | |
433 |
ncycle_cnv_high => 1 |
|
464 | ncycle_cnv_high => 12, | |
434 | ncycle_cnv => 25, |
|
465 | ncycle_cnv => 25, | |
435 | FILTER_ENABLED => 16#FF#) |
|
466 | FILTER_ENABLED => 16#FF#) | |
436 | PORT MAP ( |
|
467 | PORT MAP ( | |
437 | cnv_clk => clk_24, |
|
468 | cnv_clk => clk_24, | |
438 | cnv_rstn => rstn_24, |
|
469 | cnv_rstn => rstn_24, | |
439 | cnv => ADC_smpclk_s, |
|
470 | cnv => ADC_smpclk_s, | |
440 | clk => clk_25, |
|
471 | clk => clk_25, | |
441 | rstn => rstn_25, |
|
472 | rstn => rstn_25, | |
442 | ADC_data => ADC_data, |
|
473 | ADC_data => ADC_data, | |
443 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
474 | ADC_nOE => ADC_OEB_bar_CH_s, | |
444 | sample => sample, |
|
475 | sample => sample, | |
445 | sample_val => sample_val); |
|
476 | sample_val => sample_val); | |
446 |
|
477 | |||
447 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
478 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); | |
448 |
|
479 | |||
449 | ADC_smpclk <= ADC_smpclk_s; |
|
480 | ADC_smpclk <= ADC_smpclk_s; | |
450 | HK_smpclk <= ADC_smpclk_s; |
|
481 | HK_smpclk <= ADC_smpclk_s; | |
451 |
|
482 | |||
452 | TAG8 <= ADC_smpclk_s; |
|
483 | -- TAG8 <= ADC_smpclk_s; | |
453 |
|
484 | |||
454 | ----------------------------------------------------------------------------- |
|
485 | ----------------------------------------------------------------------------- | |
455 | -- HK |
|
486 | -- HK | |
456 | ----------------------------------------------------------------------------- |
|
487 | ----------------------------------------------------------------------------- | |
457 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
488 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); | |
458 |
|
489 | |||
459 |
END beh; |
|
490 | END beh; No newline at end of file |
@@ -1,153 +1,118 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 |
|
23 | |||
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
26 | USE ieee.numeric_std.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
27 |
|
27 | |||
28 | LIBRARY lpp; |
|
28 | LIBRARY lpp; | |
29 | USE lpp.general_purpose.ALL; |
|
29 | USE lpp.general_purpose.ALL; | |
30 | USE lpp.window_function_pkg.ALL; |
|
30 | USE lpp.window_function_pkg.ALL; | |
|
31 | USE lpp.data_type_pkg.ALL; | |||
31 |
|
32 | |||
32 | ENTITY window_function IS |
|
33 | ENTITY window_function IS | |
33 | GENERIC ( |
|
34 | GENERIC ( | |
34 | DATA_SIZE : INTEGER := 16; |
|
35 | DATA_SIZE : INTEGER := 16; | |
35 | PARAM_SIZE : INTEGER := 10 |
|
36 | PARAM_SIZE : INTEGER := 10; | |
|
37 | WINDOWS_PARAM : array_std_logic_vector_16b(0 TO 255) | |||
36 | ); |
|
38 | ); | |
37 |
|
39 | |||
38 | PORT ( |
|
40 | PORT ( | |
39 | clk : IN STD_LOGIC; |
|
41 | clk : IN STD_LOGIC; | |
40 | rstn : IN STD_LOGIC; |
|
42 | rstn : IN STD_LOGIC; | |
41 |
|
43 | |||
42 | restart_window : IN STD_LOGIC; |
|
44 | restart_window : IN STD_LOGIC; | |
43 |
|
45 | |||
44 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
46 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
45 | data_in_valid : IN STD_LOGIC; |
|
47 | data_in_valid : IN STD_LOGIC; | |
46 |
|
48 | |||
47 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
49 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
48 | data_out_valid : OUT STD_LOGIC |
|
50 | data_out_valid : OUT STD_LOGIC | |
49 | ); |
|
51 | ); | |
50 |
|
52 | |||
51 | END window_function; |
|
53 | END window_function; | |
52 |
|
54 | |||
53 | ARCHITECTURE beh OF window_function IS |
|
55 | ARCHITECTURE beh OF window_function IS | |
54 |
|
||||
55 | SUBTYPE RANGE_NB_BIT_BY_WINDOW_PARAM IS INTEGER RANGE 1 TO DATA_SIZE; |
|
|||
56 | CONSTANT NB_BIT_BY_WINDOW_PARAM : RANGE_NB_BIT_BY_WINDOW_PARAM := 16; |
|
|||
57 | CONSTANT NB_POINT_BY_WINDOW : INTEGER := 256; |
|
56 | CONSTANT NB_POINT_BY_WINDOW : INTEGER := 256; | |
58 |
|
57 | |||
59 | TYPE WINDOWS_PARAM_TYPE IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|||
60 | CONSTANT windows_param_lfr_sigmoide : WINDOWS_PARAM_TYPE(0 TO 32) := |
|
|||
61 | ( X"0000",X"0012",X"002E",X"005B", X"00A2",X"0113",X"01C7",X"02E0", --0 - 7 |
|
|||
62 | X"0498",X"073A",X"0B37",X"110D", X"193C",X"240F",X"3147",X"3FF7", --8 - 15 |
|
|||
63 | X"4EA7",X"5BDF",X"66B2",X"6EE1", X"74B7",X"78B4",X"7B56",X"7D0E", --16 - 23 |
|
|||
64 | X"7E27",X"7EDB",X"7F4C",X"7F93", X"7FC0",X"7FDC",X"7FEE",X"7FF9", --24 - 31 |
|
|||
65 | X"7FFF" ); --32 |
|
|||
66 | CONSTANT windows_param_lfr_rampe : WINDOWS_PARAM_TYPE(0 TO 32) := |
|
|||
67 | ( X"0000",X"03E1",X"07C2",X"0BA3", X"0F84",X"1365",X"1746",X"1B27", |
|
|||
68 | X"1F08",X"22E8",X"26C9",X"2AAA", X"2E8B",X"326C",X"364D",X"3A2E", |
|
|||
69 | X"3E0F",X"41F0",X"45D1",X"49B2", X"4D93",X"5174",X"5555",X"5936", |
|
|||
70 | X"5D17",X"60F7",X"64D8",X"68B9", X"6C9A",X"707B",X"745C",X"783D", |
|
|||
71 | X"7FFF" ); |
|
|||
72 | CONSTANT windows_param_lfr_echelon : WINDOWS_PARAM_TYPE(0 TO 32) := |
|
|||
73 | ( X"0000",X"0000",X"0000",X"0000", X"0000",X"0000",X"0000",X"0000", |
|
|||
74 | X"0000",X"0000",X"0000",X"0000", X"0000",X"0000",X"0000",X"0000", |
|
|||
75 | X"FFFF",X"FFFF",X"FFFF",X"FFFF", X"FFFF",X"FFFF",X"FFFF",X"FFFF", |
|
|||
76 | X"FFFF",X"FFFF",X"FFFF",X"FFFF", X"FFFF",X"FFFF",X"FFFF",X"FFFF", |
|
|||
77 | X"FFFF"); |
|
|||
78 |
|
||||
79 | CONSTANT windows_param_lfr : WINDOWS_PARAM_TYPE(0 TO 32) := windows_param_lfr_sigmoide; |
|
|||
80 |
|
||||
81 | SIGNAL windows_param : WINDOWS_PARAM_TYPE(0 TO NB_POINT_BY_WINDOW-1); |
|
|||
82 |
|
||||
83 | SIGNAL param_counter : INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1; |
|
58 | SIGNAL param_counter : INTEGER RANGE 0 TO NB_POINT_BY_WINDOW-1; | |
84 |
|
59 | |||
85 | SIGNAL data_x_param : STD_LOGIC_VECTOR(DATA_SIZE + PARAM_SIZE - 1 DOWNTO 0); |
|
60 | SIGNAL data_x_param : STD_LOGIC_VECTOR(DATA_SIZE + PARAM_SIZE - 1 DOWNTO 0); | |
86 |
|
61 | |||
87 | SIGNAL windows_param_selected_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
62 | SIGNAL windows_param_selected_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
88 | SIGNAL windows_param_selected : STD_LOGIC_VECTOR(PARAM_SIZE-1 DOWNTO 0); |
|
63 | SIGNAL windows_param_selected : STD_LOGIC_VECTOR(PARAM_SIZE-1 DOWNTO 0); | |
89 | SIGNAL data_in_valid_s : STD_LOGIC; |
|
64 | SIGNAL data_in_valid_s : STD_LOGIC; | |
90 | SIGNAL data_in_s : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
65 | SIGNAL data_in_s : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
91 |
|
66 | |||
92 | BEGIN |
|
67 | BEGIN | |
93 |
|
||||
94 | all_windows_param_0: FOR I IN 0 TO 31 GENERATE |
|
|||
95 | windows_param(I) <= windows_param_lfr(I); |
|
|||
96 | END GENERATE all_windows_param_0; |
|
|||
97 | all_windows_param_1: FOR I IN 32 TO 223 GENERATE |
|
|||
98 | windows_param(I) <= windows_param_lfr(32); |
|
|||
99 | END GENERATE all_windows_param_1; |
|
|||
100 | all_windows_param_2: FOR I IN 224 TO 255 GENERATE |
|
|||
101 | windows_param(I) <= windows_param_lfr(255-I); |
|
|||
102 | END GENERATE all_windows_param_2; |
|
|||
103 |
|
68 | |||
104 | PROCESS (clk, rstn) |
|
69 | PROCESS (clk, rstn) | |
105 | BEGIN -- PROCESS |
|
70 | BEGIN -- PROCESS | |
106 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
71 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
107 | param_counter <= 0; |
|
72 | param_counter <= 0; | |
108 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
73 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
109 | IF restart_window = '1' THEN |
|
74 | IF restart_window = '1' THEN | |
110 | param_counter <= 0; |
|
75 | param_counter <= 0; | |
111 | ELSE |
|
76 | ELSE | |
112 | IF data_in_valid = '1' THEN |
|
77 | IF data_in_valid = '1' THEN | |
113 | IF param_counter < 255 THEN |
|
78 | IF param_counter < 255 THEN | |
114 | param_counter <= param_counter + 1; |
|
79 | param_counter <= param_counter + 1; | |
115 | ELSE |
|
80 | ELSE | |
116 | param_counter <= 0; |
|
81 | param_counter <= 0; | |
117 | END IF; |
|
82 | END IF; | |
118 | END IF; |
|
83 | END IF; | |
119 | END IF; |
|
84 | END IF; | |
120 | END IF; |
|
85 | END IF; | |
121 | END PROCESS; |
|
86 | END PROCESS; | |
122 |
|
87 | |||
123 | data_in_valid_s <= data_in_valid; |
|
88 | data_in_valid_s <= data_in_valid; | |
124 | data_in_s <= data_in; |
|
89 | data_in_s <= data_in; | |
125 |
windows_param_selected_s <= |
|
90 | windows_param_selected_s <= WINDOWS_PARAM(param_counter); | |
126 | windows_param_selected <= windows_param_selected_s(15 DOWNTO 16 - PARAM_SIZE); |
|
91 | windows_param_selected <= windows_param_selected_s(15 DOWNTO 16 - PARAM_SIZE); | |
127 |
|
92 | |||
128 | WINDOWS_Multiplier : Multiplier |
|
93 | WINDOWS_Multiplier : Multiplier | |
129 | GENERIC MAP ( |
|
94 | GENERIC MAP ( | |
130 | Input_SZ_A => DATA_SIZE, |
|
95 | Input_SZ_A => DATA_SIZE, | |
131 | Input_SZ_B => PARAM_SIZE) |
|
96 | Input_SZ_B => PARAM_SIZE) | |
132 | PORT MAP ( |
|
97 | PORT MAP ( | |
133 | clk => clk, |
|
98 | clk => clk, | |
134 | reset => rstn, |
|
99 | reset => rstn, | |
135 |
|
100 | |||
136 | mult => data_in_valid_s, |
|
101 | mult => data_in_valid_s, | |
137 | OP1 => data_in_s, |
|
102 | OP1 => data_in_s, | |
138 | OP2 => windows_param_selected, |
|
103 | OP2 => windows_param_selected, | |
139 |
|
104 | |||
140 | RES => data_x_param); |
|
105 | RES => data_x_param); | |
141 |
|
106 | |||
142 | data_out <= data_x_param(DATA_SIZE + PARAM_SIZE-1 DOWNTO PARAM_SIZE); |
|
107 | data_out <= data_x_param(DATA_SIZE + PARAM_SIZE-1 DOWNTO PARAM_SIZE); | |
143 |
|
108 | |||
144 | PROCESS (clk, rstn) |
|
109 | PROCESS (clk, rstn) | |
145 | BEGIN -- PROCESS |
|
110 | BEGIN -- PROCESS | |
146 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
111 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
147 | data_out_valid <= '0'; |
|
112 | data_out_valid <= '0'; | |
148 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
113 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
149 | data_out_valid <= data_in_valid_s; |
|
114 | data_out_valid <= data_in_valid_s; | |
150 | END IF; |
|
115 | END IF; | |
151 | END PROCESS; |
|
116 | END PROCESS; | |
152 |
|
117 | |||
153 | END beh; No newline at end of file |
|
118 | END beh; |
@@ -1,44 +1,49 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
|
22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
|
23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
|
24 | USE ieee.std_logic_1164.ALL; | |
25 | USE IEEE.NUMERIC_STD.ALL; |
|
25 | USE IEEE.NUMERIC_STD.ALL; | |
26 |
|
26 | |||
|
27 | LIBRARY lpp; | |||
|
28 | USE lpp.data_type_pkg.ALL; | |||
|
29 | ||||
27 | PACKAGE window_function_pkg IS |
|
30 | PACKAGE window_function_pkg IS | |
28 |
|
31 | |||
29 | COMPONENT window_function |
|
32 | COMPONENT window_function | |
30 | GENERIC ( |
|
33 | GENERIC ( | |
31 | DATA_SIZE : INTEGER; |
|
34 | DATA_SIZE : INTEGER; | |
32 |
PARAM_SIZE : INTEGER |
|
35 | PARAM_SIZE : INTEGER; | |
|
36 | WINDOWS_PARAM : array_std_logic_vector_16b(0 TO 255) | |||
|
37 | ); | |||
33 | PORT ( |
|
38 | PORT ( | |
34 | clk : IN STD_LOGIC; |
|
39 | clk : IN STD_LOGIC; | |
35 | rstn : IN STD_LOGIC; |
|
40 | rstn : IN STD_LOGIC; | |
36 | restart_window : IN STD_LOGIC; |
|
41 | restart_window : IN STD_LOGIC; | |
37 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
42 | data_in : IN STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
38 | data_in_valid : IN STD_LOGIC; |
|
43 | data_in_valid : IN STD_LOGIC; | |
39 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); |
|
44 | data_out : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |
40 | data_out_valid : OUT STD_LOGIC); |
|
45 | data_out_valid : OUT STD_LOGIC); | |
41 | END COMPONENT; |
|
46 | END COMPONENT; | |
42 |
|
47 | |||
43 |
|
48 | |||
44 | END window_function_pkg; |
|
49 | END window_function_pkg; |
@@ -1,35 +1,55 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
|
22 | ------------------------------------------------------------------------------- | |
23 |
|
23 | |||
24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | USE ieee.numeric_std.ALL; | |||
26 |
|
27 | |||
27 | PACKAGE data_type_pkg IS |
|
28 | PACKAGE data_type_pkg IS | |
28 |
|
29 | |||
29 | TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
|
30 | TYPE array_integer IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
30 | TYPE array_real IS ARRAY (NATURAL RANGE <>) OF REAL; |
|
31 | TYPE array_real IS ARRAY (NATURAL RANGE <>) OF REAL; | |
31 | TYPE array_std_logic_vector_16b IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
32 | TYPE array_std_logic_vector_16b IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
32 |
|
33 | |||
33 | TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
34 | TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
|
35 | ||||
|
36 | FUNCTION to_array_std_logic_vector_16b ( | |||
|
37 | array_in : array_real) | |||
|
38 | RETURN array_std_logic_vector_16b; | |||
34 |
|
39 | |||
35 | END data_type_pkg; |
|
40 | END data_type_pkg; | |
|
41 | ||||
|
42 | PACKAGE BODY data_type_pkg IS | |||
|
43 | ||||
|
44 | FUNCTION to_array_std_logic_vector_16b ( | |||
|
45 | array_in : array_real) | |||
|
46 | RETURN array_std_logic_vector_16b IS | |||
|
47 | VARIABLE array_out : array_std_logic_vector_16b(array_in'RANGE); | |||
|
48 | BEGIN | |||
|
49 | all_value: FOR I IN array_in'RANGE LOOP | |||
|
50 | array_out(I) := STD_LOGIC_VECTOR(to_signed(INTEGER(array_in(I) * 2.0**15),16)); | |||
|
51 | END LOOP all_value; | |||
|
52 | RETURN array_out; | |||
|
53 | END to_array_std_logic_vector_16b; | |||
|
54 | ||||
|
55 | END data_type_pkg; |
@@ -1,115 +1,116 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
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21 | -- jean-christophe.pellion@easii-ic.com | |
22 | ---------------------------------------------------------------------------- |
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22 | ---------------------------------------------------------------------------- | |
23 | LIBRARY ieee; |
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23 | LIBRARY ieee; | |
24 | USE ieee.std_logic_1164.ALL; |
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24 | USE ieee.std_logic_1164.ALL; | |
25 | USE ieee.numeric_std.ALL; |
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25 | USE ieee.numeric_std.ALL; | |
26 | USE ieee.math_real.ALL; |
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26 | USE ieee.math_real.ALL; | |
27 |
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27 | |||
28 | LIBRARY std; |
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28 | LIBRARY std; | |
29 | USE std.textio.ALL; |
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29 | USE std.textio.ALL; | |
30 |
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30 | |||
31 | LIBRARY lpp; |
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31 | LIBRARY lpp; | |
32 | USE lpp.data_type_pkg.ALL; |
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32 | USE lpp.data_type_pkg.ALL; | |
33 |
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33 | |||
34 | PACKAGE reader_pkg IS |
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34 | PACKAGE reader_pkg IS | |
35 |
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35 | |||
36 | CONSTANT CHARACTER_COMMENT : CHARACTER := '#'; |
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36 | CONSTANT CHARACTER_COMMENT : CHARACTER := '#'; | |
37 |
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37 | |||
38 | FUNCTION get_array_real ( |
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38 | IMPURE FUNCTION get_array_real ( | |
39 |
file_ |
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39 | file_name : STRING; | |
40 | nb_data_read : INTEGER) |
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40 | nb_data_to_read : INTEGER) | |
41 | RETURN array_real; |
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41 | RETURN array_real; | |
42 |
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42 | |||
43 | FUNCTION get_array_integer ( |
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43 | IMPURE FUNCTION get_array_integer ( | |
44 |
file_ |
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44 | file_name : STRING; | |
45 | nb_data_read : INTEGER) |
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45 | nb_data_to_read : INTEGER) | |
46 | RETURN array_integer; |
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46 | RETURN array_integer; | |
47 |
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47 | |||
48 |
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48 | |||
49 | END reader_pkg; |
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49 | END reader_pkg; | |
50 |
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50 | |||
51 | PACKAGE BODY reader_pkg IS |
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51 | PACKAGE BODY reader_pkg IS | |
52 |
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52 | |||
53 | FUNCTION get_array_real ( |
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53 | IMPURE FUNCTION get_array_real ( | |
54 | file_name : STRING; |
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54 | file_name : STRING; | |
55 | nb_data_to_read : INTEGER) |
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55 | nb_data_to_read : INTEGER) | |
56 | RETURN array_real |
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56 | RETURN array_real | |
57 | IS |
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57 | IS | |
58 | VARIABLE GOOD : BOOLEAN; |
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58 | ||
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59 | VARIABLE GOOD : BOOLEAN; | |||
59 | VARIABLE array_real_v : array_real(0 TO nb_data_to_read-1); |
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60 | VARIABLE array_real_v : array_real(0 TO nb_data_to_read-1); | |
60 | VARIABLE real_p : REAL; |
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61 | VARIABLE real_p : REAL; | |
61 | VARIABLE nb_data_read : INTEGER := 0; |
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62 | VARIABLE nb_data_read : INTEGER := 0; | |
62 | FILE file_p : TEXT; |
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63 | FILE file_p : TEXT; | |
63 | VARIABLE line_p : LINE; |
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64 | VARIABLE line_p : LINE; | |
64 | BEGIN |
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65 | BEGIN | |
65 | GOOD := false; |
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66 | GOOD := false; | |
66 | file_open(file_p, file_name, read_mode); |
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67 | file_open(file_p, file_name, read_mode); | |
67 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP |
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68 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP | |
68 | readline(file_p, line_p); |
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69 | readline(file_p, line_p); | |
69 | read(line_p, real_p, GOOD); |
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70 | read(line_p, real_p, GOOD); | |
70 | IF GOOD THEN |
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71 | IF GOOD THEN | |
71 | array_real_v(nb_data_read) := real_p; |
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72 | array_real_v(nb_data_read) := real_p; | |
72 | nb_data_read := nb_data_read + 1; |
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73 | nb_data_read := nb_data_read + 1; | |
73 | END IF; |
|
74 | END IF; | |
74 | END LOOP; |
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75 | END LOOP; | |
75 | IF nb_data_read < nb_data_to_read THEN |
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76 | IF nb_data_read < nb_data_to_read THEN | |
76 | GOOD := false; |
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77 | GOOD := false; | |
77 | ELSE |
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78 | ELSE | |
78 | GOOD := true; |
|
79 | GOOD := true; | |
79 | END IF; |
|
80 | END IF; | |
80 | RETURN array_real_v; |
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81 | RETURN array_real_v; | |
81 | END get_array_real; |
|
82 | END get_array_real; | |
82 |
|
83 | |||
83 | FUNCTION get_array_integer ( |
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84 | IMPURE FUNCTION get_array_integer ( | |
84 | file_name : STRING; |
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85 | file_name : STRING; | |
85 | nb_data_to_read : INTEGER) |
|
86 | nb_data_to_read : INTEGER) | |
86 | RETURN array_integer |
|
87 | RETURN array_integer | |
87 | IS |
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88 | IS | |
88 | VARIABLE GOOD : BOOLEAN; |
|
89 | VARIABLE GOOD : BOOLEAN; | |
89 | VARIABLE array_integer_v : array_integer(0 TO nb_data_to_read-1); |
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90 | VARIABLE array_integer_v : array_integer(0 TO nb_data_to_read-1); | |
90 | VARIABLE integer_p : INTEGER; |
|
91 | VARIABLE integer_p : INTEGER; | |
91 | VARIABLE nb_data_read : INTEGER := 0; |
|
92 | VARIABLE nb_data_read : INTEGER := 0; | |
92 | FILE file_p : TEXT; |
|
93 | FILE file_p : TEXT; | |
93 | VARIABLE line_p : LINE; |
|
94 | VARIABLE line_p : LINE; | |
94 | BEGIN |
|
95 | BEGIN | |
95 | GOOD := false; |
|
96 | GOOD := false; | |
96 | file_open(file_p, file_name, read_mode); |
|
97 | file_open(file_p, file_name, read_mode); | |
97 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP |
|
98 | WHILE (NOT endfile(file_p)) AND (nb_data_read <nb_data_to_read) LOOP | |
98 | readline(file_p, line_p); |
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99 | readline(file_p, line_p); | |
99 | read(line_p, integer_p, GOOD); |
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100 | read(line_p, integer_p, GOOD); | |
100 | IF GOOD THEN |
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101 | IF GOOD THEN | |
101 | array_integer_v(nb_data_read) := integer_p; |
|
102 | array_integer_v(nb_data_read) := integer_p; | |
102 | nb_data_read := nb_data_read + 1; |
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103 | nb_data_read := nb_data_read + 1; | |
103 | END IF; |
|
104 | END IF; | |
104 | END LOOP; |
|
105 | END LOOP; | |
105 | IF nb_data_read < nb_data_to_read THEN |
|
106 | IF nb_data_read < nb_data_to_read THEN | |
106 | GOOD := false; |
|
107 | GOOD := false; | |
107 | ELSE |
|
108 | ELSE | |
108 | GOOD := true; |
|
109 | GOOD := true; | |
109 | END IF; |
|
110 | END IF; | |
110 | RETURN array_integer_v; |
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111 | RETURN array_integer_v; | |
111 | END get_array_integer; |
|
112 | END get_array_integer; | |
112 |
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113 | |||
113 |
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114 | |||
114 |
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115 | |||
115 | END reader_pkg; No newline at end of file |
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116 | END reader_pkg; |
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