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1 | LIBRARY ieee; | |||
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2 | USE ieee.std_logic_1164.ALL; | |||
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3 | ||||
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4 | ENTITY spectral_matrix_time_managment IS | |||
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5 | ||||
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6 | PORT ( | |||
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7 | clk : IN STD_LOGIC; | |||
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8 | rstn : IN STD_LOGIC; | |||
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9 | ||||
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10 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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11 | update_1 : IN STD_LOGIC; | |||
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12 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |||
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13 | ); | |||
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14 | ||||
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15 | END spectral_matrix_time_managment; | |||
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16 | ||||
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17 | ARCHITECTURE beh OF spectral_matrix_time_managment IS | |||
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18 | ||||
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19 | SIGNAL time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |||
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20 | ||||
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21 | BEGIN -- beh | |||
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22 | ||||
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23 | PROCESS (clk, rstn) | |||
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24 | BEGIN | |||
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25 | IF rstn = '0' THEN | |||
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26 | time_reg <= (OTHERS => '0'); | |||
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27 | ELSIF clk'event AND clk = '1' THEN | |||
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28 | IF update_1 = '1' THEN | |||
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29 | time_reg <= time_in; | |||
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30 | END IF; | |||
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31 | END IF; | |||
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32 | END PROCESS; | |||
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33 | ||||
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34 | time_out <= time_in; | |||
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35 | ||||
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36 | END beh; | |||
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