@@ -40,7 +40,7 ENTITY BUTTERFLY_CTRL IS | |||
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40 | 40 | sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z |
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41 | 41 | sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in |
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42 | 42 | sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z |
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43 |
sel_out : OUT STD_LOGIC_VECTOR( |
|
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43 | sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); | |
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44 | 44 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); |
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45 | 45 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) |
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46 | 46 | ); |
@@ -48,8 +48,7 END BUTTERFLY_CTRL; | |||
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48 | 48 | |
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49 | 49 | ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS |
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50 | 50 | |
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51 |
TYPE fsm_BUTTERFLY_CTRL_T IS ( |
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52 | waiting, | |
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51 | TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting, | |
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53 | 52 | add1, |
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54 | 53 | add2, |
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55 | 54 | add3, |
@@ -60,7 +59,8 ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTER | |||
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60 | 59 | mult8, |
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61 | 60 | mac9, |
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62 | 61 | last10, |
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63 |
last11 |
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62 | last11, | |
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63 | last12); | |
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64 | 64 | SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T; |
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65 | 65 | |
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66 | 66 | BEGIN |
@@ -80,121 +80,136 PROCESS (clk, rstn) | |||
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80 | 80 | --OUT |
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81 | 81 | sample_out_val <= '0'; |
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82 | 82 | |
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83 |
BUTTERFLY_CTRL_STATE <= |
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83 | BUTTERFLY_CTRL_STATE <= waiting; | |
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84 | 84 | |
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85 | 85 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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86 | 86 | |
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87 | 87 | CASE BUTTERFLY_CTRL_STATE IS |
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88 | 88 | |
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89 |
WHEN |
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89 | WHEN waiting => | |
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90 | 90 | IF sample_in_val = '1' THEN |
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91 | alu_ctrl <= ctrl_CLRMAC; | |
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92 | BUTTERFLY_CTRL_STATE <= waiting; | |
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91 | BUTTERFLY_CTRL_STATE <= add1; | |
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93 | 92 | END IF; |
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93 | sel_op1 <= "00000"; -- Are | |
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94 | sel_op2 <= "00000"; -- Bre | |
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95 | alu_comp <= "00"; | |
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96 | alu_ctrl <= ctrl_IDLE; | |
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97 | sel_out <= "0000"; | |
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98 | sample_out_val <= '0'; | |
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94 | 99 | |
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95 |
WHEN |
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100 | WHEN add1 => | |
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101 | sample_out_val <= '0'; | |
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96 | 102 | sel_op1 <= "10000"; -- Are |
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97 | 103 | sel_op2 <= "10000"; -- Bre |
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98 | 104 | alu_comp <= "10"; |
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99 | BUTTERFLY_CTRL_STATE <= add1; | |
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105 | alu_ctrl <= ctrl_ADD; | |
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106 | sel_out <= "0000"; | |
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107 | sample_out_val <= '0'; | |
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108 | BUTTERFLY_CTRL_STATE <= add2; | |
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100 | 109 | |
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101 |
WHEN add |
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110 | WHEN add2 => | |
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102 | 111 | sample_out_val <= '0'; |
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103 | 112 | sel_op1 <= "01000"; -- Aim |
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104 | 113 | sel_op2 <= "01000"; -- Bim |
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105 | 114 | alu_comp <= "10"; |
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106 | 115 | alu_ctrl <= ctrl_ADD; |
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107 |
sel_out <= " |
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108 |
BUTTERFLY_CTRL_STATE <= add |
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116 | sel_out <= "0000"; | |
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117 | BUTTERFLY_CTRL_STATE <= add3; | |
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109 | 118 | |
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110 |
WHEN add |
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119 | WHEN add3 => | |
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111 | 120 | sample_out_val <= '0'; |
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112 | 121 | sel_op1 <= "10000"; -- Are |
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113 | 122 | sel_op2 <= "10000"; -- Bre |
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114 | 123 | alu_comp <= "00"; |
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115 | 124 | alu_ctrl <= ctrl_ADD; |
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116 |
sel_out <= " |
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117 |
BUTTERFLY_CTRL_STATE <= add |
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125 | sel_out <= "0000"; | |
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126 | BUTTERFLY_CTRL_STATE <= add4; | |
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118 | 127 | |
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119 |
WHEN add |
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128 | WHEN add4 => | |
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120 | 129 | sample_out_val <= '0'; |
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121 | 130 | sel_op1 <= "01000"; -- Aim |
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122 | 131 | sel_op2 <= "01000"; -- Bim |
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123 | 132 | alu_comp <= "00"; |
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124 | 133 | alu_ctrl <= ctrl_ADD; |
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125 |
sel_out <= " |
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134 | sel_out <= "0000"; | |
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126 | 135 | sel_xyz <= "100"; -- X |
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127 |
BUTTERFLY_CTRL_STATE <= |
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136 | BUTTERFLY_CTRL_STATE <= mult5; | |
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128 | 137 | |
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129 |
WHEN |
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138 | WHEN mult5 => | |
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130 | 139 | sample_out_val <= '0'; |
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131 | 140 | sel_op1 <= "00100"; -- X |
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132 | 141 | sel_op2 <= "00100"; -- c |
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133 | 142 | alu_comp <= "00"; |
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134 |
alu_ctrl <= ctrl_ |
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135 |
sel_out <= "0000 |
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136 | sel_xyz <= "010"; | |
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137 |
BUTTERFLY_CTRL_STATE <= m |
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143 | alu_ctrl <= ctrl_MULT; | |
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144 | sel_out <= "0000"; | |
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145 | sel_xyz <= "010"; -- Y | |
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146 | BUTTERFLY_CTRL_STATE <= mac6; | |
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138 | 147 | |
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139 |
WHEN m |
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148 | WHEN mac6 => | |
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140 | 149 | sample_out_val <= '0'; |
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141 | alu_ctrl <= ctrl_MULT; | |
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142 | 150 | sel_op1 <= "00010"; -- Y |
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143 | 151 | sel_op2 <= "00100"; -- c |
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144 | 152 | alu_comp <= "10"; |
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145 |
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|
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146 | BUTTERFLY_CTRL_STATE <= mac6; | |
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153 | alu_ctrl <= ctrl_MAC; | |
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154 | sel_out <= "0001"; -- *** /!\ *** -- | |
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155 | sample_out_val <= '1'; | |
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156 | sel_xyz <= "000"; -- Y | |
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157 | BUTTERFLY_CTRL_STATE <= mac7; | |
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147 | 158 | |
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148 |
WHEN mac |
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159 | WHEN mac7 => | |
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149 | 160 | sample_out_val <= '0'; |
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150 | 161 | sel_op1 <= "00010"; -- Y |
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151 | 162 | sel_op2 <= "00001"; -- cms |
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152 | 163 | alu_comp <= "00"; |
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153 | 164 | alu_ctrl <= ctrl_MAC; |
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154 |
sel_out <= " |
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155 | BUTTERFLY_CTRL_STATE <= mac7; | |
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156 | ||
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157 | WHEN mac7 => | |
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158 | sample_out_val <= '0'; | |
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159 | sel_op1 <= "00100"; -- X | |
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160 | sel_op2 <= "00010"; -- cps | |
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161 | alu_ctrl <= ctrl_MAC; | |
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162 | alu_comp <= "00"; | |
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163 | sel_out <= "10000"; | |
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165 | sel_out <= "0010"; -- *** /!\ *** -- | |
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166 | sample_out_val <= '1'; | |
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164 | 167 | BUTTERFLY_CTRL_STATE <= mult8; |
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165 | 168 | |
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166 | 169 | WHEN mult8 => |
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167 | 170 | sample_out_val <= '0'; |
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171 | sel_op1 <= "00100"; -- X | |
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172 | sel_op2 <= "00010"; -- cps | |
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173 | alu_comp <= "00"; | |
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168 | 174 | alu_ctrl <= ctrl_MULT; |
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169 |
sel_o |
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170 |
s |
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171 | alu_comp <= "00"; | |
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172 | sel_out <= "10000"; | |
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175 | sel_out <= "0000"; | |
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176 | sample_out_val <= '0'; | |
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173 | 177 | BUTTERFLY_CTRL_STATE <= mac9; |
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174 | 178 | |
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175 | 179 | WHEN mac9 => |
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176 | 180 | sample_out_val <= '0'; |
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177 | sel_op1 <= "10000"; | |
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178 | sel_op2 <= "10000"; | |
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179 | 181 | alu_ctrl <= ctrl_MAC; |
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182 | sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU | |
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183 | sel_op2 <= "00000"; -- 1 | |
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180 | 184 | alu_comp <= "10"; |
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181 |
sel_out <= " |
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185 | sel_out <= "0000"; | |
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186 | sample_out_val <= '0'; | |
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182 | 187 | BUTTERFLY_CTRL_STATE <= last10; |
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183 | 188 | |
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184 | 189 | WHEN last10 => |
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185 | 190 | sample_out_val <= '0'; |
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186 | 191 | sel_op1 <= "10000"; |
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187 | 192 | sel_op2 <= "10000"; |
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193 | alu_comp <= "10"; | |
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188 | 194 | alu_ctrl <= ctrl_IDLE; |
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189 |
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190 |
s |
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195 | sel_out <= "0100"; -- *** /!\ *** -- | |
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196 | sample_out_val <= '1'; | |
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191 | 197 | BUTTERFLY_CTRL_STATE <= last11; |
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192 | 198 | |
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193 | 199 | WHEN last11 => |
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194 | 200 | sample_out_val <= '0'; |
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195 | alu_ctrl <= ctrl_IDLE; | |
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196 | 201 | alu_comp <= "10"; |
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197 |
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|
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202 | alu_ctrl <= ctrl_IDLE; | |
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203 | sel_out <= "0000"; | |
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204 | sample_out_val <= '0'; | |
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205 | BUTTERFLY_CTRL_STATE <= last12; | |
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206 | ||
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207 | WHEN last12 => | |
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208 | sample_out_val <= '0'; | |
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209 | alu_comp <= "10"; | |
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210 | alu_ctrl <= ctrl_IDLE; | |
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211 | sel_out <= "1000"; -- *** /!\ *** -- | |
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212 | sample_out_val <= '1'; | |
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198 | 213 | BUTTERFLY_CTRL_STATE <= waiting; |
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199 | 214 | |
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200 | 215 | WHEN OTHERS => |
@@ -46,13 +46,8 ENTITY BUTTERFLY_TOP IS | |||
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46 | 46 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
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47 | 47 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
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48 | 48 | |
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49 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
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50 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
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51 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |
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52 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |
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53 | ||
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54 | 49 | butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); |
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55 |
sel_out : OUT STD_LOGIC_VECTOR ( |
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50 | sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) | |
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56 | 51 | ); |
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57 | 52 | END BUTTERFLY_TOP; |
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58 | 53 | |
@@ -66,9 +61,6 SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( | |||
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66 | 61 | |
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67 | 62 | BEGIN |
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68 | 63 | |
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69 | alu_ctrl <= alu_ctrl_sig; | |
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70 | alu_comp <= alu_comp_sig; | |
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71 | ||
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72 | 64 | BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW |
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73 | 65 | GENERIC MAP ( |
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74 | 66 | Sample_SZ => 16) |
@@ -84,9 +76,6 BEGIN | |||
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84 | 76 | cps_in => cps_in, |
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85 | 77 | cms_in => cms_in, |
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86 | 78 | |
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87 | op1 => op1, | |
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88 | op2 => op2, | |
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89 | ||
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90 | 79 | out_alu => butterfly_out, |
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91 | 80 | |
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92 | 81 | sel_op1 => sel_op1, |
@@ -86,6 +86,10 PROCESS (clk, rstn) | |||
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86 | 86 | Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); |
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87 | 87 | elsif sel_xyz = "001" THEN |
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88 | 88 | Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); |
|
89 | else | |
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90 | X <= X; | |
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91 | Y <= Y; | |
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92 | Z <= Z; | |
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89 | 93 | end if; |
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90 | 94 | |
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91 | 95 | END IF; |
@@ -1,29 +1,32 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Paul Leroy | |
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | ||
|
23 | ||
|
24 | LIBRARY ieee; | |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | ||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Paul Leroy | |
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | ||
|
23 | ||
|
24 | LIBRARY ieee; | |
|
25 | USE ieee.std_logic_1164.ALL; | |
|
26 | ||
|
27 | LIBRARY staging_LPP; | |
|
28 | USE staging_LPP.PLE_iir_filter.ALL; | |
|
29 | ||
|
27 | 30 | PACKAGE PLE_lpp_fft IS |
|
28 | 31 | |
|
29 | 32 | COMPONENT BUTTERFLY_DATAFLOW |
@@ -41,9 +44,6 COMPONENT BUTTERFLY_DATAFLOW | |||
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41 | 44 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
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42 | 45 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
|
43 | 46 | |
|
44 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
|
45 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
|
46 | ||
|
47 | 47 | out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); |
|
48 | 48 | |
|
49 | 49 | sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z |
@@ -65,7 +65,7 COMPONENT BUTTERFLY_CTRL | |||
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65 | 65 | sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z |
|
66 | 66 | sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in |
|
67 | 67 | sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z |
|
68 |
sel_out : OUT STD_LOGIC_VECTOR( |
|
|
68 | sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); | |
|
69 | 69 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); |
|
70 | 70 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) |
|
71 | 71 | ); |
@@ -89,13 +89,31 COMPONENT BUTTERFLY_TOP | |||
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89 | 89 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
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90 | 90 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); |
|
91 | 91 | |
|
92 |
|
|
|
93 |
|
|
|
94 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |
|
95 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |
|
92 | butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |
|
93 | sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) | |
|
94 | ); | |
|
95 | END COMPONENT; | |
|
96 | 96 | |
|
97 | butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |
|
98 | sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) | |
|
97 | COMPONENT input_buffers_and_coefficients | |
|
98 | GENERIC( | |
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99 | tech : INTEGER := 0; | |
|
100 | Input_SZ_1 : INTEGER := 16; | |
|
101 | Mem_use : INTEGER := use_RAM -- 1 use RAM | |
|
102 | ); | |
|
103 | PORT( | |
|
104 | rstn : IN STD_LOGIC; | |
|
105 | clk : IN STD_LOGIC; | |
|
106 | --******************* | |
|
107 | -- PLE ************** | |
|
108 | WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
109 | RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
110 | WEN_in : IN STD_LOGIC; | |
|
111 | REN_in : IN STD_LOGIC; | |
|
112 | RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
113 | WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
114 | start : IN STD_LOGIC | |
|
115 | --******************* | |
|
116 | --******************* | |
|
99 | 117 | ); |
|
100 | 118 | END COMPONENT; |
|
101 | 119 |
@@ -44,15 +44,10 signal Bim : std_logic_vector( | |||
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44 | 44 | signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); |
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45 | 45 | signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); |
|
46 | 46 | signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); |
|
47 | ||
|
48 | signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
|
49 | signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |
|
50 | signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |
|
51 | signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |
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52 | 47 | |
|
53 | 48 | signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 ); |
|
54 | 49 | |
|
55 |
signal sel_out : std_logic_vector( |
|
|
50 | signal sel_out : std_logic_vector( 3 downto 0 ); | |
|
56 | 51 | |
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57 | 52 | signal sample_in_val : std_logic := '0'; |
|
58 | 53 | signal sample_out_val : std_logic; |
@@ -78,11 +73,6 port map( | |||
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78 | 73 | cps_in => cps, |
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79 | 74 | cms_in => cms, |
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80 | 75 | |
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81 | op1 => op1, | |
|
82 | op2 => op2, | |
|
83 | alu_ctrl => alu_ctrl_sig, | |
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84 | alu_comp => alu_comp_sig, | |
|
85 | ||
|
86 | 76 | butterfly_out => Resultat, |
|
87 | 77 | sel_out => sel_out |
|
88 | 78 | ); |
@@ -92,8 +82,10 clk <= not clk after 25 ns; | |||
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92 | 82 | process |
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93 | 83 | begin |
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94 | 84 | |
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95 | wait for 40 ns; | |
|
96 | rstn <= '1'; | |
|
85 | if rstn = '0' then | |
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86 | wait for 40 ns; | |
|
87 | rstn <= '1'; | |
|
88 | end if; | |
|
97 | 89 | |
|
98 | 90 | wait for 11 ns; |
|
99 | 91 | Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ)); |
@@ -1,13 +1,25 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 |
add wave -noupdate /testbench_butterfly_top/ |
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4 | add wave -noupdate -divider TOTO | |
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5 |
add wave -noupdate /testbench_butterfly_top/a |
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6 |
add wave -noupdate -e |
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|
7 |
add wave -noupdate -e |
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|
3 | add wave -noupdate /testbench_butterfly_top/clk | |
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4 | add wave -noupdate /testbench_butterfly_top/rstn | |
|
5 | add wave -noupdate -radix decimal /testbench_butterfly_top/are | |
|
6 | add wave -noupdate -radix decimal /testbench_butterfly_top/aim | |
|
7 | add wave -noupdate -radix decimal /testbench_butterfly_top/bre | |
|
8 | add wave -noupdate -radix decimal /testbench_butterfly_top/bim | |
|
9 | add wave -noupdate -radix decimal /testbench_butterfly_top/c | |
|
10 | add wave -noupdate -radix decimal /testbench_butterfly_top/cps | |
|
11 | add wave -noupdate -radix decimal /testbench_butterfly_top/cms | |
|
12 | add wave -noupdate -radix decimal /testbench_butterfly_top/op1 | |
|
13 | add wave -noupdate -radix decimal /testbench_butterfly_top/op2 | |
|
14 | add wave -noupdate -radix decimal /testbench_butterfly_top/resultat | |
|
15 | add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig | |
|
16 | add wave -noupdate /testbench_butterfly_top/alu_comp_sig | |
|
17 | add wave -noupdate /testbench_butterfly_top/sel_out | |
|
18 | add wave -noupdate /testbench_butterfly_top/sample_in_val | |
|
19 | add wave -noupdate /testbench_butterfly_top/sample_out_val | |
|
8 | 20 | TreeUpdate [SetDefaultTree] |
|
9 |
WaveRestoreCursors {{Cursor 1} { |
|
|
10 |
configure wave -namecolwidth |
|
|
21 | WaveRestoreCursors {{Cursor 1} {149541 ps} 0} | |
|
22 | configure wave -namecolwidth 150 | |
|
11 | 23 | configure wave -valuecolwidth 100 |
|
12 | 24 | configure wave -justifyvalue left |
|
13 | 25 | configure wave -signalnamewidth 0 |
@@ -21,4 +33,4 configure wave -griddelta 40 | |||
|
21 | 33 | configure wave -timeline 0 |
|
22 | 34 | configure wave -timelineunits ns |
|
23 | 35 | update |
|
24 |
WaveRestoreZoom {0 ps} {10 |
|
|
36 | WaveRestoreZoom {0 ps} {1050 ns} |
@@ -1,5 +1,11 | |||
|
1 | 1 | --twiddle_factors_128.vhd |
|
2 | 2 | |
|
3 | library IEEE; | |
|
4 | use IEEE.numeric_std.all; | |
|
5 | use IEEE.std_logic_1164.all; | |
|
6 | ||
|
7 | package PLE_twiddle_factors_128 is | |
|
8 | ||
|
3 | 9 | constant Coef_SZ : integer := 16; |
|
4 | 10 | constant NB_Coeffs : integer := 128; |
|
5 | 11 | |
@@ -457,3 +463,5 cms_96 & cms_97 & cms_98 & cms_99 & | |||
|
457 | 463 | cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 & |
|
458 | 464 | cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 & |
|
459 | 465 | cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 ); |
|
466 | end; | |
|
467 |
This diff has been collapsed as it changes many lines, (686 lines changed) Show them Hide them | |||
@@ -1,301 +1,385 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY staging_lpp; | |
|
26 | USE staging_lpp.PLE_general_purpose.ALL; | |
|
27 | --TODO | |
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |
|
29 | --par un resize sur un vecteur en combi | |
|
30 | ||
|
31 | ||
|
32 | ENTITY MAC IS | |
|
33 | GENERIC( | |
|
34 | Input_SZ_A : INTEGER := 8; | |
|
35 | Input_SZ_B : INTEGER := 8; | |
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
37 | ||
|
38 | ); | |
|
39 | PORT( | |
|
40 | clk : IN STD_LOGIC; | |
|
41 | reset : IN STD_LOGIC; | |
|
42 | clr_MAC : IN STD_LOGIC; | |
|
43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
|
48 | ); | |
|
49 | END MAC; | |
|
50 | ||
|
51 | ||
|
52 | ||
|
53 | ||
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |
|
55 | ||
|
56 | SIGNAL add, mult : STD_LOGIC; | |
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
58 | ||
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
62 | ||
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
66 | ||
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
69 | ||
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |
|
71 | ||
|
72 | SIGNAL add_D : STD_LOGIC; | |
|
73 |
SIGNAL |
|
|
74 |
SIGNAL |
|
|
75 |
SIGNAL |
|
|
76 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
|
77 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
|
78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
|
79 | SIGNAL clr_MAC_D : STD_LOGIC; | |
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
|
81 |
SIGNAL M |
|
|
82 | ||
|
83 |
SIGNAL |
|
|
84 |
SIGNAL |
|
|
85 | ||
|
86 | BEGIN | |
|
87 | ||
|
88 | ||
|
89 | ||
|
90 | ||
|
91 | --============================================================== | |
|
92 | --=============M A C C O N T R O L E R========================= | |
|
93 | --============================================================== | |
|
94 | MAC_CONTROLER1 : MAC_CONTROLER | |
|
95 | PORT MAP( | |
|
96 | ctrl => MAC_MUL_ADD, | |
|
97 | MULT => mult, | |
|
98 | ADD => add, | |
|
99 | LOAD_ADDER => load_mult_result, | |
|
100 | MACMUX_sel => MACMUXsel, | |
|
101 | MACMUX2_sel => MACMUX2sel | |
|
102 | ||
|
103 | ); | |
|
104 | --============================================================== | |
|
105 | ||
|
106 | ||
|
107 | ||
|
108 | ||
|
109 | --============================================================== | |
|
110 | --=============M U L T I P L I E R============================== | |
|
111 | --============================================================== | |
|
112 | Multiplieri_nst : Multiplier | |
|
113 | GENERIC MAP( | |
|
114 | Input_SZ_A => Input_SZ_A, | |
|
115 | Input_SZ_B => Input_SZ_B | |
|
116 | ) | |
|
117 | PORT MAP( | |
|
118 | clk => clk, | |
|
119 | reset => reset, | |
|
120 | mult => mult, | |
|
121 | OP1 => OP1_2C, | |
|
122 | OP2 => OP2_2C, | |
|
123 | RES => MULTout | |
|
124 | ); | |
|
125 | --============================================================== | |
|
126 | ||
|
127 | PROCESS (clk, reset) | |
|
128 | BEGIN -- PROCESS | |
|
129 | IF reset = '0' THEN -- asynchronous reset (active low) | |
|
130 | load_mult_result_D <= '0'; | |
|
131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
132 | load_mult_result_D <= load_mult_result; | |
|
133 | END IF; | |
|
134 | END PROCESS; | |
|
135 | ||
|
136 | --============================================================== | |
|
137 | --======================A D D E R ============================== | |
|
138 | --============================================================== | |
|
139 | adder_inst : Adder | |
|
140 | GENERIC MAP( | |
|
141 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
|
142 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
|
143 | ) | |
|
144 | PORT MAP( | |
|
145 | clk => clk, | |
|
146 | reset => reset, | |
|
147 | clr => clr_MAC_D, | |
|
148 | load => load_mult_result_D, | |
|
149 | add => add_D, | |
|
150 | OP1 => ADDERinA, | |
|
151 | OP2 => ADDERinB, | |
|
152 | RES => ADDERout | |
|
153 | ); | |
|
154 | ||
|
155 | --============================================================== | |
|
156 | --===================TWO COMPLEMENTERS========================== | |
|
157 | --============================================================== | |
|
158 | gen_comp : IF COMP_EN = 0 GENERATE | |
|
159 | TWO_COMPLEMENTER1 : TwoComplementer | |
|
160 | GENERIC MAP( | |
|
161 | Input_SZ => Input_SZ_A | |
|
162 | ) | |
|
163 | PORT MAP( | |
|
164 | clk => clk, | |
|
165 | reset => reset, | |
|
166 | clr => clr_MAC, | |
|
167 | TwoComp => Comp_2C(0), | |
|
168 | OP => OP1, | |
|
169 | RES => OP1_2C | |
|
170 | ); | |
|
171 | ||
|
172 | TWO_COMPLEMENTER2 : TwoComplementer | |
|
173 | GENERIC MAP( | |
|
174 | Input_SZ => Input_SZ_B | |
|
175 | ) | |
|
176 | PORT MAP( | |
|
177 |
|
|
|
178 | reset => reset, | |
|
179 | clr => clr_MAC, | |
|
180 | TwoComp => Comp_2C(1), | |
|
181 | OP => OP2, | |
|
182 | RES => OP2_2C | |
|
183 | ); | |
|
184 | END GENERATE gen_comp; | |
|
185 | ||
|
186 | no_gen_comp : IF COMP_EN = 1 GENERATE | |
|
187 | OP2_2C <= OP2; | |
|
188 | OP1_2C <= OP1; | |
|
189 | END GENERATE no_gen_comp; | |
|
190 | --============================================================== | |
|
191 | ||
|
192 | clr_MACREG1 : MAC_REG | |
|
193 | GENERIC MAP(size => 1) | |
|
194 | PORT MAP( | |
|
195 | reset => reset, | |
|
196 | clk => clk, | |
|
197 | D(0) => clr_MAC, | |
|
198 | Q(0) => clr_MAC_D | |
|
199 | ); | |
|
200 | ||
|
201 | addREG : MAC_REG | |
|
202 | GENERIC MAP(size => 1) | |
|
203 | PORT MAP( | |
|
204 | reset => reset, | |
|
205 | clk => clk, | |
|
206 | D(0) => add, | |
|
207 | Q(0) => add_D | |
|
208 | ); | |
|
209 | ||
|
210 | OP1REG : MAC_REG | |
|
211 | GENERIC MAP(size => Input_SZ_A) | |
|
212 | PORT MAP( | |
|
213 | reset => reset, | |
|
214 | clk => clk, | |
|
215 | D => OP1_2C, | |
|
216 | Q => OP1_2C_D | |
|
217 | ); | |
|
218 | ||
|
219 | ||
|
220 | OP2REG : MAC_REG | |
|
221 | GENERIC MAP(size => Input_SZ_B) | |
|
222 | PORT MAP( | |
|
223 | reset => reset, | |
|
224 | clk => clk, | |
|
225 | D => OP2_2C, | |
|
226 | Q => OP2_2C_D | |
|
227 | ); | |
|
228 | ||
|
229 | MULToutREG : MAC_REG | |
|
230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |
|
231 | PORT MAP( | |
|
232 | reset => reset, | |
|
233 | clk => clk, | |
|
234 | D => MULTout, | |
|
235 | Q => MULTout_D | |
|
236 | ); | |
|
237 | ||
|
238 | MACMUXselREG : MAC_REG | |
|
239 | GENERIC MAP(size => 1) | |
|
240 | PORT MAP( | |
|
241 | reset => reset, | |
|
242 | clk => clk, | |
|
243 | D(0) => MACMUXsel, | |
|
244 | Q(0) => MACMUXsel_D | |
|
245 | ); | |
|
246 | ||
|
247 | MACMUX2selREG : MAC_REG | |
|
248 | GENERIC MAP(size => 1) | |
|
249 | PORT MAP( | |
|
250 | reset => reset, | |
|
251 | clk => clk, | |
|
252 | D(0) => MACMUX2sel, | |
|
253 | Q(0) => MACMUX2sel_D | |
|
254 | ); | |
|
255 | ||
|
256 | MACMUX2selREG2 : MAC_REG | |
|
257 | GENERIC MAP(size => 1) | |
|
258 | PORT MAP( | |
|
259 | reset => reset, | |
|
260 | clk => clk, | |
|
261 | D(0) => MACMUX2sel_D, | |
|
262 | Q(0) => MACMUX2sel_D_D | |
|
263 | ); | |
|
264 | ||
|
265 | --============================================================== | |
|
266 | --======================M A C M U X =========================== | |
|
267 | --============================================================== | |
|
268 | MACMUX_inst : MAC_MUX | |
|
269 | GENERIC MAP( | |
|
270 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
|
271 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
|
272 | ||
|
273 | ) | |
|
274 | PORT MAP( | |
|
275 |
|
|
|
276 | INA1 => ADDERout, | |
|
277 | INA2 => OP2_2C_D_Resz, | |
|
278 | INB1 => MULTout, | |
|
279 | INB2 => OP1_2C_D_Resz, | |
|
280 | OUTA => ADDERinA, | |
|
281 | OUTB => ADDERinB | |
|
282 | ); | |
|
283 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); | |
|
284 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); | |
|
285 | --============================================================== | |
|
286 | ||
|
287 | ||
|
288 | --============================================================== | |
|
289 | --======================M A C M U X2 ========================== | |
|
290 | --============================================================== | |
|
291 | MAC_MUX2_inst : MAC_MUX2 | |
|
292 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) | |
|
293 | PORT MAP( | |
|
294 | sel => MACMUX2sel_D_D, | |
|
295 | RES2 => MULTout_D, | |
|
296 | RES1 => ADDERout, | |
|
297 | RES => RES | |
|
298 | ); | |
|
299 | --============================================================== | |
|
300 | ||
|
301 | END ar_MAC; | |
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY staging_lpp; | |
|
26 | USE staging_lpp.PLE_general_purpose.ALL; | |
|
27 | --TODO | |
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |
|
29 | --par un resize sur un vecteur en combi | |
|
30 | ||
|
31 | ||
|
32 | ENTITY MAC IS | |
|
33 | GENERIC( | |
|
34 | Input_SZ_A : INTEGER := 8; | |
|
35 | Input_SZ_B : INTEGER := 8; | |
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
|
37 | ||
|
38 | ); | |
|
39 | PORT( | |
|
40 | clk : IN STD_LOGIC; | |
|
41 | reset : IN STD_LOGIC; | |
|
42 | clr_MAC : IN STD_LOGIC; | |
|
43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
|
48 | ); | |
|
49 | END MAC; | |
|
50 | ||
|
51 | ||
|
52 | ||
|
53 | ||
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |
|
55 | ||
|
56 | SIGNAL add, mult : STD_LOGIC; | |
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
58 | ||
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
62 | ||
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
66 | ||
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
69 | ||
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |
|
71 | ||
|
72 | SIGNAL add_D : STD_LOGIC; | |
|
73 | SIGNAL add_D_D : STD_LOGIC; | |
|
74 | SIGNAL mult_D : STD_LOGIC; | |
|
75 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
76 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
77 | ||
|
78 | -- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
|
79 | -- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
|
80 | ||
|
81 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
|
82 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
|
83 | SIGNAL MACMUXsel_D_D : STD_LOGIC; | |
|
84 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
|
85 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
|
86 | SIGNAL MACMUX2sel_D_D_D : STD_LOGIC; | |
|
87 | SIGNAL clr_MAC_D : STD_LOGIC; | |
|
88 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
|
89 | SIGNAL clr_MAC_D_D_D : STD_LOGIC; | |
|
90 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
91 | SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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92 | ||
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93 | SIGNAL load_mult_result : STD_LOGIC; | |
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94 | SIGNAL load_mult_result_D : STD_LOGIC; | |
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95 | SIGNAL load_mult_result_D_D : STD_LOGIC; | |
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96 | ||
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97 | BEGIN | |
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98 | ||
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99 | ||
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100 | ||
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101 | ||
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102 | --============================================================== | |
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103 | --=============M A C C O N T R O L E R========================= | |
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104 | --============================================================== | |
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105 | MAC_CONTROLER1 : MAC_CONTROLER | |
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106 | PORT MAP( | |
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107 | ctrl => MAC_MUL_ADD, | |
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108 | MULT => mult, | |
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109 | ADD => add, | |
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110 | LOAD_ADDER => load_mult_result, | |
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111 | MACMUX_sel => MACMUXsel, | |
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112 | MACMUX2_sel => MACMUX2sel | |
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113 | ||
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114 | ); | |
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115 | --============================================================== | |
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116 | ||
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117 | ||
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118 | --============================================================== | |
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119 | --===================TWO COMPLEMENTERS========================== | |
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120 | --============================================================== | |
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121 | gen_comp : IF COMP_EN = 0 GENERATE | |
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122 | TWO_COMPLEMENTER1 : TwoComplementer | |
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123 | GENERIC MAP( | |
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124 | Input_SZ => Input_SZ_A | |
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125 | ) | |
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126 | PORT MAP( | |
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127 | clk => clk, | |
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128 | reset => reset, | |
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129 | clr => clr_MAC, | |
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130 | TwoComp => Comp_2C(0), | |
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131 | OP => OP1, | |
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132 | RES => OP1_2C | |
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133 | ); | |
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134 | ||
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135 | TWO_COMPLEMENTER2 : TwoComplementer | |
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136 | GENERIC MAP( | |
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137 | Input_SZ => Input_SZ_B | |
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138 | ) | |
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139 | PORT MAP( | |
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140 | clk => clk, | |
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141 | reset => reset, | |
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142 | clr => clr_MAC, | |
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143 | TwoComp => Comp_2C(1), | |
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144 | OP => OP2, | |
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145 | RES => OP2_2C | |
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146 | ); | |
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147 | END GENERATE gen_comp; | |
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148 | ||
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149 | no_gen_comp : IF COMP_EN = 1 GENERATE | |
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150 | process(clk,reset) | |
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151 | begin | |
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152 | if(reset='0')then | |
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153 | OP1_2C <= (others => '0'); | |
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154 | OP2_2C <= (others => '0'); | |
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155 | elsif clk'event and clk='1' then | |
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156 | if clr_MAC = '1' then | |
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157 | OP1_2C <= (others => '0'); | |
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158 | OP2_2C <= (others => '0'); | |
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159 | else | |
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160 | OP1_2C <= OP1; | |
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161 | OP2_2C <= OP2; | |
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162 | end if; | |
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163 | end if; | |
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164 | end process; | |
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165 | ||
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166 | END GENERATE no_gen_comp; | |
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167 | --============================================================== | |
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168 | ||
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169 | --============================================================== | |
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170 | --=============M U L T I P L I E R============================== | |
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171 | --============================================================== | |
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172 | ||
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173 | multREG0 : MAC_REG | |
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174 | GENERIC MAP(size => 1) | |
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175 | PORT MAP( | |
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176 | reset => reset, | |
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177 | clk => clk, | |
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178 | D(0) => mult, | |
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179 | Q(0) => mult_D | |
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180 | ); | |
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181 | ||
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182 | Multiplieri_nst : Multiplier | |
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183 | GENERIC MAP( | |
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184 | Input_SZ_A => Input_SZ_A, | |
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185 | Input_SZ_B => Input_SZ_B | |
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186 | ) | |
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187 | PORT MAP( | |
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188 | clk => clk, | |
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189 | reset => reset, | |
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190 | mult => mult_D, | |
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191 | OP1 => OP1_2C, | |
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192 | OP2 => OP2_2C, | |
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193 | RES => MULTout | |
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194 | ); | |
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195 | ||
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196 | OP1REG : MAC_REG | |
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197 | GENERIC MAP(size => Input_SZ_A) | |
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198 | PORT MAP( | |
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199 | reset => reset, | |
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200 | clk => clk, | |
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201 | D => OP1_2C, | |
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202 | Q => OP1_2C_D | |
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203 | ); | |
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204 | ||
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205 | OP2REG : MAC_REG | |
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206 | GENERIC MAP(size => Input_SZ_B) | |
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207 | PORT MAP( | |
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208 | reset => reset, | |
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209 | clk => clk, | |
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210 | D => OP2_2C, | |
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211 | Q => OP2_2C_D | |
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212 | ); | |
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213 | ||
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214 | --============================================================== | |
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215 | ||
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216 | --============================================================== | |
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217 | --======================M A C M U X =========================== | |
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218 | --============================================================== | |
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219 | ||
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220 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); | |
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221 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); | |
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222 | ||
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223 | MACMUXselREG0 : MAC_REG | |
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224 | GENERIC MAP(size => 1) | |
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225 | PORT MAP( | |
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226 | reset => reset, | |
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227 | clk => clk, | |
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228 | D(0) => MACMUXsel, | |
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229 | Q(0) => MACMUXsel_D | |
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230 | ); | |
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231 | ||
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232 | MACMUXselREG1 : MAC_REG | |
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233 | GENERIC MAP(size => 1) | |
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234 | PORT MAP( | |
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235 | reset => reset, | |
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236 | clk => clk, | |
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237 | D(0) => MACMUXsel_D, | |
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238 | Q(0) => MACMUXsel_D_D | |
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239 | ); | |
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240 | ||
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241 | MACMUX_inst : MAC_MUX | |
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242 | GENERIC MAP( | |
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243 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
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244 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
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245 | ||
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246 | ) | |
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247 | PORT MAP( | |
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248 | sel => MACMUXsel_D_D, | |
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249 | INA1 => ADDERout, | |
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250 | INA2 => OP2_2C_D_Resz, | |
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251 | INB1 => MULTout, | |
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252 | INB2 => OP1_2C_D_Resz, | |
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253 | OUTA => ADDERinA, | |
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254 | OUTB => ADDERinB | |
|
255 | ); | |
|
256 | ||
|
257 | --============================================================== | |
|
258 | ||
|
259 | --============================================================== | |
|
260 | --======================A D D E R ============================== | |
|
261 | --============================================================== | |
|
262 | ||
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263 | clr_MACREG0 : MAC_REG | |
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264 | GENERIC MAP(size => 1) | |
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265 | PORT MAP( | |
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266 | reset => reset, | |
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267 | clk => clk, | |
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268 | D(0) => clr_MAC, | |
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269 | Q(0) => clr_MAC_D | |
|
270 | ); | |
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271 | ||
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272 | clr_MACREG1 : MAC_REG | |
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273 | GENERIC MAP(size => 1) | |
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274 | PORT MAP( | |
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275 | reset => reset, | |
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276 | clk => clk, | |
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277 | D(0) => clr_MAC_D, | |
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278 | Q(0) => clr_MAC_D_D | |
|
279 | ); | |
|
280 | ||
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281 | addREG0 : MAC_REG | |
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282 | GENERIC MAP(size => 1) | |
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283 | PORT MAP( | |
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284 | reset => reset, | |
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285 | clk => clk, | |
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286 | D(0) => add, | |
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287 | Q(0) => add_D | |
|
288 | ); | |
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289 | ||
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290 | addREG1 : MAC_REG | |
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291 | GENERIC MAP(size => 1) | |
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292 | PORT MAP( | |
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293 | reset => reset, | |
|
294 | clk => clk, | |
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295 | D(0) => add_D, | |
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296 | Q(0) => add_D_D | |
|
297 | ); | |
|
298 | ||
|
299 | load_mult_resultREG : MAC_REG | |
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300 | GENERIC MAP(size => 1) | |
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301 | PORT MAP( | |
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302 | reset => reset, | |
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303 | clk => clk, | |
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304 | D(0) => load_mult_result, | |
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305 | Q(0) => load_mult_result_D | |
|
306 | ); | |
|
307 | ||
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308 | load_mult_resultREG1 : MAC_REG | |
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309 | GENERIC MAP(size => 1) | |
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310 | PORT MAP( | |
|
311 | reset => reset, | |
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312 | clk => clk, | |
|
313 | D(0) => load_mult_result_D, | |
|
314 | Q(0) => load_mult_result_D_D | |
|
315 | ); | |
|
316 | ||
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317 | adder_inst : Adder | |
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318 | GENERIC MAP( | |
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319 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
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320 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
|
321 | ) | |
|
322 | PORT MAP( | |
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323 | clk => clk, | |
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324 | reset => reset, | |
|
325 | clr => clr_MAC_D_D, | |
|
326 | load => load_mult_result_D_D, | |
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327 | add => add_D_D, | |
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328 | OP1 => ADDERinA, | |
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329 | OP2 => ADDERinB, | |
|
330 | RES => ADDERout | |
|
331 | ); | |
|
332 | ||
|
333 | --============================================================== | |
|
334 | ||
|
335 | --============================================================== | |
|
336 | --======================M A C M U X2 ========================== | |
|
337 | --============================================================== | |
|
338 | ||
|
339 | MULToutREG : MAC_REG | |
|
340 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |
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341 | PORT MAP( | |
|
342 | reset => reset, | |
|
343 | clk => clk, | |
|
344 | D => MULTout, | |
|
345 | Q => MULTout_D | |
|
346 | ); | |
|
347 | ||
|
348 | MACMUX2selREG : MAC_REG | |
|
349 | GENERIC MAP(size => 1) | |
|
350 | PORT MAP( | |
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351 | reset => reset, | |
|
352 | clk => clk, | |
|
353 | D(0) => MACMUX2sel, | |
|
354 | Q(0) => MACMUX2sel_D | |
|
355 | ); | |
|
356 | ||
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357 | MACMUX2selREG2_0 : MAC_REG | |
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358 | GENERIC MAP(size => 1) | |
|
359 | PORT MAP( | |
|
360 | reset => reset, | |
|
361 | clk => clk, | |
|
362 | D(0) => MACMUX2sel_D, | |
|
363 | Q(0) => MACMUX2sel_D_D | |
|
364 | ); | |
|
365 | ||
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366 | MACMUX2selREG2_1 : MAC_REG | |
|
367 | GENERIC MAP(size => 1) | |
|
368 | PORT MAP( | |
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369 | reset => reset, | |
|
370 | clk => clk, | |
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371 | D(0) => MACMUX2sel_D_D, | |
|
372 | Q(0) => MACMUX2sel_D_D_D | |
|
373 | ); | |
|
374 | ||
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375 | MAC_MUX2_inst : MAC_MUX2 | |
|
376 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) | |
|
377 | PORT MAP( | |
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378 | sel => MACMUX2sel_D_D_D, | |
|
379 | RES2 => MULTout_D, | |
|
380 | RES1 => ADDERout, | |
|
381 | RES => RES | |
|
382 | ); | |
|
383 | --============================================================== | |
|
384 | ||
|
385 | END ar_MAC; No newline at end of file |
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