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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 #VHDLSIMFILES=testbench.vhd
17 #SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48
49 ################## project specific targets ##########################
50
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44 use lpp.lpp_cna.all;
45
46
47 ENTITY leon3mp IS
48 GENERIC (
49 fabtech : INTEGER := CFG_FABTECH;
50 memtech : INTEGER := CFG_MEMTECH;
51 padtech : INTEGER := CFG_PADTECH;
52 clktech : INTEGER := CFG_CLKTECH;
53 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
54 dbguart : INTEGER := CFG_DUART; -- Print UART on console
55 pclow : INTEGER := CFG_PCLOW
56 );
57 PORT (
58 clk100MHz : IN STD_ULOGIC;
59 clk49_152MHz : IN STD_ULOGIC;
60 reset : IN STD_ULOGIC;
61
62 errorn : OUT STD_ULOGIC;
63
64 -- UART AHB ---------------------------------------------------------------
65 ahbrxd : IN STD_ULOGIC; -- DSU rx data
66 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
67
68 -- UART APB ---------------------------------------------------------------
69 urxd1 : IN STD_ULOGIC; -- UART1 rx data
70 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
71
72 -- RAM --------------------------------------------------------------------
73 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
74 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 nSRAM_BE0 : OUT STD_LOGIC;
76 nSRAM_BE1 : OUT STD_LOGIC;
77 nSRAM_BE2 : OUT STD_LOGIC;
78 nSRAM_BE3 : OUT STD_LOGIC;
79 nSRAM_WE : OUT STD_LOGIC;
80 nSRAM_CE : OUT STD_LOGIC;
81 nSRAM_OE : OUT STD_LOGIC;
82
83 -- SPW --------------------------------------------------------------------
84 spw1_din : IN STD_LOGIC; -- PLE
85 spw1_sin : IN STD_LOGIC; -- PLE
86 spw1_dout : OUT STD_LOGIC; -- PLE
87 spw1_sout : OUT STD_LOGIC; -- PLE
88
89 spw2_din : IN STD_LOGIC; -- JCPE --TODO
90 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
91 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
92 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
93
94 -- ADC --------------------------------------------------------------------
95 bias_fail_sw : OUT STD_LOGIC;
96 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
97 ADC_smpclk : OUT STD_LOGIC;
98 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
99
100 -- SCM CALIBRATION --------------------------------------------------------
101 SCM_CAL_EN : OUT STD_LOGIC; -- TODO A6
102 SCM_CAL_DIN : OUT STD_LOGIC; -- TODO A4
103 SCM_CAL_SCLK : OUT STD_LOGIC; -- TODO A5
104 SCM_CAL_nSYNC : OUT STD_LOGIC; -- TODO B6
105
106 ---------------------------------------------------------------------------
107 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
108 );
109 END;
110
111 ARCHITECTURE Behavioral OF leon3mp IS
112
113 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
114 -- CFG_GRETH+CFG_AHB_JTAG;
115 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
116 CFG_AHB_UART
117 +2;
118 -- 1 is for the SpaceWire module grspw, which is a master
119 -- 1 is for the LFR
120
121 CONSTANT maxahbm : INTEGER := maxahbmsp;
122
123 --Clk & Rst gοΏ½nοΏ½
124 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL resetnl : STD_ULOGIC;
127 SIGNAL clk2x : STD_ULOGIC;
128 SIGNAL lclk2x : STD_ULOGIC;
129 SIGNAL lclk25MHz : STD_ULOGIC;
130 SIGNAL lclk50MHz : STD_ULOGIC;
131 SIGNAL lclk100MHz : STD_ULOGIC;
132 SIGNAL clkm : STD_ULOGIC;
133 SIGNAL rstn : STD_ULOGIC;
134 SIGNAL rstraw : STD_ULOGIC;
135 SIGNAL pciclk : STD_ULOGIC;
136 SIGNAL sdclkl : STD_ULOGIC;
137 SIGNAL cgi : clkgen_in_type;
138 SIGNAL cgo : clkgen_out_type;
139 --- AHB / APB
140 SIGNAL apbi : apb_slv_in_type;
141 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
142 SIGNAL ahbsi : ahb_slv_in_type;
143 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
144 SIGNAL ahbmi : ahb_mst_in_type;
145 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
146 --UART
147 SIGNAL ahbuarti : uart_in_type;
148 SIGNAL ahbuarto : uart_out_type;
149 SIGNAL apbuarti : uart_in_type;
150 SIGNAL apbuarto : uart_out_type;
151 --MEM CTRLR
152 SIGNAL memi : memory_in_type;
153 SIGNAL memo : memory_out_type;
154 SIGNAL wpo : wprot_out_type;
155 SIGNAL sdo : sdram_out_type;
156 SIGNAL ramcs : STD_ULOGIC;
157 --IRQ
158 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
159 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
160 --Timer
161 SIGNAL gpti : gptimer_in_type;
162 SIGNAL gpto : gptimer_out_type;
163 --GPIO
164 SIGNAL gpioi : gpio_in_type;
165 SIGNAL gpioo : gpio_out_type;
166 --DSU
167 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
168 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
169 SIGNAL dsui : dsu_in_type;
170 SIGNAL dsuo : dsu_out_type;
171
172 ---------------------------------------------------------------------
173 --- AJOUT TEST ------------------------Signaux----------------------
174 ---------------------------------------------------------------------
175
176 ---------------------------------------------------------------------
177 CONSTANT IOAEN : INTEGER := CFG_CAN;
178 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
179
180 -- time management signal
181 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
183
184 -- Spacewire signals
185 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
186 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
187 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
188 SIGNAL spw_rxtxclk : STD_ULOGIC;
189 SIGNAL spw_rxclkn : STD_ULOGIC;
190 SIGNAL spw_clk : STD_LOGIC;
191 SIGNAL swni : grspw_in_type; -- PLE
192 SIGNAL swno : grspw_out_type; -- PLE
193 SIGNAL clkmn : STD_ULOGIC; -- PLE
194 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
195
196 -- AD Converter RHF1401
197 SIGNAL sample : Samples14v(7 DOWNTO 0);
198 SIGNAL sample_val : STD_LOGIC;
199 -----------------------------------------------------------------------------
200 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
201
202 BEGIN
203
204
205 ----------------------------------------------------------------------
206 --- Reset and Clock generation -------------------------------------
207 ----------------------------------------------------------------------
208
209 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
210 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
211
212 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
213
214
215 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
216
217 clkgen0 : clkgen -- clock generator
218 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
219 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
220 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
221
222 PROCESS(lclk100MHz)
223 BEGIN
224 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
225 lclk50MHz <= NOT lclk50MHz;
226 END IF;
227 END PROCESS;
228
229 PROCESS(lclk50MHz)
230 BEGIN
231 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
232 lclk25MHz <= NOT lclk25MHz;
233 END IF;
234 END PROCESS;
235
236 lclk2x <= lclk50MHz;
237 spw_clk <= lclk50MHz;
238
239 ----------------------------------------------------------------------
240 --- LEON3 processor / DSU / IRQ ------------------------------------
241 ----------------------------------------------------------------------
242
243 l3 : IF CFG_LEON3 = 1 GENERATE
244 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
245 u0 : leon3s -- LEON3 processor
246 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
247 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
248 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
249 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
250 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
251 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
252 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
253 irqi(i), irqo(i), dbgi(i), dbgo(i));
254 END GENERATE;
255 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
256
257 dsugen : IF CFG_DSU = 1 GENERATE
258 dsu0 : dsu3 -- LEON3 Debug Support Unit
259 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
260 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
261 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
262 dsui.enable <= '1';
263 dsui.break <= '0';
264 led(2) <= dsuo.active;
265 END GENERATE;
266 END GENERATE;
267
268 nodsu : IF CFG_DSU = 0 GENERATE
269 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
270 END GENERATE;
271
272 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
273 irqctrl0 : irqmp -- interrupt controller
274 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
275 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
276 END GENERATE;
277 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
278 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
279 irqi(i).irl <= "0000";
280 END GENERATE;
281 apbo(2) <= apb_none;
282 END GENERATE;
283
284 ----------------------------------------------------------------------
285 --- Memory controllers ---------------------------------------------
286 ----------------------------------------------------------------------
287 memctrlr : mctrl GENERIC MAP (
288 hindex => 0,
289 pindex => 0,
290 paddr => 0,
291 srbanks => 1
292 )
293 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
294
295 memi.brdyn <= '1';
296 memi.bexcn <= '1';
297 memi.writen <= '1';
298 memi.wrn <= "1111";
299 memi.bwidth <= "10";
300
301 bdr : FOR i IN 0 TO 3 GENERATE
302 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
303 PORT MAP (
304 data(31-i*8 DOWNTO 24-i*8),
305 memo.data(31-i*8 DOWNTO 24-i*8),
306 memo.bdrive(i),
307 memi.data(31-i*8 DOWNTO 24-i*8));
308 END GENERATE;
309
310 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
311 PORT MAP (address, memo.address(21 DOWNTO 2));
312
313 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
314 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
315 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
316 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
317 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
318 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
319 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
320
321 ----------------------------------------------------------------------
322 --- AHB CONTROLLER -------------------------------------------------
323 ----------------------------------------------------------------------
324 ahb0 : ahbctrl -- AHB arbiter/multiplexer
325 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
326 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
327 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
328 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
329
330 ----------------------------------------------------------------------
331 --- AHB UART -------------------------------------------------------
332 ----------------------------------------------------------------------
333 dcomgen : IF CFG_AHB_UART = 1 GENERATE
334 dcom0 : ahbuart
335 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
336 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
337 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
338 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
339 led(0) <= NOT ahbuarti.rxd;
340 led(1) <= NOT ahbuarto.txd;
341 END GENERATE;
342 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
343
344 ----------------------------------------------------------------------
345 --- APB Bridge -----------------------------------------------------
346 ----------------------------------------------------------------------
347 apb0 : apbctrl -- AHB/APB bridge
348 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
349 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
350
351 ----------------------------------------------------------------------
352 --- GPT Timer ------------------------------------------------------
353 ----------------------------------------------------------------------
354 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
355 timer0 : gptimer -- timer unit
356 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
357 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
358 nbits => CFG_GPT_TW)
359 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
360 gpti.dhalt <= dsuo.tstop;
361 gpti.extclk <= '0';
362 END GENERATE;
363 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
364
365
366 ----------------------------------------------------------------------
367 --- APB UART -------------------------------------------------------
368 ----------------------------------------------------------------------
369 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
370 uart1 : apbuart -- UART 1
371 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
372 fifosize => CFG_UART1_FIFO)
373 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
374 apbuarti.rxd <= urxd1;
375 apbuarti.extclk <= '0';
376 utxd1 <= apbuarto.txd;
377 apbuarti.ctsn <= '0';
378 END GENERATE;
379 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
380
381 -------------------------------------------------------------------------------
382 -- APB_DAC --------------------------------------------------------------------
383 -------------------------------------------------------------------------------
384 APB_DAC_1: APB_DAC
385 GENERIC MAP (
386 pindex => 14,
387 paddr => 14,
388 pmask => 16#fff#,
389 pirq => 13,
390 abits => 8)
391 PORT MAP (
392 clk => clk,
393 rst => rst,
394 apbi => apbi,
395 apbo => apbo(14),
396
397 Cal_EN => SCM_CAL_EN,
398 SYNC => SCM_CAL_nSYNC,
399 SCLK => SCM_CAL_SCLK,
400 DATA => SCM_CAL_DIN);
401
402 -------------------------------------------------------------------------------
403 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
404 -------------------------------------------------------------------------------
405 apb_lfr_time_management_1: apb_lfr_time_management
406 GENERIC MAP (
407 pindex => 6,
408 paddr => 6,
409 pmask => 16#fff#,
410 pirq => 12)
411 PORT MAP (
412 clk25MHz => clkm,
413 clk49_152MHz => clk49_152MHz,
414 resetn => rstn,
415 grspw_tick => swno.tickout,
416 apbi => apbi,
417 apbo => apbo(6),
418 coarse_time => coarse_time,
419 fine_time => fine_time);
420
421 -----------------------------------------------------------------------
422 --- SpaceWire --------------------------------------------------------
423 -----------------------------------------------------------------------
424
425 spw_rxtxclk <= spw_clk;
426 spw_rxclkn <= NOT spw_rxtxclk;
427
428 -- PADS for SPW1
429 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
430 PORT MAP (spw1_din, dtmp(0));
431 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
432 PORT MAP (spw1_sin, stmp(0));
433 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
434 PORT MAP (spw1_dout, swno.d(0));
435 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
436 PORT MAP (spw1_sout, swno.s(0));
437 -- PADS FOR SPW2
438 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
439 PORT MAP (spw2_din, dtmp(1));
440 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
441 PORT MAP (spw2_sin, stmp(1));
442 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
443 PORT MAP (spw2_dout, swno.d(1));
444 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
445 PORT MAP (spw2_sout, swno.s(1));
446
447 -- GRSPW PHY
448 --spw1_input: if CFG_SPW_GRSPW = 1 generate
449 spw_inputloop : FOR j IN 0 TO 1 GENERATE
450 spw_phy0 : grspw_phy
451 GENERIC MAP(
452 tech => fabtech,
453 rxclkbuftype => 1,
454 scantest => 0)
455 PORT MAP(
456 rxrst => swno.rxrst,
457 di => dtmp(j),
458 si => stmp(j),
459 rxclko => spw_rxclk(j),
460 do => swni.d(j),
461 ndo => swni.nd(j*5+4 DOWNTO j*5),
462 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
463 END GENERATE spw_inputloop;
464
465 -- SPW core
466 sw0 : grspwm
467 GENERIC MAP(
468 tech => apa3e,
469 hindex => 1,
470 pindex => 5,
471 paddr => 5,
472 pirq => 11,
473 sysfreq => 25000, -- CPU_FREQ
474 rmap => 1,
475 rmapcrc => 1,
476 fifosize1 => 16,
477 fifosize2 => 16,
478 rxclkbuftype => 1,
479 rxunaligned => 0,
480 rmapbufs => 4,
481 ft => 0,
482 netlist => 0,
483 ports => 2,
484 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
485 memtech => apa3e,
486 destkey => 2,
487 spwcore => 1
488 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
489 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
490 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
491 )
492 PORT MAP(rstn, clkm, spw_rxclk(0),
493 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
494 ahbmi, ahbmo(1), apbi, apbo(5),
495 swni, swno);
496
497 swni.tickin <= '0';
498 swni.rmapen <= '1';
499 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
500 swni.tickinraw <= '0';
501 swni.timein <= (OTHERS => '0');
502 swni.dcrstval <= (OTHERS => '0');
503 swni.timerrstval <= (OTHERS => '0');
504
505 -------------------------------------------------------------------------------
506 -- LFR
507 -------------------------------------------------------------------------------
508 lpp_lfr_1 : lpp_lfr
509 GENERIC MAP (
510 Mem_use => use_RAM,
511 nb_data_by_buffer_size => 32,
512 nb_word_by_buffer_size => 30,
513 nb_snapshot_param_size => 32,
514 delta_vector_size => 32,
515 delta_vector_size_f0_2 => 7, -- log2(96)
516 pindex => 15,
517 paddr => 15,
518 pmask => 16#fff#,
519 pirq_ms => 6,
520 pirq_wfp => 14,
521 hindex => 2,
522 top_lfr_version => X"00000005")
523 PORT MAP (
524 clk => clkm,
525 rstn => rstn,
526 sample_B => sample(2 DOWNTO 0),
527 sample_E => sample(7 DOWNTO 3),
528 sample_val => sample_val,
529 apbi => apbi,
530 apbo => apbo(15),
531 ahbi => ahbmi,
532 ahbo => ahbmo(2),
533 coarse_time => coarse_time,
534 fine_time => fine_time,
535 data_shaping_BW => bias_fail_sw);
536
537 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
538 GENERIC MAP (
539 ChanelCount => 8,
540 ncycle_cnv_high => 79,
541 ncycle_cnv => 500)
542 PORT MAP (
543 cnv_clk => clk49_152MHz,
544 cnv_rstn => rstn,
545 cnv => ADC_smpclk,
546 clk => clkm,
547 rstn => rstn,
548 ADC_data => ADC_data,
549 ADC_nOE => ADC_OEB_bar_CH,
550 sample => sample,
551 sample_val => sample_val);
552
553 END Behavioral;
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@@ -1,50 +1,51
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 #VHDLSIMFILES=testbench.vhd
16 #VHDLSIMFILES=testbench.vhd
17 #SIMTOP=testbench
17 #SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
22 CLEAN=soft-clean
23
23
24 TECHLIBS = proasic3e
24 TECHLIBS = proasic3e
25
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
35 ./lpp_bootloader \
36 ./lpp_cna \
36 ./lpp_cna \
37 ./lpp_uart \
37 ./lpp_uart \
38 ./lpp_usb \
38 ./lpp_usb \
39
39
40 FILESKIP = i2cmst.vhd \
40 FILESKIP = lpp_lfr_ms.vhd \
41 i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45 APB_FFT.vhd
45
46
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48 include $(GRLIB)/software/leon3/Makefile
48
49
49 ################## project specific targets ##########################
50 ################## project specific targets ##########################
50
51
Show file before | Show file after | Hide comments
@@ -1,524 +1,544
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
44
45 ENTITY leon3mp IS
45 ENTITY leon3mp IS
46 GENERIC (
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
53 pclow : INTEGER := CFG_PCLOW
54 );
54 );
55 PORT (
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
59
60 errorn : OUT STD_ULOGIC;
60 errorn : OUT STD_ULOGIC;
61
61
62 -- UART AHB ---------------------------------------------------------------
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
65
66 -- UART APB ---------------------------------------------------------------
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
69
70 -- RAM --------------------------------------------------------------------
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
80
81 -- SPW --------------------------------------------------------------------
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
91
92 -- ADC --------------------------------------------------------------------
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
97
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
100 );
101 END;
101 END;
102
102
103 ARCHITECTURE Behavioral OF leon3mp IS
103 ARCHITECTURE Behavioral OF leon3mp IS
104
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART
108 CFG_AHB_UART
109 +2;
109 +2;
110 -- 1 is for the SpaceWire module grspw, which is a master
110 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the LFR
111 -- 1 is for the LFR
112
112
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
114
114
115 --Clk & Rst gοΏ½nοΏ½
115 --Clk & Rst gοΏ½nοΏ½
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL resetnl : STD_ULOGIC;
118 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL cgi : clkgen_in_type;
129 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgo : clkgen_out_type;
130 SIGNAL cgo : clkgen_out_type;
131 --- AHB / APB
131 --- AHB / APB
132 SIGNAL apbi : apb_slv_in_type;
132 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL ahbsi : ahb_slv_in_type;
134 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbmi : ahb_mst_in_type;
136 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 --UART
138 --UART
139 SIGNAL ahbuarti : uart_in_type;
139 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarto : uart_out_type;
140 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL apbuarti : uart_in_type;
141 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarto : uart_out_type;
142 SIGNAL apbuarto : uart_out_type;
143 --MEM CTRLR
143 --MEM CTRLR
144 SIGNAL memi : memory_in_type;
144 SIGNAL memi : memory_in_type;
145 SIGNAL memo : memory_out_type;
145 SIGNAL memo : memory_out_type;
146 SIGNAL wpo : wprot_out_type;
146 SIGNAL wpo : wprot_out_type;
147 SIGNAL sdo : sdram_out_type;
147 SIGNAL sdo : sdram_out_type;
148 SIGNAL ramcs : STD_ULOGIC;
148 SIGNAL ramcs : STD_ULOGIC;
149 --IRQ
149 --IRQ
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 --Timer
152 --Timer
153 SIGNAL gpti : gptimer_in_type;
153 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpto : gptimer_out_type;
154 SIGNAL gpto : gptimer_out_type;
155 --GPIO
155 --GPIO
156 SIGNAL gpioi : gpio_in_type;
156 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioo : gpio_out_type;
157 SIGNAL gpioo : gpio_out_type;
158 --DSU
158 --DSU
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dsui : dsu_in_type;
161 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsuo : dsu_out_type;
162 SIGNAL dsuo : dsu_out_type;
163
163
164 ---------------------------------------------------------------------
164 ---------------------------------------------------------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
166 ---------------------------------------------------------------------
166 ---------------------------------------------------------------------
167
167
168 ---------------------------------------------------------------------
168 ---------------------------------------------------------------------
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171
171
172 -- time management signal
172 -- time management signal
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175
175
176 -- Spacewire signals
176 -- Spacewire signals
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
183 SIGNAL swni : grspw_in_type; -- PLE
183 SIGNAL swni : grspw_in_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
187
187
188 -- AD Converter RHF1401
188 -- AD Converter RHF1401
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
190 SIGNAL sample_val : STD_LOGIC;
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193 -----------------------------------------------------------------------------
194 SIGNAL debug_f0_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
195 SIGNAL debug_f0_data_valid : STD_LOGIC;
196 SIGNAL debug_f1_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
197 SIGNAL debug_f1_data_valid : STD_LOGIC;
198 SIGNAL debug_f2_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
199 SIGNAL debug_f2_data_valid : STD_LOGIC;
200 SIGNAL debug_f3_data : STD_LOGIC_VECTOR(95 DOWNTO 0);
201 SIGNAL debug_f3_data_valid : STD_LOGIC;
193
202
194 BEGIN
203 BEGIN
195
204
196
205
197 ----------------------------------------------------------------------
206 ----------------------------------------------------------------------
198 --- Reset and Clock generation -------------------------------------
207 --- Reset and Clock generation -------------------------------------
199 ----------------------------------------------------------------------
208 ----------------------------------------------------------------------
200
209
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
210 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
211 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203
212
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
213 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
205
214
206
215
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
216 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
208
217
209 clkgen0 : clkgen -- clock generator
218 clkgen0 : clkgen -- clock generator
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
219 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
220 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
221 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
213
222
214 PROCESS(lclk100MHz)
223 PROCESS(lclk100MHz)
215 BEGIN
224 BEGIN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
225 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
217 lclk50MHz <= NOT lclk50MHz;
226 lclk50MHz <= NOT lclk50MHz;
218 END IF;
227 END IF;
219 END PROCESS;
228 END PROCESS;
220
229
221 PROCESS(lclk50MHz)
230 PROCESS(lclk50MHz)
222 BEGIN
231 BEGIN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
232 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
224 lclk25MHz <= NOT lclk25MHz;
233 lclk25MHz <= NOT lclk25MHz;
225 END IF;
234 END IF;
226 END PROCESS;
235 END PROCESS;
227
236
228 lclk2x <= lclk50MHz;
237 lclk2x <= lclk50MHz;
229 spw_clk <= lclk50MHz;
238 spw_clk <= lclk50MHz;
230
239
231 ----------------------------------------------------------------------
240 ----------------------------------------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
241 --- LEON3 processor / DSU / IRQ ------------------------------------
233 ----------------------------------------------------------------------
242 ----------------------------------------------------------------------
234
243
235 l3 : IF CFG_LEON3 = 1 GENERATE
244 l3 : IF CFG_LEON3 = 1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
245 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
237 u0 : leon3s -- LEON3 processor
246 u0 : leon3s -- LEON3 processor
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
247 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
248 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
249 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
250 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
251 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
252 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
253 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
254 irqi(i), irqo(i), dbgi(i), dbgo(i));
246 END GENERATE;
255 END GENERATE;
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
256 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
248
257
249 dsugen : IF CFG_DSU = 1 GENERATE
258 dsugen : IF CFG_DSU = 1 GENERATE
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
259 dsu0 : dsu3 -- LEON3 Debug Support Unit
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
260 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
261 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
262 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
254 dsui.enable <= '1';
263 dsui.enable <= '1';
255 dsui.break <= '0';
264 dsui.break <= '0';
256 led(2) <= dsuo.active;
265 led(2) <= dsuo.active;
257 END GENERATE;
266 END GENERATE;
258 END GENERATE;
267 END GENERATE;
259
268
260 nodsu : IF CFG_DSU = 0 GENERATE
269 nodsu : IF CFG_DSU = 0 GENERATE
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
270 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
262 END GENERATE;
271 END GENERATE;
263
272
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
273 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
265 irqctrl0 : irqmp -- interrupt controller
274 irqctrl0 : irqmp -- interrupt controller
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
275 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
276 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
268 END GENERATE;
277 END GENERATE;
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
278 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
279 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
271 irqi(i).irl <= "0000";
280 irqi(i).irl <= "0000";
272 END GENERATE;
281 END GENERATE;
273 apbo(2) <= apb_none;
282 apbo(2) <= apb_none;
274 END GENERATE;
283 END GENERATE;
275
284
276 ----------------------------------------------------------------------
285 ----------------------------------------------------------------------
277 --- Memory controllers ---------------------------------------------
286 --- Memory controllers ---------------------------------------------
278 ----------------------------------------------------------------------
287 ----------------------------------------------------------------------
279 memctrlr : mctrl GENERIC MAP (
288 memctrlr : mctrl GENERIC MAP (
280 hindex => 0,
289 hindex => 0,
281 pindex => 0,
290 pindex => 0,
282 paddr => 0,
291 paddr => 0,
283 srbanks => 1
292 srbanks => 1
284 )
293 )
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
294 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
286
295
287 memi.brdyn <= '1';
296 memi.brdyn <= '1';
288 memi.bexcn <= '1';
297 memi.bexcn <= '1';
289 memi.writen <= '1';
298 memi.writen <= '1';
290 memi.wrn <= "1111";
299 memi.wrn <= "1111";
291 memi.bwidth <= "10";
300 memi.bwidth <= "10";
292
301
293 bdr : FOR i IN 0 TO 3 GENERATE
302 bdr : FOR i IN 0 TO 3 GENERATE
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
303 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
295 PORT MAP (
304 PORT MAP (
296 data(31-i*8 DOWNTO 24-i*8),
305 data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
306 memo.data(31-i*8 DOWNTO 24-i*8),
298 memo.bdrive(i),
307 memo.bdrive(i),
299 memi.data(31-i*8 DOWNTO 24-i*8));
308 memi.data(31-i*8 DOWNTO 24-i*8));
300 END GENERATE;
309 END GENERATE;
301
310
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
311 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
303 PORT MAP (address, memo.address(21 DOWNTO 2));
312 PORT MAP (address, memo.address(21 DOWNTO 2));
304
313
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
314 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
315 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
316 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
317 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
318 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
319 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
320 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
312
321
313 ----------------------------------------------------------------------
322 ----------------------------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
323 --- AHB CONTROLLER -------------------------------------------------
315 ----------------------------------------------------------------------
324 ----------------------------------------------------------------------
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
325 ahb0 : ahbctrl -- AHB arbiter/multiplexer
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
326 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
327 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
328 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
329 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
321
330
322 ----------------------------------------------------------------------
331 ----------------------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
332 --- AHB UART -------------------------------------------------------
324 ----------------------------------------------------------------------
333 ----------------------------------------------------------------------
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
334 dcomgen : IF CFG_AHB_UART = 1 GENERATE
326 dcom0 : ahbuart
335 dcom0 : ahbuart
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
336 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
337 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
338 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
339 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
331 led(0) <= NOT ahbuarti.rxd;
340 led(0) <= NOT ahbuarti.rxd;
332 led(1) <= NOT ahbuarto.txd;
341 led(1) <= NOT ahbuarto.txd;
333 END GENERATE;
342 END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
343 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
335
344
336 ----------------------------------------------------------------------
345 ----------------------------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
346 --- APB Bridge -----------------------------------------------------
338 ----------------------------------------------------------------------
347 ----------------------------------------------------------------------
339 apb0 : apbctrl -- AHB/APB bridge
348 apb0 : apbctrl -- AHB/APB bridge
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
349 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
350 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
342
351
343 ----------------------------------------------------------------------
352 ----------------------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
353 --- GPT Timer ------------------------------------------------------
345 ----------------------------------------------------------------------
354 ----------------------------------------------------------------------
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
355 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
347 timer0 : gptimer -- timer unit
356 timer0 : gptimer -- timer unit
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
357 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
358 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
350 nbits => CFG_GPT_TW)
359 nbits => CFG_GPT_TW)
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
360 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
352 gpti.dhalt <= dsuo.tstop;
361 gpti.dhalt <= dsuo.tstop;
353 gpti.extclk <= '0';
362 gpti.extclk <= '0';
354 END GENERATE;
363 END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
364 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
356
365
357
366
358 ----------------------------------------------------------------------
367 ----------------------------------------------------------------------
359 --- APB UART -------------------------------------------------------
368 --- APB UART -------------------------------------------------------
360 ----------------------------------------------------------------------
369 ----------------------------------------------------------------------
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
370 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
362 uart1 : apbuart -- UART 1
371 uart1 : apbuart -- UART 1
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
372 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
364 fifosize => CFG_UART1_FIFO)
373 fifosize => CFG_UART1_FIFO)
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
374 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
366 apbuarti.rxd <= urxd1;
375 apbuarti.rxd <= urxd1;
367 apbuarti.extclk <= '0';
376 apbuarti.extclk <= '0';
368 utxd1 <= apbuarto.txd;
377 utxd1 <= apbuarto.txd;
369 apbuarti.ctsn <= '0';
378 apbuarti.ctsn <= '0';
370 END GENERATE;
379 END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
380 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
372
381
373 -------------------------------------------------------------------------------
382 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
383 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
384 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1: apb_lfr_time_management
385 apb_lfr_time_management_1: apb_lfr_time_management
377 GENERIC MAP (
386 GENERIC MAP (
378 pindex => 6,
387 pindex => 6,
379 paddr => 6,
388 paddr => 6,
380 pmask => 16#fff#,
389 pmask => 16#fff#,
381 pirq => 12)
390 pirq => 12)
382 PORT MAP (
391 PORT MAP (
383 clk25MHz => clkm,
392 clk25MHz => clkm,
384 clk49_152MHz => clk49_152MHz,
393 clk49_152MHz => clk49_152MHz,
385 resetn => rstn,
394 resetn => rstn,
386 grspw_tick => swno.tickout,
395 grspw_tick => swno.tickout,
387 apbi => apbi,
396 apbi => apbi,
388 apbo => apbo(6),
397 apbo => apbo(6),
389 coarse_time => coarse_time,
398 coarse_time => coarse_time,
390 fine_time => fine_time);
399 fine_time => fine_time);
391
400
392 -----------------------------------------------------------------------
401 -----------------------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
402 --- SpaceWire --------------------------------------------------------
394 -----------------------------------------------------------------------
403 -----------------------------------------------------------------------
395
404
396 spw_rxtxclk <= spw_clk;
405 spw_rxtxclk <= spw_clk;
397 spw_rxclkn <= NOT spw_rxtxclk;
406 spw_rxclkn <= NOT spw_rxtxclk;
398
407
399 -- PADS for SPW1
408 -- PADS for SPW1
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
409 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw1_din, dtmp(0));
410 PORT MAP (spw1_din, dtmp(0));
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
411 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw1_sin, stmp(0));
412 PORT MAP (spw1_sin, stmp(0));
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
413 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw1_dout, swno.d(0));
414 PORT MAP (spw1_dout, swno.d(0));
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
415 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
407 PORT MAP (spw1_sout, swno.s(0));
416 PORT MAP (spw1_sout, swno.s(0));
408 -- PADS FOR SPW2
417 -- PADS FOR SPW2
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
418 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
410 PORT MAP (spw2_din, dtmp(1));
419 PORT MAP (spw2_din, dtmp(1));
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
420 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
412 PORT MAP (spw2_sin, stmp(1));
421 PORT MAP (spw2_sin, stmp(1));
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
422 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
414 PORT MAP (spw2_dout, swno.d(1));
423 PORT MAP (spw2_dout, swno.d(1));
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
424 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
416 PORT MAP (spw2_sout, swno.s(1));
425 PORT MAP (spw2_sout, swno.s(1));
417
426
418 -- GRSPW PHY
427 -- GRSPW PHY
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
428 --spw1_input: if CFG_SPW_GRSPW = 1 generate
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
429 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
430 spw_phy0 : grspw_phy
422 GENERIC MAP(
431 GENERIC MAP(
423 tech => fabtech,
432 tech => fabtech,
424 rxclkbuftype => 1,
433 rxclkbuftype => 1,
425 scantest => 0)
434 scantest => 0)
426 PORT MAP(
435 PORT MAP(
427 rxrst => swno.rxrst,
436 rxrst => swno.rxrst,
428 di => dtmp(j),
437 di => dtmp(j),
429 si => stmp(j),
438 si => stmp(j),
430 rxclko => spw_rxclk(j),
439 rxclko => spw_rxclk(j),
431 do => swni.d(j),
440 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
441 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
442 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
443 END GENERATE spw_inputloop;
435
444
436 -- SPW core
445 -- SPW core
437 sw0 : grspwm
446 sw0 : grspwm
438 GENERIC MAP(
447 GENERIC MAP(
439 tech => apa3e,
448 tech => apa3e,
440 hindex => 1,
449 hindex => 1,
441 pindex => 5,
450 pindex => 5,
442 paddr => 5,
451 paddr => 5,
443 pirq => 11,
452 pirq => 11,
444 sysfreq => 25000, -- CPU_FREQ
453 sysfreq => 25000, -- CPU_FREQ
445 rmap => 1,
454 rmap => 1,
446 rmapcrc => 1,
455 rmapcrc => 1,
447 fifosize1 => 16,
456 fifosize1 => 16,
448 fifosize2 => 16,
457 fifosize2 => 16,
449 rxclkbuftype => 1,
458 rxclkbuftype => 1,
450 rxunaligned => 0,
459 rxunaligned => 0,
451 rmapbufs => 4,
460 rmapbufs => 4,
452 ft => 0,
461 ft => 0,
453 netlist => 0,
462 netlist => 0,
454 ports => 2,
463 ports => 2,
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
464 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
456 memtech => apa3e,
465 memtech => apa3e,
457 destkey => 2,
466 destkey => 2,
458 spwcore => 1
467 spwcore => 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
468 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
469 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
470 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
462 )
471 )
463 PORT MAP(rstn, clkm, spw_rxclk(0),
472 PORT MAP(rstn, clkm, spw_rxclk(0),
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
473 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
465 ahbmi, ahbmo(1), apbi, apbo(5),
474 ahbmi, ahbmo(1), apbi, apbo(5),
466 swni, swno);
475 swni, swno);
467
476
468 swni.tickin <= '0';
477 swni.tickin <= '0';
469 swni.rmapen <= '1';
478 swni.rmapen <= '1';
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
479 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
471 swni.tickinraw <= '0';
480 swni.tickinraw <= '0';
472 swni.timein <= (OTHERS => '0');
481 swni.timein <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
482 swni.dcrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
483 swni.timerrstval <= (OTHERS => '0');
475
484
476 -------------------------------------------------------------------------------
485 -------------------------------------------------------------------------------
477 -- LFR
486 -- LFR
478 -------------------------------------------------------------------------------
487 -------------------------------------------------------------------------------
479 lpp_lfr_1 : lpp_lfr
488 lpp_lfr_1 : lpp_lfr
480 GENERIC MAP (
489 GENERIC MAP (
481 Mem_use => use_RAM,
490 Mem_use => use_RAM,
482 nb_data_by_buffer_size => 32,
491 nb_data_by_buffer_size => 32,
483 nb_word_by_buffer_size => 30,
492 nb_word_by_buffer_size => 30,
484 nb_snapshot_param_size => 32,
493 nb_snapshot_param_size => 32,
485 delta_vector_size => 32,
494 delta_vector_size => 32,
486 delta_vector_size_f0_2 => 7, -- log2(96)
495 delta_vector_size_f0_2 => 7, -- log2(96)
487 pindex => 15,
496 pindex => 15,
488 paddr => 15,
497 paddr => 15,
489 pmask => 16#fff#,
498 pmask => 16#fff#,
490 pirq_ms => 6,
499 pirq_ms => 6,
491 pirq_wfp => 14,
500 pirq_wfp => 14,
492 hindex => 2,
501 hindex => 2,
493 top_lfr_version => X"00000005")
502 top_lfr_version => X"00000007")
494 PORT MAP (
503 PORT MAP (
495 clk => clkm,
504 clk => clkm,
496 rstn => rstn,
505 rstn => rstn,
497 sample_B => sample(2 DOWNTO 0),
506 sample_B => sample(2 DOWNTO 0),
498 sample_E => sample(7 DOWNTO 3),
507 sample_E => sample(7 DOWNTO 3),
499 sample_val => sample_val,
508 sample_val => sample_val,
500 apbi => apbi,
509 apbi => apbi,
501 apbo => apbo(15),
510 apbo => apbo(15),
502 ahbi => ahbmi,
511 ahbi => ahbmi,
503 ahbo => ahbmo(2),
512 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
513 coarse_time => coarse_time,
505 fine_time => fine_time,
514 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
515 data_shaping_BW => bias_fail_sw,
516
517 -------------------------------------------------------------------------
518 debug_f0_data => debug_f0_data ,
519 debug_f0_data_valid => debug_f0_data_valid,
520 debug_f1_data => debug_f1_data ,
521 debug_f1_data_valid => debug_f1_data_valid,
522 debug_f2_data => debug_f2_data ,
523 debug_f2_data_valid => debug_f2_data_valid,
524 debug_f3_data => debug_f3_data ,
525 debug_f3_data_valid => debug_f3_data_valid
526 );
507
527
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
528 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
529 GENERIC MAP (
510 ChanelCount => 8,
530 ChanelCount => 8,
511 ncycle_cnv_high => 79,
531 ncycle_cnv_high => 79,
512 ncycle_cnv => 500)
532 ncycle_cnv => 500)
513 PORT MAP (
533 PORT MAP (
514 cnv_clk => clk49_152MHz,
534 cnv_clk => clk49_152MHz,
515 cnv_rstn => rstn,
535 cnv_rstn => rstn,
516 cnv => ADC_smpclk,
536 cnv => ADC_smpclk,
517 clk => clkm,
537 clk => clkm,
518 rstn => rstn,
538 rstn => rstn,
519 ADC_data => ADC_data,
539 ADC_data => ADC_data,
520 ADC_nOE => ADC_OEB_bar_CH,
540 ADC_nOE => ADC_OEB_bar_CH,
521 sample => sample,
541 sample => sample,
522 sample_val => sample_val);
542 sample_val => sample_val);
523
543
524 END Behavioral;
544 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,658 +1,695
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63
63
64 --debug
64 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
66 debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
68 debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
70 debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
72 debug_f3_data_valid : OUT STD_LOGIC
73 );
73 );
74 END lpp_lfr;
74 END lpp_lfr;
75
75
76 ARCHITECTURE beh OF lpp_lfr IS
76 ARCHITECTURE beh OF lpp_lfr IS
77 SIGNAL sample : Samples14v(7 DOWNTO 0);
77 SIGNAL sample : Samples14v(7 DOWNTO 0);
78 SIGNAL sample_s : Samples(7 DOWNTO 0);
78 SIGNAL sample_s : Samples(7 DOWNTO 0);
79 --
79 --
80 SIGNAL data_shaping_SP0 : STD_LOGIC;
80 SIGNAL data_shaping_SP0 : STD_LOGIC;
81 SIGNAL data_shaping_SP1 : STD_LOGIC;
81 SIGNAL data_shaping_SP1 : STD_LOGIC;
82 SIGNAL data_shaping_R0 : STD_LOGIC;
82 SIGNAL data_shaping_R0 : STD_LOGIC;
83 SIGNAL data_shaping_R1 : STD_LOGIC;
83 SIGNAL data_shaping_R1 : STD_LOGIC;
84 --
84 --
85 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
88 --
89 SIGNAL sample_f0_val : STD_LOGIC;
89 SIGNAL sample_f0_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f2_val : STD_LOGIC;
91 SIGNAL sample_f2_val : STD_LOGIC;
92 SIGNAL sample_f3_val : STD_LOGIC;
92 SIGNAL sample_f3_val : STD_LOGIC;
93 --
93 --
94 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
98 --
98 --
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102
102
103 -- SM
103 -- SM
104 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
105 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
108 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
109 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL error_bad_component_error : STD_LOGIC;
110 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
115 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
116 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL status_error_bad_component_error : STD_LOGIC;
117 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
118 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL config_active_interruption_onError : STD_LOGIC;
119 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
123
123
124 -- WFP
124 -- WFP
125 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
129 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
130 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
130 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
131 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
131 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
132 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
132 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
134
134
135 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
135 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
136 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
136 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
137 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
137 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
138 SIGNAL enable_f0 : STD_LOGIC;
138 SIGNAL enable_f0 : STD_LOGIC;
139 SIGNAL enable_f1 : STD_LOGIC;
139 SIGNAL enable_f1 : STD_LOGIC;
140 SIGNAL enable_f2 : STD_LOGIC;
140 SIGNAL enable_f2 : STD_LOGIC;
141 SIGNAL enable_f3 : STD_LOGIC;
141 SIGNAL enable_f3 : STD_LOGIC;
142 SIGNAL burst_f0 : STD_LOGIC;
142 SIGNAL burst_f0 : STD_LOGIC;
143 SIGNAL burst_f1 : STD_LOGIC;
143 SIGNAL burst_f1 : STD_LOGIC;
144 SIGNAL burst_f2 : STD_LOGIC;
144 SIGNAL burst_f2 : STD_LOGIC;
145 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149
149
150 SIGNAL run : STD_LOGIC;
150 SIGNAL run : STD_LOGIC;
151 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
151 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
152
152
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f0_data_out_ren : STD_LOGIC;
157 SIGNAL data_f0_data_out_ren : STD_LOGIC;
158 --f1
158 --f1
159 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f1_data_out_valid : STD_LOGIC;
161 SIGNAL data_f1_data_out_valid : STD_LOGIC;
162 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
162 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f1_data_out_ren : STD_LOGIC;
163 SIGNAL data_f1_data_out_ren : STD_LOGIC;
164 --f2
164 --f2
165 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 SIGNAL data_f2_data_out_valid : STD_LOGIC;
167 SIGNAL data_f2_data_out_valid : STD_LOGIC;
168 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
168 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
169 SIGNAL data_f2_data_out_ren : STD_LOGIC;
169 SIGNAL data_f2_data_out_ren : STD_LOGIC;
170 --f3
170 --f3
171 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL data_f3_data_out_valid : STD_LOGIC;
173 SIGNAL data_f3_data_out_valid : STD_LOGIC;
174 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
174 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
175 SIGNAL data_f3_data_out_ren : STD_LOGIC;
175 SIGNAL data_f3_data_out_ren : STD_LOGIC;
176
176
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178 --
178 --
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
181 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
182 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
182 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
183 --f1
183 --f1
184 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
185 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
186 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
186 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
187 --f2
187 --f2
188 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
189 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
190 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
190 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
191 --f3
191 --f3
192 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
193 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
194 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
194 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
195
195
196 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
197 -- DMA RR
197 -- DMA RR
198 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
199 SIGNAL dma_sel_valid : STD_LOGIC;
199 SIGNAL dma_sel_valid : STD_LOGIC;
200 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- DMA_REG
205 -- DMA_REG
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 SIGNAL ongoing_reg : STD_LOGIC;
207 SIGNAL ongoing_reg : STD_LOGIC;
208 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
208 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 SIGNAL dma_send_reg : STD_LOGIC;
209 SIGNAL dma_send_reg : STD_LOGIC;
210 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
210 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
211 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
213
213
214
214
215 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
216 -- DMA
216 -- DMA
217 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
218 SIGNAL dma_send : STD_LOGIC;
218 SIGNAL dma_send : STD_LOGIC;
219 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
219 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
220 SIGNAL dma_done : STD_LOGIC;
220 SIGNAL dma_done : STD_LOGIC;
221 SIGNAL dma_ren : STD_LOGIC;
221 SIGNAL dma_ren : STD_LOGIC;
222 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
226 -----------------------------------------------------------------------------
227 -- DEBUG
228 -----------------------------------------------------------------------------
229 --
230 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
231 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
232 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
233 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
234
235 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
243
226 BEGIN
244 BEGIN
227
245
228 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
246 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
229 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
247 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
230
248
231 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
249 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
232 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
250 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
233 END GENERATE all_channel;
251 END GENERATE all_channel;
234
252
235 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
236 lpp_lfr_filter_1 : lpp_lfr_filter
254 lpp_lfr_filter_1 : lpp_lfr_filter
237 GENERIC MAP (
255 GENERIC MAP (
238 Mem_use => Mem_use)
256 Mem_use => Mem_use)
239 PORT MAP (
257 PORT MAP (
240 sample => sample_s,
258 sample => sample_s,
241 sample_val => sample_val,
259 sample_val => sample_val,
242 clk => clk,
260 clk => clk,
243 rstn => rstn,
261 rstn => rstn,
244 data_shaping_SP0 => data_shaping_SP0,
262 data_shaping_SP0 => data_shaping_SP0,
245 data_shaping_SP1 => data_shaping_SP1,
263 data_shaping_SP1 => data_shaping_SP1,
246 data_shaping_R0 => data_shaping_R0,
264 data_shaping_R0 => data_shaping_R0,
247 data_shaping_R1 => data_shaping_R1,
265 data_shaping_R1 => data_shaping_R1,
248 sample_f0_val => sample_f0_val,
266 sample_f0_val => sample_f0_val,
249 sample_f1_val => sample_f1_val,
267 sample_f1_val => sample_f1_val,
250 sample_f2_val => sample_f2_val,
268 sample_f2_val => sample_f2_val,
251 sample_f3_val => sample_f3_val,
269 sample_f3_val => sample_f3_val,
252 sample_f0_wdata => sample_f0_data,
270 sample_f0_wdata => sample_f0_data,
253 sample_f1_wdata => sample_f1_data,
271 sample_f1_wdata => sample_f1_data,
254 sample_f2_wdata => sample_f2_data,
272 sample_f2_wdata => sample_f2_data,
255 sample_f3_wdata => sample_f3_data);
273 sample_f3_wdata => sample_f3_data);
256
274
257 -----------------------------------------------------------------------------
275 -----------------------------------------------------------------------------
258 lpp_lfr_apbreg_1: lpp_lfr_apbreg
276 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
259 GENERIC MAP (
277 GENERIC MAP (
260 nb_data_by_buffer_size => nb_data_by_buffer_size,
278 nb_data_by_buffer_size => nb_data_by_buffer_size,
261 nb_word_by_buffer_size => nb_word_by_buffer_size,
279 nb_word_by_buffer_size => nb_word_by_buffer_size,
262 nb_snapshot_param_size => nb_snapshot_param_size,
280 nb_snapshot_param_size => nb_snapshot_param_size,
263 delta_vector_size => delta_vector_size,
281 delta_vector_size => delta_vector_size,
264 delta_vector_size_f0_2 => delta_vector_size_f0_2,
282 delta_vector_size_f0_2 => delta_vector_size_f0_2,
265 pindex => pindex,
283 pindex => pindex,
266 paddr => paddr,
284 paddr => paddr,
267 pmask => pmask,
285 pmask => pmask,
268 pirq_ms => pirq_ms,
286 pirq_ms => pirq_ms,
269 pirq_wfp => pirq_wfp,
287 pirq_wfp => pirq_wfp,
270 top_lfr_version => top_lfr_version)
288 top_lfr_version => top_lfr_version)
271 PORT MAP (
289 PORT MAP (
272 HCLK => clk,
290 HCLK => clk,
273 HRESETn => rstn,
291 HRESETn => rstn,
274 apbi => apbi,
292 apbi => apbi,
275 apbo => apbo,
293 apbo => apbo,
276 ready_matrix_f0_0 => ready_matrix_f0_0,
294 ready_matrix_f0_0 => ready_matrix_f0_0,
277 ready_matrix_f0_1 => ready_matrix_f0_1,
295 ready_matrix_f0_1 => ready_matrix_f0_1,
278 ready_matrix_f1 => ready_matrix_f1,
296 ready_matrix_f1 => ready_matrix_f1,
279 ready_matrix_f2 => ready_matrix_f2,
297 ready_matrix_f2 => ready_matrix_f2,
280 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
298 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
281 error_bad_component_error => error_bad_component_error,
299 error_bad_component_error => error_bad_component_error,
282 debug_reg => debug_reg,
300 debug_reg => debug_reg,
283 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
301 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
284 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
302 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
285 status_ready_matrix_f1 => status_ready_matrix_f1,
303 status_ready_matrix_f1 => status_ready_matrix_f1,
286 status_ready_matrix_f2 => status_ready_matrix_f2,
304 status_ready_matrix_f2 => status_ready_matrix_f2,
287 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
305 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
288 status_error_bad_component_error => status_error_bad_component_error,
306 status_error_bad_component_error => status_error_bad_component_error,
289 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
307 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
290 config_active_interruption_onError => config_active_interruption_onError,
308 config_active_interruption_onError => config_active_interruption_onError,
291 addr_matrix_f0_0 => addr_matrix_f0_0,
309 addr_matrix_f0_0 => addr_matrix_f0_0,
292 addr_matrix_f0_1 => addr_matrix_f0_1,
310 addr_matrix_f0_1 => addr_matrix_f0_1,
293 addr_matrix_f1 => addr_matrix_f1,
311 addr_matrix_f1 => addr_matrix_f1,
294 addr_matrix_f2 => addr_matrix_f2,
312 addr_matrix_f2 => addr_matrix_f2,
295 status_full => status_full,
313 status_full => status_full,
296 status_full_ack => status_full_ack,
314 status_full_ack => status_full_ack,
297 status_full_err => status_full_err,
315 status_full_err => status_full_err,
298 status_new_err => status_new_err,
316 status_new_err => status_new_err,
299 data_shaping_BW => data_shaping_BW,
317 data_shaping_BW => data_shaping_BW,
300 data_shaping_SP0 => data_shaping_SP0,
318 data_shaping_SP0 => data_shaping_SP0,
301 data_shaping_SP1 => data_shaping_SP1,
319 data_shaping_SP1 => data_shaping_SP1,
302 data_shaping_R0 => data_shaping_R0,
320 data_shaping_R0 => data_shaping_R0,
303 data_shaping_R1 => data_shaping_R1,
321 data_shaping_R1 => data_shaping_R1,
304 delta_snapshot => delta_snapshot,
322 delta_snapshot => delta_snapshot,
305 delta_f0 => delta_f0,
323 delta_f0 => delta_f0,
306 delta_f0_2 => delta_f0_2,
324 delta_f0_2 => delta_f0_2,
307 delta_f1 => delta_f1,
325 delta_f1 => delta_f1,
308 delta_f2 => delta_f2,
326 delta_f2 => delta_f2,
309 nb_data_by_buffer => nb_data_by_buffer,
327 nb_data_by_buffer => nb_data_by_buffer,
310 nb_word_by_buffer => nb_word_by_buffer,
328 nb_word_by_buffer => nb_word_by_buffer,
311 nb_snapshot_param => nb_snapshot_param,
329 nb_snapshot_param => nb_snapshot_param,
312 enable_f0 => enable_f0,
330 enable_f0 => enable_f0,
313 enable_f1 => enable_f1,
331 enable_f1 => enable_f1,
314 enable_f2 => enable_f2,
332 enable_f2 => enable_f2,
315 enable_f3 => enable_f3,
333 enable_f3 => enable_f3,
316 burst_f0 => burst_f0,
334 burst_f0 => burst_f0,
317 burst_f1 => burst_f1,
335 burst_f1 => burst_f1,
318 burst_f2 => burst_f2,
336 burst_f2 => burst_f2,
319 run => run,
337 run => run,
320 addr_data_f0 => addr_data_f0,
338 addr_data_f0 => addr_data_f0,
321 addr_data_f1 => addr_data_f1,
339 addr_data_f1 => addr_data_f1,
322 addr_data_f2 => addr_data_f2,
340 addr_data_f2 => addr_data_f2,
323 addr_data_f3 => addr_data_f3,
341 addr_data_f3 => addr_data_f3,
324 start_date => start_date);
342 start_date => start_date,
343 ---------------------------------------------------------------------------
344 debug_reg0 => debug_reg0,
345 debug_reg1 => debug_reg1,
346 debug_reg2 => debug_reg2,
347 debug_reg3 => debug_reg3,
348 debug_reg4 => debug_reg4,
349 debug_reg5 => debug_reg5,
350 debug_reg6 => debug_reg6,
351 debug_reg7 => debug_reg7);
352
353 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
354 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
355 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
356 -----------------------------------------------------------------------------
357 sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
358 sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
359 sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
360 sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
361
325
362
326 -----------------------------------------------------------------------------
363 -----------------------------------------------------------------------------
327 lpp_waveform_1: lpp_waveform
364 lpp_waveform_1 : lpp_waveform
328 GENERIC MAP (
365 GENERIC MAP (
329 tech => inferred,
366 tech => inferred,
330 data_size => 6*16,
367 data_size => 6*16,
331 nb_data_by_buffer_size => nb_data_by_buffer_size,
368 nb_data_by_buffer_size => nb_data_by_buffer_size,
332 nb_word_by_buffer_size => nb_word_by_buffer_size,
369 nb_word_by_buffer_size => nb_word_by_buffer_size,
333 nb_snapshot_param_size => nb_snapshot_param_size,
370 nb_snapshot_param_size => nb_snapshot_param_size,
334 delta_vector_size => delta_vector_size,
371 delta_vector_size => delta_vector_size,
335 delta_vector_size_f0_2 => delta_vector_size_f0_2
372 delta_vector_size_f0_2 => delta_vector_size_f0_2
336 )
373 )
337 PORT MAP (
374 PORT MAP (
338 clk => clk,
375 clk => clk,
339 rstn => rstn,
376 rstn => rstn,
340
377
341 reg_run => run,
378 reg_run => run,
342 reg_start_date => start_date,
379 reg_start_date => start_date,
343 reg_delta_snapshot => delta_snapshot,
380 reg_delta_snapshot => delta_snapshot,
344 reg_delta_f0 => delta_f0,
381 reg_delta_f0 => delta_f0,
345 reg_delta_f0_2 => delta_f0_2,
382 reg_delta_f0_2 => delta_f0_2,
346 reg_delta_f1 => delta_f1,
383 reg_delta_f1 => delta_f1,
347 reg_delta_f2 => delta_f2,
384 reg_delta_f2 => delta_f2,
348
385
349 enable_f0 => enable_f0,
386 enable_f0 => enable_f0,
350 enable_f1 => enable_f1,
387 enable_f1 => enable_f1,
351 enable_f2 => enable_f2,
388 enable_f2 => enable_f2,
352 enable_f3 => enable_f3,
389 enable_f3 => enable_f3,
353 burst_f0 => burst_f0,
390 burst_f0 => burst_f0,
354 burst_f1 => burst_f1,
391 burst_f1 => burst_f1,
355 burst_f2 => burst_f2,
392 burst_f2 => burst_f2,
356
393
357 nb_data_by_buffer => nb_data_by_buffer,
394 nb_data_by_buffer => nb_data_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
395 nb_word_by_buffer => nb_word_by_buffer,
359 nb_snapshot_param => nb_snapshot_param,
396 nb_snapshot_param => nb_snapshot_param,
360 status_full => status_full,
397 status_full => status_full,
361 status_full_ack => status_full_ack,
398 status_full_ack => status_full_ack,
362 status_full_err => status_full_err,
399 status_full_err => status_full_err,
363 status_new_err => status_new_err,
400 status_new_err => status_new_err,
364
401
365 coarse_time => coarse_time,
402 coarse_time => coarse_time,
366 fine_time => fine_time,
403 fine_time => fine_time,
367
404
368 --f0
405 --f0
369 addr_data_f0 => addr_data_f0,
406 addr_data_f0 => addr_data_f0,
370 data_f0_in_valid => sample_f0_val,
407 data_f0_in_valid => sample_f0_val,
371 data_f0_in => sample_f0_data,
408 data_f0_in => sample_f0_data_debug, -- TODO : debug
372 --f1
409 --f1
373 addr_data_f1 => addr_data_f1,
410 addr_data_f1 => addr_data_f1,
374 data_f1_in_valid => sample_f1_val,
411 data_f1_in_valid => sample_f1_val,
375 data_f1_in => sample_f1_data,
412 data_f1_in => sample_f1_data_debug, -- TODO : debug,
376 --f2
413 --f2
377 addr_data_f2 => addr_data_f2,
414 addr_data_f2 => addr_data_f2,
378 data_f2_in_valid => sample_f2_val,
415 data_f2_in_valid => sample_f2_val,
379 data_f2_in => sample_f2_data,
416 data_f2_in => sample_f2_data_debug, -- TODO : debug,
380 --f3
417 --f3
381 addr_data_f3 => addr_data_f3,
418 addr_data_f3 => addr_data_f3,
382 data_f3_in_valid => sample_f3_val,
419 data_f3_in_valid => sample_f3_val,
383 data_f3_in => sample_f3_data,
420 data_f3_in => sample_f3_data_debug, -- TODO : debug,
384 -- OUTPUT -- DMA interface
421 -- OUTPUT -- DMA interface
385 --f0
422 --f0
386 data_f0_addr_out => data_f0_addr_out_s,
423 data_f0_addr_out => data_f0_addr_out_s,
387 data_f0_data_out => data_f0_data_out,
424 data_f0_data_out => data_f0_data_out,
388 data_f0_data_out_valid => data_f0_data_out_valid_s,
425 data_f0_data_out_valid => data_f0_data_out_valid_s,
389 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
426 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
390 data_f0_data_out_ren => data_f0_data_out_ren,
427 data_f0_data_out_ren => data_f0_data_out_ren,
391 --f1
428 --f1
392 data_f1_addr_out => data_f1_addr_out_s,
429 data_f1_addr_out => data_f1_addr_out_s,
393 data_f1_data_out => data_f1_data_out,
430 data_f1_data_out => data_f1_data_out,
394 data_f1_data_out_valid => data_f1_data_out_valid_s,
431 data_f1_data_out_valid => data_f1_data_out_valid_s,
395 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
432 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
396 data_f1_data_out_ren => data_f1_data_out_ren,
433 data_f1_data_out_ren => data_f1_data_out_ren,
397 --f2
434 --f2
398 data_f2_addr_out => data_f2_addr_out_s,
435 data_f2_addr_out => data_f2_addr_out_s,
399 data_f2_data_out => data_f2_data_out,
436 data_f2_data_out => data_f2_data_out,
400 data_f2_data_out_valid => data_f2_data_out_valid_s,
437 data_f2_data_out_valid => data_f2_data_out_valid_s,
401 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
438 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
402 data_f2_data_out_ren => data_f2_data_out_ren,
439 data_f2_data_out_ren => data_f2_data_out_ren,
403 --f3
440 --f3
404 data_f3_addr_out => data_f3_addr_out_s,
441 data_f3_addr_out => data_f3_addr_out_s,
405 data_f3_data_out => data_f3_data_out,
442 data_f3_data_out => data_f3_data_out,
406 data_f3_data_out_valid => data_f3_data_out_valid_s,
443 data_f3_data_out_valid => data_f3_data_out_valid_s,
407 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
444 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
408 data_f3_data_out_ren => data_f3_data_out_ren,
445 data_f3_data_out_ren => data_f3_data_out_ren,
409
446
410 --debug
447 --debug
411 debug_f0_data => debug_f0_data,
448 debug_f0_data => debug_f0_data,
412 debug_f0_data_valid => debug_f0_data_valid ,
449 debug_f0_data_valid => debug_f0_data_valid ,
413 debug_f1_data => debug_f1_data ,
450 debug_f1_data => debug_f1_data ,
414 debug_f1_data_valid => debug_f1_data_valid,
451 debug_f1_data_valid => debug_f1_data_valid,
415 debug_f2_data => debug_f2_data ,
452 debug_f2_data => debug_f2_data ,
416 debug_f2_data_valid => debug_f2_data_valid ,
453 debug_f2_data_valid => debug_f2_data_valid ,
417 debug_f3_data => debug_f3_data ,
454 debug_f3_data => debug_f3_data ,
418 debug_f3_data_valid => debug_f3_data_valid
455 debug_f3_data_valid => debug_f3_data_valid
419
456
420 );
457 );
421
458
422
459
423 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
424 -- TEMP
461 -- TEMP
425 -----------------------------------------------------------------------------
462 -----------------------------------------------------------------------------
426
463
427 PROCESS (clk, rstn)
464 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
465 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
466 IF rstn = '0' THEN -- asynchronous reset (active low)
430 data_f0_data_out_valid <= '0';
467 data_f0_data_out_valid <= '0';
431 data_f0_data_out_valid_burst <= '0';
468 data_f0_data_out_valid_burst <= '0';
432 data_f1_data_out_valid <= '0';
469 data_f1_data_out_valid <= '0';
433 data_f1_data_out_valid_burst <= '0';
470 data_f1_data_out_valid_burst <= '0';
434 data_f2_data_out_valid <= '0';
471 data_f2_data_out_valid <= '0';
435 data_f2_data_out_valid_burst <= '0';
472 data_f2_data_out_valid_burst <= '0';
436 data_f3_data_out_valid <= '0';
473 data_f3_data_out_valid <= '0';
437 data_f3_data_out_valid_burst <= '0';
474 data_f3_data_out_valid_burst <= '0';
438 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
475 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
439 data_f0_data_out_valid <= data_f0_data_out_valid_s;
476 data_f0_data_out_valid <= data_f0_data_out_valid_s;
440 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
477 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
441 data_f1_data_out_valid <= data_f1_data_out_valid_s;
478 data_f1_data_out_valid <= data_f1_data_out_valid_s;
442 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
479 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
443 data_f2_data_out_valid <= data_f2_data_out_valid_s;
480 data_f2_data_out_valid <= data_f2_data_out_valid_s;
444 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
481 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
445 data_f3_data_out_valid <= data_f3_data_out_valid_s;
482 data_f3_data_out_valid <= data_f3_data_out_valid_s;
446 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
483 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
447 END IF;
484 END IF;
448 END PROCESS;
485 END PROCESS;
449
486
450 data_f0_addr_out <= data_f0_addr_out_s;
487 data_f0_addr_out <= data_f0_addr_out_s;
451 data_f1_addr_out <= data_f1_addr_out_s;
488 data_f1_addr_out <= data_f1_addr_out_s;
452 data_f2_addr_out <= data_f2_addr_out_s;
489 data_f2_addr_out <= data_f2_addr_out_s;
453 data_f3_addr_out <= data_f3_addr_out_s;
490 data_f3_addr_out <= data_f3_addr_out_s;
454
491
455 -----------------------------------------------------------------------------
492 -----------------------------------------------------------------------------
456 -- RoundRobin Selection For DMA
493 -- RoundRobin Selection For DMA
457 -----------------------------------------------------------------------------
494 -----------------------------------------------------------------------------
458
495
459 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
496 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
460 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
497 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
461 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
498 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
462 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
499 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
463
500
464 RR_Arbiter_4_1: RR_Arbiter_4
501 RR_Arbiter_4_1 : RR_Arbiter_4
465 PORT MAP (
502 PORT MAP (
466 clk => clk,
503 clk => clk,
467 rstn => rstn,
504 rstn => rstn,
468 in_valid => dma_rr_valid,
505 in_valid => dma_rr_valid,
469 out_grant => dma_rr_grant);
506 out_grant => dma_rr_grant);
470
507
471
508
472 -----------------------------------------------------------------------------
509 -----------------------------------------------------------------------------
473 -- in : dma_rr_grant
510 -- in : dma_rr_grant
474 -- send
511 -- send
475 -- out : dma_sel
512 -- out : dma_sel
476 -- dma_valid_burst
513 -- dma_valid_burst
477 -- dma_sel_valid
514 -- dma_sel_valid
478 -----------------------------------------------------------------------------
515 -----------------------------------------------------------------------------
479 PROCESS (clk, rstn)
516 PROCESS (clk, rstn)
480 BEGIN -- PROCESS
517 BEGIN -- PROCESS
481 IF rstn = '0' THEN -- asynchronous reset (active low)
518 IF rstn = '0' THEN -- asynchronous reset (active low)
482 dma_sel <= (OTHERS => '0');
519 dma_sel <= (OTHERS => '0');
483 dma_send <= '0';
520 dma_send <= '0';
484 dma_valid_burst <= '0';
521 dma_valid_burst <= '0';
485 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
522 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
486 -- IF dma_sel = "0000" OR dma_send = '1' THEN
523 -- IF dma_sel = "0000" OR dma_send = '1' THEN
487 IF dma_sel = "0000" OR dma_done = '1' THEN
524 IF dma_sel = "0000" OR dma_done = '1' THEN
488 dma_sel <= dma_rr_grant;
525 dma_sel <= dma_rr_grant;
489 IF dma_rr_grant(0) = '1' THEN
526 IF dma_rr_grant(0) = '1' THEN
490 dma_send <= '1';
527 dma_send <= '1';
491 dma_valid_burst <= data_f0_data_out_valid_burst;
528 dma_valid_burst <= data_f0_data_out_valid_burst;
492 dma_sel_valid <= data_f0_data_out_valid;
529 dma_sel_valid <= data_f0_data_out_valid;
493 ELSIF dma_rr_grant(1) = '1' THEN
530 ELSIF dma_rr_grant(1) = '1' THEN
494 dma_send <= '1';
531 dma_send <= '1';
495 dma_valid_burst <= data_f1_data_out_valid_burst;
532 dma_valid_burst <= data_f1_data_out_valid_burst;
496 dma_sel_valid <= data_f1_data_out_valid;
533 dma_sel_valid <= data_f1_data_out_valid;
497 ELSIF dma_rr_grant(2) = '1' THEN
534 ELSIF dma_rr_grant(2) = '1' THEN
498 dma_send <= '1';
535 dma_send <= '1';
499 dma_valid_burst <= data_f2_data_out_valid_burst;
536 dma_valid_burst <= data_f2_data_out_valid_burst;
500 dma_sel_valid <= data_f2_data_out_valid;
537 dma_sel_valid <= data_f2_data_out_valid;
501 ELSIF dma_rr_grant(3) = '1' THEN
538 ELSIF dma_rr_grant(3) = '1' THEN
502 dma_send <= '1';
539 dma_send <= '1';
503 dma_valid_burst <= data_f3_data_out_valid_burst;
540 dma_valid_burst <= data_f3_data_out_valid_burst;
504 dma_sel_valid <= data_f3_data_out_valid;
541 dma_sel_valid <= data_f3_data_out_valid;
505 END IF;
542 END IF;
506 ELSE
543 ELSE
507 dma_sel <= dma_sel;
544 dma_sel <= dma_sel;
508 dma_send <= '0';
545 dma_send <= '0';
509 END IF;
546 END IF;
510 END IF;
547 END IF;
511 END PROCESS;
548 END PROCESS;
512
549
513
550
514 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
551 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
515 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
552 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
516 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
553 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
517 data_f3_addr_out ;
554 data_f3_addr_out;
518
555
519 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
556 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
520 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
557 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
521 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
558 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
522 data_f3_data_out ;
559 data_f3_data_out;
523
560
524 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
561 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
525 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
562 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
526 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
563 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
527 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
564 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
528 -- '0';
565 -- '0';
529
566
530 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
567 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
531 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
568 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
532 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
569 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
533 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
570 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
534 -- '0';
571 -- '0';
535
572
536 -- TODO
573 -- TODO
537 --dma_send <= dma_sel_valid OR dma_valid_burst;
574 --dma_send <= dma_sel_valid OR dma_valid_burst;
538
575
539 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
576 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
540 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
577 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
541 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
578 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
542 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
579 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
543
580
544 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
581 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
545 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
582 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
546 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
583 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
547 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
584 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
548
585
549
586
550 --PROCESS (clk, rstn)
587 --PROCESS (clk, rstn)
551 --BEGIN -- PROCESS
588 --BEGIN -- PROCESS
552 -- IF rstn = '0' THEN -- asynchronous reset (active low)
589 -- IF rstn = '0' THEN -- asynchronous reset (active low)
553 -- ongoing_reg <= '0';
590 -- ongoing_reg <= '0';
554 -- dma_sel_reg <= (OTHERS => '0');
591 -- dma_sel_reg <= (OTHERS => '0');
555 -- dma_send_reg <= '0';
592 -- dma_send_reg <= '0';
556 -- dma_valid_burst_reg <= '0';
593 -- dma_valid_burst_reg <= '0';
557 -- dma_address_reg <= (OTHERS => '0');
594 -- dma_address_reg <= (OTHERS => '0');
558 -- dma_data_reg <= (OTHERS => '0');
595 -- dma_data_reg <= (OTHERS => '0');
559 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
596 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
560 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
597 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
561 -- ongoing_reg <= '1';
598 -- ongoing_reg <= '1';
562 -- dma_valid_burst_reg <= dma_valid_burst;
599 -- dma_valid_burst_reg <= dma_valid_burst;
563 -- dma_sel_reg <= dma_sel;
600 -- dma_sel_reg <= dma_sel;
564 -- ELSE
601 -- ELSE
565 -- IF dma_done = '1' THEN
602 -- IF dma_done = '1' THEN
566 -- ongoing_reg <= '0';
603 -- ongoing_reg <= '0';
567 -- END IF;
604 -- END IF;
568 -- END IF;
605 -- END IF;
569 -- dma_send_reg <= dma_send;
606 -- dma_send_reg <= dma_send;
570 -- dma_address_reg <= dma_address;
607 -- dma_address_reg <= dma_address;
571 -- dma_data_reg <= dma_data;
608 -- dma_data_reg <= dma_data;
572 -- END IF;
609 -- END IF;
573 --END PROCESS;
610 --END PROCESS;
574
611
575 dma_data_2 <= dma_data;
612 dma_data_2 <= dma_data;
576 --PROCESS (clk, rstn)
613 --PROCESS (clk, rstn)
577 --BEGIN -- PROCESS
614 --BEGIN -- PROCESS
578 -- IF rstn = '0' THEN -- asynchronous reset (active low)
615 -- IF rstn = '0' THEN -- asynchronous reset (active low)
579 -- dma_data_2 <= (OTHERS => '0');
616 -- dma_data_2 <= (OTHERS => '0');
580 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
617 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
581 -- dma_data_2 <= dma_data;
618 -- dma_data_2 <= dma_data;
582
619
583 -- END IF;
620 -- END IF;
584 --END PROCESS;
621 --END PROCESS;
585
622
586
623
587 -----------------------------------------------------------------------------
624 -----------------------------------------------------------------------------
588 -- DMA
625 -- DMA
589 -----------------------------------------------------------------------------
626 -----------------------------------------------------------------------------
590 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
627 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
591 GENERIC MAP (
628 GENERIC MAP (
592 tech => inferred,
629 tech => inferred,
593 hindex => hindex)
630 hindex => hindex)
594 PORT MAP (
631 PORT MAP (
595 HCLK => clk,
632 HCLK => clk,
596 HRESETn => rstn,
633 HRESETn => rstn,
597 run => run,
634 run => run,
598 AHB_Master_In => ahbi,
635 AHB_Master_In => ahbi,
599 AHB_Master_Out => ahbo,
636 AHB_Master_Out => ahbo,
600
637
601 send => dma_send,--_reg,
638 send => dma_send, --_reg,
602 valid_burst => dma_valid_burst,--_reg,
639 valid_burst => dma_valid_burst, --_reg,
603 done => dma_done,
640 done => dma_done,
604 ren => dma_ren,
641 ren => dma_ren,
605 address => dma_address,--_reg,
642 address => dma_address, --_reg,
606 data => dma_data_2);--_reg);
643 data => dma_data_2); --_reg);
607
644
608 -----------------------------------------------------------------------------
645 -----------------------------------------------------------------------------
609 -- Matrix Spectral - TODO
646 -- Matrix Spectral - TODO
610 -----------------------------------------------------------------------------
647 -----------------------------------------------------------------------------
611 -----------------------------------------------------------------------------
648 -----------------------------------------------------------------------------
612 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
649 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
613 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
650 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
614 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
651 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
615 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
652 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
616 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
653 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
617 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
654 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
618
655
619 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
656 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
620 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
657 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
621 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
658 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
622 -------------------------------------------------------------------------------
659 -------------------------------------------------------------------------------
623 --lpp_lfr_ms_1: lpp_lfr_ms
660 --lpp_lfr_ms_1: lpp_lfr_ms
624 -- GENERIC MAP (
661 -- GENERIC MAP (
625 -- hindex => hindex_ms)
662 -- hindex => hindex_ms)
626 -- PORT MAP (
663 -- PORT MAP (
627 -- clk => clk,
664 -- clk => clk,
628 -- rstn => rstn,
665 -- rstn => rstn,
629 -- sample_f0_wen => sample_f0_wen,
666 -- sample_f0_wen => sample_f0_wen,
630 -- sample_f0_wdata => sample_f0_wdata,
667 -- sample_f0_wdata => sample_f0_wdata,
631 -- sample_f1_wen => sample_f1_wen,
668 -- sample_f1_wen => sample_f1_wen,
632 -- sample_f1_wdata => sample_f1_wdata,
669 -- sample_f1_wdata => sample_f1_wdata,
633 -- sample_f3_wen => sample_f3_wen,
670 -- sample_f3_wen => sample_f3_wen,
634 -- sample_f3_wdata => sample_f3_wdata,
671 -- sample_f3_wdata => sample_f3_wdata,
635 -- AHB_Master_In => ahbi_ms,
672 -- AHB_Master_In => ahbi_ms,
636 -- AHB_Master_Out => ahbo_ms,
673 -- AHB_Master_Out => ahbo_ms,
637
674
638 -- ready_matrix_f0_0 => ready_matrix_f0_0,
675 -- ready_matrix_f0_0 => ready_matrix_f0_0,
639 -- ready_matrix_f0_1 => ready_matrix_f0_1,
676 -- ready_matrix_f0_1 => ready_matrix_f0_1,
640 -- ready_matrix_f1 => ready_matrix_f1,
677 -- ready_matrix_f1 => ready_matrix_f1,
641 -- ready_matrix_f2 => ready_matrix_f2,
678 -- ready_matrix_f2 => ready_matrix_f2,
642 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
679 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
643 -- error_bad_component_error => error_bad_component_error,
680 -- error_bad_component_error => error_bad_component_error,
644 -- debug_reg => debug_reg,
681 -- debug_reg => debug_reg,
645 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
682 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
646 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
683 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
647 -- status_ready_matrix_f1 => status_ready_matrix_f1,
684 -- status_ready_matrix_f1 => status_ready_matrix_f1,
648 -- status_ready_matrix_f2 => status_ready_matrix_f2,
685 -- status_ready_matrix_f2 => status_ready_matrix_f2,
649 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
686 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
650 -- status_error_bad_component_error => status_error_bad_component_error,
687 -- status_error_bad_component_error => status_error_bad_component_error,
651 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
688 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
652 -- config_active_interruption_onError => config_active_interruption_onError,
689 -- config_active_interruption_onError => config_active_interruption_onError,
653 -- addr_matrix_f0_0 => addr_matrix_f0_0,
690 -- addr_matrix_f0_0 => addr_matrix_f0_0,
654 -- addr_matrix_f0_1 => addr_matrix_f0_1,
691 -- addr_matrix_f0_1 => addr_matrix_f0_1,
655 -- addr_matrix_f1 => addr_matrix_f1,
692 -- addr_matrix_f1 => addr_matrix_f1,
656 -- addr_matrix_f2 => addr_matrix_f2);
693 -- addr_matrix_f2 => addr_matrix_f2);
657
694
658 END beh;
695 END beh;
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@@ -1,475 +1,493
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 -- IN
62 -- IN
63 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
70
71 -- OUT
71 -- OUT
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78
78
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
87 -- WaveForm picker Reg
87 -- WaveForm picker Reg
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92
92
93 -- OUT
93 -- OUT
94 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_BW : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
99
99
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108
108
109 enable_f0 : OUT STD_LOGIC;
109 enable_f0 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
113
113
114 burst_f0 : OUT STD_LOGIC;
114 burst_f0 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
117
117
118 run : OUT STD_LOGIC;
118 run : OUT STD_LOGIC;
119
119
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 ---------------------------------------------------------------------------
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
125
134
126 ---------------------------------------------------------------------------
135 ---------------------------------------------------------------------------
127 );
136 );
128
137
129 END lpp_lfr_apbreg;
138 END lpp_lfr_apbreg;
130
139
131 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
132
141
133 CONSTANT REVISION : INTEGER := 1;
142 CONSTANT REVISION : INTEGER := 1;
134
143
135 CONSTANT pconfig : apb_config_type := (
144 CONSTANT pconfig : apb_config_type := (
136 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
137 1 => apb_iobar(paddr, pmask));
146 1 => apb_iobar(paddr, pmask));
138
147
139 TYPE lpp_SpectralMatrix_regs IS RECORD
148 TYPE lpp_SpectralMatrix_regs IS RECORD
140 config_active_interruption_onNewMatrix : STD_LOGIC;
149 config_active_interruption_onNewMatrix : STD_LOGIC;
141 config_active_interruption_onError : STD_LOGIC;
150 config_active_interruption_onError : STD_LOGIC;
142 status_ready_matrix_f0_0 : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
143 status_ready_matrix_f0_1 : STD_LOGIC;
152 status_ready_matrix_f0_1 : STD_LOGIC;
144 status_ready_matrix_f1 : STD_LOGIC;
153 status_ready_matrix_f1 : STD_LOGIC;
145 status_ready_matrix_f2 : STD_LOGIC;
154 status_ready_matrix_f2 : STD_LOGIC;
146 status_error_anticipating_empty_fifo : STD_LOGIC;
155 status_error_anticipating_empty_fifo : STD_LOGIC;
147 status_error_bad_component_error : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
148 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 END RECORD;
161 END RECORD;
153 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
154
163
155 TYPE lpp_WaveformPicker_regs IS RECORD
164 TYPE lpp_WaveformPicker_regs IS RECORD
156 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 data_shaping_BW : STD_LOGIC;
168 data_shaping_BW : STD_LOGIC;
160 data_shaping_SP0 : STD_LOGIC;
169 data_shaping_SP0 : STD_LOGIC;
161 data_shaping_SP1 : STD_LOGIC;
170 data_shaping_SP1 : STD_LOGIC;
162 data_shaping_R0 : STD_LOGIC;
171 data_shaping_R0 : STD_LOGIC;
163 data_shaping_R1 : STD_LOGIC;
172 data_shaping_R1 : STD_LOGIC;
164 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
167 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
170 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
171 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
172 enable_f0 : STD_LOGIC;
181 enable_f0 : STD_LOGIC;
173 enable_f1 : STD_LOGIC;
182 enable_f1 : STD_LOGIC;
174 enable_f2 : STD_LOGIC;
183 enable_f2 : STD_LOGIC;
175 enable_f3 : STD_LOGIC;
184 enable_f3 : STD_LOGIC;
176 burst_f0 : STD_LOGIC;
185 burst_f0 : STD_LOGIC;
177 burst_f1 : STD_LOGIC;
186 burst_f1 : STD_LOGIC;
178 burst_f2 : STD_LOGIC;
187 burst_f2 : STD_LOGIC;
179 run : STD_LOGIC;
188 run : STD_LOGIC;
180 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
185 END RECORD;
194 END RECORD;
186 SIGNAL reg_wp : lpp_WaveformPicker_regs;
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
187
196
188 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
189
198
190 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
191 -- IRQ
200 -- IRQ
192 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
193 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
194 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
195 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
196 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
197 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
198 SIGNAL ored_irq_wfp : STD_LOGIC;
207 SIGNAL ored_irq_wfp : STD_LOGIC;
199
208
200 BEGIN -- beh
209 BEGIN -- beh
201
210
202 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
203 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
204 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
205 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
206 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
207 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
208
217
209 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
210 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
211 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
212 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
213 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
214 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
215
224
216
225
217 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
218 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
219 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
220 data_shaping_R0 <= reg_wp.data_shaping_R0;
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
221 data_shaping_R1 <= reg_wp.data_shaping_R1;
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
222
231
223 delta_snapshot <= reg_wp.delta_snapshot;
232 delta_snapshot <= reg_wp.delta_snapshot;
224 delta_f0 <= reg_wp.delta_f0;
233 delta_f0 <= reg_wp.delta_f0;
225 delta_f0_2 <= reg_wp.delta_f0_2;
234 delta_f0_2 <= reg_wp.delta_f0_2;
226 delta_f1 <= reg_wp.delta_f1;
235 delta_f1 <= reg_wp.delta_f1;
227 delta_f2 <= reg_wp.delta_f2;
236 delta_f2 <= reg_wp.delta_f2;
228 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
229 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
230 nb_snapshot_param <= reg_wp.nb_snapshot_param;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
231
240
232 enable_f0 <= reg_wp.enable_f0;
241 enable_f0 <= reg_wp.enable_f0;
233 enable_f1 <= reg_wp.enable_f1;
242 enable_f1 <= reg_wp.enable_f1;
234 enable_f2 <= reg_wp.enable_f2;
243 enable_f2 <= reg_wp.enable_f2;
235 enable_f3 <= reg_wp.enable_f3;
244 enable_f3 <= reg_wp.enable_f3;
236
245
237 burst_f0 <= reg_wp.burst_f0;
246 burst_f0 <= reg_wp.burst_f0;
238 burst_f1 <= reg_wp.burst_f1;
247 burst_f1 <= reg_wp.burst_f1;
239 burst_f2 <= reg_wp.burst_f2;
248 burst_f2 <= reg_wp.burst_f2;
240
249
241 run <= reg_wp.run;
250 run <= reg_wp.run;
242
251
243 addr_data_f0 <= reg_wp.addr_data_f0;
252 addr_data_f0 <= reg_wp.addr_data_f0;
244 addr_data_f1 <= reg_wp.addr_data_f1;
253 addr_data_f1 <= reg_wp.addr_data_f1;
245 addr_data_f2 <= reg_wp.addr_data_f2;
254 addr_data_f2 <= reg_wp.addr_data_f2;
246 addr_data_f3 <= reg_wp.addr_data_f3;
255 addr_data_f3 <= reg_wp.addr_data_f3;
247
256
248 start_date <= reg_wp.start_date;
257 start_date <= reg_wp.start_date;
249
258
250 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
251 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
252 BEGIN -- PROCESS lpp_dma_top
261 BEGIN -- PROCESS lpp_dma_top
253 IF HRESETn = '0' THEN -- asynchronous reset (active low)
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
254 reg_sp.config_active_interruption_onNewMatrix <= '0';
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
255 reg_sp.config_active_interruption_onError <= '0';
264 reg_sp.config_active_interruption_onError <= '0';
256 reg_sp.status_ready_matrix_f0_0 <= '0';
265 reg_sp.status_ready_matrix_f0_0 <= '0';
257 reg_sp.status_ready_matrix_f0_1 <= '0';
266 reg_sp.status_ready_matrix_f0_1 <= '0';
258 reg_sp.status_ready_matrix_f1 <= '0';
267 reg_sp.status_ready_matrix_f1 <= '0';
259 reg_sp.status_ready_matrix_f2 <= '0';
268 reg_sp.status_ready_matrix_f2 <= '0';
260 reg_sp.status_error_anticipating_empty_fifo <= '0';
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
261 reg_sp.status_error_bad_component_error <= '0';
270 reg_sp.status_error_bad_component_error <= '0';
262 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
263 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
264 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
265 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
266 prdata <= (OTHERS => '0');
275 prdata <= (OTHERS => '0');
267
276
268 apbo.pirq <= (OTHERS => '0');
277 apbo.pirq <= (OTHERS => '0');
269
278
270 status_full_ack <= (OTHERS => '0');
279 status_full_ack <= (OTHERS => '0');
271
280
272 reg_wp.data_shaping_BW <= '0';
281 reg_wp.data_shaping_BW <= '0';
273 reg_wp.data_shaping_SP0 <= '0';
282 reg_wp.data_shaping_SP0 <= '0';
274 reg_wp.data_shaping_SP1 <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
275 reg_wp.data_shaping_R0 <= '0';
284 reg_wp.data_shaping_R0 <= '0';
276 reg_wp.data_shaping_R1 <= '0';
285 reg_wp.data_shaping_R1 <= '0';
277 reg_wp.enable_f0 <= '0';
286 reg_wp.enable_f0 <= '0';
278 reg_wp.enable_f1 <= '0';
287 reg_wp.enable_f1 <= '0';
279 reg_wp.enable_f2 <= '0';
288 reg_wp.enable_f2 <= '0';
280 reg_wp.enable_f3 <= '0';
289 reg_wp.enable_f3 <= '0';
281 reg_wp.burst_f0 <= '0';
290 reg_wp.burst_f0 <= '0';
282 reg_wp.burst_f1 <= '0';
291 reg_wp.burst_f1 <= '0';
283 reg_wp.burst_f2 <= '0';
292 reg_wp.burst_f2 <= '0';
284 reg_wp.run <= '0';
293 reg_wp.run <= '0';
285 reg_wp.addr_data_f0 <= (OTHERS => '0');
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
286 reg_wp.addr_data_f1 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
287 reg_wp.addr_data_f2 <= (OTHERS => '0');
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
288 reg_wp.addr_data_f3 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
289 reg_wp.status_full <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
290 reg_wp.status_full_err <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
291 reg_wp.status_new_err <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
292 reg_wp.delta_snapshot <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
293 reg_wp.delta_f0 <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
294 reg_wp.delta_f0_2 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
295 reg_wp.delta_f1 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
296 reg_wp.delta_f2 <= (OTHERS => '0');
305 reg_wp.delta_f2 <= (OTHERS => '0');
297 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
298 reg_wp.nb_snapshot_param <= (OTHERS => '0');
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
299 reg_wp.start_date <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
300
309
301 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
302 status_full_ack <= (OTHERS => '0');
311 status_full_ack <= (OTHERS => '0');
303
312
304 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
305 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
306 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
307 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
308
317
309 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
310 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
311 all_status: FOR I IN 3 DOWNTO 0 LOOP
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
312 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
313 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
314 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
315 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
316 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
317 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
318 END LOOP all_status;
327 END LOOP all_status;
319
328
320 paddr := "000000";
329 paddr := "000000";
321 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
322 prdata <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
323 IF apbi.psel(pindex) = '1' THEN
332 IF apbi.psel(pindex) = '1' THEN
324 -- APB DMA READ --
333 -- APB DMA READ --
325 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
326 --
335 --
327 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
328 prdata(1) <= reg_sp.config_active_interruption_onError;
337 prdata(1) <= reg_sp.config_active_interruption_onError;
329 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
330 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
331 prdata(2) <= reg_sp.status_ready_matrix_f1;
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
332 prdata(3) <= reg_sp.status_ready_matrix_f2;
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
333 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
334 prdata(5) <= reg_sp.status_error_bad_component_error;
343 prdata(5) <= reg_sp.status_error_bad_component_error;
335 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
336 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
337 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
338 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
339 WHEN "000110" => prdata <= debug_reg;
348 WHEN "000110" => prdata <= debug_reg;
340 --
349 --
341 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
342 prdata(1) <= reg_wp.data_shaping_SP0;
351 prdata(1) <= reg_wp.data_shaping_SP0;
343 prdata(2) <= reg_wp.data_shaping_SP1;
352 prdata(2) <= reg_wp.data_shaping_SP1;
344 prdata(3) <= reg_wp.data_shaping_R0;
353 prdata(3) <= reg_wp.data_shaping_R0;
345 prdata(4) <= reg_wp.data_shaping_R1;
354 prdata(4) <= reg_wp.data_shaping_R1;
346 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
347 prdata(1) <= reg_wp.enable_f1;
356 prdata(1) <= reg_wp.enable_f1;
348 prdata(2) <= reg_wp.enable_f2;
357 prdata(2) <= reg_wp.enable_f2;
349 prdata(3) <= reg_wp.enable_f3;
358 prdata(3) <= reg_wp.enable_f3;
350 prdata(4) <= reg_wp.burst_f0;
359 prdata(4) <= reg_wp.burst_f0;
351 prdata(5) <= reg_wp.burst_f1;
360 prdata(5) <= reg_wp.burst_f1;
352 prdata(6) <= reg_wp.burst_f2;
361 prdata(6) <= reg_wp.burst_f2;
353 prdata(7) <= reg_wp.run;
362 prdata(7) <= reg_wp.run;
354 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
355 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
356 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
357 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
358 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
359 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
360 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
361 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
362 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
363 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
364 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
365 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
366 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
367 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
368 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
369 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
370 ----------------------------------------------------
379 ----------------------------------------------------
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 ----------------------------------------------------
371 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
372 WHEN OTHERS => NULL;
390 WHEN OTHERS => NULL;
373 END CASE;
391 END CASE;
374 IF (apbi.pwrite AND apbi.penable) = '1' THEN
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
375 -- APB DMA WRITE --
393 -- APB DMA WRITE --
376 CASE paddr(7 DOWNTO 2) IS
394 CASE paddr(7 DOWNTO 2) IS
377 --
395 --
378 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
379 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
380 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
381 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
382 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
383 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
384 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
385 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
386 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
387 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
388 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
389 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
390 --
408 --
391 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
392 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
393 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
394 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
395 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
396 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
397 reg_wp.enable_f1 <= apbi.pwdata(1);
415 reg_wp.enable_f1 <= apbi.pwdata(1);
398 reg_wp.enable_f2 <= apbi.pwdata(2);
416 reg_wp.enable_f2 <= apbi.pwdata(2);
399 reg_wp.enable_f3 <= apbi.pwdata(3);
417 reg_wp.enable_f3 <= apbi.pwdata(3);
400 reg_wp.burst_f0 <= apbi.pwdata(4);
418 reg_wp.burst_f0 <= apbi.pwdata(4);
401 reg_wp.burst_f1 <= apbi.pwdata(5);
419 reg_wp.burst_f1 <= apbi.pwdata(5);
402 reg_wp.burst_f2 <= apbi.pwdata(6);
420 reg_wp.burst_f2 <= apbi.pwdata(6);
403 reg_wp.run <= apbi.pwdata(7);
421 reg_wp.run <= apbi.pwdata(7);
404 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
405 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
406 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
407 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
408 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
409 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
410 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
411 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
412 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
413 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
414 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
415 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
416 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
417 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
418 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
419 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
420 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
421 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
422 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
423 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
424 --
442 --
425 WHEN OTHERS => NULL;
443 WHEN OTHERS => NULL;
426 END CASE;
444 END CASE;
427 END IF;
445 END IF;
428 END IF;
446 END IF;
429
447
430 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
431 ready_matrix_f0_1 OR
449 ready_matrix_f0_1 OR
432 ready_matrix_f1 OR
450 ready_matrix_f1 OR
433 ready_matrix_f2)
451 ready_matrix_f2)
434 )
452 )
435 OR
453 OR
436 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
437 error_bad_component_error)
455 error_bad_component_error)
438 ));
456 ));
439
457
440 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
441 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
442 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
443 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
444 -- );
462 -- );
445 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
446
464
447 END IF;
465 END IF;
448 END PROCESS lpp_lfr_apbreg;
466 END PROCESS lpp_lfr_apbreg;
449
467
450 apbo.pindex <= pindex;
468 apbo.pindex <= pindex;
451 apbo.pconfig <= pconfig;
469 apbo.pconfig <= pconfig;
452 apbo.prdata <= prdata;
470 apbo.prdata <= prdata;
453
471
454 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
455 -- IRQ
473 -- IRQ
456 -----------------------------------------------------------------------------
474 -----------------------------------------------------------------------------
457 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
458
476
459 PROCESS (HCLK, HRESETn)
477 PROCESS (HCLK, HRESETn)
460 BEGIN -- PROCESS
478 BEGIN -- PROCESS
461 IF HRESETn = '0' THEN -- asynchronous reset (active low)
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
462 irq_wfp_reg <= (OTHERS => '0');
480 irq_wfp_reg <= (OTHERS => '0');
463 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
464 irq_wfp_reg <= irq_wfp_reg_s;
482 irq_wfp_reg <= irq_wfp_reg_s;
465 END IF;
483 END IF;
466 END PROCESS;
484 END PROCESS;
467
485
468 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
469 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
470 END GENERATE all_irq_wfp;
488 END GENERATE all_irq_wfp;
471
489
472 irq_wfp_ZERO <= (OTHERS => '0');
490 irq_wfp_ZERO <= (OTHERS => '0');
473 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
474
492
475 END beh;
493 END beh;
Show file before | Show file after | Hide comments
@@ -1,212 +1,221
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
80 delta_vector_size : INTEGER;
80 delta_vector_size : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex : INTEGER;
87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 );
89 );
90 PORT (
90 PORT (
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
93 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_B : IN Samples14v(2 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
95 sample_val : IN STD_LOGIC;
95 sample_val : IN STD_LOGIC;
96 apbi : IN apb_slv_in_type;
96 apbi : IN apb_slv_in_type;
97 apbo : OUT apb_slv_out_type;
97 apbo : OUT apb_slv_out_type;
98 ahbi : IN AHB_Mst_In_Type;
98 ahbi : IN AHB_Mst_In_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
103
103
104 --debug
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
112 debug_f3_data_valid : OUT STD_LOGIC );
113 END COMPONENT;
113 END COMPONENT;
114
114
115 COMPONENT lpp_lfr_apbreg
115 COMPONENT lpp_lfr_apbreg
116 GENERIC (
116 GENERIC (
117 nb_data_by_buffer_size : INTEGER;
117 nb_data_by_buffer_size : INTEGER;
118 nb_word_by_buffer_size : INTEGER;
118 nb_word_by_buffer_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
120 delta_vector_size : INTEGER;
120 delta_vector_size : INTEGER;
121 delta_vector_size_f0_2 : INTEGER;
121 delta_vector_size_f0_2 : INTEGER;
122 pindex : INTEGER;
122 pindex : INTEGER;
123 paddr : INTEGER;
123 paddr : INTEGER;
124 pmask : INTEGER;
124 pmask : INTEGER;
125 pirq_ms : INTEGER;
125 pirq_ms : INTEGER;
126 pirq_wfp : INTEGER;
126 pirq_wfp : INTEGER;
127 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
127 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
128 PORT (
128 PORT (
129 HCLK : IN STD_ULOGIC;
129 HCLK : IN STD_ULOGIC;
130 HRESETn : IN STD_ULOGIC;
130 HRESETn : IN STD_ULOGIC;
131 apbi : IN apb_slv_in_type;
131 apbi : IN apb_slv_in_type;
132 apbo : OUT apb_slv_out_type;
132 apbo : OUT apb_slv_out_type;
133 ready_matrix_f0_0 : IN STD_LOGIC;
133 ready_matrix_f0_0 : IN STD_LOGIC;
134 ready_matrix_f0_1 : IN STD_LOGIC;
134 ready_matrix_f0_1 : IN STD_LOGIC;
135 ready_matrix_f1 : IN STD_LOGIC;
135 ready_matrix_f1 : IN STD_LOGIC;
136 ready_matrix_f2 : IN STD_LOGIC;
136 ready_matrix_f2 : IN STD_LOGIC;
137 error_anticipating_empty_fifo : IN STD_LOGIC;
137 error_anticipating_empty_fifo : IN STD_LOGIC;
138 error_bad_component_error : IN STD_LOGIC;
138 error_bad_component_error : IN STD_LOGIC;
139 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 status_ready_matrix_f0_0 : OUT STD_LOGIC;
140 status_ready_matrix_f0_0 : OUT STD_LOGIC;
141 status_ready_matrix_f0_1 : OUT STD_LOGIC;
141 status_ready_matrix_f0_1 : OUT STD_LOGIC;
142 status_ready_matrix_f1 : OUT STD_LOGIC;
142 status_ready_matrix_f1 : OUT STD_LOGIC;
143 status_ready_matrix_f2 : OUT STD_LOGIC;
143 status_ready_matrix_f2 : OUT STD_LOGIC;
144 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
144 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
145 status_error_bad_component_error : OUT STD_LOGIC;
145 status_error_bad_component_error : OUT STD_LOGIC;
146 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
146 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
147 config_active_interruption_onError : OUT STD_LOGIC;
147 config_active_interruption_onError : OUT STD_LOGIC;
148 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
152 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
154 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
154 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
156 data_shaping_BW : OUT STD_LOGIC;
156 data_shaping_BW : OUT STD_LOGIC;
157 data_shaping_SP0 : OUT STD_LOGIC;
157 data_shaping_SP0 : OUT STD_LOGIC;
158 data_shaping_SP1 : OUT STD_LOGIC;
158 data_shaping_SP1 : OUT STD_LOGIC;
159 data_shaping_R0 : OUT STD_LOGIC;
159 data_shaping_R0 : OUT STD_LOGIC;
160 data_shaping_R1 : OUT STD_LOGIC;
160 data_shaping_R1 : OUT STD_LOGIC;
161 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
166 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
167 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 enable_f0 : OUT STD_LOGIC;
169 enable_f0 : OUT STD_LOGIC;
170 enable_f1 : OUT STD_LOGIC;
170 enable_f1 : OUT STD_LOGIC;
171 enable_f2 : OUT STD_LOGIC;
171 enable_f2 : OUT STD_LOGIC;
172 enable_f3 : OUT STD_LOGIC;
172 enable_f3 : OUT STD_LOGIC;
173 burst_f0 : OUT STD_LOGIC;
173 burst_f0 : OUT STD_LOGIC;
174 burst_f1 : OUT STD_LOGIC;
174 burst_f1 : OUT STD_LOGIC;
175 burst_f2 : OUT STD_LOGIC;
175 burst_f2 : OUT STD_LOGIC;
176 run : OUT STD_LOGIC;
176 run : OUT STD_LOGIC;
177 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 ---------------------------------------------------------------------------
183 debug_reg0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
182 END COMPONENT;
191 END COMPONENT;
183
192
184 COMPONENT lpp_top_ms
193 COMPONENT lpp_top_ms
185 GENERIC (
194 GENERIC (
186 Mem_use : INTEGER;
195 Mem_use : INTEGER;
187 nb_burst_available_size : INTEGER;
196 nb_burst_available_size : INTEGER;
188 nb_snapshot_param_size : INTEGER;
197 nb_snapshot_param_size : INTEGER;
189 delta_snapshot_size : INTEGER;
198 delta_snapshot_size : INTEGER;
190 delta_f2_f0_size : INTEGER;
199 delta_f2_f0_size : INTEGER;
191 delta_f2_f1_size : INTEGER;
200 delta_f2_f1_size : INTEGER;
192 pindex : INTEGER;
201 pindex : INTEGER;
193 paddr : INTEGER;
202 paddr : INTEGER;
194 pmask : INTEGER;
203 pmask : INTEGER;
195 pirq_ms : INTEGER;
204 pirq_ms : INTEGER;
196 pirq_wfp : INTEGER;
205 pirq_wfp : INTEGER;
197 hindex_wfp : INTEGER;
206 hindex_wfp : INTEGER;
198 hindex_ms : INTEGER);
207 hindex_ms : INTEGER);
199 PORT (
208 PORT (
200 clk : IN STD_LOGIC;
209 clk : IN STD_LOGIC;
201 rstn : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
202 sample_B : IN Samples14v(2 DOWNTO 0);
211 sample_B : IN Samples14v(2 DOWNTO 0);
203 sample_E : IN Samples14v(4 DOWNTO 0);
212 sample_E : IN Samples14v(4 DOWNTO 0);
204 sample_val : IN STD_LOGIC;
213 sample_val : IN STD_LOGIC;
205 apbi : IN apb_slv_in_type;
214 apbi : IN apb_slv_in_type;
206 apbo : OUT apb_slv_out_type;
215 apbo : OUT apb_slv_out_type;
207 ahbi_ms : IN AHB_Mst_In_Type;
216 ahbi_ms : IN AHB_Mst_In_Type;
208 ahbo_ms : OUT AHB_Mst_Out_Type;
217 ahbo_ms : OUT AHB_Mst_Out_Type;
209 data_shaping_BW : OUT STD_LOGIC);
218 data_shaping_BW : OUT STD_LOGIC);
210 END COMPONENT;
219 END COMPONENT;
211
220
212 END lpp_lfr_pkg;
221 END lpp_lfr_pkg;
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@@ -1,457 +1,471
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
40
40
41 GENERIC (
41 GENERIC (
42 tech : INTEGER := inferred;
42 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
47 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
48 delta_vector_size_f0_2 : INTEGER := 3);
49
49
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53
53
54 ---- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
57
58 --config
58 --config
59 reg_run : IN STD_LOGIC;
59 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
66
67 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
71
71
72 burst_f0 : IN STD_LOGIC;
72 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
75
75
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 -- INPUT
84 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
87
88 --f0
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
104
105 ---------------------------------------------------------------------------
105 ---------------------------------------------------------------------------
106 -- OUTPUT
106 -- OUTPUT
107 --f0
107 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
131
131
132 --debug
132 --debug
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 debug_f0_data_valid : OUT STD_LOGIC;
134 debug_f0_data_valid : OUT STD_LOGIC;
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 debug_f1_data_valid : OUT STD_LOGIC;
136 debug_f1_data_valid : OUT STD_LOGIC;
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 debug_f2_data_valid : OUT STD_LOGIC;
138 debug_f2_data_valid : OUT STD_LOGIC;
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
140 debug_f3_data_valid : OUT STD_LOGIC
141 );
141 );
142
142
143 END lpp_waveform;
143 END lpp_waveform;
144
144
145 ARCHITECTURE beh OF lpp_waveform IS
145 ARCHITECTURE beh OF lpp_waveform IS
146 SIGNAL start_snapshot_f0 : STD_LOGIC;
146 SIGNAL start_snapshot_f0 : STD_LOGIC;
147 SIGNAL start_snapshot_f1 : STD_LOGIC;
147 SIGNAL start_snapshot_f1 : STD_LOGIC;
148 SIGNAL start_snapshot_f2 : STD_LOGIC;
148 SIGNAL start_snapshot_f2 : STD_LOGIC;
149
149
150 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
154
154
155 SIGNAL data_f0_out_valid : STD_LOGIC;
155 SIGNAL data_f0_out_valid : STD_LOGIC;
156 SIGNAL data_f1_out_valid : STD_LOGIC;
156 SIGNAL data_f1_out_valid : STD_LOGIC;
157 SIGNAL data_f2_out_valid : STD_LOGIC;
157 SIGNAL data_f2_out_valid : STD_LOGIC;
158 SIGNAL data_f3_out_valid : STD_LOGIC;
158 SIGNAL data_f3_out_valid : STD_LOGIC;
159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
160 --
160 --
161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 --
174 --
175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 --
179 --
180 SIGNAL run : STD_LOGIC;
180 SIGNAL run : STD_LOGIC;
181 --
181 --
182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
186 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188
189
189 BEGIN -- beh
190 BEGIN -- beh
190
191
191 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
192 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
192 GENERIC MAP (
193 GENERIC MAP (
193 delta_vector_size => delta_vector_size,
194 delta_vector_size => delta_vector_size,
194 delta_vector_size_f0_2 => delta_vector_size_f0_2
195 delta_vector_size_f0_2 => delta_vector_size_f0_2
195 )
196 )
196 PORT MAP (
197 PORT MAP (
197 clk => clk,
198 clk => clk,
198 rstn => rstn,
199 rstn => rstn,
199 reg_run => reg_run,
200 reg_run => reg_run,
200 reg_start_date => reg_start_date,
201 reg_start_date => reg_start_date,
201 reg_delta_snapshot => reg_delta_snapshot,
202 reg_delta_snapshot => reg_delta_snapshot,
202 reg_delta_f0 => reg_delta_f0,
203 reg_delta_f0 => reg_delta_f0,
203 reg_delta_f0_2 => reg_delta_f0_2,
204 reg_delta_f0_2 => reg_delta_f0_2,
204 reg_delta_f1 => reg_delta_f1,
205 reg_delta_f1 => reg_delta_f1,
205 reg_delta_f2 => reg_delta_f2,
206 reg_delta_f2 => reg_delta_f2,
206 coarse_time => coarse_time(30 DOWNTO 0),
207 coarse_time => coarse_time(30 DOWNTO 0),
207 data_f0_valid => data_f0_in_valid,
208 data_f0_valid => data_f0_in_valid,
208 data_f2_valid => data_f2_in_valid,
209 data_f2_valid => data_f2_in_valid,
209 start_snapshot_f0 => start_snapshot_f0,
210 start_snapshot_f0 => start_snapshot_f0,
210 start_snapshot_f1 => start_snapshot_f1,
211 start_snapshot_f1 => start_snapshot_f1,
211 start_snapshot_f2 => start_snapshot_f2,
212 start_snapshot_f2 => start_snapshot_f2,
212 wfp_on => run);
213 wfp_on => run);
213
214
214 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
215 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
215 GENERIC MAP (
216 GENERIC MAP (
216 data_size => data_size,
217 data_size => data_size,
217 nb_snapshot_param_size => nb_snapshot_param_size)
218 nb_snapshot_param_size => nb_snapshot_param_size)
218 PORT MAP (
219 PORT MAP (
219 clk => clk,
220 clk => clk,
220 rstn => rstn,
221 rstn => rstn,
221 run => run,
222 run => run,
222 enable => enable_f0,
223 enable => enable_f0,
223 burst_enable => burst_f0,
224 burst_enable => burst_f0,
224 nb_snapshot_param => nb_snapshot_param,
225 nb_snapshot_param => nb_snapshot_param,
225 start_snapshot => start_snapshot_f0,
226 start_snapshot => start_snapshot_f0,
226 data_in => data_f0_in,
227 data_in => data_f0_in,
227 data_in_valid => data_f0_in_valid,
228 data_in_valid => data_f0_in_valid,
228 data_out => data_f0_out,
229 data_out => data_f0_out,
229 data_out_valid => data_f0_out_valid);
230 data_out_valid => data_f0_out_valid);
230
231
231 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
232 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
232
233
233 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
234 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
234 GENERIC MAP (
235 GENERIC MAP (
235 data_size => data_size,
236 data_size => data_size,
236 nb_snapshot_param_size => nb_snapshot_param_size+1)
237 nb_snapshot_param_size => nb_snapshot_param_size+1)
237 PORT MAP (
238 PORT MAP (
238 clk => clk,
239 clk => clk,
239 rstn => rstn,
240 rstn => rstn,
240 run => run,
241 run => run,
241 enable => enable_f1,
242 enable => enable_f1,
242 burst_enable => burst_f1,
243 burst_enable => burst_f1,
243 nb_snapshot_param => nb_snapshot_param_more_one,
244 nb_snapshot_param => nb_snapshot_param_more_one,
244 start_snapshot => start_snapshot_f1,
245 start_snapshot => start_snapshot_f1,
245 data_in => data_f1_in,
246 data_in => data_f1_in,
246 data_in_valid => data_f1_in_valid,
247 data_in_valid => data_f1_in_valid,
247 data_out => data_f1_out,
248 data_out => data_f1_out,
248 data_out_valid => data_f1_out_valid);
249 data_out_valid => data_f1_out_valid);
249
250
250 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
251 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
251 GENERIC MAP (
252 GENERIC MAP (
252 data_size => data_size,
253 data_size => data_size,
253 nb_snapshot_param_size => nb_snapshot_param_size+1)
254 nb_snapshot_param_size => nb_snapshot_param_size+1)
254 PORT MAP (
255 PORT MAP (
255 clk => clk,
256 clk => clk,
256 rstn => rstn,
257 rstn => rstn,
257 run => run,
258 run => run,
258 enable => enable_f2,
259 enable => enable_f2,
259 burst_enable => burst_f2,
260 burst_enable => burst_f2,
260 nb_snapshot_param => nb_snapshot_param_more_one,
261 nb_snapshot_param => nb_snapshot_param_more_one,
261 start_snapshot => start_snapshot_f2,
262 start_snapshot => start_snapshot_f2,
262 data_in => data_f2_in,
263 data_in => data_f2_in,
263 data_in_valid => data_f2_in_valid,
264 data_in_valid => data_f2_in_valid,
264 data_out => data_f2_out,
265 data_out => data_f2_out,
265 data_out_valid => data_f2_out_valid);
266 data_out_valid => data_f2_out_valid);
266
267
267 lpp_waveform_burst_f3 : lpp_waveform_burst
268 lpp_waveform_burst_f3 : lpp_waveform_burst
268 GENERIC MAP (
269 GENERIC MAP (
269 data_size => data_size)
270 data_size => data_size)
270 PORT MAP (
271 PORT MAP (
271 clk => clk,
272 clk => clk,
272 rstn => rstn,
273 rstn => rstn,
273 run => run,
274 run => run,
274 enable => enable_f3,
275 enable => enable_f3,
275 data_in => data_f3_in,
276 data_in => data_f3_in,
276 data_in_valid => data_f3_in_valid,
277 data_in_valid => data_f3_in_valid,
277 data_out => data_f3_out,
278 data_out => data_f3_out,
278 data_out_valid => data_f3_out_valid);
279 data_out_valid => data_f3_out_valid);
279
280
280 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
281 -- DEBUG
282 -- DEBUG
282 debug_f0_data_valid <= data_f0_out_valid;
283 debug_f0_data_valid <= data_f0_out_valid;
283 debug_f0_data <= data_f0_out;
284 debug_f0_data <= data_f0_out;
284 debug_f1_data_valid <= data_f1_out_valid;
285 debug_f1_data_valid <= data_f1_out_valid;
285 debug_f1_data <= data_f1_out;
286 debug_f1_data <= data_f1_out;
286 debug_f2_data_valid <= data_f2_out_valid;
287 debug_f2_data_valid <= data_f2_out_valid;
287 debug_f2_data <= data_f2_out;
288 debug_f2_data <= data_f2_out;
288 debug_f3_data_valid <= data_f3_out_valid;
289 debug_f3_data_valid <= data_f3_out_valid;
289 debug_f3_data <= data_f3_out;
290 debug_f3_data <= data_f3_out;
290 -----------------------------------------------------------------------------
291 -----------------------------------------------------------------------------
291
292
292 PROCESS (clk, rstn)
293 PROCESS (clk, rstn)
293 BEGIN -- PROCESS
294 BEGIN -- PROCESS
294 IF rstn = '0' THEN -- asynchronous reset (active low)
295 IF rstn = '0' THEN -- asynchronous reset (active low)
295 time_reg1 <= (OTHERS => '0');
296 time_reg1 <= (OTHERS => '0');
296 time_reg2 <= (OTHERS => '0');
297 time_reg2 <= (OTHERS => '0');
297 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
298 time_reg1 <= fine_time & coarse_time;
299 time_reg1 <= fine_time & coarse_time;
299 time_reg2 <= time_reg1;
300 time_reg2 <= time_reg1;
300 END IF;
301 END IF;
301 END PROCESS;
302 END PROCESS;
302
303
303 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
304 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
304 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
305 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
305 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
306 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
306 PORT MAP (
307 PORT MAP (
307 HCLK => clk,
308 HCLK => clk,
308 HRESETn => rstn,
309 HRESETn => rstn,
309 run => run,
310 run => run,
310 valid_in => valid_in(I),
311 valid_in => valid_in(I),
311 ack_in => valid_ack(I),
312 ack_in => valid_ack(I),
312 time_in => time_reg2, -- Todo
313 time_in => time_reg2, -- Todo
313 valid_out => valid_out(I),
314 valid_out => valid_out(I),
314 time_out => time_out(I), -- Todo
315 time_out => time_out(I), -- Todo
315 error => status_new_err(I));
316 error => status_new_err(I));
316 END GENERATE all_input_valid;
317 END GENERATE all_input_valid;
317
318
318 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
319 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
319 data_out(0,I) <= data_f0_out(I);
320 data_out(0,I) <= data_f0_out(I);
320 data_out(1,I) <= data_f1_out(I);
321 data_out(1,I) <= data_f1_out(I);
321 data_out(2,I) <= data_f2_out(I);
322 data_out(2,I) <= data_f2_out(I);
322 data_out(3,I) <= data_f3_out(I);
323 data_out(3,I) <= data_f3_out(I);
323 END GENERATE all_bit_of_data_out;
324 END GENERATE all_bit_of_data_out;
324
325
326 -----------------------------------------------------------------------------
327 -- TODO : debug
328 -----------------------------------------------------------------------------
329 --all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
330 -- all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
331 -- time_out_2(J,I) <= time_out(J)(I);
332 -- END GENERATE all_sample_of_time_out;
333 --END GENERATE all_bit_of_time_out;
334 time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
335 time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
336 time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
337 time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
338
325 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
339 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
326 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
340 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
327 time_out_2(J,I) <= time_out(J)(I);
341 time_out_2(J,I) <= time_out_debug(J)(I);
328 END GENERATE all_sample_of_time_out;
342 END GENERATE all_sample_of_time_out;
329 END GENERATE all_bit_of_time_out;
343 END GENERATE all_bit_of_time_out;
330
344
331 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
345 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
332 GENERIC MAP (tech => tech,
346 GENERIC MAP (tech => tech,
333 nb_data_by_buffer_size =>nb_data_by_buffer_size)
347 nb_data_by_buffer_size =>nb_data_by_buffer_size)
334 PORT MAP (
348 PORT MAP (
335 clk => clk,
349 clk => clk,
336 rstn => rstn,
350 rstn => rstn,
337 run => run,
351 run => run,
338 nb_data_by_buffer => nb_data_by_buffer,
352 nb_data_by_buffer => nb_data_by_buffer,
339 data_in_valid => valid_out,
353 data_in_valid => valid_out,
340 data_in_ack => valid_ack,
354 data_in_ack => valid_ack,
341 data_in => data_out,
355 data_in => data_out,
342 time_in => time_out_2,
356 time_in => time_out_2,
343
357
344 data_out => wdata,
358 data_out => wdata,
345 data_out_wen => data_wen,
359 data_out_wen => data_wen,
346 full_almost => full_almost,
360 full_almost => full_almost,
347 full => full);
361 full => full);
348
362
349 lpp_waveform_fifo_1 : lpp_waveform_fifo
363 lpp_waveform_fifo_1 : lpp_waveform_fifo
350 GENERIC MAP (tech => tech)
364 GENERIC MAP (tech => tech)
351 PORT MAP (
365 PORT MAP (
352 clk => clk,
366 clk => clk,
353 rstn => rstn,
367 rstn => rstn,
354 run => run,
368 run => run,
355
369
356 empty => empty,
370 empty => empty,
357 empty_almost => empty_almost,
371 empty_almost => empty_almost,
358
372
359 data_ren => data_ren,
373 data_ren => data_ren,
360 rdata => rdata,
374 rdata => rdata,
361
375
362
376
363 full_almost => full_almost,
377 full_almost => full_almost,
364 full => full,
378 full => full,
365 data_wen => data_wen,
379 data_wen => data_wen,
366 wdata => wdata);
380 wdata => wdata);
367
381
368 data_f0_data_out <= rdata;
382 data_f0_data_out <= rdata;
369 data_f1_data_out <= rdata;
383 data_f1_data_out <= rdata;
370 data_f2_data_out <= rdata;
384 data_f2_data_out <= rdata;
371 data_f3_data_out <= rdata;
385 data_f3_data_out <= rdata;
372
386
373 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
387 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
374 -- GENERIC MAP (
388 -- GENERIC MAP (
375 -- tech => tech)
389 -- tech => tech)
376 -- PORT MAP (
390 -- PORT MAP (
377 -- clk => clk,
391 -- clk => clk,
378 -- rstn => rstn,
392 -- rstn => rstn,
379 -- run => run,
393 -- run => run,
380
394
381 -- empty_almost => empty_almost,
395 -- empty_almost => empty_almost,
382 -- empty => empty,
396 -- empty => empty,
383 -- data_ren => data_ren,
397 -- data_ren => data_ren,
384
398
385 -- rdata_0 => data_f0_data_out,
399 -- rdata_0 => data_f0_data_out,
386 -- rdata_1 => data_f1_data_out,
400 -- rdata_1 => data_f1_data_out,
387 -- rdata_2 => data_f2_data_out,
401 -- rdata_2 => data_f2_data_out,
388 -- rdata_3 => data_f3_data_out,
402 -- rdata_3 => data_f3_data_out,
389
403
390 -- full_almost => full_almost,
404 -- full_almost => full_almost,
391 -- full => full,
405 -- full => full,
392 -- data_wen => data_wen,
406 -- data_wen => data_wen,
393 -- wdata => wdata);
407 -- wdata => wdata);
394
408
395
409
396
410
397
411
398 data_ren <= data_f3_data_out_ren &
412 data_ren <= data_f3_data_out_ren &
399 data_f2_data_out_ren &
413 data_f2_data_out_ren &
400 data_f1_data_out_ren &
414 data_f1_data_out_ren &
401 data_f0_data_out_ren;
415 data_f0_data_out_ren;
402
416
403 -----------------------------------------------------------------------------
417 -----------------------------------------------------------------------------
404 -- TODO : set the alterance : time, data, data, .....
418 -- TODO : set the alterance : time, data, data, .....
405 -----------------------------------------------------------------------------
419 -----------------------------------------------------------------------------
406 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
420 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
407 GENERIC MAP (
421 GENERIC MAP (
408 nb_data_by_buffer_size => nb_word_by_buffer_size)
422 nb_data_by_buffer_size => nb_word_by_buffer_size)
409 PORT MAP (
423 PORT MAP (
410 clk => clk,
424 clk => clk,
411 rstn => rstn,
425 rstn => rstn,
412 run => run,
426 run => run,
413
427
414 -------------------------------------------------------------------------
428 -------------------------------------------------------------------------
415 -- CONFIG
429 -- CONFIG
416 -------------------------------------------------------------------------
430 -------------------------------------------------------------------------
417 nb_data_by_buffer => nb_word_by_buffer,
431 nb_data_by_buffer => nb_word_by_buffer,
418
432
419 addr_data_f0 => addr_data_f0,
433 addr_data_f0 => addr_data_f0,
420 addr_data_f1 => addr_data_f1,
434 addr_data_f1 => addr_data_f1,
421 addr_data_f2 => addr_data_f2,
435 addr_data_f2 => addr_data_f2,
422 addr_data_f3 => addr_data_f3,
436 addr_data_f3 => addr_data_f3,
423 -------------------------------------------------------------------------
437 -------------------------------------------------------------------------
424 -- CTRL
438 -- CTRL
425 -------------------------------------------------------------------------
439 -------------------------------------------------------------------------
426 -- IN
440 -- IN
427 empty => empty,
441 empty => empty,
428 empty_almost => empty_almost,
442 empty_almost => empty_almost,
429 data_ren => data_ren,
443 data_ren => data_ren,
430
444
431 -------------------------------------------------------------------------
445 -------------------------------------------------------------------------
432 -- STATUS
446 -- STATUS
433 -------------------------------------------------------------------------
447 -------------------------------------------------------------------------
434 status_full => status_full,
448 status_full => status_full,
435 status_full_ack => status_full_ack,
449 status_full_ack => status_full_ack,
436 status_full_err => status_full_err,
450 status_full_err => status_full_err,
437
451
438 -------------------------------------------------------------------------
452 -------------------------------------------------------------------------
439 -- ADDR DATA OUT
453 -- ADDR DATA OUT
440 -------------------------------------------------------------------------
454 -------------------------------------------------------------------------
441 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
455 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
442 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
456 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
443 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
457 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
444 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
458 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
445
459
446 data_f0_data_out_valid => data_f0_data_out_valid,
460 data_f0_data_out_valid => data_f0_data_out_valid,
447 data_f1_data_out_valid => data_f1_data_out_valid,
461 data_f1_data_out_valid => data_f1_data_out_valid,
448 data_f2_data_out_valid => data_f2_data_out_valid,
462 data_f2_data_out_valid => data_f2_data_out_valid,
449 data_f3_data_out_valid => data_f3_data_out_valid,
463 data_f3_data_out_valid => data_f3_data_out_valid,
450
464
451 data_f0_addr_out => data_f0_addr_out,
465 data_f0_addr_out => data_f0_addr_out,
452 data_f1_addr_out => data_f1_addr_out,
466 data_f1_addr_out => data_f1_addr_out,
453 data_f2_addr_out => data_f2_addr_out,
467 data_f2_addr_out => data_f2_addr_out,
454 data_f3_addr_out => data_f3_addr_out
468 data_f3_addr_out => data_f3_addr_out
455 );
469 );
456
470
457 END beh;
471 END beh;
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