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Migrating from GPLV2 to V3, and cleand some files. /!\ Unstable /!\
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #include "apb_lcd_driver.h"
20 #include "lpp_apb_functions.h"
21 #include "lpp_apb_functions.h"
22 #include <stdio.h>
23
24 int lcdbusy(lcd_device* lcd)
25 {
26 return (!(lcd->cfg_reg&readyFlag)==readyFlag);
27 }
28
29
30 lcd_device* lcdopen(int count)
31 {
32 lcd_device* dev;
33 dev = (lcd_device*) apbgetdevice(LPP_LCD_CTRLR,VENDOR_LPP,count);
34 return dev;
35 //* scan APB bus an return the count(th) lcd controler */
36
37 }
38
39
40
41 lcd_err lcdsendcmd(lcd_device* lcd,int cmd)
42 {
43 lcd_err err;
44 err = lcd_error_no_error;
45 if (lcd!=NULL)
46 {
47 while(lcdbusy(lcd));
48 lcd->cfg_reg = cmd;
49 return err;
50 }
51 else
52 {
53 err = lcd_error_not_openned ;
54 return err;
55 }
56 }
57
58
59
60 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value)
61 {
62 lcd_err err;
63 err = lcd_error_no_error;
64 return err;
65 }
66
67
68
69 lcd_err lcdprint(lcd_device* lcd,int position,const char* value)
70 {
71 lcd_err err;
72 err = lcd_error_no_error;
73 if (lcd!=NULL)
74 {
75 int i = position;
76 int n = 0;
77 while(value[n]!= '\0' && i<lcdCharCnt)
78 {
79 if(value[n] == '\n')
80 {
81 i=40;n++;
82 }
83 lcd->Frame_buff[i++] = value[n++];
84 }
85 return err;
86 }
87 else
88 {
89 err = lcd_error_not_openned ;
90 return err;
91 }
92 }
93
94
95
96 lcd_err lcdclear(lcd_device* lcd)
97 {
98 lcd_err err;
99 err = lcd_error_no_error;
100 if (lcd!=NULL)
101 {
102 int i=0;
103 for(i=0;i<lcdCharCnt;i++)
104 {
105 lcd->Frame_buff[i] = ' ';
106 }
107 return err;
108 }
109 err = lcd_error_not_openned ;
110 return err;
111 }
112
113
114
115
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #ifndef APB_LCD_DRIVER_H
20 #define APB_LCD_DRIVER_H
21
22 #define readyFlag 1024
23 #define lcdCharCnt 80
24
25
26 /** @todo implemente some shift functions */
27
28
29 /*===================================================
30 T Y P E S D E F
31 ====================================================*/
32
33
34
35 /** error type used for most of lcd functions */
36 typedef int lcd_err;
37
38 /** lcd error ennum for higher abstraction level when error decoding */
39 enum lcd_error
40 {
41 lcd_error_no_error, /**< no error append while function execution */
42 lcd_error_not_ready, /**< the lcd isn't available*/
43 lcd_error_not_openned, /**< the device guiven to the function isn't opened*/
44 lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */
45 };
46
47
48 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */
49 enum lcd_CMD_time
50 {
51 lcd_4us = 0x0FF,
52 lcd_100us = 0x1FF,
53 lcd_4ms = 0x2FF,
54 lcd_20ms = 0x3FF
55 };
56
57 /** list of availiable lcd commands use whith an AND mask whith cmd time */
58 enum lcd_CMD
59 {
60 CursorON = 0xF0E,
61 CursorOFF = 0xF0C
62 };
63
64 /** structure representing the lcd registers */
65 struct lcd_driver
66 {
67 int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/
68 int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */
69 };
70
71 typedef struct lcd_driver lcd_device;
72
73 /*===================================================
74 F U N C T I O N S
75 ====================================================*/
76
77 /** says if the lcd is busy */
78 int lcdbusy(lcd_device * lcd);
79
80 /** Opens and returns the counth lcd found on APB bus else NULL */
81 lcd_device* lcdopen(int count);
82
83 /** Sends a command to the given device, don't forget to guive the time of the cmd */
84 lcd_err lcdsendcmd(lcd_device* lcd,int cmd);
85
86 /** Sets a char on the given device at given position */
87 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value);
88
89 /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */
90 lcd_err lcdprint(lcd_device* lcd,int position,const char* value);
91
92 /** Writes space character on each adress of the lcd screen */
93 lcd_err lcdclear(lcd_device* lcd);
94
95 #endif
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #include "stdio.h"
20 #include "lpp_apb_functions.h"
21 #include "apb_lcd_driver.h"
22
23
24 int main()
25 {
26 lcd_device* lcd0;
27 struct apbdevinfo lcd0info;
28 lcd0 = lcdopen(0);
29 char message[lcdCharCnt+1];
30 if(lcd0!= NULL)
31 {
32 apbgetdeviceinfofromid(LPP_LCD_CTRLR,VENDOR_LPP,0,&lcd0info);
33 printf("find lcd device @ %8x\n",(int)lcd0);
34 apbprintdeviceinfo(lcd0info);
35 }
36
37 printf("hello\n");
38 lcdclear(lcd0);
39 int d=0;
40 while(d!=10)
41 {
42 scanf("%d",&d);
43 switch(d)
44 {
45 case 0:
46 lcdsendcmd(lcd0,CursorOFF&lcd_100us);
47 printf("cursor OFF \n");
48 sprintf(message,"cursor OFF %d",d);
49 lcdprint(lcd0,0,message);
50 break;
51 case 1:
52 lcdsendcmd(lcd0,CursorON&lcd_100us);
53 printf("cursor ON \n");
54 sprintf(message,"cursor ON %d ",d);
55 lcdprint(lcd0,0,message);
56 break;
57 case 2:
58 sprintf(message,"Test line 2_%d\nline2",d);
59 lcdprint(lcd0,0,message);
60 break;
61 case 3:
62 apbprintdeviceslist();
63 break;
64 case 10:
65 sprintf(message,"QUIT %d ",d);
66 lcdprint(lcd0,0,message);
67 return 0;
68 break;
69 default:
70 sprintf(message,"Not a CMD %d ",d);
71 lcdprint(lcd0,0,message);
72 break;
73 }
74 }
75 return 0;
76 }
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #include "lpp_apb_functions.h"
20 #include <stdio.h>
21
22
23
24 int* apbgetdevice(int PID,int VID,int count)
25 {
26 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg));
27 int id;
28 id = (PID<<12) | (VID<<24);
29 while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF))
30 {
31 if((dev->idReg & 0xFFFFF000) == id)
32 {
33 if(count == 0)
34 {
35 return (int*) (APB_BASE_ADDRS | (dev->bar&0xFFF00000)>>12);
36 }
37 count-=1;
38 }
39 dev += 1;
40 }
41 return NULL;
42 }
43
44
45 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo)
46 {
47
48 devinfo->productID = (dev->idReg>>12) & 0xFFF;
49 devinfo->vendorID = (dev->idReg>>24) & 0xFF;
50 devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS;
51 devinfo->irq = dev->idReg & 0x1F;
52 devinfo->mask = (dev->bar>>4)&0xFFF;
53 devinfo->version = (dev->idReg>>5)&0x1F;
54 }
55
56 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo)
57 {
58 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD + sizeof(struct apbPnPreg));
59 int id;
60 id = (PID<<12) | (VID<<24);
61 while(dev != (struct apbPnPreg*)(APB_TBL_HEAD|0xFFF))
62 {
63 if((dev->idReg & 0xFFFFF000) == id)
64 {
65 if(count == 0)
66 {
67 devinfo->productID = PID;
68 devinfo->vendorID = VID;
69 devinfo->address = ((dev->bar>>12) & 0xFFF00)|APB_BASE_ADDRS;
70 devinfo->irq = dev->idReg & 0x1F;
71 devinfo->mask = (dev->bar>>4)&0xFFF;
72 devinfo->version = (dev->idReg>>5)&0x1F;
73 return;
74 }
75 count-=1;
76 }
77 dev += 1;
78 }
79 }
80
81
82
83 void apbprintdeviceinfo(struct apbdevinfo devinfo)
84 {
85 printf("Vendor ID = 0x%x\n",devinfo.vendorID);
86 printf("Product ID = 0x%x\n",devinfo.productID);
87 printf("Device address = 0x%x\n",devinfo.address);
88 printf("Device Irq = %d\n",devinfo.irq);
89 printf("Device mask = 0x%x\n",devinfo.mask);
90 printf("Device Version = %d\n",devinfo.version);
91 }
92
93
94 void apbprintdeviceslist()
95 {
96 struct apbdevinfo devinfo;
97 struct apbPnPreg* dev = (struct apbPnPreg*)(APB_TBL_HEAD );//+ sizeof(struct apbPnPreg));
98 int i =0;
99 int fisrtBAR;
100 while((dev->idReg == 0) && (i<APB_MAX_DEVICES))
101 {
102 dev += 1;
103 i+=1;
104 }
105 fisrtBAR = dev->bar;
106 for(i=i;i<APB_MAX_DEVICES;i++)
107 {
108 if((dev->idReg != 0 ))
109 {
110 apbgetdeviceinfofromdevptr(dev,&devinfo);
111 printf("\n\n======= new device found========\n");
112 apbprintdeviceinfo(devinfo);
113 }
114 dev += 1;
115 if(dev->bar == fisrtBAR)
116 break;
117 }
118 }
119
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #ifndef LPP_APB_FUNCTIONS_H
20 #define LPP_APB_FUNCTIONS_H
21
22 #define APB_TBL_HEAD 0x800FF000
23 #define APB_BASE_ADDRS 0x80000000
24 #define APB_MAX_DEVICES 256
25
26 #define VENDOR_LPP 0x19
27
28 #define ROCKET_TM 0x001
29 #define otherCore 0x002
30 #define LPP_SIMPLE_DIODE 0x003
31 #define LPP_MULTI_DIODE 0x004
32 #define LPP_LCD_CTRLR 0x005
33
34 /** @todo implemente a descriptor structure for any APB device */
35
36
37 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
38 struct apbPnPreg
39 {
40 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
41 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
42 };
43
44 struct apbdevinfo
45 {
46 int vendorID;
47 int productID;
48 int version;
49 int irq;
50 int address;
51 int mask;
52 };
53
54 /** This Function scans APB devices table and returns counth device according to VID and PID */
55 int* apbgetdevice(int PID,int VID,int count);
56 /** This Function scans APB devices table and returns counth device informations according VID and PID */
57 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
58
59 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
60
61
62 void apbprintdeviceinfo(struct apbdevinfo devinfo);
63
64 void apbprintdeviceslist();
65 #endif // LPP_APB_FUNCTIONS_H
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21
22
23 entity Clk_divider is
24 generic(OSC_freqHz : integer := 50000000;
25 TargetFreq_Hz : integer := 50000);
26 Port ( clk : in STD_LOGIC;
27 reset : in STD_LOGIC;
28 clk_divided : out STD_LOGIC);
29 end Clk_divider;
30
31 architecture ar_Clk_divider of Clk_divider is
32
33 Constant clk_TRIGER : integer := (OSC_freqHz/(2*TargetFreq_Hz))+1;
34
35
36 signal cpt1 : integer;
37
38 signal clk_int : std_logic := '0';
39
40
41 begin
42
43 clk_divided <= clk_int;
44
45
46 process(reset,clk)
47 begin
48 if reset = '0' then
49 cpt1 <= 0;
50 clk_int <= '0';
51 elsif clk'event and clk = '1' then
52 if cpt1 = clk_TRIGER then
53 clk_int <= not clk_int;
54 cpt1 <= 0;
55 else
56 cpt1 <= cpt1 + 1;
57 end if;
58 end if;
59 end process;
60
61
62 end ar_Clk_divider;
63
64
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21
22
23
24 entity AD7688_drvr is
25 generic(ChanelCount : integer;
26 clkkHz : integer);
27 Port ( clk : in STD_LOGIC;
28 reset : in STD_LOGIC;
29 smplClk: in STD_LOGIC;
30 smpout : out Samples_out(ChanelCount-1 downto 0);
31 AD_in : in AD7688_in(ChanelCount-1 downto 0);
32 AD_out : out AD7688_out);
33 end AD7688_drvr;
34
35 architecture ar_AD7688_drvr of AD7688_drvr is
36
37 constant convTrigger : integer:= clkkHz*1.6/1000; --tconv = 1.6µs
38
39 signal i : integer range 0 to convTrigger :=0;
40
41 begin
42
43 sckgen: process(clk,reset)
44 begin
45 if reset = '0' then
46 i <= 0;
47 AD_out.CNV <= '0';
48 elsif clk'event and clk = '1' then
49 end if;
50 end process;
51
52
53 end ar_AD7688_drvr;
54
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.all;
21
22
23
24 package lpp_ad_conv is
25
26
27 type AD7688_out is
28 record
29 CNV : std_logic;
30 SCK : std_logic;
31 end record;
32
33 type AD7688_in_element is
34 record
35 SDI : std_logic;
36 end record;
37
38 type AD7688_in is array(natural range <>) of AD7688_in_element;
39
40 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0);
41
42 component AD7688_drvr is
43 generic(ChanelCount : integer;
44 clkkHz : integer);
45 Port ( clk : in STD_LOGIC;
46 reset : in STD_LOGIC;
47 smplClk: in STD_LOGIC;
48 smpout : out Samples_out(ChanelCount-1 downto 0);
49 AD_in : in AD7688_in(ChanelCount-1 downto 0);
50 AD_out : out AD7688_out);
51 end component;
52
53
54
55
56
57 end lpp_ad_conv;
58
59
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1 GNU GENERAL PUBLIC LICENSE
2 Version 3, 29 June 2007
3
4 Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
5 Everyone is permitted to copy and distribute verbatim copies
6 of this license document, but changing it is not allowed.
7
8 Preamble
9
10 The GNU General Public License is a free, copyleft license for
11 software and other kinds of works.
12
13 The licenses for most software and other practical works are designed
14 to take away your freedom to share and change the works. By contrast,
15 the GNU General Public License is intended to guarantee your freedom to
16 share and change all versions of a program--to make sure it remains free
17 software for all its users. We, the Free Software Foundation, use the
18 GNU General Public License for most of our software; it applies also to
19 any other work released this way by its authors. You can apply it to
20 your programs, too.
21
22 When we speak of free software, we are referring to freedom, not
23 price. Our General Public Licenses are designed to make sure that you
24 have the freedom to distribute copies of free software (and charge for
25 them if you wish), that you receive source code or can get it if you
26 want it, that you can change the software or use pieces of it in new
27 free programs, and that you know you can do these things.
28
29 To protect your rights, we need to prevent others from denying you
30 these rights or asking you to surrender the rights. Therefore, you have
31 certain responsibilities if you distribute copies of the software, or if
32 you modify it: responsibilities to respect the freedom of others.
33
34 For example, if you distribute copies of such a program, whether
35 gratis or for a fee, you must pass on to the recipients the same
36 freedoms that you received. You must make sure that they, too, receive
37 or can get the source code. And you must show them these terms so they
38 know their rights.
39
40 Developers that use the GNU GPL protect your rights with two steps:
41 (1) assert copyright on the software, and (2) offer you this License
42 giving you legal permission to copy, distribute and/or modify it.
43
44 For the developers' and authors' protection, the GPL clearly explains
45 that there is no warranty for this free software. For both users' and
46 authors' sake, the GPL requires that modified versions be marked as
47 changed, so that their problems will not be attributed erroneously to
48 authors of previous versions.
49
50 Some devices are designed to deny users access to install or run
51 modified versions of the software inside them, although the manufacturer
52 can do so. This is fundamentally incompatible with the aim of
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54 pattern of such abuse occurs in the area of products for individuals to
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435 9. Acceptance Not Required for Having Copies.
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446 10. Automatic Licensing of Downstream Recipients.
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471 11. Patents.
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473 A "contributor" is a copyright holder who authorizes use under this
474 License of the Program or a work on which the Program is based. The
475 work thus licensed is called the contributor's "contributor version".
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477 A contributor's "essential patent claims" are all patent claims
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481 but do not include claims that would be infringed only as a
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534 or that patent license was granted, prior to 28 March 2007.
535
536 Nothing in this License shall be construed as excluding or limiting
537 any implied license or other defenses to infringement that may
538 otherwise be available to you under applicable patent law.
539
540 12. No Surrender of Others' Freedom.
541
542 If conditions are imposed on you (whether by court order, agreement or
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544 excuse you from the conditions of this License. If you cannot convey a
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546 License and any other pertinent obligations, then as a consequence you may
547 not convey it at all. For example, if you agree to terms that obligate you
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549 the Program, the only way you could satisfy both those terms and this
550 License would be to refrain entirely from conveying the Program.
551
552 13. Use with the GNU Affero General Public License.
553
554 Notwithstanding any other provision of this License, you have
555 permission to link or combine any covered work with a work licensed
556 under version 3 of the GNU Affero General Public License into a single
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559 but the special requirements of the GNU Affero General Public License,
560 section 13, concerning interaction through a network will apply to the
561 combination as such.
562
563 14. Revised Versions of this License.
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565 The Free Software Foundation may publish revised and/or new versions of
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567 be similar in spirit to the present version, but may differ in detail to
568 address new problems or concerns.
569
570 Each version is given a distinguishing version number. If the
571 Program specifies that a certain numbered version of the GNU General
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573 option of following the terms and conditions either of that numbered
574 version or of any later version published by the Free Software
575 Foundation. If the Program does not specify a version number of the
576 GNU General Public License, you may choose any version ever published
577 by the Free Software Foundation.
578
579 If the Program specifies that a proxy can decide which future
580 versions of the GNU General Public License can be used, that proxy's
581 public statement of acceptance of a version permanently authorizes you
582 to choose that version for the Program.
583
584 Later license versions may give you additional or different
585 permissions. However, no additional obligations are imposed on any
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587 later version.
588
589 15. Disclaimer of Warranty.
590
591 THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
592 APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
593 HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
594 OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
595 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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597 IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
598 ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
599
600 16. Limitation of Liability.
601
602 IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
603 WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
604 THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
605 GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
606 USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
607 DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
608 PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
609 EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
610 SUCH DAMAGES.
611
612 17. Interpretation of Sections 15 and 16.
613
614 If the disclaimer of warranty and limitation of liability provided
615 above cannot be given local legal effect according to their terms,
616 reviewing courts shall apply local law that most closely approximates
617 an absolute waiver of all civil liability in connection with the
618 Program, unless a warranty or assumption of liability accompanies a
619 copy of the Program in return for a fee.
620
621 END OF TERMS AND CONDITIONS
622
623 How to Apply These Terms to Your New Programs
624
625 If you develop a new program, and you want it to be of the greatest
626 possible use to the public, the best way to achieve this is to make it
627 free software which everyone can redistribute and change under these terms.
628
629 To do so, attach the following notices to the program. It is safest
630 to attach them to the start of each source file to most effectively
631 state the exclusion of warranty; and each file should have at least
632 the "copyright" line and a pointer to where the full notice is found.
633
634 <one line to give the program's name and a brief idea of what it does.>
635 Copyright (C) <year> <name of author>
636
637 This program is free software: you can redistribute it and/or modify
638 it under the terms of the GNU General Public License as published by
639 the Free Software Foundation, either version 3 of the License, or
640 (at your option) any later version.
641
642 This program is distributed in the hope that it will be useful,
643 but WITHOUT ANY WARRANTY; without even the implied warranty of
644 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645 GNU General Public License for more details.
646
647 You should have received a copy of the GNU General Public License
648 along with this program. If not, see <http://www.gnu.org/licenses/>.
649
650 Also add information on how to contact you by electronic and paper mail.
651
652 If the program does terminal interaction, make it output a short
653 notice like this when it starts in an interactive mode:
654
655 <program> Copyright (C) <year> <name of author>
656 This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
657 This is free software, and you are welcome to redistribute it
658 under certain conditions; type `show c' for details.
659
660 The hypothetical commands `show w' and `show c' should show the appropriate
661 parts of the General Public License. Of course, your program's commands
662 might be different; for a GUI interface, you would use an "about box".
663
664 You should also get your employer (if you work as a programmer) or school,
665 if any, to sign a "copyright disclaimer" for the program, if necessary.
666 For more information on this, and how to apply and follow the GNU GPL, see
667 <http://www.gnu.org/licenses/>.
668
669 The GNU General Public License does not permit incorporating your program
670 into proprietary programs. If your program is a subroutine library, you
671 may consider it more useful to permit linking proprietary applications with
672 the library. If this is what you want to do, use the GNU Lesser General
673 Public License instead of this License. But first, please read
674 <http://www.gnu.org/philosophy/why-not-lgpl.html>.
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
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1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
3 echo " PDF Doc generator "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
24 echo
25 echo
26 echo
27
28
29
30
31 cd doc/latex
32 make
33 cp refman.pdf ../../VHD_lib.pdf
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@@ -1,50 +1,54
1 SCRIPTSDIR=scripts/
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7
7
8
8
9
9
10
10
11 all: help
11 all: help
12
12
13 help:
13 help:
14 @echo
14 @echo
15 @echo " batch targets:"
15 @echo " batch targets:"
16 @echo
16 @echo
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
18 @echo " make dist : create a tar file for using into an other computer"
18 @echo " make dist : create a tar file for using into an other computer"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer"
20 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
20 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
21 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
21 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
22 @echo " make doc : make documentation for VHDL IPs"
22 @echo " make doc : make documentation for VHDL IPs"
23 @echo " make pdf : make pdf documentation for VHDL IPs"
23 @echo " make pdf : make pdf documentation for VHDL IPs"
24 @echo
24 @echo
25
25
26 allGPL:
26 allGPL:
27 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R
27 @echo "Scanning VHDL files ..."
28 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
29 @echo "Scanning C files ..."
30 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
31 @echo "Scanning H files ..."
32 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
28
33
29 init: allGPL
34 init:
30 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
35 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
31 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
36 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
32
37
33
38
34 Patch-GRLIB: init doc
39 Patch-GRLIB: init doc
35 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
40 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
36
41
37
42
38 dist: init
43 dist: init
39 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
44 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
40
45
41 Patched-dist: Patch-GRLIB
46 Patched-dist: Patch-GRLIB
42 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
47 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
43
48
44
49
45 doc:
50 doc:
46 doxygen lib/lpp/Doxyfile
51 doxygen lib/lpp/Doxyfile
47
52
48 pdf:
53 pdf: doc
49 make lib/lpp/doc/latex
54 sh $(SCRIPTSDIR)/doc.sh
50 cp lib/lpp/doc/latex/refman.pdf lib/lpp/doc/VHD_lib.pdf
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@@ -1,164 +1,161
1
2
3
4 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
5 -- LEON3 Demonstration design test bench configuration
2 -- LEON3 Demonstration design test bench configuration
6 -- Copyright (C) 2009 Aeroflex Gaisler
3 -- Copyright (C) 2009 Aeroflex Gaisler
7 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
8
5
9
6
10 library techmap;
7 library techmap;
11 use techmap.gencomp.all;
8 use techmap.gencomp.all;
12
9
13 package config is
10 package config is
14 -- Technology and synthesis options
11 -- Technology and synthesis options
15 constant CFG_FABTECH : integer := spartan3e;
12 constant CFG_FABTECH : integer := spartan3e;
16 constant CFG_MEMTECH : integer := spartan3e;
13 constant CFG_MEMTECH : integer := spartan3e;
17 constant CFG_PADTECH : integer := spartan3e;
14 constant CFG_PADTECH : integer := spartan3e;
18 constant CFG_NOASYNC : integer := 0;
15 constant CFG_NOASYNC : integer := 0;
19 constant CFG_SCAN : integer := 0;
16 constant CFG_SCAN : integer := 0;
20 -- Clock generator
17 -- Clock generator
21 constant CFG_CLKTECH : integer := spartan3e;
18 constant CFG_CLKTECH : integer := spartan3e;
22 constant CFG_CLKMUL : integer := (4);
19 constant CFG_CLKMUL : integer := (4);
23 constant CFG_CLKDIV : integer := (5);
20 constant CFG_CLKDIV : integer := (5);
24 constant CFG_OCLKDIV : integer := 1;
21 constant CFG_OCLKDIV : integer := 1;
25 constant CFG_OCLKBDIV : integer := 0;
22 constant CFG_OCLKBDIV : integer := 0;
26 constant CFG_OCLKCDIV : integer := 0;
23 constant CFG_OCLKCDIV : integer := 0;
27 constant CFG_PCIDLL : integer := 0;
24 constant CFG_PCIDLL : integer := 0;
28 constant CFG_PCISYSCLK: integer := 0;
25 constant CFG_PCISYSCLK: integer := 0;
29 constant CFG_CLK_NOFB : integer := 0;
26 constant CFG_CLK_NOFB : integer := 0;
30 -- LEON3 processor core
27 -- LEON3 processor core
31 constant CFG_LEON3 : integer := 1;
28 constant CFG_LEON3 : integer := 1;
32 constant CFG_NCPU : integer := (1);
29 constant CFG_NCPU : integer := (1);
33 constant CFG_NWIN : integer := (8);
30 constant CFG_NWIN : integer := (8);
34 constant CFG_V8 : integer := 2;
31 constant CFG_V8 : integer := 2;
35 constant CFG_MAC : integer := 0;
32 constant CFG_MAC : integer := 0;
36 constant CFG_BP : integer := 1;
33 constant CFG_BP : integer := 1;
37 constant CFG_SVT : integer := 1;
34 constant CFG_SVT : integer := 1;
38 constant CFG_RSTADDR : integer := 16#00000#;
35 constant CFG_RSTADDR : integer := 16#00000#;
39 constant CFG_LDDEL : integer := (1);
36 constant CFG_LDDEL : integer := (1);
40 constant CFG_NOTAG : integer := 1;
37 constant CFG_NOTAG : integer := 1;
41 constant CFG_NWP : integer := (2);
38 constant CFG_NWP : integer := (2);
42 constant CFG_PWD : integer := 1*2;
39 constant CFG_PWD : integer := 1*2;
43 constant CFG_FPU : integer := 0 + 16*0;
40 constant CFG_FPU : integer := 0 + 16*0;
44 constant CFG_GRFPUSH : integer := 0;
41 constant CFG_GRFPUSH : integer := 0;
45 constant CFG_ICEN : integer := 1;
42 constant CFG_ICEN : integer := 1;
46 constant CFG_ISETS : integer := 2;
43 constant CFG_ISETS : integer := 2;
47 constant CFG_ISETSZ : integer := 4;
44 constant CFG_ISETSZ : integer := 4;
48 constant CFG_ILINE : integer := 8;
45 constant CFG_ILINE : integer := 8;
49 constant CFG_IREPL : integer := 2;
46 constant CFG_IREPL : integer := 2;
50 constant CFG_ILOCK : integer := 0;
47 constant CFG_ILOCK : integer := 0;
51 constant CFG_ILRAMEN : integer := 0;
48 constant CFG_ILRAMEN : integer := 0;
52 constant CFG_ILRAMADDR: integer := 16#8E#;
49 constant CFG_ILRAMADDR: integer := 16#8E#;
53 constant CFG_ILRAMSZ : integer := 1;
50 constant CFG_ILRAMSZ : integer := 1;
54 constant CFG_DCEN : integer := 1;
51 constant CFG_DCEN : integer := 1;
55 constant CFG_DSETS : integer := 2;
52 constant CFG_DSETS : integer := 2;
56 constant CFG_DSETSZ : integer := 4;
53 constant CFG_DSETSZ : integer := 4;
57 constant CFG_DLINE : integer := 4;
54 constant CFG_DLINE : integer := 4;
58 constant CFG_DREPL : integer := 2;
55 constant CFG_DREPL : integer := 2;
59 constant CFG_DLOCK : integer := 0;
56 constant CFG_DLOCK : integer := 0;
60 constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
57 constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
61 constant CFG_DFIXED : integer := 16#0#;
58 constant CFG_DFIXED : integer := 16#0#;
62 constant CFG_DLRAMEN : integer := 0;
59 constant CFG_DLRAMEN : integer := 0;
63 constant CFG_DLRAMADDR: integer := 16#8F#;
60 constant CFG_DLRAMADDR: integer := 16#8F#;
64 constant CFG_DLRAMSZ : integer := 1;
61 constant CFG_DLRAMSZ : integer := 1;
65 constant CFG_MMUEN : integer := 1;
62 constant CFG_MMUEN : integer := 1;
66 constant CFG_ITLBNUM : integer := 8;
63 constant CFG_ITLBNUM : integer := 8;
67 constant CFG_DTLBNUM : integer := 8;
64 constant CFG_DTLBNUM : integer := 8;
68 constant CFG_TLB_TYPE : integer := 0 + 1*2;
65 constant CFG_TLB_TYPE : integer := 0 + 1*2;
69 constant CFG_TLB_REP : integer := 0;
66 constant CFG_TLB_REP : integer := 0;
70 constant CFG_MMU_PAGE : integer := 0;
67 constant CFG_MMU_PAGE : integer := 0;
71 constant CFG_DSU : integer := 1;
68 constant CFG_DSU : integer := 1;
72 constant CFG_ITBSZ : integer := 4;
69 constant CFG_ITBSZ : integer := 4;
73 constant CFG_ATBSZ : integer := 4;
70 constant CFG_ATBSZ : integer := 4;
74 constant CFG_LEON3FT_EN : integer := 0;
71 constant CFG_LEON3FT_EN : integer := 0;
75 constant CFG_IUFT_EN : integer := 0;
72 constant CFG_IUFT_EN : integer := 0;
76 constant CFG_FPUFT_EN : integer := 0;
73 constant CFG_FPUFT_EN : integer := 0;
77 constant CFG_RF_ERRINJ : integer := 0;
74 constant CFG_RF_ERRINJ : integer := 0;
78 constant CFG_CACHE_FT_EN : integer := 0;
75 constant CFG_CACHE_FT_EN : integer := 0;
79 constant CFG_CACHE_ERRINJ : integer := 0;
76 constant CFG_CACHE_ERRINJ : integer := 0;
80 constant CFG_LEON3_NETLIST: integer := 0;
77 constant CFG_LEON3_NETLIST: integer := 0;
81 constant CFG_DISAS : integer := 0 + 0;
78 constant CFG_DISAS : integer := 0 + 0;
82 constant CFG_PCLOW : integer := 2;
79 constant CFG_PCLOW : integer := 2;
83 -- AMBA settings
80 -- AMBA settings
84 constant CFG_DEFMST : integer := (0);
81 constant CFG_DEFMST : integer := (0);
85 constant CFG_RROBIN : integer := 1;
82 constant CFG_RROBIN : integer := 1;
86 constant CFG_SPLIT : integer := 0;
83 constant CFG_SPLIT : integer := 0;
87 constant CFG_AHBIO : integer := 16#FFF#;
84 constant CFG_AHBIO : integer := 16#FFF#;
88 constant CFG_APBADDR : integer := 16#800#;
85 constant CFG_APBADDR : integer := 16#800#;
89 constant CFG_AHB_MON : integer := 0;
86 constant CFG_AHB_MON : integer := 0;
90 constant CFG_AHB_MONERR : integer := 0;
87 constant CFG_AHB_MONERR : integer := 0;
91 constant CFG_AHB_MONWAR : integer := 0;
88 constant CFG_AHB_MONWAR : integer := 0;
92 constant CFG_AHB_DTRACE : integer := 0;
89 constant CFG_AHB_DTRACE : integer := 0;
93 -- DSU UART
90 -- DSU UART
94 constant CFG_AHB_UART : integer := 1;
91 constant CFG_AHB_UART : integer := 1;
95 -- JTAG based DSU interface
92 -- JTAG based DSU interface
96 constant CFG_AHB_JTAG : integer := 0;
93 constant CFG_AHB_JTAG : integer := 0;
97 -- Ethernet DSU
94 -- Ethernet DSU
98 constant CFG_DSU_ETH : integer := 0 + 0;
95 constant CFG_DSU_ETH : integer := 0 + 0;
99 constant CFG_ETH_BUF : integer := 1;
96 constant CFG_ETH_BUF : integer := 1;
100 constant CFG_ETH_IPM : integer := 16#C0A8#;
97 constant CFG_ETH_IPM : integer := 16#C0A8#;
101 constant CFG_ETH_IPL : integer := 16#0033#;
98 constant CFG_ETH_IPL : integer := 16#0033#;
102 constant CFG_ETH_ENM : integer := 16#020000#;
99 constant CFG_ETH_ENM : integer := 16#020000#;
103 constant CFG_ETH_ENL : integer := 16#000009#;
100 constant CFG_ETH_ENL : integer := 16#000009#;
104 -- LEON2 memory controller
101 -- LEON2 memory controller
105 constant CFG_MCTRL_LEON2 : integer := 1;
102 constant CFG_MCTRL_LEON2 : integer := 1;
106 constant CFG_MCTRL_RAM8BIT : integer := 0;
103 constant CFG_MCTRL_RAM8BIT : integer := 0;
107 constant CFG_MCTRL_RAM16BIT : integer := 0;
104 constant CFG_MCTRL_RAM16BIT : integer := 0;
108 constant CFG_MCTRL_5CS : integer := 0;
105 constant CFG_MCTRL_5CS : integer := 0;
109 constant CFG_MCTRL_SDEN : integer := 0;
106 constant CFG_MCTRL_SDEN : integer := 0;
110 constant CFG_MCTRL_SEPBUS : integer := 0;
107 constant CFG_MCTRL_SEPBUS : integer := 0;
111 constant CFG_MCTRL_INVCLK : integer := 0;
108 constant CFG_MCTRL_INVCLK : integer := 0;
112 constant CFG_MCTRL_SD64 : integer := 0;
109 constant CFG_MCTRL_SD64 : integer := 0;
113 constant CFG_MCTRL_PAGE : integer := 0 + 0;
110 constant CFG_MCTRL_PAGE : integer := 0 + 0;
114 -- DDR controller
111 -- DDR controller
115 constant CFG_DDRSP : integer := 1;
112 constant CFG_DDRSP : integer := 1;
116 constant CFG_DDRSP_INIT : integer := 1;
113 constant CFG_DDRSP_INIT : integer := 1;
117 constant CFG_DDRSP_FREQ : integer := (90);
114 constant CFG_DDRSP_FREQ : integer := (90);
118 constant CFG_DDRSP_COL : integer := (10);
115 constant CFG_DDRSP_COL : integer := (10);
119 constant CFG_DDRSP_SIZE : integer := (64);
116 constant CFG_DDRSP_SIZE : integer := (64);
120 constant CFG_DDRSP_RSKEW : integer := (40);
117 constant CFG_DDRSP_RSKEW : integer := (40);
121 -- AHB ROM
118 -- AHB ROM
122 constant CFG_AHBROMEN : integer := 0;
119 constant CFG_AHBROMEN : integer := 0;
123 constant CFG_AHBROPIP : integer := 0;
120 constant CFG_AHBROPIP : integer := 0;
124 constant CFG_AHBRODDR : integer := 16#000#;
121 constant CFG_AHBRODDR : integer := 16#000#;
125 constant CFG_ROMADDR : integer := 16#000#;
122 constant CFG_ROMADDR : integer := 16#000#;
126 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
123 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
127 -- AHB RAM
124 -- AHB RAM
128 constant CFG_AHBRAMEN : integer := 0;
125 constant CFG_AHBRAMEN : integer := 0;
129 constant CFG_AHBRSZ : integer := 1;
126 constant CFG_AHBRSZ : integer := 1;
130 constant CFG_AHBRADDR : integer := 16#A00#;
127 constant CFG_AHBRADDR : integer := 16#A00#;
131 -- Gaisler Ethernet core
128 -- Gaisler Ethernet core
132 constant CFG_GRETH : integer := 0;
129 constant CFG_GRETH : integer := 0;
133 constant CFG_GRETH1G : integer := 0;
130 constant CFG_GRETH1G : integer := 0;
134 constant CFG_ETH_FIFO : integer := 8;
131 constant CFG_ETH_FIFO : integer := 8;
135 -- UART 1
132 -- UART 1
136 constant CFG_UART1_ENABLE : integer := 1;
133 constant CFG_UART1_ENABLE : integer := 1;
137 constant CFG_UART1_FIFO : integer := 8;
134 constant CFG_UART1_FIFO : integer := 8;
138 -- LEON3 interrupt controller
135 -- LEON3 interrupt controller
139 constant CFG_IRQ3_ENABLE : integer := 1;
136 constant CFG_IRQ3_ENABLE : integer := 1;
140 constant CFG_IRQ3_NSEC : integer := 0;
137 constant CFG_IRQ3_NSEC : integer := 0;
141
138
142 -- Modular timer
139 -- Modular timer
143 constant CFG_GPT_ENABLE : integer := 1;
140 constant CFG_GPT_ENABLE : integer := 1;
144 constant CFG_GPT_NTIM : integer := (2);
141 constant CFG_GPT_NTIM : integer := (2);
145 constant CFG_GPT_SW : integer := (8);
142 constant CFG_GPT_SW : integer := (8);
146 constant CFG_GPT_TW : integer := (32);
143 constant CFG_GPT_TW : integer := (32);
147 constant CFG_GPT_IRQ : integer := (8);
144 constant CFG_GPT_IRQ : integer := (8);
148 constant CFG_GPT_SEPIRQ : integer := 1;
145 constant CFG_GPT_SEPIRQ : integer := 1;
149 constant CFG_GPT_WDOGEN : integer := 0;
146 constant CFG_GPT_WDOGEN : integer := 0;
150 constant CFG_GPT_WDOG : integer := 16#0#;
147 constant CFG_GPT_WDOG : integer := 16#0#;
151
148
152 -- GPIO port
149 -- GPIO port
153 constant CFG_GRGPIO_ENABLE : integer := 1;
150 constant CFG_GRGPIO_ENABLE : integer := 1;
154 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
151 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
155 constant CFG_GRGPIO_WIDTH : integer := (8);
152 constant CFG_GRGPIO_WIDTH : integer := (8);
156
153
157 -- VGA and PS2/ interface
154 -- VGA and PS2/ interface
158 constant CFG_KBD_ENABLE : integer := 0;
155 constant CFG_KBD_ENABLE : integer := 0;
159 constant CFG_VGA_ENABLE : integer := 0;
156 constant CFG_VGA_ENABLE : integer := 0;
160 constant CFG_SVGA_ENABLE : integer := 0;
157 constant CFG_SVGA_ENABLE : integer := 0;
161
158
162 -- GRLIB debugging
159 -- GRLIB debugging
163 constant CFG_DUART : integer := 0;
160 constant CFG_DUART : integer := 0;
164 end;
161 end;
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@@ -1,87 +1,68
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 09:21:03 10/19/2010
24 -- Design Name:
25 -- Module Name: FRAME_CLK_GEN - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
19 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
40 use IEEE.NUMERIC_STD.ALL;
21 use IEEE.NUMERIC_STD.ALL;
41 library lpp;
22 library lpp;
42 use lpp.amba_lcd_16x2_ctrlr.all;
23 use lpp.amba_lcd_16x2_ctrlr.all;
43
24
44 entity FRAME_CLK_GEN is
25 entity FRAME_CLK_GEN is
45 generic(OSC_freqKHz : integer := 50000);
26 generic(OSC_freqKHz : integer := 50000);
46 Port ( clk : in STD_LOGIC;
27 Port ( clk : in STD_LOGIC;
47 reset : in STD_LOGIC;
28 reset : in STD_LOGIC;
48 FRAME_CLK : out STD_LOGIC);
29 FRAME_CLK : out STD_LOGIC);
49 end FRAME_CLK_GEN;
30 end FRAME_CLK_GEN;
50
31
51 architecture Behavioral of FRAME_CLK_GEN is
32 architecture Behavioral of FRAME_CLK_GEN is
52
33
53 Constant Goal_FRAME_CLK_FREQ : integer := 25;
34 Constant Goal_FRAME_CLK_FREQ : integer := 25;
54
35
55 Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
36 Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
56
37
57 signal CPT : integer := 0;
38 signal CPT : integer := 0;
58 signal FRAME_CLK_reg : std_logic :='0';
39 signal FRAME_CLK_reg : std_logic :='0';
59
40
60 begin
41 begin
61
42
62 FRAME_CLK <= FRAME_CLK_reg;
43 FRAME_CLK <= FRAME_CLK_reg;
63
44
64 process(reset,clk)
45 process(reset,clk)
65 begin
46 begin
66 if reset = '0' then
47 if reset = '0' then
67 CPT <= 0;
48 CPT <= 0;
68 FRAME_CLK_reg <= '0';
49 FRAME_CLK_reg <= '0';
69 elsif clk'event and clk = '1' then
50 elsif clk'event and clk = '1' then
70 if CPT = FRAME_CLK_TRIG then
51 if CPT = FRAME_CLK_TRIG then
71 CPT <= 0;
52 CPT <= 0;
72 FRAME_CLK_reg <= not FRAME_CLK_reg;
53 FRAME_CLK_reg <= not FRAME_CLK_reg;
73 else
54 else
74 CPT <= CPT + 1;
55 CPT <= CPT + 1;
75 end if;
56 end if;
76 end if;
57 end if;
77 end process;
58 end process;
78 end Behavioral;
59 end Behavioral;
79
60
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61
81
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Package File Template
20 --
21 -- Purpose: This package defines supplemental types, subtypes,
22 -- constants, and functions
23
24
25 library IEEE;
19 library IEEE;
26 use IEEE.STD_LOGIC_1164.all;
20 use IEEE.STD_LOGIC_1164.all;
27 library lpp;
21 library lpp;
28 use lpp.amba_lcd_16x2_ctrlr.all;
22 use lpp.amba_lcd_16x2_ctrlr.all;
29
23
30
24
31
25
32 package LCD_16x2_CFG is
26 package LCD_16x2_CFG is
33
27
34
28
35 constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
29 constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
36 constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
30 constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
37 constant RetHome : std_logic_vector(7 downto 0):= X"02";
31 constant RetHome : std_logic_vector(7 downto 0):= X"02";
38 constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
32 constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
39 constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E";
33 constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E";
40
34
41 constant CursorON : std_logic_vector(7 downto 0):= X"0E";
35 constant CursorON : std_logic_vector(7 downto 0):= X"0E";
42 constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
36 constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
43
37
44 --===========================================================|
38 --===========================================================|
45 --======L C D D R I V E R T I M I N G C O D E=====|
39 --======L C D D R I V E R T I M I N G C O D E=====|
46 --===========================================================|
40 --===========================================================|
47
41
48 constant Duration_4us : std_logic_vector(1 downto 0) := "00";
42 constant Duration_4us : std_logic_vector(1 downto 0) := "00";
49 constant Duration_100us : std_logic_vector(1 downto 0) := "01";
43 constant Duration_100us : std_logic_vector(1 downto 0) := "01";
50 constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
44 constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
51 constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
45 constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
52
46
53
47
54
48
55 end LCD_16x2_CFG;
49 end LCD_16x2_CFG;
56
50
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 10:09:57 10/13/2010
24 -- Design Name:
25 -- Module Name: LCD_2x16_DRIVER - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38
19
39 ---TDODO => Clean Enable pulse FSM
20 ---TDODO => Clean Enable pulse FSM
40 library IEEE;
21 library IEEE;
41 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_1164.ALL;
42 use IEEE.NUMERIC_STD.all;
23 use IEEE.NUMERIC_STD.all;
43 library lpp;
24 library lpp;
44 use lpp.amba_lcd_16x2_ctrlr.all;
25 use lpp.amba_lcd_16x2_ctrlr.all;
45 use lpp.lcd_16x2_cfg.all;
26 use lpp.lcd_16x2_cfg.all;
46
27
47 entity LCD_16x2_DRIVER is
28 entity LCD_16x2_DRIVER is
48 generic(
29 generic(
49 OSC_Freq_KHz : integer:=50000
30 OSC_Freq_KHz : integer:=50000
50 );
31 );
51 Port(
32 Port(
52 reset : in STD_LOGIC;
33 reset : in STD_LOGIC;
53 clk : in STD_LOGIC;
34 clk : in STD_LOGIC;
54 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
35 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
55 SYNCH : out LCD_DRVR_SYNCH_BUSS;
36 SYNCH : out LCD_DRVR_SYNCH_BUSS;
56 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
37 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
57 );
38 );
58 end LCD_16x2_DRIVER;
39 end LCD_16x2_DRIVER;
59
40
60 architecture Behavioral of LCD_16x2_DRIVER is
41 architecture Behavioral of LCD_16x2_DRIVER is
61
42
62 type stateT is (idle,Enable0,Enable1,Enable2,tempo);
43 type stateT is (idle,Enable0,Enable1,Enable2,tempo);
63 signal state : stateT;
44 signal state : stateT;
64
45
65
46
66 constant trigger_4us : integer := 5;
47 constant trigger_4us : integer := 5;
67 constant trigger_100us : integer := 100;
48 constant trigger_100us : integer := 100;
68 constant trigger_4ms : integer := 4200;
49 constant trigger_4ms : integer := 4200;
69 constant trigger_20ms : integer := 20000;
50 constant trigger_20ms : integer := 20000;
70
51
71
52
72 signal i : integer :=0;
53 signal i : integer :=0;
73 signal reset_i : std_logic := '0';
54 signal reset_i : std_logic := '0';
74 signal tempoTRIG : integer :=0;
55 signal tempoTRIG : integer :=0;
75
56
76 signal clk_1us : std_logic;
57 signal clk_1us : std_logic;
77 signal clk_1us_reg : std_logic;
58 signal clk_1us_reg : std_logic;
78
59
79 begin
60 begin
80
61
81
62
82 CLK0: LCD_CLK_GENERATOR
63 CLK0: LCD_CLK_GENERATOR
83 generic map(OSC_Freq_KHz)
64 generic map(OSC_Freq_KHz)
84 Port map( clk,reset,clk_1us);
65 Port map( clk,reset,clk_1us);
85
66
86
67
87
68
88 process(clk_1us,reset_i)
69 process(clk_1us,reset_i)
89 begin
70 begin
90 if reset_i = '0' then
71 if reset_i = '0' then
91 i <= 0;
72 i <= 0;
92 elsif clk_1us'event and clk_1us ='1' then
73 elsif clk_1us'event and clk_1us ='1' then
93 i <= i+1;
74 i <= i+1;
94 end if;
75 end if;
95 end process;
76 end process;
96
77
97 LCD_CTRL.LCD_RW <= '0';
78 LCD_CTRL.LCD_RW <= '0';
98
79
99 process(clk,reset)
80 process(clk,reset)
100 begin
81 begin
101 if reset = '0' then
82 if reset = '0' then
102 state <= idle;
83 state <= idle;
103 LCD_CTRL.LCD_E <= '0';
84 LCD_CTRL.LCD_E <= '0';
104 SYNCH.DRVR_READY <= '0';
85 SYNCH.DRVR_READY <= '0';
105 SYNCH.LCD_INITIALISED <= '0';
86 SYNCH.LCD_INITIALISED <= '0';
106 reset_i <= '0';
87 reset_i <= '0';
107 elsif clk'event and clk = '1' then
88 elsif clk'event and clk = '1' then
108 case state is
89 case state is
109 when idle =>
90 when idle =>
110 SYNCH.LCD_INITIALISED <= '1';
91 SYNCH.LCD_INITIALISED <= '1';
111 LCD_CTRL.LCD_E <= '0';
92 LCD_CTRL.LCD_E <= '0';
112 if DRIVER_CMD.Exec = '1' then
93 if DRIVER_CMD.Exec = '1' then
113 state <= Enable0;
94 state <= Enable0;
114 reset_i <= '1';
95 reset_i <= '1';
115 SYNCH.DRVR_READY <= '0';
96 SYNCH.DRVR_READY <= '0';
116 LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word;
97 LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word;
117 LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data;
98 LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data;
118 case DRIVER_CMD.Duration is
99 case DRIVER_CMD.Duration is
119 when Duration_4us =>
100 when Duration_4us =>
120 tempoTRIG <= trigger_4us;
101 tempoTRIG <= trigger_4us;
121 when Duration_100us =>
102 when Duration_100us =>
122 tempoTRIG <= trigger_100us;
103 tempoTRIG <= trigger_100us;
123 when Duration_4ms =>
104 when Duration_4ms =>
124 tempoTRIG <= trigger_4ms;
105 tempoTRIG <= trigger_4ms;
125 when Duration_20ms =>
106 when Duration_20ms =>
126 tempoTRIG <= trigger_20ms;
107 tempoTRIG <= trigger_20ms;
127 when others =>
108 when others =>
128 tempoTRIG <= trigger_20ms;
109 tempoTRIG <= trigger_20ms;
129 end case;
110 end case;
130 else
111 else
131 SYNCH.DRVR_READY <= '1';
112 SYNCH.DRVR_READY <= '1';
132 reset_i <= '0';
113 reset_i <= '0';
133 end if;
114 end if;
134 when Enable0 =>
115 when Enable0 =>
135 if i = 1 then
116 if i = 1 then
136 reset_i <= '0';
117 reset_i <= '0';
137 LCD_CTRL.LCD_E <= '1';
118 LCD_CTRL.LCD_E <= '1';
138 state <= Enable1;
119 state <= Enable1;
139 else
120 else
140 reset_i <= '1';
121 reset_i <= '1';
141 LCD_CTRL.LCD_E <= '0';
122 LCD_CTRL.LCD_E <= '0';
142 end if;
123 end if;
143 when Enable1 =>
124 when Enable1 =>
144 if i = 2 then
125 if i = 2 then
145 reset_i <= '0';
126 reset_i <= '0';
146 LCD_CTRL.LCD_E <= '0';
127 LCD_CTRL.LCD_E <= '0';
147 state <= Enable2;
128 state <= Enable2;
148 else
129 else
149 reset_i <= '1';
130 reset_i <= '1';
150 LCD_CTRL.LCD_E <= '1';
131 LCD_CTRL.LCD_E <= '1';
151 end if;
132 end if;
152 when Enable2 =>
133 when Enable2 =>
153 if i = 1 then
134 if i = 1 then
154 reset_i <= '0';
135 reset_i <= '0';
155 LCD_CTRL.LCD_E <= '0';
136 LCD_CTRL.LCD_E <= '0';
156 state <= tempo;
137 state <= tempo;
157 else
138 else
158 reset_i <= '1';
139 reset_i <= '1';
159 LCD_CTRL.LCD_E <= '0';
140 LCD_CTRL.LCD_E <= '0';
160 end if;
141 end if;
161 when tempo =>
142 when tempo =>
162 if i = tempoTRIG then
143 if i = tempoTRIG then
163 reset_i <= '0';
144 reset_i <= '0';
164 state <= idle;
145 state <= idle;
165 else
146 else
166 reset_i <= '1';
147 reset_i <= '1';
167 end if;
148 end if;
168 end case;
149 end case;
169 end if;
150 end if;
170 end process;
151 end process;
171
152
172 end Behavioral;
153 end Behavioral;
173
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 08:32:21 10/19/2010
24 -- Design Name:
25 -- Module Name: LCD_16x2_ENGINE - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
19 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
40 use IEEE.NUMERIC_STD.ALL;
21 use IEEE.NUMERIC_STD.ALL;
41
22
42 library lpp;
23 library lpp;
43 use lpp.amba_lcd_16x2_ctrlr.all;
24 use lpp.amba_lcd_16x2_ctrlr.all;
44 use lpp.LCD_16x2_CFG.all;
25 use lpp.LCD_16x2_CFG.all;
45
26
46
27
47 entity LCD_16x2_ENGINE is
28 entity LCD_16x2_ENGINE is
48 generic(OSC_freqKHz : integer := 50000);
29 generic(OSC_freqKHz : integer := 50000);
49 Port ( clk : in STD_LOGIC;
30 Port ( clk : in STD_LOGIC;
50 reset : in STD_LOGIC;
31 reset : in STD_LOGIC;
51 DATA : in FRM_Buff_Space;
32 DATA : in FRM_Buff_Space;
52 CMD : in std_logic_vector(10 downto 0);
33 CMD : in std_logic_vector(10 downto 0);
53 Exec : in std_logic;
34 Exec : in std_logic;
54 Ready : out std_logic;
35 Ready : out std_logic;
55 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
36 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
56 );
37 );
57 end LCD_16x2_ENGINE;
38 end LCD_16x2_ENGINE;
58
39
59 architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
40 architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
60
41
61 constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
42 constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
62
43
63
44
64
45
65 signal SYNCH : LCD_DRVR_SYNCH_BUSS;
46 signal SYNCH : LCD_DRVR_SYNCH_BUSS;
66 signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
47 signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
67 signal FRAME_CLK : std_logic;
48 signal FRAME_CLK : std_logic;
68
49
69 signal FRAME_CLK_reg : std_logic;
50 signal FRAME_CLK_reg : std_logic;
70 signal RefreshFlag : std_logic;
51 signal RefreshFlag : std_logic;
71 signal CMD_Flag : std_logic;
52 signal CMD_Flag : std_logic;
72 signal Exec_Reg : std_logic;
53 signal Exec_Reg : std_logic;
73
54
74 type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
55 type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
75 signal state : state_t;
56 signal state : state_t;
76 signal i : integer range 0 to lcd_space_size := 0;
57 signal i : integer range 0 to lcd_space_size := 0;
77
58
78
59
79
60
80 begin
61 begin
81
62
82 Driver0 : LCD_16x2_DRIVER
63 Driver0 : LCD_16x2_DRIVER
83 generic map(OSC_freqKHz)
64 generic map(OSC_freqKHz)
84 Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
65 Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
85
66
86 FRAME_CLK_GEN0 : FRAME_CLK_GEN
67 FRAME_CLK_GEN0 : FRAME_CLK_GEN
87 generic map(OSC_freqKHz)
68 generic map(OSC_freqKHz)
88 Port map( clk,reset,FRAME_CLK);
69 Port map( clk,reset,FRAME_CLK);
89
70
90
71
91
72
92 process(reset,clk)
73 process(reset,clk)
93 begin
74 begin
94 if reset = '0' then
75 if reset = '0' then
95 state <= INIT0;
76 state <= INIT0;
96 Ready <= '0';
77 Ready <= '0';
97 RefreshFlag <= '0';
78 RefreshFlag <= '0';
98 i <= 0;
79 i <= 0;
99 elsif clk'event and clk ='1' then
80 elsif clk'event and clk ='1' then
100 FRAME_CLK_reg <= FRAME_CLK;
81 FRAME_CLK_reg <= FRAME_CLK;
101 Exec_Reg <= Exec;
82 Exec_Reg <= Exec;
102
83
103 if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
84 if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
104 RefreshFlag <= '1';
85 RefreshFlag <= '1';
105 elsif state = Refresh or state = Refresh0 or state = Refresh1 then
86 elsif state = Refresh or state = Refresh0 or state = Refresh1 then
106 RefreshFlag <= '0';
87 RefreshFlag <= '0';
107 end if;
88 end if;
108
89
109 if Exec_Reg = '0' and Exec = '1' then
90 if Exec_Reg = '0' and Exec = '1' then
110 CMD_Flag <= '1';
91 CMD_Flag <= '1';
111 elsif state = ExecCMD0 or state = ExecCMD1 then
92 elsif state = ExecCMD0 or state = ExecCMD1 then
112 CMD_Flag <= '0';
93 CMD_Flag <= '0';
113 end if;
94 end if;
114
95
115 case state is
96 case state is
116 when INIT0 =>
97 when INIT0 =>
117 if SYNCH.DRVR_READY = '1' then
98 if SYNCH.DRVR_READY = '1' then
118 DRIVER_CMD.Exec <= '1';
99 DRIVER_CMD.Exec <= '1';
119 DRIVER_CMD.Duration <= Duration_20ms;
100 DRIVER_CMD.Duration <= Duration_20ms;
120 DRIVER_CMD.CMD_Data <= '0';
101 DRIVER_CMD.CMD_Data <= '0';
121 DRIVER_CMD.Word <= ConfigTbl(i);
102 DRIVER_CMD.Word <= ConfigTbl(i);
122 i <= i + 1;
103 i <= i + 1;
123 state <= INIT1;
104 state <= INIT1;
124 else
105 else
125 DRIVER_CMD.Exec <= '0';
106 DRIVER_CMD.Exec <= '0';
126 end if;
107 end if;
127 when INIT1 =>
108 when INIT1 =>
128 state <= INIT2;
109 state <= INIT2;
129 DRIVER_CMD.Exec <= '0';
110 DRIVER_CMD.Exec <= '0';
130 when INIT2 =>
111 when INIT2 =>
131 if SYNCH.DRVR_READY = '1' then
112 if SYNCH.DRVR_READY = '1' then
132 if i = 5 then
113 if i = 5 then
133 state <= Idle;
114 state <= Idle;
134 else
115 else
135 state <= INIT0;
116 state <= INIT0;
136 end if;
117 end if;
137 end if;
118 end if;
138 when Idle=>
119 when Idle=>
139 DRIVER_CMD.Exec <= '0';
120 DRIVER_CMD.Exec <= '0';
140 if RefreshFlag = '1' then
121 if RefreshFlag = '1' then
141 Ready <= '0';
122 Ready <= '0';
142 state <= Refresh;
123 state <= Refresh;
143 elsif CMD_Flag = '1' then
124 elsif CMD_Flag = '1' then
144 Ready <= '0';
125 Ready <= '0';
145 state <= ExecCMD0;
126 state <= ExecCMD0;
146 else
127 else
147 Ready <= '1';
128 Ready <= '1';
148 end if;
129 end if;
149 i <= 0;
130 i <= 0;
150 when Refresh=>
131 when Refresh=>
151 if SYNCH.DRVR_READY = '1' then
132 if SYNCH.DRVR_READY = '1' then
152 DRIVER_CMD.Exec <= '1';
133 DRIVER_CMD.Exec <= '1';
153 DRIVER_CMD.Duration <= Duration_100us;
134 DRIVER_CMD.Duration <= Duration_100us;
154 DRIVER_CMD.CMD_Data <= '1';
135 DRIVER_CMD.CMD_Data <= '1';
155 DRIVER_CMD.Word <= DATA(i);
136 DRIVER_CMD.Word <= DATA(i);
156 state <= Refresh0;
137 state <= Refresh0;
157 else
138 else
158 DRIVER_CMD.Exec <= '0';
139 DRIVER_CMD.Exec <= '0';
159 end if;
140 end if;
160 when Refresh0=>
141 when Refresh0=>
161 i <= i + 1;
142 i <= i + 1;
162 state <= Refresh1;
143 state <= Refresh1;
163 DRIVER_CMD.Exec <= '0';
144 DRIVER_CMD.Exec <= '0';
164 when Refresh1=>
145 when Refresh1=>
165 if SYNCH.DRVR_READY = '1' then
146 if SYNCH.DRVR_READY = '1' then
166 if i = lcd_space_size then
147 if i = lcd_space_size then
167 -- state <= ReturnHome;
148 -- state <= ReturnHome;
168 state <= Idle;
149 state <= Idle;
169 -- elsif i = 16 then
150 -- elsif i = 16 then
170 -- state <= GoLine2;
151 -- state <= GoLine2;
171 else
152 else
172 state <= Refresh;
153 state <= Refresh;
173 end if;
154 end if;
174 end if;
155 end if;
175
156
176 when ExecCMD0=>
157 when ExecCMD0=>
177 if SYNCH.DRVR_READY = '1' then
158 if SYNCH.DRVR_READY = '1' then
178 DRIVER_CMD.Exec <= '1';
159 DRIVER_CMD.Exec <= '1';
179 DRIVER_CMD.Duration <= CMD(9 downto 8);
160 DRIVER_CMD.Duration <= CMD(9 downto 8);
180 DRIVER_CMD.CMD_Data <= '0';
161 DRIVER_CMD.CMD_Data <= '0';
181 DRIVER_CMD.Word <= CMD(7 downto 0);
162 DRIVER_CMD.Word <= CMD(7 downto 0);
182 state <= ExecCMD1;
163 state <= ExecCMD1;
183 else
164 else
184 DRIVER_CMD.Exec <= '0';
165 DRIVER_CMD.Exec <= '0';
185 end if;
166 end if;
186
167
187 when ExecCMD1=>
168 when ExecCMD1=>
188 state <= Idle;
169 state <= Idle;
189 DRIVER_CMD.Exec <= '0';
170 DRIVER_CMD.Exec <= '0';
190
171
191 when GoLine2=>
172 when GoLine2=>
192 if SYNCH.DRVR_READY = '1' then
173 if SYNCH.DRVR_READY = '1' then
193 DRIVER_CMD.Exec <= '1';
174 DRIVER_CMD.Exec <= '1';
194 DRIVER_CMD.Duration <= Duration_4ms;
175 DRIVER_CMD.Duration <= Duration_4ms;
195 DRIVER_CMD.CMD_Data <= '0';
176 DRIVER_CMD.CMD_Data <= '0';
196 DRIVER_CMD.Word <= X"C0";
177 DRIVER_CMD.Word <= X"C0";
197 state <= GoLine2_0;
178 state <= GoLine2_0;
198 else
179 else
199 DRIVER_CMD.Exec <= '0';
180 DRIVER_CMD.Exec <= '0';
200 end if;
181 end if;
201 when GoLine2_0=>
182 when GoLine2_0=>
202 state <= Refresh;
183 state <= Refresh;
203 DRIVER_CMD.Exec <= '0';
184 DRIVER_CMD.Exec <= '0';
204 when ReturnHome=>
185 when ReturnHome=>
205 if SYNCH.DRVR_READY = '1' then
186 if SYNCH.DRVR_READY = '1' then
206 DRIVER_CMD.Exec <= '1';
187 DRIVER_CMD.Exec <= '1';
207 DRIVER_CMD.Duration <= Duration_4ms;
188 DRIVER_CMD.Duration <= Duration_4ms;
208 DRIVER_CMD.CMD_Data <= '0';
189 DRIVER_CMD.CMD_Data <= '0';
209 DRIVER_CMD.Word <= RetHome;
190 DRIVER_CMD.Word <= RetHome;
210 state <= Idle;
191 state <= Idle;
211 else
192 else
212 DRIVER_CMD.Exec <= '0';
193 DRIVER_CMD.Exec <= '0';
213 end if;
194 end if;
214 end case;
195 end case;
215 end if;
196 end if;
216 end process;
197 end process;
217
198
218
199
219 end ar_LCD_16x2_ENGINE;
200 end ar_LCD_16x2_ENGINE;
220
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 10:09:57 10/13/2010
24 -- Design Name:
25 -- Module Name: LCD_2x16_DRIVER - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
19 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
40 use IEEE.NUMERIC_STD.all;
21 use IEEE.NUMERIC_STD.all;
41 library lpp;
22 library lpp;
42 use lpp.amba_lcd_16x2_ctrlr.all;
23 use lpp.amba_lcd_16x2_ctrlr.all;
43
24
44 entity LCD_2x16_DRIVER is
25 entity LCD_2x16_DRIVER is
45 generic(
26 generic(
46 OSC_Freq_MHz : integer:=60;
27 OSC_Freq_MHz : integer:=60;
47 Refresh_RateHz : integer:=5
28 Refresh_RateHz : integer:=5
48 );
29 );
49 Port ( clk : in STD_LOGIC;
30 Port ( clk : in STD_LOGIC;
50 reset : in STD_LOGIC;
31 reset : in STD_LOGIC;
51 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
32 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
52 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
33 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
53 LCD_RS : out STD_LOGIC;
34 LCD_RS : out STD_LOGIC;
54 LCD_RW : out STD_LOGIC;
35 LCD_RW : out STD_LOGIC;
55 LCD_E : out STD_LOGIC;
36 LCD_E : out STD_LOGIC;
56 LCD_RET : out STD_LOGIC;
37 LCD_RET : out STD_LOGIC;
57 LCD_CS1 : out STD_LOGIC;
38 LCD_CS1 : out STD_LOGIC;
58 LCD_CS2 : out STD_LOGIC;
39 LCD_CS2 : out STD_LOGIC;
59 STATEOUT: out std_logic_vector(3 downto 0);
40 STATEOUT: out std_logic_vector(3 downto 0);
60 refreshPulse : out std_logic
41 refreshPulse : out std_logic
61 );
42 );
62 end LCD_2x16_DRIVER;
43 end LCD_2x16_DRIVER;
63
44
64 architecture Behavioral of LCD_2x16_DRIVER is
45 architecture Behavioral of LCD_2x16_DRIVER is
65
46
66 type stateT is(Rst,Configure,IDLE,RefreshScreen);
47 type stateT is(Rst,Configure,IDLE,RefreshScreen);
67 signal state : stateT;
48 signal state : stateT;
68
49
69 signal ShortTimePulse : std_logic;
50 signal ShortTimePulse : std_logic;
70 signal MidleTimePulse : std_logic;
51 signal MidleTimePulse : std_logic;
71 signal Refresh_RatePulse : std_logic;
52 signal Refresh_RatePulse : std_logic;
72 signal Start : STD_LOGIC;
53 signal Start : STD_LOGIC;
73
54
74 signal CFGM_LCD_RS : std_logic;
55 signal CFGM_LCD_RS : std_logic;
75 signal CFGM_LCD_RW : std_logic;
56 signal CFGM_LCD_RW : std_logic;
76 signal CFGM_LCD_E : std_logic;
57 signal CFGM_LCD_E : std_logic;
77 signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
58 signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
78 signal CFGM_Enable : std_logic;
59 signal CFGM_Enable : std_logic;
79 signal CFGM_completed : std_logic;
60 signal CFGM_completed : std_logic;
80
61
81
62
82 signal FRMW_LCD_RS : std_logic;
63 signal FRMW_LCD_RS : std_logic;
83 signal FRMW_LCD_RW : std_logic;
64 signal FRMW_LCD_RW : std_logic;
84 signal FRMW_LCD_E : std_logic;
65 signal FRMW_LCD_E : std_logic;
85 signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
66 signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
86 signal FRMW_Enable : std_logic;
67 signal FRMW_Enable : std_logic;
87 signal FRMW_completed : std_logic;
68 signal FRMW_completed : std_logic;
88
69
89 begin
70 begin
90
71
91
72
92 Counter : LCD_Counter
73 Counter : LCD_Counter
93 generic map(OSC_Freq_MHz,Refresh_RateHz)
74 generic map(OSC_Freq_MHz,Refresh_RateHz)
94 port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
75 port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
95
76
96 ConfigModule : Config_Module
77 ConfigModule : Config_Module
97 port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
78 port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
98
79
99
80
100 FrameWriter : FRAME_WRITER
81 FrameWriter : FRAME_WRITER
101 port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
82 port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
102
83
103
84
104 STATEOUT(0) <= '1' when state = Rst else '0';
85 STATEOUT(0) <= '1' when state = Rst else '0';
105 STATEOUT(1) <= '1' when state = Configure else '0';
86 STATEOUT(1) <= '1' when state = Configure else '0';
106 STATEOUT(2) <= '1' when state = IDLE else '0';
87 STATEOUT(2) <= '1' when state = IDLE else '0';
107 STATEOUT(3) <= '1' when state = RefreshScreen else '0';
88 STATEOUT(3) <= '1' when state = RefreshScreen else '0';
108
89
109
90
110
91
111 refreshPulse <= Refresh_RatePulse;
92 refreshPulse <= Refresh_RatePulse;
112
93
113 Start <= '1';
94 Start <= '1';
114
95
115 process(reset,clk)
96 process(reset,clk)
116 begin
97 begin
117 if reset = '0' then
98 if reset = '0' then
118 LCD_data <= (others=>'0');
99 LCD_data <= (others=>'0');
119 LCD_RS <= '0';
100 LCD_RS <= '0';
120 LCD_RW <= '0';
101 LCD_RW <= '0';
121 LCD_RET <= '0';
102 LCD_RET <= '0';
122 LCD_CS1 <= '0';
103 LCD_CS1 <= '0';
123 LCD_CS2 <= '0';
104 LCD_CS2 <= '0';
124 LCD_E <= '0';
105 LCD_E <= '0';
125 state <= Rst;
106 state <= Rst;
126 CFGM_Enable <= '0';
107 CFGM_Enable <= '0';
127 FRMW_Enable <= '0';
108 FRMW_Enable <= '0';
128 elsif clk'event and clk ='1' then
109 elsif clk'event and clk ='1' then
129 case state is
110 case state is
130 when Rst =>
111 when Rst =>
131 LCD_data <= (others=>'0');
112 LCD_data <= (others=>'0');
132 LCD_RS <= '0';
113 LCD_RS <= '0';
133 LCD_RW <= '0';
114 LCD_RW <= '0';
134 LCD_E <= '0';
115 LCD_E <= '0';
135 CFGM_Enable <= '1';
116 CFGM_Enable <= '1';
136 FRMW_Enable <= '0';
117 FRMW_Enable <= '0';
137 if Refresh_RatePulse = '1' then
118 if Refresh_RatePulse = '1' then
138 state <= Configure;
119 state <= Configure;
139 end if;
120 end if;
140 when Configure =>
121 when Configure =>
141 LCD_data <= CFGM_LCD_data;
122 LCD_data <= CFGM_LCD_data;
142 LCD_RS <= CFGM_LCD_RS;
123 LCD_RS <= CFGM_LCD_RS;
143 LCD_RW <= CFGM_LCD_RW;
124 LCD_RW <= CFGM_LCD_RW;
144 LCD_E <= CFGM_LCD_E;
125 LCD_E <= CFGM_LCD_E;
145 CFGM_Enable <= '0';
126 CFGM_Enable <= '0';
146 if CFGM_completed = '1' then
127 if CFGM_completed = '1' then
147 state <= IDLE;
128 state <= IDLE;
148 end if;
129 end if;
149 when IDLE =>
130 when IDLE =>
150 if Refresh_RatePulse = '1' then
131 if Refresh_RatePulse = '1' then
151 state <= RefreshScreen;
132 state <= RefreshScreen;
152 FRMW_Enable <= '1';
133 FRMW_Enable <= '1';
153 end if;
134 end if;
154 LCD_RS <= '0';
135 LCD_RS <= '0';
155 LCD_RW <= '0';
136 LCD_RW <= '0';
156 LCD_E <= '0';
137 LCD_E <= '0';
157 LCD_data <= (others=>'0');
138 LCD_data <= (others=>'0');
158 when RefreshScreen =>
139 when RefreshScreen =>
159 LCD_data <= FRMW_LCD_data;
140 LCD_data <= FRMW_LCD_data;
160 LCD_RS <= FRMW_LCD_RS;
141 LCD_RS <= FRMW_LCD_RS;
161 LCD_RW <= FRMW_LCD_RW;
142 LCD_RW <= FRMW_LCD_RW;
162 LCD_E <= FRMW_LCD_E;
143 LCD_E <= FRMW_LCD_E;
163 FRMW_Enable <= '0';
144 FRMW_Enable <= '0';
164 if FRMW_completed = '1' then
145 if FRMW_completed = '1' then
165 state <= IDLE;
146 state <= IDLE;
166 end if;
147 end if;
167 end case;
148 end case;
168 end if;
149 end if;
169 end process;
150 end process;
170 end Behavioral;
151 end Behavioral;
171
152
172
153
173
154
174
155
175
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@@ -1,91 +1,72
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 08:52:25 10/18/2010
24 -- Design Name:
25 -- Module Name: LCD_CLK_GENERATOR - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
19 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
40 use IEEE.NUMERIC_STD.ALL;
21 use IEEE.NUMERIC_STD.ALL;
41 library lpp;
22 library lpp;
42 use lpp.amba_lcd_16x2_ctrlr.all;
23 use lpp.amba_lcd_16x2_ctrlr.all;
43
24
44 entity LCD_CLK_GENERATOR is
25 entity LCD_CLK_GENERATOR is
45 generic(OSC_freqKHz : integer := 50000);
26 generic(OSC_freqKHz : integer := 50000);
46 Port ( clk : in STD_LOGIC;
27 Port ( clk : in STD_LOGIC;
47 reset : in STD_LOGIC;
28 reset : in STD_LOGIC;
48 clk_1us : out STD_LOGIC);
29 clk_1us : out STD_LOGIC);
49 end LCD_CLK_GENERATOR;
30 end LCD_CLK_GENERATOR;
50
31
51 architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
32 architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
52
33
53 Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
34 Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
54
35
55
36
56 signal cpt1 : integer;
37 signal cpt1 : integer;
57
38
58 signal clk_1us_int : std_logic := '0';
39 signal clk_1us_int : std_logic := '0';
59
40
60
41
61 begin
42 begin
62
43
63 clk_1us <= clk_1us_int;
44 clk_1us <= clk_1us_int;
64
45
65
46
66 process(reset,clk)
47 process(reset,clk)
67 begin
48 begin
68 if reset = '0' then
49 if reset = '0' then
69 cpt1 <= 0;
50 cpt1 <= 0;
70 clk_1us_int <= '0';
51 clk_1us_int <= '0';
71 elsif clk'event and clk = '1' then
52 elsif clk'event and clk = '1' then
72 if cpt1 = clk_1usTRIGER then
53 if cpt1 = clk_1usTRIGER then
73 clk_1us_int <= not clk_1us_int;
54 clk_1us_int <= not clk_1us_int;
74 cpt1 <= 0;
55 cpt1 <= 0;
75 else
56 else
76 cpt1 <= cpt1 + 1;
57 cpt1 <= cpt1 + 1;
77 end if;
58 end if;
78 end if;
59 end if;
79 end process;
60 end process;
80
61
81
62
82 end ar_LCD_CLK_GENERATOR;
63 end ar_LCD_CLK_GENERATOR;
83
64
84
65
85
66
86
67
87
68
88
69
89
70
90
71
91
72
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@@ -1,123 +1,105
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 08:44:41 10/14/2010
24 -- Design Name:
25 -- Module Name: Top_LCD - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
20 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_1164.ALL;
40
22
41 library lpp;
23 library lpp;
42 use lpp.amba_lcd_16x2_ctrlr.all;
24 use lpp.amba_lcd_16x2_ctrlr.all;
43 use lpp.LCD_16x2_CFG.all;
25 use lpp.LCD_16x2_CFG.all;
44
26
45
27
46 entity AMBA_LCD_16x2_DRIVER is
28 entity AMBA_LCD_16x2_DRIVER is
47 Port ( reset : in STD_LOGIC;
29 Port ( reset : in STD_LOGIC;
48 clk : in STD_LOGIC;
30 clk : in STD_LOGIC;
49 Bp0 : in STD_LOGIC;
31 Bp0 : in STD_LOGIC;
50 Bp1 : in STD_LOGIC;
32 Bp1 : in STD_LOGIC;
51 Bp2 : in STD_LOGIC;
33 Bp2 : in STD_LOGIC;
52 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
34 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
53 LCD_RS : out STD_LOGIC;
35 LCD_RS : out STD_LOGIC;
54 LCD_RW : out STD_LOGIC;
36 LCD_RW : out STD_LOGIC;
55 LCD_E : out STD_LOGIC;
37 LCD_E : out STD_LOGIC;
56 LCD_RET : out STD_LOGIC;
38 LCD_RET : out STD_LOGIC;
57 LCD_CS1 : out STD_LOGIC;
39 LCD_CS1 : out STD_LOGIC;
58 LCD_CS2 : out STD_LOGIC;
40 LCD_CS2 : out STD_LOGIC;
59 SF_CE0 : out std_logic
41 SF_CE0 : out std_logic
60 );
42 );
61 end AMBA_LCD_16x2_DRIVER;
43 end AMBA_LCD_16x2_DRIVER;
62
44
63 architecture Behavioral of AMBA_LCD_16x2_DRIVER is
45 architecture Behavioral of AMBA_LCD_16x2_DRIVER is
64
46
65 signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
47 signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
66 signal CMD : std_logic_vector(10 downto 0);
48 signal CMD : std_logic_vector(10 downto 0);
67 signal Exec : std_logic;
49 signal Exec : std_logic;
68 signal Ready : std_logic;
50 signal Ready : std_logic;
69 signal rst : std_logic;
51 signal rst : std_logic;
70 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
52 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
71
53
72 begin
54 begin
73
55
74 LCD_data <= LCD_CTRL.LCD_DATA;
56 LCD_data <= LCD_CTRL.LCD_DATA;
75 LCD_RS <= LCD_CTRL.LCD_RS;
57 LCD_RS <= LCD_CTRL.LCD_RS;
76 LCD_RW <= LCD_CTRL.LCD_RW;
58 LCD_RW <= LCD_CTRL.LCD_RW;
77 LCD_E <= LCD_CTRL.LCD_E;
59 LCD_E <= LCD_CTRL.LCD_E;
78
60
79
61
80 LCD_RET <= '0';
62 LCD_RET <= '0';
81 LCD_CS1 <= '0';
63 LCD_CS1 <= '0';
82 LCD_CS2 <= '0';
64 LCD_CS2 <= '0';
83
65
84 SF_CE0 <= '1';
66 SF_CE0 <= '1';
85
67
86
68
87
69
88
70
89 Driver0 : LCD_16x2_ENGINE
71 Driver0 : LCD_16x2_ENGINE
90 generic map(50000)
72 generic map(50000)
91 Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
73 Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
92
74
93 FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
75 FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
94 X"42" when Bp1 = '1' else
76 X"42" when Bp1 = '1' else
95 X"43" when Bp2 = '1' else
77 X"43" when Bp2 = '1' else
96 X"44";
78 X"44";
97
79
98 FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
80 FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
99 X"47" when Bp1 = '1' else
81 X"47" when Bp1 = '1' else
100 X"48" when Bp2 = '1' else
82 X"48" when Bp2 = '1' else
101 X"49";
83 X"49";
102
84
103
85
104 CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
86 CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
105 Duration_100us & CursorOFF;
87 Duration_100us & CursorOFF;
106
88
107
89
108 Exec <= Bp1;
90 Exec <= Bp1;
109
91
110 FramBUFF(2*8+7 downto 2*8) <= X"23";
92 FramBUFF(2*8+7 downto 2*8) <= X"23";
111 FramBUFF(3*8+7 downto 3*8) <= X"66";
93 FramBUFF(3*8+7 downto 3*8) <= X"66";
112 FramBUFF(4*8+7 downto 4*8) <= X"67";
94 FramBUFF(4*8+7 downto 4*8) <= X"67";
113 FramBUFF(5*8+7 downto 5*8) <= X"68";
95 FramBUFF(5*8+7 downto 5*8) <= X"68";
114 FramBUFF(17*8+7 downto 17*8) <= X"69";
96 FramBUFF(17*8+7 downto 17*8) <= X"69";
115 --FramBUFF(16*2*8-1 downto 16) <= (others => '0');
97 --FramBUFF(16*2*8-1 downto 16) <= (others => '0');
116
98
117 end Behavioral;
99 end Behavioral;
118
100
119
101
120
102
121
103
122
104
123
105
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@@ -1,171 +1,170
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 library grlib;
21 library grlib;
23 use grlib.amba.all;
22 use grlib.amba.all;
24 use grlib.stdlib.all;
23 use grlib.stdlib.all;
25 use grlib.devices.all;
24 use grlib.devices.all;
26
25
27
26
28 package amba_lcd_16x2_ctrlr is
27 package amba_lcd_16x2_ctrlr is
29
28
30 constant lcd_space_size : integer := 80;
29 constant lcd_space_size : integer := 80;
31
30
32 type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0);
31 type FRM_Buff_Space is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0);
33
32
34
33
35 type LCD_DRVR_CTRL_BUSS is
34 type LCD_DRVR_CTRL_BUSS is
36 record
35 record
37 LCD_RW : std_logic;
36 LCD_RW : std_logic;
38 LCD_RS : std_logic;
37 LCD_RS : std_logic;
39 LCD_E : std_logic;
38 LCD_E : std_logic;
40 LCD_DATA : std_logic_vector(7 downto 0);
39 LCD_DATA : std_logic_vector(7 downto 0);
41 end record;
40 end record;
42
41
43 type LCD_DRVR_SYNCH_BUSS is
42 type LCD_DRVR_SYNCH_BUSS is
44 record
43 record
45 DRVR_READY : std_logic;
44 DRVR_READY : std_logic;
46 LCD_INITIALISED : std_logic;
45 LCD_INITIALISED : std_logic;
47 end record;
46 end record;
48
47
49
48
50 type LCD_DRVR_CMD_BUSS is
49 type LCD_DRVR_CMD_BUSS is
51 record
50 record
52 Word : std_logic_vector(7 downto 0);
51 Word : std_logic_vector(7 downto 0);
53 CMD_Data : std_logic; --CMD = '0' and data = '1'
52 CMD_Data : std_logic; --CMD = '0' and data = '1'
54 Exec : std_logic;
53 Exec : std_logic;
55 Duration : std_logic_vector(1 downto 0);
54 Duration : std_logic_vector(1 downto 0);
56 end record;
55 end record;
57 type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
56 type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
58
57
59
58
60
59
61 component LCD_16x2_DRIVER is
60 component LCD_16x2_DRIVER is
62 generic(
61 generic(
63 OSC_Freq_MHz : integer:=60
62 OSC_Freq_MHz : integer:=60
64 );
63 );
65 Port ( reset : in STD_LOGIC;
64 Port ( reset : in STD_LOGIC;
66 clk : in STD_LOGIC;
65 clk : in STD_LOGIC;
67 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
66 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
68 SYNCH : out LCD_DRVR_SYNCH_BUSS;
67 SYNCH : out LCD_DRVR_SYNCH_BUSS;
69 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
68 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
70 );
69 );
71 end component;
70 end component;
72
71
73
72
74
73
75 component amba_lcd_16x2_driver is
74 component amba_lcd_16x2_driver is
76 Port ( reset : in STD_LOGIC;
75 Port ( reset : in STD_LOGIC;
77 clk : in STD_LOGIC;
76 clk : in STD_LOGIC;
78 Bp0 : in STD_LOGIC;
77 Bp0 : in STD_LOGIC;
79 Bp1 : in STD_LOGIC;
78 Bp1 : in STD_LOGIC;
80 Bp2 : in STD_LOGIC;
79 Bp2 : in STD_LOGIC;
81 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
80 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
82 LCD_RS : out STD_LOGIC;
81 LCD_RS : out STD_LOGIC;
83 LCD_RW : out STD_LOGIC;
82 LCD_RW : out STD_LOGIC;
84 LCD_E : out STD_LOGIC;
83 LCD_E : out STD_LOGIC;
85 LCD_RET : out STD_LOGIC;
84 LCD_RET : out STD_LOGIC;
86 LCD_CS1 : out STD_LOGIC;
85 LCD_CS1 : out STD_LOGIC;
87 LCD_CS2 : out STD_LOGIC;
86 LCD_CS2 : out STD_LOGIC;
88 SF_CE0 : out std_logic
87 SF_CE0 : out std_logic
89 );
88 );
90 end component;
89 end component;
91
90
92
91
93
92
94 component FRAME_CLK_GEN is
93 component FRAME_CLK_GEN is
95 generic(OSC_freqKHz : integer := 50000);
94 generic(OSC_freqKHz : integer := 50000);
96 Port ( clk : in STD_LOGIC;
95 Port ( clk : in STD_LOGIC;
97 reset : in STD_LOGIC;
96 reset : in STD_LOGIC;
98 FRAME_CLK : out STD_LOGIC);
97 FRAME_CLK : out STD_LOGIC);
99 end component;
98 end component;
100
99
101
100
102
101
103 component LCD_2x16_DRIVER is
102 component LCD_2x16_DRIVER is
104 generic(
103 generic(
105 OSC_Freq_MHz : integer:=60;
104 OSC_Freq_MHz : integer:=60;
106 Refresh_RateHz : integer:=5
105 Refresh_RateHz : integer:=5
107 );
106 );
108 Port ( clk : in STD_LOGIC;
107 Port ( clk : in STD_LOGIC;
109 reset : in STD_LOGIC;
108 reset : in STD_LOGIC;
110 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
109 FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
111 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
110 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
112 LCD_RS : out STD_LOGIC;
111 LCD_RS : out STD_LOGIC;
113 LCD_RW : out STD_LOGIC;
112 LCD_RW : out STD_LOGIC;
114 LCD_E : out STD_LOGIC;
113 LCD_E : out STD_LOGIC;
115 LCD_RET : out STD_LOGIC;
114 LCD_RET : out STD_LOGIC;
116 LCD_CS1 : out STD_LOGIC;
115 LCD_CS1 : out STD_LOGIC;
117 LCD_CS2 : out STD_LOGIC;
116 LCD_CS2 : out STD_LOGIC;
118 STATEOUT: out std_logic_vector(3 downto 0);
117 STATEOUT: out std_logic_vector(3 downto 0);
119 refreshPulse : out std_logic
118 refreshPulse : out std_logic
120 );
119 );
121 end component;
120 end component;
122
121
123
122
124 component LCD_CLK_GENERATOR is
123 component LCD_CLK_GENERATOR is
125 generic(OSC_freqKHz : integer := 50000);
124 generic(OSC_freqKHz : integer := 50000);
126 Port ( clk : in STD_LOGIC;
125 Port ( clk : in STD_LOGIC;
127 reset : in STD_LOGIC;
126 reset : in STD_LOGIC;
128 clk_1us : out STD_LOGIC);
127 clk_1us : out STD_LOGIC);
129 end component;
128 end component;
130
129
131 component LCD_16x2_ENGINE is
130 component LCD_16x2_ENGINE is
132 generic(OSC_freqKHz : integer := 50000);
131 generic(OSC_freqKHz : integer := 50000);
133 Port ( clk : in STD_LOGIC;
132 Port ( clk : in STD_LOGIC;
134 reset : in STD_LOGIC;
133 reset : in STD_LOGIC;
135 DATA : in FRM_Buff_Space;
134 DATA : in FRM_Buff_Space;
136 CMD : in std_logic_vector(10 downto 0);
135 CMD : in std_logic_vector(10 downto 0);
137 Exec : in std_logic;
136 Exec : in std_logic;
138 Ready : out std_logic;
137 Ready : out std_logic;
139 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
138 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
140 );
139 );
141 end component;
140 end component;
142
141
143
142
144
143
145 component apb_lcd_ctrlr is
144 component apb_lcd_ctrlr is
146 generic (
145 generic (
147 pindex : integer := 0;
146 pindex : integer := 0;
148 paddr : integer := 0;
147 paddr : integer := 0;
149 pmask : integer := 16#fff#;
148 pmask : integer := 16#fff#;
150 pirq : integer := 0;
149 pirq : integer := 0;
151 abits : integer := 8);
150 abits : integer := 8);
152 port (
151 port (
153 rst : in std_ulogic;
152 rst : in std_ulogic;
154 clk : in std_ulogic;
153 clk : in std_ulogic;
155 apbi : in apb_slv_in_type;
154 apbi : in apb_slv_in_type;
156 apbo : out apb_slv_out_type;
155 apbo : out apb_slv_out_type;
157 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
156 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
158 LCD_RS : out STD_LOGIC;
157 LCD_RS : out STD_LOGIC;
159 LCD_RW : out STD_LOGIC;
158 LCD_RW : out STD_LOGIC;
160 LCD_E : out STD_LOGIC;
159 LCD_E : out STD_LOGIC;
161 LCD_RET : out STD_LOGIC;
160 LCD_RET : out STD_LOGIC;
162 LCD_CS1 : out STD_LOGIC;
161 LCD_CS1 : out STD_LOGIC;
163 LCD_CS2 : out STD_LOGIC;
162 LCD_CS2 : out STD_LOGIC;
164 SF_CE0 : out std_logic
163 SF_CE0 : out std_logic
165 );
164 );
166 end component;
165 end component;
167
166
168
167
169
168
170
169
171 end;
170 end;
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@@ -1,182 +1,163
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 -- Company:
21 -- Engineer:
22 --
23 -- Create Date: 08:44:41 10/14/2010
24 -- Design Name:
25 -- Module Name: Top_LCD - Behavioral
26 -- Project Name:
27 -- Target Devices:
28 -- Tool versions:
29 -- Description:
30 --
31 -- Dependencies:
32 --
33 -- Revision:
34 -- Revision 0.01 - File Created
35 -- Additional Comments:
36 --
37 ----------------------------------------------------------------------------------
38 library IEEE;
19 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
20 use IEEE.STD_LOGIC_1164.ALL;
40 use ieee.numeric_std.all;
21 use ieee.numeric_std.all;
41 library grlib;
22 library grlib;
42 use grlib.amba.all;
23 use grlib.amba.all;
43 use grlib.stdlib.all;
24 use grlib.stdlib.all;
44 use grlib.devices.all;
25 use grlib.devices.all;
45 library lpp;
26 library lpp;
46 use lpp.amba_lcd_16x2_ctrlr.all;
27 use lpp.amba_lcd_16x2_ctrlr.all;
47 use lpp.LCD_16x2_CFG.all;
28 use lpp.LCD_16x2_CFG.all;
48 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
49
30
50 entity apb_lcd_ctrlr is
31 entity apb_lcd_ctrlr is
51 generic (
32 generic (
52 pindex : integer := 0;
33 pindex : integer := 0;
53 paddr : integer := 0;
34 paddr : integer := 0;
54 pmask : integer := 16#fff#;
35 pmask : integer := 16#fff#;
55 pirq : integer := 0;
36 pirq : integer := 0;
56 abits : integer := 8);
37 abits : integer := 8);
57 port (
38 port (
58 rst : in std_ulogic;
39 rst : in std_ulogic;
59 clk : in std_ulogic;
40 clk : in std_ulogic;
60 apbi : in apb_slv_in_type;
41 apbi : in apb_slv_in_type;
61 apbo : out apb_slv_out_type;
42 apbo : out apb_slv_out_type;
62 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
43 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
63 LCD_RS : out STD_LOGIC;
44 LCD_RS : out STD_LOGIC;
64 LCD_RW : out STD_LOGIC;
45 LCD_RW : out STD_LOGIC;
65 LCD_E : out STD_LOGIC;
46 LCD_E : out STD_LOGIC;
66 LCD_RET : out STD_LOGIC;
47 LCD_RET : out STD_LOGIC;
67 LCD_CS1 : out STD_LOGIC;
48 LCD_CS1 : out STD_LOGIC;
68 LCD_CS2 : out STD_LOGIC;
49 LCD_CS2 : out STD_LOGIC;
69 SF_CE0 : out std_logic
50 SF_CE0 : out std_logic
70 );
51 );
71 end apb_lcd_ctrlr;
52 end apb_lcd_ctrlr;
72
53
73 architecture Behavioral of apb_lcd_ctrlr is
54 architecture Behavioral of apb_lcd_ctrlr is
74
55
75 signal FramBUFF : FRM_Buff_Space;
56 signal FramBUFF : FRM_Buff_Space;
76 signal CMD : std_logic_vector(10 downto 0);
57 signal CMD : std_logic_vector(10 downto 0);
77 signal Exec : std_logic;
58 signal Exec : std_logic;
78 signal Ready : std_logic;
59 signal Ready : std_logic;
79 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
60 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
80
61
81
62
82
63
83 constant REVISION : integer := 1;
64 constant REVISION : integer := 1;
84
65
85 constant pconfig : apb_config_type := (
66 constant pconfig : apb_config_type := (
86 0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
67 0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
87 1 => apb_iobar(paddr, pmask));
68 1 => apb_iobar(paddr, pmask));
88
69
89
70
90 --type FRM_Buff_El is std_logic_vector(31 downto 0);
71 --type FRM_Buff_El is std_logic_vector(31 downto 0);
91 type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
72 type FRM_Buff_Reg is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
92
73
93
74
94 type LCD_ctrlr_Reg is record
75 type LCD_ctrlr_Reg is record
95 CTRL_Reg : std_logic_vector(31 downto 0);
76 CTRL_Reg : std_logic_vector(31 downto 0);
96 FRAME_BUFF : FRM_Buff_Reg;
77 FRAME_BUFF : FRM_Buff_Reg;
97 end record;
78 end record;
98
99 signal r : LCD_ctrlr_Reg;
100
79
101 signal Rdata : std_logic_vector(31 downto 0);
80 signal r : LCD_ctrlr_Reg;
102
81
103 begin
82 signal Rdata : std_logic_vector(31 downto 0);
83
84 begin
104
85
105 LCD_data <= LCD_CTRL.LCD_DATA;
86 LCD_data <= LCD_CTRL.LCD_DATA;
106 LCD_RS <= LCD_CTRL.LCD_RS;
87 LCD_RS <= LCD_CTRL.LCD_RS;
107 LCD_RW <= LCD_CTRL.LCD_RW;
88 LCD_RW <= LCD_CTRL.LCD_RW;
108 LCD_E <= LCD_CTRL.LCD_E;
89 LCD_E <= LCD_CTRL.LCD_E;
109
90
110
91
111 LCD_RET <= '0';
92 LCD_RET <= '0';
112 LCD_CS1 <= '0';
93 LCD_CS1 <= '0';
113 LCD_CS2 <= '0';
94 LCD_CS2 <= '0';
114
95
115 SF_CE0 <= '1';
96 SF_CE0 <= '1';
116
97
117 CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value
98 CMD(7 downto 0) <= r.CTRL_Reg(7 downto 0); --CMD value
118 CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value
99 CMD(9 downto 8) <= r.CTRL_Reg(9 downto 8); --CMD tempo value
119
100
120 r.CTRL_Reg(10) <= Ready;
101 r.CTRL_Reg(10) <= Ready;
121
102
122 Driver0 : LCD_16x2_ENGINE
103 Driver0 : LCD_16x2_ENGINE
123 generic map(50000)
104 generic map(50000)
124 Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
105 Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
125
106
126 FRM_BF : for i in 0 to lcd_space_size-1 generate
107 FRM_BF : for i in 0 to lcd_space_size-1 generate
127 FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0);
108 FramBUFF(i) <= r.FRAME_BUFF(i)(7 downto 0);
128 end generate;
109 end generate;
110
129
111
130
112 process(rst,clk)
131 process(rst,clk)
113 begin
132 begin
114 if rst = '0' then
133 if rst = '0' then
134 r.CTRL_Reg(9 downto 0) <= (others => '0');
115 r.CTRL_Reg(9 downto 0) <= (others => '0');
135 Exec <= '0';
116 Exec <= '0';
136 elsif clk'event and clk = '1' then
117 elsif clk'event and clk = '1' then
137
118
138 --APB Write OP
119 --APB Write OP
139 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
120 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
140 case apbi.paddr(7 downto 2) is
121 case apbi.paddr(7 downto 2) is
141 when "000000" =>
122 when "000000" =>
142 r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
123 r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
143 Exec <= '1';
124 Exec <= '1';
144 when others =>
125 when others =>
145 writeC: for i in 1 to lcd_space_size loop
126 writeC: for i in 1 to lcd_space_size loop
146 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
127 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
147 r.FRAME_BUFF(i-1) <= apbi.pwdata;
128 r.FRAME_BUFF(i-1) <= apbi.pwdata;
148 end if;
129 end if;
149 Exec <= '0';
130 Exec <= '0';
150 end loop;
131 end loop;
151 end case;
132 end case;
152 else
133 else
153 Exec <= '0';
134 Exec <= '0';
154 end if;
135 end if;
155
136
156 --APB READ OP
137 --APB READ OP
157 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
138 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
158 case apbi.paddr(7 downto 2) is
139 case apbi.paddr(7 downto 2) is
159 when "000000" =>
140 when "000000" =>
160 Rdata <= r.CTRL_Reg;
141 Rdata <= r.CTRL_Reg;
161 when others =>
142 when others =>
162 readC: for i in 1 to lcd_space_size loop
143 readC: for i in 1 to lcd_space_size loop
163 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
144 if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
164 Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
145 Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
165 end if;
146 end if;
166 end loop;
147 end loop;
167 end case;
148 end case;
168 end if;
149 end if;
169
150
170 end if;
151 end if;
171 apbo.pconfig <= pconfig;
152 apbo.pconfig <= pconfig;
172 end process;
153 end process;
173
154
174 apbo.prdata <= Rdata when apbi.penable = '1' ;
155 apbo.prdata <= Rdata when apbi.penable = '1' ;
175
156
176 end Behavioral;
157 end Behavioral;
177
158
178
159
179
160
180
161
181
162
182
163
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@@ -1,4 +1,7
1 ./general_purpose
1 ./general_purpose
2 ./lpp_ad_Conv
3 ./lpp_CNA_amba
4 ./lpp_uart
2 ./lpp_amba
5 ./lpp_amba
3 ./dsp/iir_filter
6 ./dsp/iir_filter
4 ./amba_lcd_16x2_ctrlr
7 ./amba_lcd_16x2_ctrlr
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@@ -1,193 +1,192
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- APB_IIR_CEL.vhd
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 use ieee.numeric_std.all;
21 use ieee.numeric_std.all;
23 library grlib;
22 library grlib;
24 use grlib.amba.all;
23 use grlib.amba.all;
25 use grlib.stdlib.all;
24 use grlib.stdlib.all;
26 use grlib.devices.all;
25 use grlib.devices.all;
27 library lpp;
26 library lpp;
28 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
29 use lpp.FILTERcfg.all;
28 use lpp.FILTERcfg.all;
30 use lpp.general_purpose.all;
29 use lpp.general_purpose.all;
31 use lpp.lpp_amba.all;
30 use lpp.lpp_amba.all;
32
31
33 entity APB_IIR_CEL is
32 entity APB_IIR_CEL is
34 generic (
33 generic (
35 pindex : integer := 0;
34 pindex : integer := 0;
36 paddr : integer := 0;
35 paddr : integer := 0;
37 pmask : integer := 16#fff#;
36 pmask : integer := 16#fff#;
38 pirq : integer := 0;
37 pirq : integer := 0;
39 abits : integer := 8;
38 abits : integer := 8;
40 Sample_SZ : integer := Smpl_SZ
39 Sample_SZ : integer := Smpl_SZ
41 );
40 );
42 port (
41 port (
43 rst : in std_logic;
42 rst : in std_logic;
44 clk : in std_logic;
43 clk : in std_logic;
45 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
47 sample_clk : in std_logic;
46 sample_clk : in std_logic;
48 sample_clk_out : out std_logic;
47 sample_clk_out : out std_logic;
49 sample_in : in samplT;
48 sample_in : in samplT;
50 sample_out : out samplT
49 sample_out : out samplT
51 );
50 );
52 end;
51 end;
53
52
54
53
55 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
54 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
56
55
57 constant REVISION : integer := 1;
56 constant REVISION : integer := 1;
58
57
59 constant pconfig : apb_config_type := (
58 constant pconfig : apb_config_type := (
60 0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
59 0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
61 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask));
62
61
63
62
64
63
65 type FILTERreg is record
64 type FILTERreg is record
66 regin : in_IIR_CEL_reg;
65 regin : in_IIR_CEL_reg;
67 regout : out_IIR_CEL_reg;
66 regout : out_IIR_CEL_reg;
68 end record;
67 end record;
69
68
70 signal r : FILTERreg;
69 signal r : FILTERreg;
71 signal filter_reset : std_logic:='0';
70 signal filter_reset : std_logic:='0';
72 signal smp_cnt : integer :=0;
71 signal smp_cnt : integer :=0;
73 signal sample_clk_out_R : std_logic;
72 signal sample_clk_out_R : std_logic;
74 begin
73 begin
75
74
76 filter_reset <= rst and r.regin.config(0);
75 filter_reset <= rst and r.regin.config(0);
77 sample_clk_out <= sample_clk_out_R;
76 sample_clk_out <= sample_clk_out_R;
78
77
79 filter : IIR_CEL_FILTER
78 filter : IIR_CEL_FILTER
80 generic map(Sample_SZ => Sample_SZ)
79 generic map(Sample_SZ => Sample_SZ)
81 port map(
80 port map(
82 reset => filter_reset,
81 reset => filter_reset,
83 clk => clk,
82 clk => clk,
84 sample_clk => sample_clk,
83 sample_clk => sample_clk,
85 regs_in => r.regin,
84 regs_in => r.regin,
86 regs_out => r.regout,
85 regs_out => r.regout,
87 sample_in => sample_in,
86 sample_in => sample_in,
88 sample_out => sample_out
87 sample_out => sample_out
89 );
88 );
90
89
91 process(rst,sample_clk)
90 process(rst,sample_clk)
92 begin
91 begin
93 if rst = '0' then
92 if rst = '0' then
94 smp_cnt <= 0;
93 smp_cnt <= 0;
95 sample_clk_out_R <= '0';
94 sample_clk_out_R <= '0';
96 elsif sample_clk'event and sample_clk = '1' then
95 elsif sample_clk'event and sample_clk = '1' then
97 if smp_cnt = 1 then
96 if smp_cnt = 1 then
98 smp_cnt <= 0;
97 smp_cnt <= 0;
99 sample_clk_out_R <= not sample_clk_out_R;
98 sample_clk_out_R <= not sample_clk_out_R;
100 else
99 else
101 smp_cnt <= smp_cnt +1;
100 smp_cnt <= smp_cnt +1;
102 end if;
101 end if;
103 end if;
102 end if;
104 end process;
103 end process;
105
104
106
105
107 process(rst,clk)
106 process(rst,clk)
108 begin
107 begin
109 if rst = '0' then
108 if rst = '0' then
110 r.regin.coefsTB.NumCoefs <= NumCoefs_cel;
109 r.regin.coefsTB.NumCoefs <= NumCoefs_cel;
111 r.regin.coefsTB.DenCoefs <= DenCoefs_cel;
110 r.regin.coefsTB.DenCoefs <= DenCoefs_cel;
112 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
111 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
113
112
114 elsif clk'event and clk = '1' then
113 elsif clk'event and clk = '1' then
115
114
116
115
117 --APB Write OP
116 --APB Write OP
118 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
117 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
119 case apbi.paddr(7 downto 2) is
118 case apbi.paddr(7 downto 2) is
120 when "000000" =>
119 when "000000" =>
121 r.regin.config(0) <= apbi.pwdata(0);
120 r.regin.config(0) <= apbi.pwdata(0);
122 when "000001" =>
121 when "000001" =>
123 r.regin.virgPos <= apbi.pwdata(4 downto 0);
122 r.regin.virgPos <= apbi.pwdata(4 downto 0);
124 when others =>
123 when others =>
125 for i in 0 to Cels_count-1 loop
124 for i in 0 to Cels_count-1 loop
126 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
125 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
127 case apbi.paddr(4 downto 2) is
126 case apbi.paddr(4 downto 2) is
128 when "000" =>
127 when "000" =>
129 r.regin.coefsTB.NumCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
128 r.regin.coefsTB.NumCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
130 when "001" =>
129 when "001" =>
131 r.regin.coefsTB.NumCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
130 r.regin.coefsTB.NumCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
132 when "010" =>
131 when "010" =>
133 r.regin.coefsTB.NumCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
132 r.regin.coefsTB.NumCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
134 when "011" =>
133 when "011" =>
135 r.regin.coefsTB.DenCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
134 r.regin.coefsTB.DenCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
136 when "100" =>
135 when "100" =>
137 r.regin.coefsTB.DenCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
136 r.regin.coefsTB.DenCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
138 when "101" =>
137 when "101" =>
139 r.regin.coefsTB.DenCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
138 r.regin.coefsTB.DenCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
140 when others =>
139 when others =>
141 end case;
140 end case;
142 end if;
141 end if;
143 end loop;
142 end loop;
144 end case;
143 end case;
145 end if;
144 end if;
146
145
147 --APB READ OP
146 --APB READ OP
148 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
147 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
149 case apbi.paddr(7 downto 2) is
148 case apbi.paddr(7 downto 2) is
150 when "000000" =>
149 when "000000" =>
151
150
152 when "000001" =>
151 when "000001" =>
153 apbo.prdata(4 downto 0) <= r.regin.virgPos;
152 apbo.prdata(4 downto 0) <= r.regin.virgPos;
154 when others =>
153 when others =>
155 for i in 0 to Cels_count-1 loop
154 for i in 0 to Cels_count-1 loop
156 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
155 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
157 case apbi.paddr(4 downto 2) is
156 case apbi.paddr(4 downto 2) is
158 when "000" =>
157 when "000" =>
159 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(0));
158 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(0));
160 when "001" =>
159 when "001" =>
161 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(1));
160 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(1));
162 when "010" =>
161 when "010" =>
163 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(2));
162 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(2));
164 when "011" =>
163 when "011" =>
165 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(0));
164 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(0));
166 when "100" =>
165 when "100" =>
167 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(1));
166 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(1));
168 when "101" =>
167 when "101" =>
169 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(2));
168 apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(2));
170 when others =>
169 when others =>
171 end case;
170 end case;
172 end if;
171 end if;
173 end loop;
172 end loop;
174 end case;
173 end case;
175 end if;
174 end if;
176
175
177 end if;
176 end if;
178 apbo.pconfig <= pconfig;
177 apbo.pconfig <= pconfig;
179 end process;
178 end process;
180
179
181
180
182
181
183 -- pragma translate_off
182 -- pragma translate_off
184 bootmsg : report_version
183 bootmsg : report_version
185 generic map ("apbuart" & tost(pindex) &
184 generic map ("apbuart" & tost(pindex) &
186 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
185 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
187 ", irq " & tost(pirq));
186 ", irq " & tost(pirq));
188 -- pragma translate_on
187 -- pragma translate_on
189
188
190
189
191
190
192 end ar_APB_IIR_CEL;
191 end ar_APB_IIR_CEL;
193
192
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@@ -1,102 +1,101
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- FILTER.vhd
19 library IEEE;
20 library IEEE;
20 use IEEE.numeric_std.all;
21 use IEEE.numeric_std.all;
21 use IEEE.std_logic_1164.all;
22 use IEEE.std_logic_1164.all;
22 library lpp;
23 library lpp;
23 use lpp.iir_filter.all;
24 use lpp.iir_filter.all;
24 use lpp.FILTERcfg.all;
25 use lpp.FILTERcfg.all;
25 use lpp.general_purpose.all;
26 use lpp.general_purpose.all;
26 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
27 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
27 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
28 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
28 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
29 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
29
30
30 entity FILTER is
31 entity FILTER is
31 port(
32 port(
32
33
33 reset : in std_logic;
34 reset : in std_logic;
34 clk : in std_logic;
35 clk : in std_logic;
35 sample_clk : in std_logic;
36 sample_clk : in std_logic;
36 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
37 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
37 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
38 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
38 );
39 );
39 end entity;
40 end entity;
40
41
41
42
42
43
43
44
44
45
45 architecture ar_FILTER of FILTER is
46 architecture ar_FILTER of FILTER is
46
47
47
48
48
49
49
50
50 signal ALU_ctrl : std_logic_vector(3 downto 0);
51 signal ALU_ctrl : std_logic_vector(3 downto 0);
51 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
52 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
52 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
53 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
53 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
54 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
54
55
55 begin
56 begin
56
57
57 --==============================================================
58 --==============================================================
58 --=========================A L U================================
59 --=========================A L U================================
59 --==============================================================
60 --==============================================================
60 ALU1 : entity ALU
61 ALU1 : entity ALU
61 generic map(
62 generic map(
62 Arith_en => 1,
63 Arith_en => 1,
63 Logic_en => 0,
64 Logic_en => 0,
64 Input_SZ_1 => Smpl_SZ,
65 Input_SZ_1 => Smpl_SZ,
65 Input_SZ_2 => Coef_SZ
66 Input_SZ_2 => Coef_SZ
66
67
67 )
68 )
68 port map(
69 port map(
69 clk => clk,
70 clk => clk,
70 reset => reset,
71 reset => reset,
71 ctrl => ALU_ctrl,
72 ctrl => ALU_ctrl,
72 OP1 => Sample,
73 OP1 => Sample,
73 OP2 => Coef,
74 OP2 => Coef,
74 RES => ALU_OUT
75 RES => ALU_OUT
75 );
76 );
76 --==============================================================
77 --==============================================================
77
78
78 --==============================================================
79 --==============================================================
79 --===============F I L T E R C O N T R O L E R================
80 --===============F I L T E R C O N T R O L E R================
80 --==============================================================
81 --==============================================================
81 filterctrlr1 : FilterCTRLR
82 filterctrlr1 : FilterCTRLR
82 port map(
83 port map(
83 reset => reset,
84 reset => reset,
84 clk => clk,
85 clk => clk,
85 sample_clk => sample_clk,
86 sample_clk => sample_clk,
86 ALU_Ctrl => ALU_ctrl,
87 ALU_Ctrl => ALU_ctrl,
87 sample_in => sample_Tbl,
88 sample_in => sample_Tbl,
88 coef => Coef,
89 coef => Coef,
89 sample => Sample
90 sample => Sample
90 );
91 );
91 --==============================================================
92 --==============================================================
92
93
93 chanelCut : for i in 0 to ChanelsCNT-1 generate
94 chanelCut : for i in 0 to ChanelsCNT-1 generate
94 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
95 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
95 end generate;
96 end generate;
96
97
97
98
98
99
99
100
100 end ar_FILTER;
101 end ar_FILTER;
101
102
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@@ -1,226 +1,225
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- FILTER_RAM_CTRLR.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.iir_filter.all;
23 use lpp.iir_filter.all;
25 use lpp.FILTERcfg.all;
24 use lpp.FILTERcfg.all;
26 use lpp.general_purpose.all;
25 use lpp.general_purpose.all;
27
26
28 --TODO am�liorer la flexibilit� de la config de la RAM.
27 --TODO am�liorer la flexibilit� de la config de la RAM.
29
28
30 entity FILTER_RAM_CTRLR is
29 entity FILTER_RAM_CTRLR is
31 port(
30 port(
32 reset : in std_logic;
31 reset : in std_logic;
33 clk : in std_logic;
32 clk : in std_logic;
34 run : in std_logic;
33 run : in std_logic;
35 GO_0 : in std_logic;
34 GO_0 : in std_logic;
36 B_A : in std_logic;
35 B_A : in std_logic;
37 writeForce : in std_logic;
36 writeForce : in std_logic;
38 next_blk : in std_logic;
37 next_blk : in std_logic;
39 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
38 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
40 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
39 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
41 );
40 );
42 end FILTER_RAM_CTRLR;
41 end FILTER_RAM_CTRLR;
43
42
44
43
45 architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
44 architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
46
45
47 signal WD : std_logic_vector(35 downto 0);
46 signal WD : std_logic_vector(35 downto 0);
48 signal WD_D : std_logic_vector(35 downto 0);
47 signal WD_D : std_logic_vector(35 downto 0);
49 signal RD : std_logic_vector(35 downto 0);
48 signal RD : std_logic_vector(35 downto 0);
50 signal WEN, REN : std_logic;
49 signal WEN, REN : std_logic;
51 signal WADDR_back : std_logic_vector(7 downto 0);
50 signal WADDR_back : std_logic_vector(7 downto 0);
52 signal WADDR_back_D: std_logic_vector(7 downto 0);
51 signal WADDR_back_D: std_logic_vector(7 downto 0);
53 signal RADDR : std_logic_vector(7 downto 0);
52 signal RADDR : std_logic_vector(7 downto 0);
54 signal WADDR : std_logic_vector(7 downto 0);
53 signal WADDR : std_logic_vector(7 downto 0);
55 signal WADDR_D : std_logic_vector(7 downto 0);
54 signal WADDR_D : std_logic_vector(7 downto 0);
56 signal run_D : std_logic;
55 signal run_D : std_logic;
57 signal run_D_inv : std_logic;
56 signal run_D_inv : std_logic;
58 signal run_inv : std_logic;
57 signal run_inv : std_logic;
59 signal next_blk_D : std_logic;
58 signal next_blk_D : std_logic;
60 signal MUX2_inst1_sel : std_logic;
59 signal MUX2_inst1_sel : std_logic;
61
60
62
61
63 begin
62 begin
64
63
65 sample_out <= RD(Smpl_SZ-1 downto 0);
64 sample_out <= RD(Smpl_SZ-1 downto 0);
66
65
67 MUX2_inst1_sel <= run_D and not next_blk;
66 MUX2_inst1_sel <= run_D and not next_blk;
68 run_D_inv <= not run_D;
67 run_D_inv <= not run_D;
69 run_inv <= not run;
68 run_inv <= not run;
70 WEN <= run_D_inv and not writeForce;
69 WEN <= run_D_inv and not writeForce;
71 REN <= run_inv ;--and not next_blk;
70 REN <= run_inv ;--and not next_blk;
72
71
73
72
74 --==============================================================
73 --==============================================================
75 --=========================R A M================================
74 --=========================R A M================================
76 --==============================================================
75 --==============================================================
77 memRAM : if Mem_use = use_RAM generate
76 memRAM : if Mem_use = use_RAM generate
78 RAMblk :RAM
77 RAMblk :RAM
79 port map(
78 port map(
80 WD => WD_D,
79 WD => WD_D,
81 RD => RD,
80 RD => RD,
82 WEN => WEN,
81 WEN => WEN,
83 REN => REN,
82 REN => REN,
84 WADDR => WADDR,
83 WADDR => WADDR,
85 RADDR => RADDR,
84 RADDR => RADDR,
86 RWCLK => clk,
85 RWCLK => clk,
87 RESET => reset
86 RESET => reset
88 ) ;
87 ) ;
89 end generate;
88 end generate;
90
89
91 memCEL : if Mem_use = use_CEL generate
90 memCEL : if Mem_use = use_CEL generate
92 RAMblk :RAM_CEL
91 RAMblk :RAM_CEL
93 port map(
92 port map(
94 WD => WD_D,
93 WD => WD_D,
95 RD => RD,
94 RD => RD,
96 WEN => WEN,
95 WEN => WEN,
97 REN => REN,
96 REN => REN,
98 WADDR => WADDR,
97 WADDR => WADDR,
99 RADDR => RADDR,
98 RADDR => RADDR,
100 RWCLK => clk,
99 RWCLK => clk,
101 RESET => reset
100 RESET => reset
102 ) ;
101 ) ;
103 end generate;
102 end generate;
104 --==============================================================
103 --==============================================================
105 --==============================================================
104 --==============================================================
106
105
107
106
108 ADDRcntr_inst : ADDRcntr
107 ADDRcntr_inst : ADDRcntr
109 port map(
108 port map(
110 clk => clk,
109 clk => clk,
111 reset => reset,
110 reset => reset,
112 count => run,
111 count => run,
113 clr => GO_0,
112 clr => GO_0,
114 Q => RADDR
113 Q => RADDR
115 );
114 );
116
115
117
116
118
117
119 MUX2_inst1 :MUX2
118 MUX2_inst1 :MUX2
120 generic map(Input_SZ => Smpl_SZ)
119 generic map(Input_SZ => Smpl_SZ)
121 port map(
120 port map(
122 sel => MUX2_inst1_sel,
121 sel => MUX2_inst1_sel,
123 IN1 => sample_in,
122 IN1 => sample_in,
124 IN2 => RD(Smpl_SZ-1 downto 0),
123 IN2 => RD(Smpl_SZ-1 downto 0),
125 RES => WD(Smpl_SZ-1 downto 0)
124 RES => WD(Smpl_SZ-1 downto 0)
126 );
125 );
127
126
128
127
129 MUX2_inst2 :MUX2
128 MUX2_inst2 :MUX2
130 generic map(Input_SZ => 8)
129 generic map(Input_SZ => 8)
131 port map(
130 port map(
132 sel => next_blk_D,
131 sel => next_blk_D,
133 IN1 => WADDR_D,
132 IN1 => WADDR_D,
134 IN2 => WADDR_back_D,
133 IN2 => WADDR_back_D,
135 RES => WADDR
134 RES => WADDR
136 );
135 );
137
136
138
137
139 next_blkRreg :REG
138 next_blkRreg :REG
140 generic map(size => 1)
139 generic map(size => 1)
141 port map(
140 port map(
142 reset => reset,
141 reset => reset,
143 clk => clk,
142 clk => clk,
144 D(0) => next_blk,
143 D(0) => next_blk,
145 Q(0) => next_blk_D
144 Q(0) => next_blk_D
146 );
145 );
147
146
148 WADDR_backreg :REG
147 WADDR_backreg :REG
149 generic map(size => 8)
148 generic map(size => 8)
150 port map(
149 port map(
151 reset => reset,
150 reset => reset,
152 clk => B_A,
151 clk => B_A,
153 D => RADDR,
152 D => RADDR,
154 Q => WADDR_back
153 Q => WADDR_back
155 );
154 );
156
155
157 WADDR_backreg2 :REG
156 WADDR_backreg2 :REG
158 generic map(size => 8)
157 generic map(size => 8)
159 port map(
158 port map(
160 reset => reset,
159 reset => reset,
161 clk => B_A,
160 clk => B_A,
162 D => WADDR_back,
161 D => WADDR_back,
163 Q => WADDR_back_D
162 Q => WADDR_back_D
164 );
163 );
165
164
166 WDRreg :REG
165 WDRreg :REG
167 generic map(size => Smpl_SZ)
166 generic map(size => Smpl_SZ)
168 port map(
167 port map(
169 reset => reset,
168 reset => reset,
170 clk => clk,
169 clk => clk,
171 D => WD(Smpl_SZ-1 downto 0),
170 D => WD(Smpl_SZ-1 downto 0),
172 Q => WD_D(Smpl_SZ-1 downto 0)
171 Q => WD_D(Smpl_SZ-1 downto 0)
173 );
172 );
174
173
175 RunRreg :REG
174 RunRreg :REG
176 generic map(size => 1)
175 generic map(size => 1)
177 port map(
176 port map(
178 reset => reset,
177 reset => reset,
179 clk => clk,
178 clk => clk,
180 D(0) => run,
179 D(0) => run,
181 Q(0) => run_D
180 Q(0) => run_D
182 );
181 );
183
182
184
183
185
184
186 ADDRreg :REG
185 ADDRreg :REG
187 generic map(size => 8)
186 generic map(size => 8)
188 port map(
187 port map(
189 reset => reset,
188 reset => reset,
190 clk => clk,
189 clk => clk,
191 D => RADDR,
190 D => RADDR,
192 Q => WADDR_D
191 Q => WADDR_D
193 );
192 );
194
193
195
194
196
195
197 end ar_FILTER_RAM_CTRLR;
196 end ar_FILTER_RAM_CTRLR;
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Show file before | Show file after | Hide comments
@@ -1,242 +1,241
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- FILTERcfg.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23
22
24
23
25 package FILTERcfg is
24 package FILTERcfg is
26
25
27
26
28 --===========================================================|
27 --===========================================================|
29 --================A L U C O N T R O L======================|
28 --================A L U C O N T R O L======================|
30 --===========================================================|
29 --===========================================================|
31 constant IDLE : std_logic_vector(3 downto 0) := "0000";
30 constant IDLE : std_logic_vector(3 downto 0) := "0000";
32 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
31 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
33 constant MULT : std_logic_vector(3 downto 0) := "0010";
32 constant MULT : std_logic_vector(3 downto 0) := "0010";
34 constant ADD : std_logic_vector(3 downto 0) := "0011";
33 constant ADD : std_logic_vector(3 downto 0) := "0011";
35 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
34 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
36
35
37
36
38 --===========================================================|
37 --===========================================================|
39 --========F I L T E R C O N F I G V A L U E S=============|
38 --========F I L T E R C O N F I G V A L U E S=============|
40 --===========================================================|
39 --===========================================================|
41 --____________________________
40 --____________________________
42 --Bus Width and chanels number|
41 --Bus Width and chanels number|
43 --____________________________|
42 --____________________________|
44 constant ChanelsCNT : integer := 6;
43 constant ChanelsCNT : integer := 6;
45 constant Smpl_SZ : integer := 16;
44 constant Smpl_SZ : integer := 16;
46 constant Coef_SZ : integer := 9;
45 constant Coef_SZ : integer := 9;
47 constant Scalefac_SZ: integer := 3;
46 constant Scalefac_SZ: integer := 3;
48 constant Cels_count : integer := 5;
47 constant Cels_count : integer := 5;
49 --____
48 --____
50 --RAM |
49 --RAM |
51 --____|
50 --____|
52 constant use_RAM : integer := 1;
51 constant use_RAM : integer := 1;
53 constant use_CEL : integer := 0;
52 constant use_CEL : integer := 0;
54
53
55 constant Mem_use : integer := 1;
54 constant Mem_use : integer := 1;
56
55
57 --===========================================================|
56 --===========================================================|
58 --=============C O E F S ====================================|
57 --=============C O E F S ====================================|
59 --===========================================================|
58 --===========================================================|
60 -- create a specific type of data for coefs to avoid errors |
59 -- create a specific type of data for coefs to avoid errors |
61 --===========================================================|
60 --===========================================================|
62
61
63 type coefT is array(Coef_SZ-1 downto 0) of std_logic;
62 type coefT is array(Coef_SZ-1 downto 0) of std_logic;
64 type scaleValT is array(natural range <>) of integer;
63 type scaleValT is array(natural range <>) of integer;
65
64
66 type coef_celT is array(0 to 2) of coefT;
65 type coef_celT is array(0 to 2) of coefT;
67
66
68 type coefsT is array(natural range <>) of coefT ;
67 type coefsT is array(natural range <>) of coefT ;
69
68
70 type coefs_celT is array(natural range <>) of coef_celT;
69 type coefs_celT is array(natural range <>) of coef_celT;
71
70
72 type samplT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
71 type samplT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
73
72
74
73
75
74
76
75
77 type coefs_celsT is record
76 type coefs_celsT is record
78 NumCoefs : coefs_celT(0 to Cels_count-1);
77 NumCoefs : coefs_celT(0 to Cels_count-1);
79 DenCoefs : coefs_celT(0 to Cels_count-1);
78 DenCoefs : coefs_celT(0 to Cels_count-1);
80 end record;
79 end record;
81
80
82
81
83 type in_IIR_CEL_reg is record
82 type in_IIR_CEL_reg is record
84 config : std_logic_vector(31 downto 0);
83 config : std_logic_vector(31 downto 0);
85 coefsTB : coefs_celsT;
84 coefsTB : coefs_celsT;
86 virgPos : std_logic_vector(4 downto 0);
85 virgPos : std_logic_vector(4 downto 0);
87 end record;
86 end record;
88 type out_IIR_CEL_reg is record
87 type out_IIR_CEL_reg is record
89 config : std_logic_vector(31 downto 0);
88 config : std_logic_vector(31 downto 0);
90 status : std_logic_vector(31 downto 0);
89 status : std_logic_vector(31 downto 0);
91 end record;
90 end record;
92
91
93
92
94 --============================================================
93 --============================================================
95 -- create each initial values for each coefs ============
94 -- create each initial values for each coefs ============
96 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
95 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
97 --============================================================
96 --============================================================
98 constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
97 constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
99 constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
98 constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
100 constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
99 constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
101 constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
100 constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
102 constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
101 constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
103 constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
102 constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
104 constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
103 constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
105
104
106 constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
105 constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
107 constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
106 constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
108 constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
107 constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
109 constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
108 constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
110 constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
109 constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
111
110
112
111
113 constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
112 constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
114 constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
113 constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
115 constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
114 constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
116
115
117 constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
116 constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
118 constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
117 constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
119 constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
118 constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
120
119
121 constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
120 constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
122 constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
121 constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
123 constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
122 constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
124
123
125 constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
124 constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
126 constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
125 constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
127 constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
126 constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
128
127
129 constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
128 constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
130 constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
129 constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
131 constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
130 constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
132
131
133 constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
132 constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
134 constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
133 constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
135 constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
134 constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
136
135
137 constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
136 constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
138 constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
137 constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
139 constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
138 constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
140
139
141
140
142 constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
141 constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
143 constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
142 constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
144 constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
143 constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
145
144
146 constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
145 constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
147 constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
146 constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
148 constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
147 constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
149
148
150 constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
149 constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
151 constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
150 constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
152 constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
151 constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
153
152
154 constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
153 constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
155 constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
154 constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
156 constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
155 constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
157
156
158 constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
157 constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
159 constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
158 constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
160 constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
159 constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
161
160
162 constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
161 constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
163 constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
162 constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
164 constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
163 constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
165 constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
164 constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
166 constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
165 constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
167 constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
166 constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
168
167
169
168
170 constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
169 constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
171 constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
170 constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
172 constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
171 constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
173 constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
172 constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
174 constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
173 constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
175 constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
174 constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
176 constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
175 constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
177
176
178 constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
177 constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
179 constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
178 constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
180 constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
179 constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
181 constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
180 constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
182 constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
181 constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
183 constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
182 constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
184 constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
183 constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
185
184
186
185
187
186
188 constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
187 constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
189 constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
188 constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
190 constant virgPos : integer := 7;
189 constant virgPos : integer := 7;
191
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197
196
198 signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
197 signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
199 signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
198 signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
200
199
201
200
202 signal sample_Tbl : samplT;
201 signal sample_Tbl : samplT;
203
202
204
203
205 end;
204 end;
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Show file before | Show file after | Hide comments
@@ -1,263 +1,262
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- FilterCTRLR.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.iir_filter.all;
23 use lpp.iir_filter.all;
25 use lpp.FILTERcfg.all;
24 use lpp.FILTERcfg.all;
26 use lpp.general_purpose.all;
25 use lpp.general_purpose.all;
27
26
28 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
27 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
29
28
30 entity FilterCTRLR is
29 entity FilterCTRLR is
31 port(
30 port(
32 reset : in std_logic;
31 reset : in std_logic;
33 clk : in std_logic;
32 clk : in std_logic;
34 sample_clk : in std_logic;
33 sample_clk : in std_logic;
35 ALU_Ctrl : out std_logic_vector(3 downto 0);
34 ALU_Ctrl : out std_logic_vector(3 downto 0);
36 sample_in : in samplT;
35 sample_in : in samplT;
37 coef : out std_logic_vector(Coef_SZ-1 downto 0);
36 coef : out std_logic_vector(Coef_SZ-1 downto 0);
38 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
37 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
39 );
38 );
40 end FilterCTRLR;
39 end FilterCTRLR;
41
40
42
41
43 architecture ar_FilterCTRLR of FilterCTRLR is
42 architecture ar_FilterCTRLR of FilterCTRLR is
44
43
45 constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
44 constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
46 constant DENCoefsCnt : integer:= DenominatorCoefs'high;
45 constant DENCoefsCnt : integer:= DenominatorCoefs'high;
47
46
48 signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
47 signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
49 signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
48 signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
50
49
51 signal chanelCnt : integer range 0 to 15:=0;
50 signal chanelCnt : integer range 0 to 15:=0;
52
51
53 signal WD : std_logic_vector(35 downto 0);
52 signal WD : std_logic_vector(35 downto 0);
54 signal WD_D : std_logic_vector(35 downto 0);
53 signal WD_D : std_logic_vector(35 downto 0);
55 signal RD : std_logic_vector(35 downto 0);
54 signal RD : std_logic_vector(35 downto 0);
56 signal WEN, REN,WEN_D : std_logic;
55 signal WEN, REN,WEN_D : std_logic;
57 signal WADDR_back : std_logic_vector(7 downto 0);
56 signal WADDR_back : std_logic_vector(7 downto 0);
58 signal ADDR : std_logic_vector(7 downto 0);
57 signal ADDR : std_logic_vector(7 downto 0);
59 signal ADDR_D : std_logic_vector(7 downto 0);
58 signal ADDR_D : std_logic_vector(7 downto 0);
60 signal clk_inv : std_logic;
59 signal clk_inv : std_logic;
61
60
62 type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
61 type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
63 signal in_Rotate_Buff : Rotate_BuffT;
62 signal in_Rotate_Buff : Rotate_BuffT;
64 signal out_Rotate_Buff : Rotate_BuffT;
63 signal out_Rotate_Buff : Rotate_BuffT;
65
64
66 signal sample_clk_old : std_logic;
65 signal sample_clk_old : std_logic;
67
66
68 type stateT is (waiting,computeNUM,computeDEN,NextChanel);
67 type stateT is (waiting,computeNUM,computeDEN,NextChanel);
69 signal state : stateT;
68 signal state : stateT;
70
69
71 begin
70 begin
72 clk_inv <= not clk;
71 clk_inv <= not clk;
73
72
74 process(clk,reset)
73 process(clk,reset)
75 begin
74 begin
76 if reset = '0' then
75 if reset = '0' then
77 state <= waiting;
76 state <= waiting;
78 WEN <= '1';
77 WEN <= '1';
79 REN <= '1';
78 REN <= '1';
80 ADDR <= (others => '0');
79 ADDR <= (others => '0');
81 WD <= (others => '0');
80 WD <= (others => '0');
82 NcoefCnt <= 0;
81 NcoefCnt <= 0;
83 DcoefCnt <= 0;
82 DcoefCnt <= 0;
84 chanelCnt <= 0;
83 chanelCnt <= 0;
85 ALU_Ctrl <= clr_mac;
84 ALU_Ctrl <= clr_mac;
86 sample_clk_old <= '0';
85 sample_clk_old <= '0';
87 coef <= (others => '0');
86 coef <= (others => '0');
88 sample <= (others => '0');
87 sample <= (others => '0');
89 rst:for i in 0 to ChanelsCNT-1 loop
88 rst:for i in 0 to ChanelsCNT-1 loop
90 in_Rotate_Buff(i) <= (others => '0');
89 in_Rotate_Buff(i) <= (others => '0');
91 end loop;
90 end loop;
92 elsif clk'event and clk = '1' then
91 elsif clk'event and clk = '1' then
93
92
94 sample_clk_old <= sample_clk;
93 sample_clk_old <= sample_clk;
95
94
96 --=================================================================
95 --=================================================================
97 --===============DATA processing===================================
96 --===============DATA processing===================================
98 --=================================================================
97 --=================================================================
99 case state is
98 case state is
100 when waiting=>
99 when waiting=>
101
100
102 if sample_clk_old = '0' and sample_clk = '1' then
101 if sample_clk_old = '0' and sample_clk = '1' then
103 ALU_Ctrl <= MAC_op;
102 ALU_Ctrl <= MAC_op;
104 sample <= in_Rotate_Buff(0);
103 sample <= in_Rotate_Buff(0);
105 coef <= std_logic_vector(NumeratorCoefs(0));
104 coef <= std_logic_vector(NumeratorCoefs(0));
106 else
105 else
107 ALU_Ctrl <= clr_mac;
106 ALU_Ctrl <= clr_mac;
108 loadinput: for i in 0 to ChanelsCNT-1 loop
107 loadinput: for i in 0 to ChanelsCNT-1 loop
109 in_Rotate_Buff(i) <= sample_in(i);
108 in_Rotate_Buff(i) <= sample_in(i);
110 end loop;
109 end loop;
111 end if;
110 end if;
112
111
113 when computeNUM=>
112 when computeNUM=>
114 ALU_Ctrl <= MAC_op;
113 ALU_Ctrl <= MAC_op;
115 sample <= RD(Smpl_SZ-1 downto 0);
114 sample <= RD(Smpl_SZ-1 downto 0);
116 coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
115 coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
117
116
118 when computeDEN=>
117 when computeDEN=>
119 ALU_Ctrl <= MAC_op;
118 ALU_Ctrl <= MAC_op;
120 sample <= RD(Smpl_SZ-1 downto 0);
119 sample <= RD(Smpl_SZ-1 downto 0);
121 coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
120 coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
122
121
123 when NextChanel=>
122 when NextChanel=>
124 rotate : for i in 0 to ChanelsCNT-2 loop
123 rotate : for i in 0 to ChanelsCNT-2 loop
125 in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
124 in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
126 end loop;
125 end loop;
127 rotatetoo: if ChanelsCNT > 1 then
126 rotatetoo: if ChanelsCNT > 1 then
128 sample <= in_Rotate_Buff(1);
127 sample <= in_Rotate_Buff(1);
129 coef <= std_logic_vector(NumeratorCoefs(0));
128 coef <= std_logic_vector(NumeratorCoefs(0));
130 end if;
129 end if;
131 end case;
130 end case;
132
131
133 --=================================================================
132 --=================================================================
134 --===============RAM read write====================================
133 --===============RAM read write====================================
135 --=================================================================
134 --=================================================================
136 case state is
135 case state is
137 when waiting=>
136 when waiting=>
138 if sample_clk_old = '0' and sample_clk = '1' then
137 if sample_clk_old = '0' and sample_clk = '1' then
139 REN <= '0';
138 REN <= '0';
140 else
139 else
141 REN <= '1';
140 REN <= '1';
142 end if;
141 end if;
143 ADDR <= (others => '0');
142 ADDR <= (others => '0');
144 WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
143 WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
145 WEN <= '1';
144 WEN <= '1';
146
145
147 when computeNUM=>
146 when computeNUM=>
148 WD <= RD;
147 WD <= RD;
149 REN <= '0';
148 REN <= '0';
150 WEN <= '0';
149 WEN <= '0';
151 ADDR <= std_logic_vector(unsigned(ADDR)+1);
150 ADDR <= std_logic_vector(unsigned(ADDR)+1);
152 when computeDEN=>
151 when computeDEN=>
153 WD <= RD;
152 WD <= RD;
154 REN <= '0';
153 REN <= '0';
155 WEN <= '0';
154 WEN <= '0';
156 ADDR <= std_logic_vector(unsigned(ADDR)+1);
155 ADDR <= std_logic_vector(unsigned(ADDR)+1);
157 when NextChanel=>
156 when NextChanel=>
158 REN <= '1';
157 REN <= '1';
159 WEN <= '1';
158 WEN <= '1';
160 end case;
159 end case;
161 --=================================================================
160 --=================================================================
162
161
163
162
164 --=================================================================
163 --=================================================================
165 --===============FSM Management====================================
164 --===============FSM Management====================================
166 --=================================================================
165 --=================================================================
167 case state is
166 case state is
168 when waiting=>
167 when waiting=>
169 if sample_clk_old = '0' and sample_clk = '1' then
168 if sample_clk_old = '0' and sample_clk = '1' then
170 state <= computeNUM;
169 state <= computeNUM;
171 end if;
170 end if;
172 DcoefCnt <= 0;
171 DcoefCnt <= 0;
173 NcoefCnt <= 1;
172 NcoefCnt <= 1;
174 chanelCnt<= 0;
173 chanelCnt<= 0;
175 when computeNUM=>
174 when computeNUM=>
176 if NcoefCnt = NumCoefsCnt then
175 if NcoefCnt = NumCoefsCnt then
177 state <= computeDEN;
176 state <= computeDEN;
178 NcoefCnt <= 1;
177 NcoefCnt <= 1;
179 else
178 else
180 NcoefCnt <= NcoefCnt+1;
179 NcoefCnt <= NcoefCnt+1;
181 end if;
180 end if;
182 when computeDEN=>
181 when computeDEN=>
183 if DcoefCnt = DENCoefsCnt then
182 if DcoefCnt = DENCoefsCnt then
184 state <= NextChanel;
183 state <= NextChanel;
185 DcoefCnt <= 0;
184 DcoefCnt <= 0;
186 else
185 else
187 DcoefCnt <= DcoefCnt+1;
186 DcoefCnt <= DcoefCnt+1;
188 end if;
187 end if;
189 when NextChanel=>
188 when NextChanel=>
190 if chanelCnt = (ChanelsCNT-1) then
189 if chanelCnt = (ChanelsCNT-1) then
191 state <= waiting;
190 state <= waiting;
192 else
191 else
193 chanelCnt<= chanelCnt+1;
192 chanelCnt<= chanelCnt+1;
194 state <= computeNUM;
193 state <= computeNUM;
195 end if;
194 end if;
196 end case;
195 end case;
197 --=================================================================
196 --=================================================================
198
197
199 end if;
198 end if;
200 end process;
199 end process;
201
200
202 ADDRreg : REG
201 ADDRreg : REG
203 generic map(size => 8)
202 generic map(size => 8)
204 port map(
203 port map(
205 reset => reset,
204 reset => reset,
206 clk => clk,
205 clk => clk,
207 D => ADDR,
206 D => ADDR,
208 Q => ADDR_D
207 Q => ADDR_D
209 );
208 );
210
209
211 WDreg :REG
210 WDreg :REG
212 generic map(size => 36)
211 generic map(size => 36)
213 port map(
212 port map(
214 reset => reset,
213 reset => reset,
215 clk => clk,
214 clk => clk,
216 D => WD,
215 D => WD,
217 Q => WD_D
216 Q => WD_D
218 );
217 );
219
218
220 WRreg :REG
219 WRreg :REG
221 generic map(size => 1)
220 generic map(size => 1)
222 port map(
221 port map(
223 reset => reset,
222 reset => reset,
224 clk => clk,
223 clk => clk,
225 D(0) => WEN,
224 D(0) => WEN,
226 Q(0) => WEN_D
225 Q(0) => WEN_D
227 );
226 );
228 --==============================================================
227 --==============================================================
229 --=========================R A M================================
228 --=========================R A M================================
230 --==============================================================
229 --==============================================================
231 memRAM : if Mem_use = use_RAM generate
230 memRAM : if Mem_use = use_RAM generate
232 RAMblk :RAM
231 RAMblk :RAM
233 port map(
232 port map(
234 WD => WD_D,
233 WD => WD_D,
235 RD => RD,
234 RD => RD,
236 WEN => WEN_D,
235 WEN => WEN_D,
237 REN => REN,
236 REN => REN,
238 WADDR => ADDR_D,
237 WADDR => ADDR_D,
239 RADDR => ADDR,
238 RADDR => ADDR,
240 RWCLK => clk_inv,
239 RWCLK => clk_inv,
241 RESET => reset
240 RESET => reset
242 ) ;
241 ) ;
243 end generate;
242 end generate;
244
243
245 memCEL : if Mem_use = use_CEL generate
244 memCEL : if Mem_use = use_CEL generate
246 RAMblk :RAM
245 RAMblk :RAM
247 port map(
246 port map(
248 WD => WD_D,
247 WD => WD_D,
249 RD => RD,
248 RD => RD,
250 WEN => WEN_D,
249 WEN => WEN_D,
251 REN => REN,
250 REN => REN,
252 WADDR => ADDR_D,
251 WADDR => ADDR_D,
253 RADDR => ADDR,
252 RADDR => ADDR,
254 RWCLK => clk_inv,
253 RWCLK => clk_inv,
255 RESET => reset
254 RESET => reset
256 ) ;
255 ) ;
257 end generate;
256 end generate;
258
257
259 --==============================================================
258 --==============================================================
260
259
261
260
262
261
263 end ar_FilterCTRLR;
262 end ar_FilterCTRLR;
Show file before | Show file after | Hide comments
@@ -1,293 +1,296
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- IIR_CEL_CTRLR.vhd
19 ------------------------------------------------------------------------------
20 -- This file is a part of the LPP VHDL IP LIBRARY
21 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
22 --
20 library IEEE;
23 library IEEE;
21 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
25 use IEEE.std_logic_1164.all;
23 library lpp;
26 library lpp;
24 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
25 use lpp.FILTERcfg.all;
28 use lpp.FILTERcfg.all;
26 use lpp.general_purpose.all;
29 use lpp.general_purpose.all;
27
30
28 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
31 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
29
32
30 entity IIR_CEL_CTRLR is
33 entity IIR_CEL_CTRLR is
31 generic(Sample_SZ : integer := 16);
34 generic(Sample_SZ : integer := 16);
32 port(
35 port(
33 reset : in std_logic;
36 reset : in std_logic;
34 clk : in std_logic;
37 clk : in std_logic;
35 sample_clk : in std_logic;
38 sample_clk : in std_logic;
36 sample_in : in samplT;
39 sample_in : in samplT;
37 sample_out : out samplT;
40 sample_out : out samplT;
38 virg_pos : in integer;
41 virg_pos : in integer;
39 coefs : in coefs_celsT
42 coefs : in coefs_celsT
40 );
43 );
41 end IIR_CEL_CTRLR;
44 end IIR_CEL_CTRLR;
42
45
43
46
44
47
45
48
46 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
49 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
47
50
48 signal smpl_clk_old : std_logic := '0';
51 signal smpl_clk_old : std_logic := '0';
49 signal WD_sel : std_logic := '0';
52 signal WD_sel : std_logic := '0';
50 signal Read : std_logic := '0';
53 signal Read : std_logic := '0';
51 signal SVG_ADDR : std_logic := '0';
54 signal SVG_ADDR : std_logic := '0';
52 signal count : std_logic := '0';
55 signal count : std_logic := '0';
53 signal Write : std_logic := '0';
56 signal Write : std_logic := '0';
54 signal WADDR_sel : std_logic := '0';
57 signal WADDR_sel : std_logic := '0';
55 signal GO_0 : std_logic := '0';
58 signal GO_0 : std_logic := '0';
56
59
57 signal RAM_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
60 signal RAM_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
58 signal RAM_sample_in_bk: std_logic_vector(Sample_SZ-1 downto 0);
61 signal RAM_sample_in_bk: std_logic_vector(Sample_SZ-1 downto 0);
59 signal RAM_sample_out : std_logic_vector(Sample_SZ-1 downto 0);
62 signal RAM_sample_out : std_logic_vector(Sample_SZ-1 downto 0);
60 signal ALU_ctrl : std_logic_vector(3 downto 0);
63 signal ALU_ctrl : std_logic_vector(3 downto 0);
61 signal ALU_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
64 signal ALU_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
62 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
65 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
63 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
66 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
64 signal curentCel : integer range 0 to Cels_count-1 := 0;
67 signal curentCel : integer range 0 to Cels_count-1 := 0;
65 signal curentChan : integer range 0 to ChanelsCNT-1 := 0;
68 signal curentChan : integer range 0 to ChanelsCNT-1 := 0;
66
69
67 signal sample_in_BUFF : samplT;
70 signal sample_in_BUFF : samplT;
68 signal sample_out_BUFF : samplT;
71 signal sample_out_BUFF : samplT;
69
72
70
73
71
74
72 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
75 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
73
76
74 signal IIR_CEL_STATE : fsmIIR_CEL_T;
77 signal IIR_CEL_STATE : fsmIIR_CEL_T;
75
78
76 begin
79 begin
77
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81
84
82 RAM_CTRLR2inst : RAM_CTRLR2
85 RAM_CTRLR2inst : RAM_CTRLR2
83 generic map(Input_SZ_1 => Sample_SZ)
86 generic map(Input_SZ_1 => Sample_SZ)
84 port map(
87 port map(
85 reset => reset,
88 reset => reset,
86 clk => clk,
89 clk => clk,
87 WD_sel => WD_sel,
90 WD_sel => WD_sel,
88 Read => Read,
91 Read => Read,
89 WADDR_sel => WADDR_sel,
92 WADDR_sel => WADDR_sel,
90 count => count,
93 count => count,
91 SVG_ADDR => SVG_ADDR,
94 SVG_ADDR => SVG_ADDR,
92 Write => Write,
95 Write => Write,
93 GO_0 => GO_0,
96 GO_0 => GO_0,
94 sample_in => RAM_sample_in,
97 sample_in => RAM_sample_in,
95 sample_out => RAM_sample_out
98 sample_out => RAM_sample_out
96 );
99 );
97
100
98
101
99
102
100 ALU_inst :ALU
103 ALU_inst :ALU
101 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
104 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
102 port map(
105 port map(
103 clk => clk,
106 clk => clk,
104 reset => reset,
107 reset => reset,
105 ctrl => ALU_ctrl,
108 ctrl => ALU_ctrl,
106 OP1 => ALU_sample_in,
109 OP1 => ALU_sample_in,
107 OP2 => ALU_coef_in,
110 OP2 => ALU_coef_in,
108 RES => ALU_out
111 RES => ALU_out
109 );
112 );
110
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118
116 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
119 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
117 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
120 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
118 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
121 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
119 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
122 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
120 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
123 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
121 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
124 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
122 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
125 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
123
126
124 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
127 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
125
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131
134
132 process(clk,reset)
135 process(clk,reset)
133 variable result : std_logic_vector(Sample_SZ-1 downto 0);
136 variable result : std_logic_vector(Sample_SZ-1 downto 0);
134
137
135 begin
138 begin
136
139
137 if reset = '0' then
140 if reset = '0' then
138
141
139 smpl_clk_old <= '0';
142 smpl_clk_old <= '0';
140 RAM_sample_in <= (others=> '0');
143 RAM_sample_in <= (others=> '0');
141 ALU_ctrl <= IDLE;
144 ALU_ctrl <= IDLE;
142 ALU_sample_in <= (others=> '0');
145 ALU_sample_in <= (others=> '0');
143 ALU_Coef_in <= (others=> '0');
146 ALU_Coef_in <= (others=> '0');
144 RAM_sample_in_bk<= (others=> '0');
147 RAM_sample_in_bk<= (others=> '0');
145 curentCel <= 0;
148 curentCel <= 0;
146 curentChan <= 0;
149 curentChan <= 0;
147 IIR_CEL_STATE <= waiting;
150 IIR_CEL_STATE <= waiting;
148 reset : for i in 0 to ChanelsCNT-1 loop
151 reset : for i in 0 to ChanelsCNT-1 loop
149 sample_in_BUFF(i) <= (others => '0');
152 sample_in_BUFF(i) <= (others => '0');
150 sample_out_BUFF(i) <= (others => '0');
153 sample_out_BUFF(i) <= (others => '0');
151 sample_out(i) <= (others => '0');
154 sample_out(i) <= (others => '0');
152 end loop;
155 end loop;
153
156
154 elsif clk'event and clk = '1' then
157 elsif clk'event and clk = '1' then
155
158
156 smpl_clk_old <= sample_clk;
159 smpl_clk_old <= sample_clk;
157
160
158 case IIR_CEL_STATE is
161 case IIR_CEL_STATE is
159
162
160 when waiting =>
163 when waiting =>
161 if sample_clk = '1' and smpl_clk_old = '0' then
164 if sample_clk = '1' and smpl_clk_old = '0' then
162 IIR_CEL_STATE <= pipe1;
165 IIR_CEL_STATE <= pipe1;
163 RAM_sample_in <= sample_in_BUFF(0);
166 RAM_sample_in <= sample_in_BUFF(0);
164 ALU_sample_in <= sample_in_BUFF(0);
167 ALU_sample_in <= sample_in_BUFF(0);
165
168
166 else
169 else
167 ALU_ctrl <= IDLE;
170 ALU_ctrl <= IDLE;
168 sample_in_BUFF <= sample_in;
171 sample_in_BUFF <= sample_in;
169 sample_out <= sample_out_BUFF;
172 sample_out <= sample_out_BUFF;
170
173
171 end if;
174 end if;
172 curentCel <= 0;
175 curentCel <= 0;
173 curentChan <= 0;
176 curentChan <= 0;
174
177
175 when pipe1 =>
178 when pipe1 =>
176 IIR_CEL_STATE <= computeb1;
179 IIR_CEL_STATE <= computeb1;
177 ALU_ctrl <= MAC_op;
180 ALU_ctrl <= MAC_op;
178 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(0));
181 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(0));
179
182
180 when computeb1 =>
183 when computeb1 =>
181
184
182 ALU_ctrl <= MAC_op;
185 ALU_ctrl <= MAC_op;
183 ALU_sample_in <= RAM_sample_out;
186 ALU_sample_in <= RAM_sample_out;
184 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(1));
187 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(1));
185 IIR_CEL_STATE <= computeb2;
188 IIR_CEL_STATE <= computeb2;
186 RAM_sample_in <= RAM_sample_in_bk;
189 RAM_sample_in <= RAM_sample_in_bk;
187 when computeb2 =>
190 when computeb2 =>
188 ALU_sample_in <= RAM_sample_out;
191 ALU_sample_in <= RAM_sample_out;
189 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(2));
192 ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(2));
190 IIR_CEL_STATE <= computea1;
193 IIR_CEL_STATE <= computea1;
191
194
192
195
193 when computea1 =>
196 when computea1 =>
194 ALU_sample_in <= RAM_sample_out;
197 ALU_sample_in <= RAM_sample_out;
195 ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(1));
198 ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(1));
196 IIR_CEL_STATE <= computea2;
199 IIR_CEL_STATE <= computea2;
197
200
198
201
199 when computea2 =>
202 when computea2 =>
200 ALU_sample_in <= RAM_sample_out;
203 ALU_sample_in <= RAM_sample_out;
201 ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(2));
204 ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(2));
202 IIR_CEL_STATE <= next_cel;
205 IIR_CEL_STATE <= next_cel;
203
206
204
207
205 when next_cel =>
208 when next_cel =>
206 ALU_ctrl <= clr_mac;
209 ALU_ctrl <= clr_mac;
207 IIR_CEL_STATE <= pipe2;
210 IIR_CEL_STATE <= pipe2;
208
211
209 when pipe2 =>
212 when pipe2 =>
210 IIR_CEL_STATE <= pipe3;
213 IIR_CEL_STATE <= pipe3;
211
214
212
215
213 when pipe3 =>
216 when pipe3 =>
214
217
215 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
218 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
216
219
217 sample_out_BUFF(0) <= result;
220 sample_out_BUFF(0) <= result;
218 RAM_sample_in_bk <= result;
221 RAM_sample_in_bk <= result;
219 RAM_sample_in <= result;
222 RAM_sample_in <= result;
220 if curentCel = Cels_count-1 then
223 if curentCel = Cels_count-1 then
221 IIR_CEL_STATE <= next_chan;
224 IIR_CEL_STATE <= next_chan;
222 curentCel <= 0;
225 curentCel <= 0;
223 else
226 else
224 curentCel <= curentCel + 1;
227 curentCel <= curentCel + 1;
225 IIR_CEL_STATE <= pipe1;
228 IIR_CEL_STATE <= pipe1;
226 ALU_sample_in <= result;
229 ALU_sample_in <= result;
227 end if;
230 end if;
228 when next_chan =>
231 when next_chan =>
229
232
230 rotate : for i in 0 to ChanelsCNT-2 loop
233 rotate : for i in 0 to ChanelsCNT-2 loop
231 sample_in_BUFF(i) <= sample_in_BUFF(i+1);
234 sample_in_BUFF(i) <= sample_in_BUFF(i+1);
232 sample_out_BUFF(i) <= sample_out_BUFF(i+1);
235 sample_out_BUFF(i) <= sample_out_BUFF(i+1);
233 end loop;
236 end loop;
234 sample_in_BUFF(ChanelsCNT-1) <= sample_in_BUFF(0);
237 sample_in_BUFF(ChanelsCNT-1) <= sample_in_BUFF(0);
235 sample_out_BUFF(ChanelsCNT-1)<= sample_out_BUFF(0);
238 sample_out_BUFF(ChanelsCNT-1)<= sample_out_BUFF(0);
236
239
237 if curentChan = (ChanelsCNT-1) then
240 if curentChan = (ChanelsCNT-1) then
238 IIR_CEL_STATE <= waiting;
241 IIR_CEL_STATE <= waiting;
239 ALU_ctrl <= clr_mac;
242 ALU_ctrl <= clr_mac;
240 else
243 else
241 curentChan <= curentChan + 1;
244 curentChan <= curentChan + 1;
242 IIR_CEL_STATE <= pipe1;
245 IIR_CEL_STATE <= pipe1;
243 ALU_sample_in <= sample_in_BUFF(1);
246 ALU_sample_in <= sample_in_BUFF(1);
244 RAM_sample_in <= sample_in_BUFF(1);
247 RAM_sample_in <= sample_in_BUFF(1);
245 end if;
248 end if;
246 end case;
249 end case;
247
250
248 end if;
251 end if;
249 end process;
252 end process;
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258
256 end ar_IIR_CEL_CTRLR;
259 end ar_IIR_CEL_CTRLR;
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@@ -1,90 +1,88
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- IIR_CEL_FILTER.vhd
19 library IEEE;
20
20 use IEEE.numeric_std.all;
21 library IEEE;
21 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
22 library lpp;
23 use IEEE.std_logic_1164.all;
23 use lpp.iir_filter.all;
24 library lpp;
24 use lpp.FILTERcfg.all;
25 use lpp.iir_filter.all;
25 use lpp.general_purpose.all;
26 use lpp.FILTERcfg.all;
26
27 use lpp.general_purpose.all;
27 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
28
28
29 --TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
29 entity IIR_CEL_FILTER is
30
30 generic(Sample_SZ : integer := 16);
31 entity IIR_CEL_FILTER is
31 port(
32 generic(Sample_SZ : integer := 16);
32 reset : in std_logic;
33 port(
33 clk : in std_logic;
34 reset : in std_logic;
34 sample_clk : in std_logic;
35 clk : in std_logic;
35 regs_in : in in_IIR_CEL_reg;
36 sample_clk : in std_logic;
36 regs_out : in out_IIR_CEL_reg;
37 regs_in : in in_IIR_CEL_reg;
37 sample_in : in samplT;
38 regs_out : in out_IIR_CEL_reg;
38 sample_out : out samplT
39 sample_in : in samplT;
39
40 sample_out : out samplT
40 );
41
41 end IIR_CEL_FILTER;
42 );
42
43 end IIR_CEL_FILTER;
43
44
44
45
45
46
46 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
47
47
48 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
48 signal virg_pos : integer;
49
49 begin
50 signal virg_pos : integer;
50
51 begin
51 virg_pos <= to_integer(unsigned(regs_in.virgPos));
52
52
53 virg_pos <= to_integer(unsigned(regs_in.virgPos));
53
54
54 CTRLR : IIR_CEL_CTRLR
55
55 generic map (Sample_SZ => Sample_SZ)
56 CTRLR : IIR_CEL_CTRLR
56 port map(
57 generic map (Sample_SZ => Sample_SZ)
57 reset => reset,
58 port map(
58 clk => clk,
59 reset => reset,
59 sample_clk => sample_clk,
60 clk => clk,
60 sample_in => sample_in,
61 sample_clk => sample_clk,
61 sample_out => sample_out,
62 sample_in => sample_in,
62 virg_pos => virg_pos,
63 sample_out => sample_out,
63 coefs => regs_in.coefsTB
64 virg_pos => virg_pos,
64 );
65 coefs => regs_in.coefsTB
65
66 );
66
67
67
68
68
69
69
70
70 end ar_IIR_CEL_FILTER;
71
71
72 end ar_IIR_CEL_FILTER;
72
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@@ -1,62 +1,61
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- RAM.vhd
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 use IEEE.numeric_std.all;
21 use IEEE.numeric_std.all;
23
22
24 entity RAM is
23 entity RAM is
25 port( WD : in std_logic_vector(35 downto 0); RD : out
24 port( WD : in std_logic_vector(35 downto 0); RD : out
26 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
25 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
27 WADDR : in std_logic_vector(7 downto 0); RADDR : in
26 WADDR : in std_logic_vector(7 downto 0); RADDR : in
28 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
27 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
29 ) ;
28 ) ;
30 end RAM;
29 end RAM;
31
30
32
31
33 architecture DEF_ARCH of RAM is
32 architecture DEF_ARCH of RAM is
34 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
33 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
35 signal RAMarray : RAMarrayT:=(others => X"000000000");
34 signal RAMarray : RAMarrayT:=(others => X"000000000");
36 signal RD_int : std_logic_vector(35 downto 0);
35 signal RD_int : std_logic_vector(35 downto 0);
37
36
38 begin
37 begin
39
38
40 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
39 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
41
40
42
41
43 process(RWclk,reset)
42 process(RWclk,reset)
44 begin
43 begin
45 if reset = '0' then
44 if reset = '0' then
46 RD <= (X"000000000");
45 RD <= (X"000000000");
47 rst:for i in 0 to 255 loop
46 rst:for i in 0 to 255 loop
48 RAMarray(i) <= (others => '0');
47 RAMarray(i) <= (others => '0');
49 end loop;
48 end loop;
50
49
51 elsif RWclk'event and RWclk = '1' then
50 elsif RWclk'event and RWclk = '1' then
52 if REN = '0' then
51 if REN = '0' then
53 RD <= RD_int;
52 RD <= RD_int;
54 end if;
53 end if;
55
54
56 if WEN = '0' then
55 if WEN = '0' then
57 RAMarray(to_integer(unsigned(WADDR))) <= WD;
56 RAMarray(to_integer(unsigned(WADDR))) <= WD;
58 end if;
57 end if;
59
58
60 end if;
59 end if;
61 end process;
60 end process;
62 end DEF_ARCH;
61 end DEF_ARCH;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- RAM_CEL.vhd
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 use IEEE.numeric_std.all;
21 use IEEE.numeric_std.all;
23
22
24 entity RAM_CEL is
23 entity RAM_CEL is
25 port( WD : in std_logic_vector(35 downto 0); RD : out
24 port( WD : in std_logic_vector(35 downto 0); RD : out
26 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
25 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
27 WADDR : in std_logic_vector(7 downto 0); RADDR : in
26 WADDR : in std_logic_vector(7 downto 0); RADDR : in
28 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
27 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
29 ) ;
28 ) ;
30 end RAM_CEL;
29 end RAM_CEL;
31
30
32
31
33
32
34 architecture ar_RAM_CEL of RAM_CEL is
33 architecture ar_RAM_CEL of RAM_CEL is
35 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
34 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
36 signal RAMarray : RAMarrayT:=(others => X"000000000");
35 signal RAMarray : RAMarrayT:=(others => X"000000000");
37 signal RD_int : std_logic_vector(35 downto 0);
36 signal RD_int : std_logic_vector(35 downto 0);
38
37
39 begin
38 begin
40
39
41 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
40 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
42
41
43
42
44 process(RWclk,reset)
43 process(RWclk,reset)
45 begin
44 begin
46 if reset = '0' then
45 if reset = '0' then
47 RD <= (X"000000000");
46 RD <= (X"000000000");
48 rst:for i in 0 to 255 loop
47 rst:for i in 0 to 255 loop
49 RAMarray(i) <= (others => '0');
48 RAMarray(i) <= (others => '0');
50 end loop;
49 end loop;
51
50
52 elsif RWclk'event and RWclk = '1' then
51 elsif RWclk'event and RWclk = '1' then
53 if REN = '0' then
52 if REN = '0' then
54 RD <= RD_int;
53 RD <= RD_int;
55 end if;
54 end if;
56
55
57 if WEN = '0' then
56 if WEN = '0' then
58 RAMarray(to_integer(unsigned(WADDR))) <= WD;
57 RAMarray(to_integer(unsigned(WADDR))) <= WD;
59 end if;
58 end if;
60
59
61 end if;
60 end if;
62 end process;
61 end process;
63 end ar_RAM_CEL;
62 end ar_RAM_CEL;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- RAM_CTRLR2.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.iir_filter.all;
23 use lpp.iir_filter.all;
25 use lpp.FILTERcfg.all;
24 use lpp.FILTERcfg.all;
26 use lpp.general_purpose.all;
25 use lpp.general_purpose.all;
27
26
28 --TODO am�liorer la flexibilit� de la config de la RAM.
27 --TODO am�liorer la flexibilit� de la config de la RAM.
29
28
30 entity RAM_CTRLR2 is
29 entity RAM_CTRLR2 is
31 generic(
30 generic(
32 Input_SZ_1 : integer := 16
31 Input_SZ_1 : integer := 16
33 );
32 );
34 port(
33 port(
35 reset : in std_logic;
34 reset : in std_logic;
36 clk : in std_logic;
35 clk : in std_logic;
37 WD_sel : in std_logic;
36 WD_sel : in std_logic;
38 Read : in std_logic;
37 Read : in std_logic;
39 WADDR_sel : in std_logic;
38 WADDR_sel : in std_logic;
40 count : in std_logic;
39 count : in std_logic;
41 SVG_ADDR : in std_logic;
40 SVG_ADDR : in std_logic;
42 Write : in std_logic;
41 Write : in std_logic;
43 GO_0 : in std_logic;
42 GO_0 : in std_logic;
44 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
43 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
45 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
44 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
46 );
45 );
47 end RAM_CTRLR2;
46 end RAM_CTRLR2;
48
47
49
48
50 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
49 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
51
50
52 signal WD : std_logic_vector(35 downto 0);
51 signal WD : std_logic_vector(35 downto 0);
53 signal WD_D : std_logic_vector(35 downto 0);
52 signal WD_D : std_logic_vector(35 downto 0);
54 signal RD : std_logic_vector(35 downto 0);
53 signal RD : std_logic_vector(35 downto 0);
55 signal WEN, REN : std_logic;
54 signal WEN, REN : std_logic;
56 signal WADDR_back : std_logic_vector(7 downto 0);
55 signal WADDR_back : std_logic_vector(7 downto 0);
57 signal WADDR_back_D: std_logic_vector(7 downto 0);
56 signal WADDR_back_D: std_logic_vector(7 downto 0);
58 signal RADDR : std_logic_vector(7 downto 0);
57 signal RADDR : std_logic_vector(7 downto 0);
59 signal WADDR : std_logic_vector(7 downto 0);
58 signal WADDR : std_logic_vector(7 downto 0);
60 signal WADDR_D : std_logic_vector(7 downto 0);
59 signal WADDR_D : std_logic_vector(7 downto 0);
61
60
62
61
63
62
64 begin
63 begin
65
64
66 sample_out <= RD(Smpl_SZ-1 downto 0);
65 sample_out <= RD(Smpl_SZ-1 downto 0);
67
66
68
67
69 WEN <= not Write;
68 WEN <= not Write;
70 REN <= not read;
69 REN <= not read;
71
70
72
71
73 --==============================================================
72 --==============================================================
74 --=========================R A M================================
73 --=========================R A M================================
75 --==============================================================
74 --==============================================================
76 memRAM : if Mem_use = use_RAM generate
75 memRAM : if Mem_use = use_RAM generate
77 RAMblk :RAM
76 RAMblk :RAM
78 port map(
77 port map(
79 WD => WD_D,
78 WD => WD_D,
80 RD => RD,
79 RD => RD,
81 WEN => WEN,
80 WEN => WEN,
82 REN => REN,
81 REN => REN,
83 WADDR => WADDR,
82 WADDR => WADDR,
84 RADDR => RADDR,
83 RADDR => RADDR,
85 RWCLK => clk,
84 RWCLK => clk,
86 RESET => reset
85 RESET => reset
87 ) ;
86 ) ;
88 end generate;
87 end generate;
89
88
90 memCEL : if Mem_use = use_CEL generate
89 memCEL : if Mem_use = use_CEL generate
91 RAMblk :RAM_CEL
90 RAMblk :RAM_CEL
92 port map(
91 port map(
93 WD => WD_D,
92 WD => WD_D,
94 RD => RD,
93 RD => RD,
95 WEN => WEN,
94 WEN => WEN,
96 REN => REN,
95 REN => REN,
97 WADDR => WADDR,
96 WADDR => WADDR,
98 RADDR => RADDR,
97 RADDR => RADDR,
99 RWCLK => clk,
98 RWCLK => clk,
100 RESET => reset
99 RESET => reset
101 ) ;
100 ) ;
102 end generate;
101 end generate;
103 --==============================================================
102 --==============================================================
104 --==============================================================
103 --==============================================================
105
104
106
105
107 ADDRcntr_inst : ADDRcntr
106 ADDRcntr_inst : ADDRcntr
108 port map(
107 port map(
109 clk => clk,
108 clk => clk,
110 reset => reset,
109 reset => reset,
111 count => count,
110 count => count,
112 clr => GO_0,
111 clr => GO_0,
113 Q => RADDR
112 Q => RADDR
114 );
113 );
115
114
116
115
117
116
118 MUX2_inst1 :MUX2
117 MUX2_inst1 :MUX2
119 generic map(Input_SZ => Smpl_SZ)
118 generic map(Input_SZ => Smpl_SZ)
120 port map(
119 port map(
121 sel => WD_sel,
120 sel => WD_sel,
122 IN1 => sample_in,
121 IN1 => sample_in,
123 IN2 => RD(Smpl_SZ-1 downto 0),
122 IN2 => RD(Smpl_SZ-1 downto 0),
124 RES => WD(Smpl_SZ-1 downto 0)
123 RES => WD(Smpl_SZ-1 downto 0)
125 );
124 );
126
125
127
126
128 MUX2_inst2 :MUX2
127 MUX2_inst2 :MUX2
129 generic map(Input_SZ => 8)
128 generic map(Input_SZ => 8)
130 port map(
129 port map(
131 sel => WADDR_sel,
130 sel => WADDR_sel,
132 IN1 => WADDR_D,
131 IN1 => WADDR_D,
133 IN2 => WADDR_back_D,
132 IN2 => WADDR_back_D,
134 RES => WADDR
133 RES => WADDR
135 );
134 );
136
135
137
136
138
137
139
138
140 WADDR_backreg :REG
139 WADDR_backreg :REG
141 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
140 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
142 port map(
141 port map(
143 reset => reset,
142 reset => reset,
144 clk => SVG_ADDR,
143 clk => SVG_ADDR,
145 D => RADDR,
144 D => RADDR,
146 Q => WADDR_back
145 Q => WADDR_back
147 );
146 );
148
147
149 WADDR_backreg2 :REG
148 WADDR_backreg2 :REG
150 generic map(size => 8)
149 generic map(size => 8)
151 port map(
150 port map(
152 reset => reset,
151 reset => reset,
153 clk => SVG_ADDR,
152 clk => SVG_ADDR,
154 D => WADDR_back,
153 D => WADDR_back,
155 Q => WADDR_back_D
154 Q => WADDR_back_D
156 );
155 );
157
156
158 WDRreg :REG
157 WDRreg :REG
159 generic map(size => Smpl_SZ)
158 generic map(size => Smpl_SZ)
160 port map(
159 port map(
161 reset => reset,
160 reset => reset,
162 clk => clk,
161 clk => clk,
163 D => WD(Smpl_SZ-1 downto 0),
162 D => WD(Smpl_SZ-1 downto 0),
164 Q => WD_D(Smpl_SZ-1 downto 0)
163 Q => WD_D(Smpl_SZ-1 downto 0)
165 );
164 );
166
165
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169
168
170 ADDRreg :REG
169 ADDRreg :REG
171 generic map(size => 8)
170 generic map(size => 8)
172 port map(
171 port map(
173 reset => reset,
172 reset => reset,
174 clk => clk,
173 clk => clk,
175 D => RADDR,
174 D => RADDR,
176 Q => WADDR_D
175 Q => WADDR_D
177 );
176 );
178
177
179
178
180
179
181 end ar_RAM_CTRLR2;
180 end ar_RAM_CTRLR2;
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@@ -1,114 +1,113
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- TestbenshMAC.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23
22
24
23
25
24
26 entity TestbenshMAC is
25 entity TestbenshMAC is
27 end TestbenshMAC;
26 end TestbenshMAC;
28
27
29
28
30
29
31
30
32 architecture ar_TestbenshMAC of TestbenshMAC is
31 architecture ar_TestbenshMAC of TestbenshMAC is
33
32
34
33
35
34
36 constant OP1sz : integer := 16;
35 constant OP1sz : integer := 16;
37 constant OP2sz : integer := 12;
36 constant OP2sz : integer := 12;
38 --IDLE =00 MAC =01 MULT =10 ADD =11
37 --IDLE =00 MAC =01 MULT =10 ADD =11
39 constant IDLE : std_logic_vector(1 downto 0) := "00";
38 constant IDLE : std_logic_vector(1 downto 0) := "00";
40 constant MAC : std_logic_vector(1 downto 0) := "01";
39 constant MAC : std_logic_vector(1 downto 0) := "01";
41 constant MULT : std_logic_vector(1 downto 0) := "10";
40 constant MULT : std_logic_vector(1 downto 0) := "10";
42 constant ADD : std_logic_vector(1 downto 0) := "11";
41 constant ADD : std_logic_vector(1 downto 0) := "11";
43
42
44 signal clk : std_logic:='0';
43 signal clk : std_logic:='0';
45 signal reset : std_logic:='0';
44 signal reset : std_logic:='0';
46 signal clrMAC : std_logic:='0';
45 signal clrMAC : std_logic:='0';
47 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
46 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
48 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
47 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
49 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
48 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
50 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
49 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
51
50
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53
52
54
53
55 begin
54 begin
56
55
57
56
58 MAC1 : entity LPP_IIR_FILTER.MAC
57 MAC1 : entity LPP_IIR_FILTER.MAC
59 generic map(
58 generic map(
60 Input_SZ_A => OP1sz,
59 Input_SZ_A => OP1sz,
61 Input_SZ_B => OP2sz
60 Input_SZ_B => OP2sz
62
61
63 )
62 )
64 port map(
63 port map(
65 clk => clk,
64 clk => clk,
66 reset => reset,
65 reset => reset,
67 clr_MAC => clrMAC,
66 clr_MAC => clrMAC,
68 MAC_MUL_ADD => MAC_MUL_ADD,
67 MAC_MUL_ADD => MAC_MUL_ADD,
69 OP1 => Operand1,
68 OP1 => Operand1,
70 OP2 => Operand2,
69 OP2 => Operand2,
71 RES => Resultat
70 RES => Resultat
72 );
71 );
73
72
74 clk <= not clk after 25 ns;
73 clk <= not clk after 25 ns;
75
74
76 process
75 process
77 begin
76 begin
78 wait for 40 ns;
77 wait for 40 ns;
79 reset <= '1';
78 reset <= '1';
80 wait for 11 ns;
79 wait for 11 ns;
81 Operand1 <= X"0001";
80 Operand1 <= X"0001";
82 Operand2 <= X"001";
81 Operand2 <= X"001";
83 MAC_MUL_ADD <= ADD;
82 MAC_MUL_ADD <= ADD;
84 wait for 50 ns;
83 wait for 50 ns;
85 Operand1 <= X"0001";
84 Operand1 <= X"0001";
86 Operand2 <= X"100";
85 Operand2 <= X"100";
87 wait for 50 ns;
86 wait for 50 ns;
88 Operand1 <= X"0001";
87 Operand1 <= X"0001";
89 Operand2 <= X"001";
88 Operand2 <= X"001";
90 MAC_MUL_ADD <= MULT;
89 MAC_MUL_ADD <= MULT;
91 wait for 50 ns;
90 wait for 50 ns;
92 Operand1 <= X"0002";
91 Operand1 <= X"0002";
93 Operand2 <= X"002";
92 Operand2 <= X"002";
94 wait for 50 ns;
93 wait for 50 ns;
95 clrMAC <= '1';
94 clrMAC <= '1';
96 wait for 50 ns;
95 wait for 50 ns;
97 clrMAC <= '0';
96 clrMAC <= '0';
98 Operand1 <= X"0001";
97 Operand1 <= X"0001";
99 Operand2 <= X"003";
98 Operand2 <= X"003";
100 MAC_MUL_ADD <= MAC;
99 MAC_MUL_ADD <= MAC;
101 wait;
100 wait;
102 end process;
101 end process;
103 end ar_TestbenshMAC;
102 end ar_TestbenshMAC;
104
103
105
104
106
105
107
106
108
107
109
108
110
109
111
110
112
111
113
112
114
113
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@@ -1,19 +1,18
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Top_Filtre_IIR.vhd No newline at end of file
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@@ -1,161 +1,162
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 ------------------------------------------------------------------------------
19 library ieee;
20 library ieee;
20 use ieee.std_logic_1164.all;
21 use ieee.std_logic_1164.all;
21 library grlib;
22 library grlib;
22 use grlib.amba.all;
23 use grlib.amba.all;
23 use grlib.stdlib.all;
24 use grlib.stdlib.all;
24 use grlib.devices.all;
25 use grlib.devices.all;
25 library lpp;
26 library lpp;
26 use lpp.FILTERcfg.all;
27 use lpp.FILTERcfg.all;
27
28
28
29
29
30
30 package iir_filter is
31 package iir_filter is
31
32
32 component APB_IIR_CEL is
33 component APB_IIR_CEL is
33 generic (
34 generic (
34 pindex : integer := 0;
35 pindex : integer := 0;
35 paddr : integer := 0;
36 paddr : integer := 0;
36 pmask : integer := 16#fff#;
37 pmask : integer := 16#fff#;
37 pirq : integer := 0;
38 pirq : integer := 0;
38 abits : integer := 8;
39 abits : integer := 8;
39 Sample_SZ : integer := Smpl_SZ
40 Sample_SZ : integer := Smpl_SZ
40 );
41 );
41 port (
42 port (
42 rst : in std_logic;
43 rst : in std_logic;
43 clk : in std_logic;
44 clk : in std_logic;
44 apbi : in apb_slv_in_type;
45 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
46 apbo : out apb_slv_out_type;
46 sample_clk : in std_logic;
47 sample_clk : in std_logic;
47 sample_clk_out : out std_logic;
48 sample_clk_out : out std_logic;
48 sample_in : in samplT;
49 sample_in : in samplT;
49 sample_out : out samplT
50 sample_out : out samplT
50 );
51 );
51 end component;
52 end component;
52
53
53
54
54 component FILTER is
55 component FILTER is
55 port(
56 port(
56
57
57 reset : in std_logic;
58 reset : in std_logic;
58 clk : in std_logic;
59 clk : in std_logic;
59 sample_clk : in std_logic;
60 sample_clk : in std_logic;
60 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
61 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
61 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
62 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
62 );
63 );
63 end component;
64 end component;
64
65
65
66
66
67
67 component FilterCTRLR is
68 component FilterCTRLR is
68 port(
69 port(
69 reset : in std_logic;
70 reset : in std_logic;
70 clk : in std_logic;
71 clk : in std_logic;
71 sample_clk : in std_logic;
72 sample_clk : in std_logic;
72 ALU_Ctrl : out std_logic_vector(3 downto 0);
73 ALU_Ctrl : out std_logic_vector(3 downto 0);
73 sample_in : in samplT;
74 sample_in : in samplT;
74 coef : out std_logic_vector(Coef_SZ-1 downto 0);
75 coef : out std_logic_vector(Coef_SZ-1 downto 0);
75 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
76 sample : out std_logic_vector(Smpl_SZ-1 downto 0)
76 );
77 );
77 end component;
78 end component;
78
79
79
80
80 component FILTER_RAM_CTRLR is
81 component FILTER_RAM_CTRLR is
81 port(
82 port(
82 reset : in std_logic;
83 reset : in std_logic;
83 clk : in std_logic;
84 clk : in std_logic;
84 run : in std_logic;
85 run : in std_logic;
85 GO_0 : in std_logic;
86 GO_0 : in std_logic;
86 B_A : in std_logic;
87 B_A : in std_logic;
87 writeForce : in std_logic;
88 writeForce : in std_logic;
88 next_blk : in std_logic;
89 next_blk : in std_logic;
89 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
90 sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
90 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
91 sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
91 );
92 );
92 end component;
93 end component;
93
94
94
95
95 component IIR_CEL_CTRLR is
96 component IIR_CEL_CTRLR is
96 generic(Sample_SZ : integer := 16);
97 generic(Sample_SZ : integer := 16);
97 port(
98 port(
98 reset : in std_logic;
99 reset : in std_logic;
99 clk : in std_logic;
100 clk : in std_logic;
100 sample_clk : in std_logic;
101 sample_clk : in std_logic;
101 sample_in : in samplT;
102 sample_in : in samplT;
102 sample_out : out samplT;
103 sample_out : out samplT;
103 virg_pos : in integer;
104 virg_pos : in integer;
104 coefs : in coefs_celsT
105 coefs : in coefs_celsT
105 );
106 );
106 end component;
107 end component;
107
108
108
109
109 component RAM is
110 component RAM is
110 port( WD : in std_logic_vector(35 downto 0); RD : out
111 port( WD : in std_logic_vector(35 downto 0); RD : out
111 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
112 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
112 WADDR : in std_logic_vector(7 downto 0); RADDR : in
113 WADDR : in std_logic_vector(7 downto 0); RADDR : in
113 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
114 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
114 ) ;
115 ) ;
115 end component;
116 end component;
116
117
117
118
118 component RAM_CEL is
119 component RAM_CEL is
119 port( WD : in std_logic_vector(35 downto 0); RD : out
120 port( WD : in std_logic_vector(35 downto 0); RD : out
120 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
121 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
121 WADDR : in std_logic_vector(7 downto 0); RADDR : in
122 WADDR : in std_logic_vector(7 downto 0); RADDR : in
122 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
123 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
123 ) ;
124 ) ;
124 end component;
125 end component;
125
126
126 component IIR_CEL_FILTER is
127 component IIR_CEL_FILTER is
127 generic(Sample_SZ : integer := 16);
128 generic(Sample_SZ : integer := 16);
128 port(
129 port(
129 reset : in std_logic;
130 reset : in std_logic;
130 clk : in std_logic;
131 clk : in std_logic;
131 sample_clk : in std_logic;
132 sample_clk : in std_logic;
132 regs_in : in in_IIR_CEL_reg;
133 regs_in : in in_IIR_CEL_reg;
133 regs_out : in out_IIR_CEL_reg;
134 regs_out : in out_IIR_CEL_reg;
134 sample_in : in samplT;
135 sample_in : in samplT;
135 sample_out : out samplT
136 sample_out : out samplT
136
137
137 );
138 );
138 end component;
139 end component;
139
140
140
141
141 component RAM_CTRLR2 is
142 component RAM_CTRLR2 is
142 generic(
143 generic(
143 Input_SZ_1 : integer := 16
144 Input_SZ_1 : integer := 16
144 );
145 );
145 port(
146 port(
146 reset : in std_logic;
147 reset : in std_logic;
147 clk : in std_logic;
148 clk : in std_logic;
148 WD_sel : in std_logic;
149 WD_sel : in std_logic;
149 Read : in std_logic;
150 Read : in std_logic;
150 WADDR_sel : in std_logic;
151 WADDR_sel : in std_logic;
151 count : in std_logic;
152 count : in std_logic;
152 SVG_ADDR : in std_logic;
153 SVG_ADDR : in std_logic;
153 Write : in std_logic;
154 Write : in std_logic;
154 GO_0 : in std_logic;
155 GO_0 : in std_logic;
155 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
156 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
156 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
157 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
157 );
158 );
158 end component;
159 end component;
159
160
160
161
161 end;
162 end;
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@@ -1,62 +1,61
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- ADDRcntr.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity ADDRcntr is
27 entity ADDRcntr is
29 port(
28 port(
30 clk : in std_logic;
29 clk : in std_logic;
31 reset : in std_logic;
30 reset : in std_logic;
32 count : in std_logic;
31 count : in std_logic;
33 clr : in std_logic;
32 clr : in std_logic;
34 Q : out std_logic_vector(7 downto 0)
33 Q : out std_logic_vector(7 downto 0)
35 );
34 );
36 end entity;
35 end entity;
37
36
38
37
39
38
40
39
41 architecture ar_ADDRcntr of ADDRcntr is
40 architecture ar_ADDRcntr of ADDRcntr is
42
41
43 signal reg : std_logic_vector(7 downto 0);
42 signal reg : std_logic_vector(7 downto 0);
44
43
45 begin
44 begin
46
45
47 Q <= REG;
46 Q <= REG;
48
47
49 process(clk,reset)
48 process(clk,reset)
50 begin
49 begin
51 if reset = '0' then
50 if reset = '0' then
52 REG <= (others => '0');
51 REG <= (others => '0');
53 elsif clk'event and clk ='1' then
52 elsif clk'event and clk ='1' then
54 if clr = '1' then
53 if clr = '1' then
55 REG <= (others => '0');
54 REG <= (others => '0');
56 elsif count ='1' then
55 elsif count ='1' then
57 REG <= std_logic_vector(unsigned(REG)+1);
56 REG <= std_logic_vector(unsigned(REG)+1);
58 end if;
57 end if;
59 end if;
58 end if;
60 end process;
59 end process;
61
60
62 end ar_ADDRcntr;
61 end ar_ADDRcntr;
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@@ -1,101 +1,103
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- ALU.vhd
19 ------------------------------------------------------------------------------
20 -- This file is a part of the LPP VHDL IP LIBRARY
21 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
20 library IEEE;
22 library IEEE;
21 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
23 library lpp;
25 library lpp;
24 use lpp.general_purpose.all;
26 use lpp.general_purpose.all;
25 --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
27 --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
26 --NOT =0101 AND =0110 OR =0111 XOR =1000
28 --NOT =0101 AND =0110 OR =0111 XOR =1000
27 --SHIFTleft =1001 SHIFTright =1010
29 --SHIFTleft =1001 SHIFTright =1010
28
30
29 entity ALU is
31 entity ALU is
30 generic(
32 generic(
31 Arith_en : integer := 1;
33 Arith_en : integer := 1;
32 Logic_en : integer := 1;
34 Logic_en : integer := 1;
33 Input_SZ_1 : integer := 16;
35 Input_SZ_1 : integer := 16;
34 Input_SZ_2 : integer := 9
36 Input_SZ_2 : integer := 9
35
37
36 );
38 );
37 port(
39 port(
38 clk : in std_logic;
40 clk : in std_logic;
39 reset : in std_logic;
41 reset : in std_logic;
40 ctrl : in std_logic_vector(3 downto 0);
42 ctrl : in std_logic_vector(3 downto 0);
41 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
43 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
44 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
45 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
44 );
46 );
45 end entity;
47 end entity;
46
48
47
49
48
50
49 architecture ar_ALU of ALU is
51 architecture ar_ALU of ALU is
50
52
51
53
52
54
53 signal clr_MAC : std_logic:='1';
55 signal clr_MAC : std_logic:='1';
54
56
55
57
56 begin
58 begin
57
59
58 clr_MAC <= '1' when ctrl = "0100" else '0';
60 clr_MAC <= '1' when ctrl = "0100" else '0';
59
61
60
62
61 arith : if Arith_en = 1 generate
63 arith : if Arith_en = 1 generate
62
64
63
65
64 MACinst : MAC
66 MACinst : MAC
65 generic map(
67 generic map(
66 Input_SZ_A => Input_SZ_1,
68 Input_SZ_A => Input_SZ_1,
67 Input_SZ_B => Input_SZ_2
69 Input_SZ_B => Input_SZ_2
68
70
69 )
71 )
70 port map(
72 port map(
71 clk => clk,
73 clk => clk,
72 reset => reset,
74 reset => reset,
73 clr_MAC => clr_MAC,
75 clr_MAC => clr_MAC,
74 MAC_MUL_ADD => ctrl(1 downto 0),
76 MAC_MUL_ADD => ctrl(1 downto 0),
75 OP1 => OP1,
77 OP1 => OP1,
76 OP2 => OP2,
78 OP2 => OP2,
77 RES => RES
79 RES => RES
78 );
80 );
79
81
80 end generate;
82 end generate;
81
83
82 process(clk,reset)
84 process(clk,reset)
83 begin
85 begin
84 if reset = '0' then
86 if reset = '0' then
85 elsif clk'event and clk ='1' then
87 elsif clk'event and clk ='1' then
86
88
87 end if;
89 end if;
88 end process;
90 end process;
89 end architecture;
91 end architecture;
90
92
91
93
92
94
93
95
94
96
95
97
96
98
97
99
98
100
99
101
100
102
101
103
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@@ -1,70 +1,69
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Adder.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity Adder is
27 entity Adder is
29 generic(
28 generic(
30 Input_SZ_A : integer := 16;
29 Input_SZ_A : integer := 16;
31 Input_SZ_B : integer := 16
30 Input_SZ_B : integer := 16
32
31
33 );
32 );
34 port(
33 port(
35 clk : in std_logic;
34 clk : in std_logic;
36 reset : in std_logic;
35 reset : in std_logic;
37 clr : in std_logic;
36 clr : in std_logic;
38 add : in std_logic;
37 add : in std_logic;
39 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
38 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
40 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
39 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
41 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
40 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
42 );
41 );
43 end entity;
42 end entity;
44
43
45
44
46
45
47
46
48 architecture ar_Adder of Adder is
47 architecture ar_Adder of Adder is
49
48
50 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
49 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
51 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
50 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
52
51
53 begin
52 begin
54
53
55 RES <= REG;
54 RES <= REG;
56 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
55 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
57
56
58 process(clk,reset)
57 process(clk,reset)
59 begin
58 begin
60 if reset = '0' then
59 if reset = '0' then
61 REG <= (others => '0');
60 REG <= (others => '0');
62 elsif clk'event and clk ='1' then
61 elsif clk'event and clk ='1' then
63 if clr = '1' then
62 if clr = '1' then
64 REG <= (others => '0');
63 REG <= (others => '0');
65 elsif add = '1' then
64 elsif add = '1' then
66 REG <= RESADD;
65 REG <= RESADD;
67 end if;
66 end if;
68 end if;
67 end if;
69 end process;
68 end process;
70 end ar_Adder;
69 end ar_Adder;
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@@ -1,276 +1,262
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- MAC.vhd
20 library IEEE;
6 library IEEE;
21 use IEEE.numeric_std.all;
7 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
8 use IEEE.std_logic_1164.all;
23 library lpp;
9 library lpp;
24 use lpp.general_purpose.all;
10 use lpp.general_purpose.all;
25 --TODO
11 --TODO
26 --terminer le testbensh puis changer le resize dans les instanciations
12 --terminer le testbensh puis changer le resize dans les instanciations
27 --par un resize sur un vecteur en combi
13 --par un resize sur un vecteur en combi
28
14
29
15
30
16
31
17
32
18
33 entity MAC is
19 entity MAC is
34 generic(
20 generic(
35 Input_SZ_A : integer := 8;
21 Input_SZ_A : integer := 8;
36 Input_SZ_B : integer := 8
22 Input_SZ_B : integer := 8
37
23
38 );
24 );
39 port(
25 port(
40 clk : in std_logic;
26 clk : in std_logic;
41 reset : in std_logic;
27 reset : in std_logic;
42 clr_MAC : in std_logic;
28 clr_MAC : in std_logic;
43 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
29 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
44 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
30 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
45 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
31 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
46 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
32 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
47 );
33 );
48 end MAC;
34 end MAC;
49
35
50
36
51
37
52
38
53 architecture ar_MAC of MAC is
39 architecture ar_MAC of MAC is
54
40
55
41
56
42
57
43
58
44
59 signal add,mult : std_logic;
45 signal add,mult : std_logic;
60 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
46 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
61
47
62 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
48 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
63 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65
51
66
52
67 signal MACMUXsel : std_logic;
53 signal MACMUXsel : std_logic;
68 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
54 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
69 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
70
56
71
57
72
58
73 signal MACMUX2sel : std_logic;
59 signal MACMUX2sel : std_logic;
74
60
75 signal add_D : std_logic;
61 signal add_D : std_logic;
76 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
62 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
77 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
63 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
78 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
79 signal MACMUXsel_D : std_logic;
65 signal MACMUXsel_D : std_logic;
80 signal MACMUX2sel_D : std_logic;
66 signal MACMUX2sel_D : std_logic;
81 signal MACMUX2sel_D_D : std_logic;
67 signal MACMUX2sel_D_D : std_logic;
82 signal clr_MAC_D : std_logic;
68 signal clr_MAC_D : std_logic;
83 signal clr_MAC_D_D : std_logic;
69 signal clr_MAC_D_D : std_logic;
84
70
85
71
86
72
87
73
88
74
89 begin
75 begin
90
76
91
77
92
78
93
79
94 --==============================================================
80 --==============================================================
95 --=============M A C C O N T R O L E R=========================
81 --=============M A C C O N T R O L E R=========================
96 --==============================================================
82 --==============================================================
97 MAC_CONTROLER1 : MAC_CONTROLER
83 MAC_CONTROLER1 : MAC_CONTROLER
98 port map(
84 port map(
99 ctrl => MAC_MUL_ADD,
85 ctrl => MAC_MUL_ADD,
100 MULT => mult,
86 MULT => mult,
101 ADD => add,
87 ADD => add,
102 MACMUX_sel => MACMUXsel,
88 MACMUX_sel => MACMUXsel,
103 MACMUX2_sel => MACMUX2sel
89 MACMUX2_sel => MACMUX2sel
104
90
105 );
91 );
106 --==============================================================
92 --==============================================================
107
93
108
94
109
95
110
96
111 --==============================================================
97 --==============================================================
112 --=============M U L T I P L I E R==============================
98 --=============M U L T I P L I E R==============================
113 --==============================================================
99 --==============================================================
114 Multiplieri_nst : Multiplier
100 Multiplieri_nst : Multiplier
115 generic map(
101 generic map(
116 Input_SZ_A => Input_SZ_A,
102 Input_SZ_A => Input_SZ_A,
117 Input_SZ_B => Input_SZ_B
103 Input_SZ_B => Input_SZ_B
118 )
104 )
119 port map(
105 port map(
120 clk => clk,
106 clk => clk,
121 reset => reset,
107 reset => reset,
122 mult => mult,
108 mult => mult,
123 OP1 => OP1,
109 OP1 => OP1,
124 OP2 => OP2,
110 OP2 => OP2,
125 RES => MULTout
111 RES => MULTout
126 );
112 );
127
113
128 --==============================================================
114 --==============================================================
129
115
130
116
131
117
132
118
133 --==============================================================
119 --==============================================================
134 --======================A D D E R ==============================
120 --======================A D D E R ==============================
135 --==============================================================
121 --==============================================================
136 adder_inst : Adder
122 adder_inst : Adder
137 generic map(
123 generic map(
138 Input_SZ_A => Input_SZ_A+Input_SZ_B,
124 Input_SZ_A => Input_SZ_A+Input_SZ_B,
139 Input_SZ_B => Input_SZ_A+Input_SZ_B
125 Input_SZ_B => Input_SZ_A+Input_SZ_B
140 )
126 )
141 port map(
127 port map(
142 clk => clk,
128 clk => clk,
143 reset => reset,
129 reset => reset,
144 clr => clr_MAC_D,
130 clr => clr_MAC_D,
145 add => add_D,
131 add => add_D,
146 OP1 => ADDERinA,
132 OP1 => ADDERinA,
147 OP2 => ADDERinB,
133 OP2 => ADDERinB,
148 RES => ADDERout
134 RES => ADDERout
149 );
135 );
150
136
151 --==============================================================
137 --==============================================================
152
138
153
139
154 clr_MACREG1 : MAC_REG
140 clr_MACREG1 : MAC_REG
155 generic map(size => 1)
141 generic map(size => 1)
156 port map(
142 port map(
157 reset => reset,
143 reset => reset,
158 clk => clk,
144 clk => clk,
159 D(0) => clr_MAC,
145 D(0) => clr_MAC,
160 Q(0) => clr_MAC_D
146 Q(0) => clr_MAC_D
161 );
147 );
162
148
163 clr_MACREG2 : MAC_REG
149 clr_MACREG2 : MAC_REG
164 generic map(size => 1)
150 generic map(size => 1)
165 port map(
151 port map(
166 reset => reset,
152 reset => reset,
167 clk => clk,
153 clk => clk,
168 D(0) => clr_MAC_D,
154 D(0) => clr_MAC_D,
169 Q(0) => clr_MAC_D_D
155 Q(0) => clr_MAC_D_D
170 );
156 );
171
157
172 addREG : MAC_REG
158 addREG : MAC_REG
173 generic map(size => 1)
159 generic map(size => 1)
174 port map(
160 port map(
175 reset => reset,
161 reset => reset,
176 clk => clk,
162 clk => clk,
177 D(0) => add,
163 D(0) => add,
178 Q(0) => add_D
164 Q(0) => add_D
179 );
165 );
180
166
181 OP1REG : MAC_REG
167 OP1REG : MAC_REG
182 generic map(size => Input_SZ_A)
168 generic map(size => Input_SZ_A)
183 port map(
169 port map(
184 reset => reset,
170 reset => reset,
185 clk => clk,
171 clk => clk,
186 D => OP1,
172 D => OP1,
187 Q => OP1_D
173 Q => OP1_D
188 );
174 );
189
175
190
176
191 OP2REG : MAC_REG
177 OP2REG : MAC_REG
192 generic map(size => Input_SZ_B)
178 generic map(size => Input_SZ_B)
193 port map(
179 port map(
194 reset => reset,
180 reset => reset,
195 clk => clk,
181 clk => clk,
196 D => OP2,
182 D => OP2,
197 Q => OP2_D
183 Q => OP2_D
198 );
184 );
199
185
200
186
201 MULToutREG : MAC_REG
187 MULToutREG : MAC_REG
202 generic map(size => Input_SZ_A+Input_SZ_B)
188 generic map(size => Input_SZ_A+Input_SZ_B)
203 port map(
189 port map(
204 reset => reset,
190 reset => reset,
205 clk => clk,
191 clk => clk,
206 D => MULTout,
192 D => MULTout,
207 Q => MULTout_D
193 Q => MULTout_D
208 );
194 );
209
195
210
196
211 MACMUXselREG : MAC_REG
197 MACMUXselREG : MAC_REG
212 generic map(size => 1)
198 generic map(size => 1)
213 port map(
199 port map(
214 reset => reset,
200 reset => reset,
215 clk => clk,
201 clk => clk,
216 D(0) => MACMUXsel,
202 D(0) => MACMUXsel,
217 Q(0) => MACMUXsel_D
203 Q(0) => MACMUXsel_D
218 );
204 );
219
205
220 MACMUX2selREG : MAC_REG
206 MACMUX2selREG : MAC_REG
221 generic map(size => 1)
207 generic map(size => 1)
222 port map(
208 port map(
223 reset => reset,
209 reset => reset,
224 clk => clk,
210 clk => clk,
225 D(0) => MACMUX2sel,
211 D(0) => MACMUX2sel,
226 Q(0) => MACMUX2sel_D
212 Q(0) => MACMUX2sel_D
227 );
213 );
228
214
229 MACMUX2selREG2 : MAC_REG
215 MACMUX2selREG2 : MAC_REG
230 generic map(size => 1)
216 generic map(size => 1)
231 port map(
217 port map(
232 reset => reset,
218 reset => reset,
233 clk => clk,
219 clk => clk,
234 D(0) => MACMUX2sel_D,
220 D(0) => MACMUX2sel_D,
235 Q(0) => MACMUX2sel_D_D
221 Q(0) => MACMUX2sel_D_D
236 );
222 );
237
223
238 --==============================================================
224 --==============================================================
239 --======================M A C M U X ===========================
225 --======================M A C M U X ===========================
240 --==============================================================
226 --==============================================================
241 MACMUX_inst : MAC_MUX
227 MACMUX_inst : MAC_MUX
242 generic map(
228 generic map(
243 Input_SZ_A => Input_SZ_A+Input_SZ_B,
229 Input_SZ_A => Input_SZ_A+Input_SZ_B,
244 Input_SZ_B => Input_SZ_A+Input_SZ_B
230 Input_SZ_B => Input_SZ_A+Input_SZ_B
245
231
246 )
232 )
247 port map(
233 port map(
248 sel => MACMUXsel_D,
234 sel => MACMUXsel_D,
249 INA1 => ADDERout,
235 INA1 => ADDERout,
250 INA2 => OP2_D_Resz,
236 INA2 => OP2_D_Resz,
251 INB1 => MULTout,
237 INB1 => MULTout,
252 INB2 => OP1_D_Resz,
238 INB2 => OP1_D_Resz,
253 OUTA => ADDERinA,
239 OUTA => ADDERinA,
254 OUTB => ADDERinB
240 OUTB => ADDERinB
255 );
241 );
256 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
242 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
257 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
243 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
258 --==============================================================
244 --==============================================================
259
245
260
246
261 --==============================================================
247 --==============================================================
262 --======================M A C M U X2 ==========================
248 --======================M A C M U X2 ==========================
263 --==============================================================
249 --==============================================================
264 MAC_MUX2_inst : MAC_MUX2
250 MAC_MUX2_inst : MAC_MUX2
265 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
251 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
266 port map(
252 port map(
267 sel => MACMUX2sel_D_D,
253 sel => MACMUX2sel_D_D,
268 RES2 => MULTout_D,
254 RES2 => MULTout_D,
269 RES1 => ADDERout,
255 RES1 => ADDERout,
270 RES => RES
256 RES => RES
271 );
257 );
272
258
273
259
274 --==============================================================
260 --==============================================================
275
261
276 end ar_MAC;
262 end ar_MAC;
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@@ -1,67 +1,67
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- MAC_CONTROLER.vhd
19 ------------------------------------------------------------------------------
20 library IEEE;
20 library IEEE;
21 use IEEE.numeric_std.all;
21 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
22 use IEEE.std_logic_1164.all;
23 library lpp;
23 library lpp;
24 use lpp.general_purpose.all;
24 use lpp.general_purpose.all;
25
25
26
26
27 --IDLE =00 MAC =01 MULT =10 ADD =11
27 --IDLE =00 MAC =01 MULT =10 ADD =11
28
28
29
29
30 entity MAC_CONTROLER is
30 entity MAC_CONTROLER is
31 port(
31 port(
32 ctrl : in std_logic_vector(1 downto 0);
32 ctrl : in std_logic_vector(1 downto 0);
33 MULT : out std_logic;
33 MULT : out std_logic;
34 ADD : out std_logic;
34 ADD : out std_logic;
35 MACMUX_sel : out std_logic;
35 MACMUX_sel : out std_logic;
36 MACMUX2_sel : out std_logic
36 MACMUX2_sel : out std_logic
37
37
38 );
38 );
39 end MAC_CONTROLER;
39 end MAC_CONTROLER;
40
40
41
41
42
42
43
43
44
44
45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
46
46
47 begin
47 begin
48
48
49
49
50
50
51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
53 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
53 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
54 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
54 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
55
55
56
56
57 end ar_MAC_CONTROLER;
57 end ar_MAC_CONTROLER;
58
58
59
59
60
60
61
61
62
62
63
63
64
64
65
65
66
66
67
67
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@@ -1,55 +1,54
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- MAC_MUX.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity MAC_MUX is
27 entity MAC_MUX is
29 generic(
28 generic(
30 Input_SZ_A : integer := 16;
29 Input_SZ_A : integer := 16;
31 Input_SZ_B : integer := 16
30 Input_SZ_B : integer := 16
32
31
33 );
32 );
34 port(
33 port(
35 sel : in std_logic;
34 sel : in std_logic;
36 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
35 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
37 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
36 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
38 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
39 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
38 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
40 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
39 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
41 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
40 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
42 );
41 );
43 end entity;
42 end entity;
44
43
45
44
46
45
47
46
48 architecture ar_MAC_MUX of MAC_MUX is
47 architecture ar_MAC_MUX of MAC_MUX is
49
48
50 begin
49 begin
51
50
52 OUTA <= INA1 when sel = '0' else INA2;
51 OUTA <= INA1 when sel = '0' else INA2;
53 OUTB <= INB1 when sel = '0' else INB2;
52 OUTB <= INB1 when sel = '0' else INB2;
54
53
55 end ar_MAC_MUX;
54 end ar_MAC_MUX;
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@@ -1,47 +1,46
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- MAC_MUX2.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity MAC_MUX2 is
27 entity MAC_MUX2 is
29 generic(Input_SZ : integer := 16);
28 generic(Input_SZ : integer := 16);
30 port(
29 port(
31 sel : in std_logic;
30 sel : in std_logic;
32 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
31 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
33 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
32 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
34 RES : out std_logic_vector(Input_SZ-1 downto 0)
33 RES : out std_logic_vector(Input_SZ-1 downto 0)
35 );
34 );
36 end entity;
35 end entity;
37
36
38
37
39
38
40
39
41 architecture ar_MAC_MUX2 of MAC_MUX2 is
40 architecture ar_MAC_MUX2 of MAC_MUX2 is
42
41
43 begin
42 begin
44
43
45 RES <= RES1 when sel = '0' else RES2;
44 RES <= RES1 when sel = '0' else RES2;
46
45
47 end ar_MAC_MUX2;
46 end ar_MAC_MUX2;
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@@ -1,60 +1,59
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- MAC_REG.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity MAC_REG is
27 entity MAC_REG is
29 generic(size : integer := 16);
28 generic(size : integer := 16);
30 port(
29 port(
31 reset : in std_logic;
30 reset : in std_logic;
32 clk : in std_logic;
31 clk : in std_logic;
33 D : in std_logic_vector(size-1 downto 0);
32 D : in std_logic_vector(size-1 downto 0);
34 Q : out std_logic_vector(size-1 downto 0)
33 Q : out std_logic_vector(size-1 downto 0)
35 );
34 );
36 end entity;
35 end entity;
37
36
38
37
39
38
40 architecture ar_MAC_REG of MAC_REG is
39 architecture ar_MAC_REG of MAC_REG is
41 begin
40 begin
42 process(clk,reset)
41 process(clk,reset)
43 begin
42 begin
44 if reset = '0' then
43 if reset = '0' then
45 Q <= (others => '0');
44 Q <= (others => '0');
46 elsif clk'event and clk ='1' then
45 elsif clk'event and clk ='1' then
47 Q <= D;
46 Q <= D;
48 end if;
47 end if;
49 end process;
48 end process;
50 end ar_MAC_REG;
49 end ar_MAC_REG;
51
50
52
51
53
52
54
53
55
54
56
55
57
56
58
57
59
58
60
59
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@@ -1,47 +1,46
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- MUX2.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity MUX2 is
27 entity MUX2 is
29 generic(Input_SZ : integer := 16);
28 generic(Input_SZ : integer := 16);
30 port(
29 port(
31 sel : in std_logic;
30 sel : in std_logic;
32 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
31 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
33 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
32 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
34 RES : out std_logic_vector(Input_SZ-1 downto 0)
33 RES : out std_logic_vector(Input_SZ-1 downto 0)
35 );
34 );
36 end entity;
35 end entity;
37
36
38
37
39
38
40
39
41 architecture ar_MUX2 of MUX2 is
40 architecture ar_MUX2 of MUX2 is
42
41
43 begin
42 begin
44
43
45 RES <= IN1 when sel = '0' else IN2;
44 RES <= IN1 when sel = '0' else IN2;
46
45
47 end ar_MUX2;
46 end ar_MUX2;
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@@ -1,78 +1,77
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Multiplier.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23
22
24 library lpp;
23 library lpp;
25 use lpp.general_purpose.all;
24 use lpp.general_purpose.all;
26
25
27
26
28
27
29 entity Multiplier is
28 entity Multiplier is
30 generic(
29 generic(
31 Input_SZ_A : integer := 16;
30 Input_SZ_A : integer := 16;
32 Input_SZ_B : integer := 16
31 Input_SZ_B : integer := 16
33
32
34 );
33 );
35 port(
34 port(
36 clk : in std_logic;
35 clk : in std_logic;
37 reset : in std_logic;
36 reset : in std_logic;
38 mult : in std_logic;
37 mult : in std_logic;
39 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
38 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
40 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
39 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
41 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
40 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
42 );
41 );
43 end Multiplier;
42 end Multiplier;
44
43
45
44
46
45
47
46
48
47
49 architecture ar_Multiplier of Multiplier is
48 architecture ar_Multiplier of Multiplier is
50
49
51 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
53
52
54
53
55 begin
54 begin
56
55
57 RES <= REG;
56 RES <= REG;
58 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
57 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
59 process(clk,reset)
58 process(clk,reset)
60 begin
59 begin
61 if reset = '0' then
60 if reset = '0' then
62 REG <= (others => '0');
61 REG <= (others => '0');
63 elsif clk'event and clk ='1' then
62 elsif clk'event and clk ='1' then
64 if mult = '1' then
63 if mult = '1' then
65 REG <= RESMULT;
64 REG <= RESMULT;
66 end if;
65 end if;
67 end if;
66 end if;
68 end process;
67 end process;
69
68
70 end ar_Multiplier;
69 end ar_Multiplier;
71
70
72
71
73
72
74
73
75
74
76
75
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76
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@@ -1,48 +1,47
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- REG.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26 entity REG is
25 entity REG is
27 generic(size : integer := 16 ; initial_VALUE : integer := 0);
26 generic(size : integer := 16 ; initial_VALUE : integer := 0);
28 port(
27 port(
29 reset : in std_logic;
28 reset : in std_logic;
30 clk : in std_logic;
29 clk : in std_logic;
31 D : in std_logic_vector(size-1 downto 0);
30 D : in std_logic_vector(size-1 downto 0);
32 Q : out std_logic_vector(size-1 downto 0)
31 Q : out std_logic_vector(size-1 downto 0)
33 );
32 );
34 end entity;
33 end entity;
35
34
36
35
37
36
38 architecture ar_REG of REG is
37 architecture ar_REG of REG is
39 begin
38 begin
40 process(clk,reset)
39 process(clk,reset)
41 begin
40 begin
42 if reset = '0' then
41 if reset = '0' then
43 Q <= std_logic_vector(to_unsigned(initial_VALUE,size));
42 Q <= std_logic_vector(to_unsigned(initial_VALUE,size));
44 elsif clk'event and clk ='1' then
43 elsif clk'event and clk ='1' then
45 Q <= D;
44 Q <= D;
46 end if;
45 end if;
47 end process;
46 end process;
48 end ar_REG;
47 end ar_REG;
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@@ -1,66 +1,65
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Shifter.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23 library lpp;
22 library lpp;
24 use lpp.general_purpose.all;
23 use lpp.general_purpose.all;
25
24
26
25
27
26
28 entity RShifter is
27 entity RShifter is
29 generic(
28 generic(
30 Input_SZ : integer := 16;
29 Input_SZ : integer := 16;
31 shift_SZ : integer := 4
30 shift_SZ : integer := 4
32 );
31 );
33 port(
32 port(
34 clk : in std_logic;
33 clk : in std_logic;
35 reset : in std_logic;
34 reset : in std_logic;
36 shift : in std_logic;
35 shift : in std_logic;
37 OP : in std_logic_vector(Input_SZ-1 downto 0);
36 OP : in std_logic_vector(Input_SZ-1 downto 0);
38 cnt : in std_logic_vector(shift_SZ-1 downto 0);
37 cnt : in std_logic_vector(shift_SZ-1 downto 0);
39 RES : out std_logic_vector(Input_SZ-1 downto 0)
38 RES : out std_logic_vector(Input_SZ-1 downto 0)
40 );
39 );
41 end entity;
40 end entity;
42
41
43
42
44
43
45
44
46 architecture ar_RShifter of RShifter is
45 architecture ar_RShifter of RShifter is
47
46
48 signal REG : std_logic_vector(Input_SZ-1 downto 0);
47 signal REG : std_logic_vector(Input_SZ-1 downto 0);
49 signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0);
48 signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0);
50
49
51 begin
50 begin
52
51
53 RES <= REG;
52 RES <= REG;
54 RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt))));
53 RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt))));
55
54
56 process(clk,reset)
55 process(clk,reset)
57 begin
56 begin
58 if reset = '0' then
57 if reset = '0' then
59 REG <= (others => '0');
58 REG <= (others => '0');
60 elsif clk'event and clk ='1' then
59 elsif clk'event and clk ='1' then
61 if shift = '1' then
60 if shift = '1' then
62 REG <= RESSHIFT;
61 REG <= RESSHIFT;
63 end if;
62 end if;
64 end if;
63 end if;
65 end process;
64 end process;
66 end ar_RShifter;
65 end ar_RShifter;
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@@ -1,136 +1,135
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- TestbenshALU.vhd
20 library IEEE;
19 library IEEE;
21 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
23
22
24
23
25
24
26 entity TestbenshALU is
25 entity TestbenshALU is
27 end TestbenshALU;
26 end TestbenshALU;
28
27
29
28
30
29
31
30
32 architecture ar_TestbenshALU of TestbenshALU is
31 architecture ar_TestbenshALU of TestbenshALU is
33
32
34
33
35
34
36 constant OP1sz : integer := 16;
35 constant OP1sz : integer := 16;
37 constant OP2sz : integer := 12;
36 constant OP2sz : integer := 12;
38 --IDLE =00 MAC =01 MULT =10 ADD =11
37 --IDLE =00 MAC =01 MULT =10 ADD =11
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
38 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC : std_logic_vector(3 downto 0) := "0001";
39 constant MAC : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
40 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
41 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
42 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44
43
45 signal clk : std_logic:='0';
44 signal clk : std_logic:='0';
46 signal reset : std_logic:='0';
45 signal reset : std_logic:='0';
47 signal ctrl : std_logic_vector(3 downto 0):=IDLE;
46 signal ctrl : std_logic_vector(3 downto 0):=IDLE;
48 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
47 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
49 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
48 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
50 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
49 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
51
50
52
51
53
52
54
53
55 begin
54 begin
56
55
57 ALU1 : entity LPP_IIR_FILTER.ALU
56 ALU1 : entity LPP_IIR_FILTER.ALU
58 generic map(
57 generic map(
59 Arith_en => 1,
58 Arith_en => 1,
60 Logic_en => 0,
59 Logic_en => 0,
61 Input_SZ_1 => OP1sz,
60 Input_SZ_1 => OP1sz,
62 Input_SZ_2 => OP2sz
61 Input_SZ_2 => OP2sz
63
62
64 )
63 )
65 port map(
64 port map(
66 clk => clk,
65 clk => clk,
67 reset => reset,
66 reset => reset,
68 ctrl => ctrl,
67 ctrl => ctrl,
69 OP1 => Operand1,
68 OP1 => Operand1,
70 OP2 => Operand2,
69 OP2 => Operand2,
71 RES => Resultat
70 RES => Resultat
72 );
71 );
73
72
74
73
75
74
76
75
77 clk <= not clk after 25 ns;
76 clk <= not clk after 25 ns;
78
77
79 process
78 process
80 begin
79 begin
81 wait for 40 ns;
80 wait for 40 ns;
82 reset <= '1';
81 reset <= '1';
83 wait for 11 ns;
82 wait for 11 ns;
84 Operand1 <= X"0001";
83 Operand1 <= X"0001";
85 Operand2 <= X"001";
84 Operand2 <= X"001";
86 ctrl <= ADD;
85 ctrl <= ADD;
87 wait for 50 ns;
86 wait for 50 ns;
88 Operand1 <= X"0001";
87 Operand1 <= X"0001";
89 Operand2 <= X"100";
88 Operand2 <= X"100";
90 wait for 50 ns;
89 wait for 50 ns;
91 Operand1 <= X"0001";
90 Operand1 <= X"0001";
92 Operand2 <= X"001";
91 Operand2 <= X"001";
93 ctrl <= MULT;
92 ctrl <= MULT;
94 wait for 50 ns;
93 wait for 50 ns;
95 Operand1 <= X"0002";
94 Operand1 <= X"0002";
96 Operand2 <= X"002";
95 Operand2 <= X"002";
97 wait for 50 ns;
96 wait for 50 ns;
98 ctrl <= clr_mac;
97 ctrl <= clr_mac;
99 wait for 50 ns;
98 wait for 50 ns;
100 Operand1 <= X"0001";
99 Operand1 <= X"0001";
101 Operand2 <= X"003";
100 Operand2 <= X"003";
102 ctrl <= MAC;
101 ctrl <= MAC;
103 wait for 50 ns;
102 wait for 50 ns;
104 Operand1 <= X"0001";
103 Operand1 <= X"0001";
105 Operand2 <= X"001";
104 Operand2 <= X"001";
106 wait for 50 ns;
105 wait for 50 ns;
107 Operand1 <= X"0011";
106 Operand1 <= X"0011";
108 Operand2 <= X"003";
107 Operand2 <= X"003";
109 wait for 50 ns;
108 wait for 50 ns;
110 Operand1 <= X"1001";
109 Operand1 <= X"1001";
111 Operand2 <= X"003";
110 Operand2 <= X"003";
112 wait for 50 ns;
111 wait for 50 ns;
113 Operand1 <= X"0001";
112 Operand1 <= X"0001";
114 Operand2 <= X"000";
113 Operand2 <= X"000";
115 wait for 50 ns;
114 wait for 50 ns;
116 Operand1 <= X"0001";
115 Operand1 <= X"0001";
117 Operand2 <= X"003";
116 Operand2 <= X"003";
118 wait for 50 ns;
117 wait for 50 ns;
119 Operand1 <= X"0101";
118 Operand1 <= X"0101";
120 Operand2 <= X"053";
119 Operand2 <= X"053";
121 wait for 50 ns;
120 wait for 50 ns;
122 ctrl <= clr_mac;
121 ctrl <= clr_mac;
123 wait;
122 wait;
124 end process;
123 end process;
125 end ar_TestbenshALU;
124 end ar_TestbenshALU;
126
125
127
126
128
127
129
128
130
129
131
130
132
131
133
132
134
133
135
134
136
135
Show file before | Show file after | Hide comments
@@ -1,195 +1,208
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22
21
23
22
24
23
25 package general_purpose is
24 package general_purpose is
26
25
26
27
28 component Clk_divider is
29 generic(OSC_freqHz : integer := 50000000;
30 TargetFreq_Hz : integer := 50000);
31 Port ( clk : in STD_LOGIC;
32 reset : in STD_LOGIC;
33 clk_divided : out STD_LOGIC);
34 end component;
35
36
37
38
39
27 component Adder is
40 component Adder is
28 generic(
41 generic(
29 Input_SZ_A : integer := 16;
42 Input_SZ_A : integer := 16;
30 Input_SZ_B : integer := 16
43 Input_SZ_B : integer := 16
31
44
32 );
45 );
33 port(
46 port(
34 clk : in std_logic;
47 clk : in std_logic;
35 reset : in std_logic;
48 reset : in std_logic;
36 clr : in std_logic;
49 clr : in std_logic;
37 add : in std_logic;
50 add : in std_logic;
38 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
51 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
39 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
52 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
40 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
53 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
41 );
54 );
42 end component;
55 end component;
43
56
44 component ADDRcntr is
57 component ADDRcntr is
45 port(
58 port(
46 clk : in std_logic;
59 clk : in std_logic;
47 reset : in std_logic;
60 reset : in std_logic;
48 count : in std_logic;
61 count : in std_logic;
49 clr : in std_logic;
62 clr : in std_logic;
50 Q : out std_logic_vector(7 downto 0)
63 Q : out std_logic_vector(7 downto 0)
51 );
64 );
52 end component;
65 end component;
53
66
54 component ALU is
67 component ALU is
55 generic(
68 generic(
56 Arith_en : integer := 1;
69 Arith_en : integer := 1;
57 Logic_en : integer := 1;
70 Logic_en : integer := 1;
58 Input_SZ_1 : integer := 16;
71 Input_SZ_1 : integer := 16;
59 Input_SZ_2 : integer := 9
72 Input_SZ_2 : integer := 9
60
73
61 );
74 );
62 port(
75 port(
63 clk : in std_logic;
76 clk : in std_logic;
64 reset : in std_logic;
77 reset : in std_logic;
65 ctrl : in std_logic_vector(3 downto 0);
78 ctrl : in std_logic_vector(3 downto 0);
66 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
79 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
67 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
80 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
68 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
81 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
69 );
82 );
70 end component;
83 end component;
71
84
72
85
73 component MAC is
86 component MAC is
74 generic(
87 generic(
75 Input_SZ_A : integer := 8;
88 Input_SZ_A : integer := 8;
76 Input_SZ_B : integer := 8
89 Input_SZ_B : integer := 8
77
90
78 );
91 );
79 port(
92 port(
80 clk : in std_logic;
93 clk : in std_logic;
81 reset : in std_logic;
94 reset : in std_logic;
82 clr_MAC : in std_logic;
95 clr_MAC : in std_logic;
83 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
96 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
84 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
97 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
85 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
98 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
86 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
99 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
87 );
100 );
88 end component;
101 end component;
89
102
90
103
91 component MAC_CONTROLER is
104 component MAC_CONTROLER is
92 port(
105 port(
93 ctrl : in std_logic_vector(1 downto 0);
106 ctrl : in std_logic_vector(1 downto 0);
94 MULT : out std_logic;
107 MULT : out std_logic;
95 ADD : out std_logic;
108 ADD : out std_logic;
96 MACMUX_sel : out std_logic;
109 MACMUX_sel : out std_logic;
97 MACMUX2_sel : out std_logic
110 MACMUX2_sel : out std_logic
98
111
99 );
112 );
100 end component;
113 end component;
101
114
102 component MAC_MUX is
115 component MAC_MUX is
103 generic(
116 generic(
104 Input_SZ_A : integer := 16;
117 Input_SZ_A : integer := 16;
105 Input_SZ_B : integer := 16
118 Input_SZ_B : integer := 16
106
119
107 );
120 );
108 port(
121 port(
109 sel : in std_logic;
122 sel : in std_logic;
110 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
123 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
111 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
124 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
112 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
125 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
113 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
126 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
114 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
127 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
115 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
128 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
116 );
129 );
117 end component;
130 end component;
118
131
119
132
120 component MAC_MUX2 is
133 component MAC_MUX2 is
121 generic(Input_SZ : integer := 16);
134 generic(Input_SZ : integer := 16);
122 port(
135 port(
123 sel : in std_logic;
136 sel : in std_logic;
124 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
137 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
125 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
138 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
126 RES : out std_logic_vector(Input_SZ-1 downto 0)
139 RES : out std_logic_vector(Input_SZ-1 downto 0)
127 );
140 );
128 end component;
141 end component;
129
142
130
143
131 component MAC_REG is
144 component MAC_REG is
132 generic(size : integer := 16);
145 generic(size : integer := 16);
133 port(
146 port(
134 reset : in std_logic;
147 reset : in std_logic;
135 clk : in std_logic;
148 clk : in std_logic;
136 D : in std_logic_vector(size-1 downto 0);
149 D : in std_logic_vector(size-1 downto 0);
137 Q : out std_logic_vector(size-1 downto 0)
150 Q : out std_logic_vector(size-1 downto 0)
138 );
151 );
139 end component;
152 end component;
140
153
141
154
142 component MUX2 is
155 component MUX2 is
143 generic(Input_SZ : integer := 16);
156 generic(Input_SZ : integer := 16);
144 port(
157 port(
145 sel : in std_logic;
158 sel : in std_logic;
146 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
159 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
147 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
160 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
148 RES : out std_logic_vector(Input_SZ-1 downto 0)
161 RES : out std_logic_vector(Input_SZ-1 downto 0)
149 );
162 );
150 end component;
163 end component;
151
164
152 component Multiplier is
165 component Multiplier is
153 generic(
166 generic(
154 Input_SZ_A : integer := 16;
167 Input_SZ_A : integer := 16;
155 Input_SZ_B : integer := 16
168 Input_SZ_B : integer := 16
156
169
157 );
170 );
158 port(
171 port(
159 clk : in std_logic;
172 clk : in std_logic;
160 reset : in std_logic;
173 reset : in std_logic;
161 mult : in std_logic;
174 mult : in std_logic;
162 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
175 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
163 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
176 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
164 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
177 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
165 );
178 );
166 end component;
179 end component;
167
180
168 component REG is
181 component REG is
169 generic(size : integer := 16 ; initial_VALUE : integer := 0);
182 generic(size : integer := 16 ; initial_VALUE : integer := 0);
170 port(
183 port(
171 reset : in std_logic;
184 reset : in std_logic;
172 clk : in std_logic;
185 clk : in std_logic;
173 D : in std_logic_vector(size-1 downto 0);
186 D : in std_logic_vector(size-1 downto 0);
174 Q : out std_logic_vector(size-1 downto 0)
187 Q : out std_logic_vector(size-1 downto 0)
175 );
188 );
176 end component;
189 end component;
177
190
178
191
179
192
180 component RShifter is
193 component RShifter is
181 generic(
194 generic(
182 Input_SZ : integer := 16;
195 Input_SZ : integer := 16;
183 shift_SZ : integer := 4
196 shift_SZ : integer := 4
184 );
197 );
185 port(
198 port(
186 clk : in std_logic;
199 clk : in std_logic;
187 reset : in std_logic;
200 reset : in std_logic;
188 shift : in std_logic;
201 shift : in std_logic;
189 OP : in std_logic_vector(Input_SZ-1 downto 0);
202 OP : in std_logic_vector(Input_SZ-1 downto 0);
190 cnt : in std_logic_vector(shift_SZ-1 downto 0);
203 cnt : in std_logic_vector(shift_SZ-1 downto 0);
191 RES : out std_logic_vector(Input_SZ-1 downto 0)
204 RES : out std_logic_vector(Input_SZ-1 downto 0)
192 );
205 );
193 end component;
206 end component;
194
207
195 end;
208 end;
Show file before | Show file after | Hide comments
@@ -1,13 +1,14
1 Adder.vhd
1 Adder.vhd
2 ADDRcntr.vhd
2 ADDRcntr.vhd
3 ALU.vhd
3 ALU.vhd
4 Clk_divider.vhd
4 general_purpose.vhd
5 general_purpose.vhd
5 MAC_CONTROLER.vhd
6 MAC_CONTROLER.vhd
6 MAC_MUX2.vhd
7 MAC_MUX2.vhd
7 MAC_MUX.vhd
8 MAC_MUX.vhd
8 MAC_REG.vhd
9 MAC_REG.vhd
9 MAC.vhd
10 MAC.vhd
10 Multiplier.vhd
11 Multiplier.vhd
11 MUX2.vhd
12 MUX2.vhd
12 REG.vhd
13 REG.vhd
13 Shifter.vhd
14 Shifter.vhd
Show file before | Show file after | Hide comments
@@ -1,126 +1,118
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 library ieee;
14 --
14 use ieee.std_logic_1164.all;
15 -- You should have received a copy of the GNU General Public License
15 library grlib;
16 -- along with this program; if not, write to the Free Software
16 use grlib.amba.all;
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 use grlib.stdlib.all;
18 -------------------------------------------------------------------------------
18 use grlib.devices.all;
19 -- APB_CNA.vhd
19 library lpp;
20
20 use lpp.lpp_CNA_amba.all;
21 library ieee;
21
22 use ieee.std_logic_1164.all;
22
23 library grlib;
23 entity APB_CNA is
24 use grlib.amba.all;
24 generic (
25 use grlib.stdlib.all;
25 pindex : integer := 0;
26 use grlib.devices.all;
26 paddr : integer := 0;
27 library lpp;
27 pmask : integer := 16#fff#;
28 use lpp.lpp_CNA_amba.all;
28 pirq : integer := 0;
29
29 abits : integer := 8);
30
30 port (
31 entity APB_CNA is
31 clk : in std_logic;
32 generic (
32 rst : in std_logic;
33 pindex : integer := 0;
33 apbi : in apb_slv_in_type;
34 paddr : integer := 0;
34 apbo : out apb_slv_out_type;
35 pmask : integer := 16#fff#;
35 SYNC : out std_logic;
36 pirq : integer := 0;
36 SCLK : out std_logic;
37 abits : integer := 8);
37 DATA : out std_logic
38 port (
38 );
39 clk : in std_logic;
39 end APB_CNA;
40 rst : in std_logic;
40
41 apbi : in apb_slv_in_type;
41
42 apbo : out apb_slv_out_type;
42 architecture ar_APB_CNA of APB_CNA is
43 SYNC : out std_logic;
43
44 SCLK : out std_logic;
44 constant REVISION : integer := 1;
45 DATA : out std_logic
45
46 );
46 constant pconfig : apb_config_type := (
47 end APB_CNA;
47 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
48
48 1 => apb_iobar(paddr, pmask));
49
49
50 architecture ar_APB_CNA of APB_CNA is
50 signal flag_nw : std_logic;
51
51 signal bp : std_logic;
52 constant REVISION : integer := 1;
52 signal Rz : std_logic;
53
53 signal flag_sd : std_logic;
54 constant pconfig : apb_config_type := (
54 signal Rdata : std_logic_vector(31 downto 0);
55 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
55
56 1 => apb_iobar(paddr, pmask));
56 type CNA_ctrlr_Reg is record
57
57 CNA_Cfg : std_logic_vector(3 downto 0);
58 signal flag_nw : std_logic;
58 CNA_Data : std_logic_vector(15 downto 0);
59 signal bp : std_logic;
59 end record;
60 signal Rz : std_logic;
60
61 signal flag_sd : std_logic;
61 signal Rec : CNA_ctrlr_Reg;
62 signal Rdata : std_logic_vector(31 downto 0);
62 --signal ConfigREG : std_logic_vector(3 downto 0);
63
63 --signal DataREG : std_logic_vector(15 downto 0);
64 type CNA_ctrlr_Reg is record
64
65 CNA_Cfg : std_logic_vector(3 downto 0);
65 begin
66 CNA_Data : std_logic_vector(15 downto 0);
66
67 end record;
67 bp <= Rec.CNA_Cfg(0);
68
68 flag_nw <= Rec.CNA_Cfg(1);
69 signal Rec : CNA_ctrlr_Reg;
69 Rec.CNA_Cfg(2) <= flag_sd;
70 --signal ConfigREG : std_logic_vector(3 downto 0);
70 Rec.CNA_Cfg(3) <= Rz;
71 --signal DataREG : std_logic_vector(15 downto 0);
71
72
72
73 begin
73
74
74 CONVERTER : entity Work.CNA_TabloC
75 bp <= Rec.CNA_Cfg(0);
75 port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
76 flag_nw <= Rec.CNA_Cfg(1);
76
77 Rec.CNA_Cfg(2) <= flag_sd;
77
78 Rec.CNA_Cfg(3) <= Rz;
78
79
79 process(rst,clk)
80
80 begin
81
81 if(rst='0')then
82 CONVERTER : entity Work.CNA_TabloC
82 Rec.CNA_Data <= (others => '0');
83 port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
83
84
84 elsif(clk'event and clk='1')then
85
85
86
86
87 process(rst,clk)
87 --APB Write OP
88 begin
88 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
89 if(rst='0')then
89 case apbi.paddr(abits-1 downto 2) is
90 Rec.CNA_Data <= (others => '0');
90 when "000000" =>
91
91 Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
92 elsif(clk'event and clk='1')then
92 when "000001" =>
93
93 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
94
94 when others =>
95 --APB Write OP
95 null;
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 end case;
97 case apbi.paddr(abits-1 downto 2) is
97 end if;
98 when "000000" =>
98
99 Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
99 --APB READ OP
100 when "000001" =>
100 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
101 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
101 case apbi.paddr(abits-1 downto 2) is
102 when others =>
102 when "000000" =>
103 null;
103 Rdata(31 downto 4) <= X"ABCDEF5";
104 end case;
104 Rdata(3 downto 0) <= Rec.CNA_Cfg;
105 end if;
105 when "000001" =>
106
106 Rdata(31 downto 16) <= X"FD18";
107 --APB READ OP
107 Rdata(15 downto 0) <= Rec.CNA_Data;
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 when others =>
109 case apbi.paddr(abits-1 downto 2) is
109 Rdata <= (others => '0');
110 when "000000" =>
110 end case;
111 Rdata(31 downto 4) <= X"ABCDEF5";
111 end if;
112 Rdata(3 downto 0) <= Rec.CNA_Cfg;
112
113 when "000001" =>
113 end if;
114 Rdata(31 downto 16) <= X"FD18";
114 apbo.pconfig <= pconfig;
115 Rdata(15 downto 0) <= Rec.CNA_Data;
115 end process;
116 when others =>
116
117 Rdata <= (others => '0');
117 apbo.prdata <= Rdata when apbi.penable = '1';
118 end case;
118 end ar_APB_CNA;
119 end if;
120
121 end if;
122 apbo.pconfig <= pconfig;
123 end process;
124
125 apbo.prdata <= Rdata when apbi.penable = '1';
126 end ar_APB_CNA; No newline at end of file
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@@ -1,71 +1,88
1 -- CNA_TabloC.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.std_logic_1164.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.numeric_std.all;
4 --
5 use work.Convertisseur_config.all;
5 -- This program is free software; you can redistribute it and/or modify
6
6 -- it under the terms of the GNU General Public License as published by
7 entity CNA_TabloC is
7 -- the Free Software Foundation; either version 3 of the License, or
8 port(
8 -- (at your option) any later version.
9 clock : in std_logic;
9 --
10 rst : in std_logic;
10 -- This program is distributed in the hope that it will be useful,
11 flag_nw : in std_logic;
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 bp : in std_logic;
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 Data_C : in std_logic_vector(15 downto 0);
13 -- GNU General Public License for more details.
14 SYNC : out std_logic;
14 --
15 SCLK : out std_logic;
15 -- You should have received a copy of the GNU General Public License
16 Rz : out std_logic;
16 -- along with this program; if not, write to the Free Software
17 flag_sd : out std_logic;
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 Data : out std_logic
18 -------------------------------------------------------------------------------
19 );
19 library IEEE;
20 end CNA_TabloC;
20 use IEEE.std_logic_1164.all;
21
21 use IEEE.numeric_std.all;
22
22 use work.Convertisseur_config.all;
23 architecture ar_CNA_TabloC of CNA_TabloC is
23
24
24 entity CNA_TabloC is
25 component CLKINT
25 port(
26 port( A : in std_logic := 'U';
26 clock : in std_logic;
27 Y : out std_logic);
27 rst : in std_logic;
28 end component;
28 flag_nw : in std_logic;
29
29 bp : in std_logic;
30 signal clk : std_logic;
30 Data_C : in std_logic_vector(15 downto 0);
31 --signal reset : std_logic;
31 SYNC : out std_logic;
32
32 SCLK : out std_logic;
33 signal raz : std_logic;
33 Rz : out std_logic;
34 signal sys_clk : std_logic;
34 flag_sd : out std_logic;
35 signal Data_int : std_logic_vector(15 downto 0);
35 Data : out std_logic
36 signal OKAI_send : std_logic;
36 );
37
37 end CNA_TabloC;
38 begin
38
39
39
40
40 architecture ar_CNA_TabloC of CNA_TabloC is
41 CLKINT_0 : CLKINT
41
42 port map(A => clock, Y => clk);
42 component CLKINT
43
43 port( A : in std_logic := 'U';
44 CLKINT_1 : CLKINT
44 Y : out std_logic);
45 port map(A => rst, Y => raz);
45 end component;
46
46
47
47 signal clk : std_logic;
48 SystemCLK : entity work.Clock_Serie
48 --signal reset : std_logic;
49 generic map (nb_serial)
49
50 port map (clk,raz,sys_clk);
50 signal raz : std_logic;
51
51 signal sys_clk : std_logic;
52
52 signal Data_int : std_logic_vector(15 downto 0);
53 Signal_sync : entity work.GeneSYNC_flag
53 signal OKAI_send : std_logic;
54 port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
54
55
55 begin
56
56
57 Serial : entity work.serialize
57
58 port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
58 CLKINT_0 : CLKINT
59
59 port map(A => clock, Y => clk);
60
60
61 --raz <= not reset;
61 CLKINT_1 : CLKINT
62 Rz <= raz;
62 port map(A => rst, Y => raz);
63 SCLK <= not sys_clk;
63
64 --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12));
64
65 --Data_TOT <= "0001" & Data_Cvec;
65 SystemCLK : entity work.Clock_Serie
66
66 generic map (nb_serial)
67 with bp select
67 port map (clk,raz,sys_clk);
68 Data_int <= X"9555" when '1',
68
69 Data_C when others;
69
70
70 Signal_sync : entity work.GeneSYNC_flag
71 end ar_CNA_TabloC; No newline at end of file
71 port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
72
73
74 Serial : entity work.serialize
75 port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
76
77
78 --raz <= not reset;
79 Rz <= raz;
80 SCLK <= not sys_clk;
81 --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12));
82 --Data_TOT <= "0001" & Data_Cvec;
83
84 with bp select
85 Data_int <= X"9555" when '1',
86 Data_C when others;
87
88 end ar_CNA_TabloC;
Show file before | Show file after | Hide comments
@@ -1,24 +1,41
1 -- Convertisseur_config.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.std_logic_1164.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.numeric_std.all;
4 --
5
5 -- This program is free software; you can redistribute it and/or modify
6 Package Convertisseur_config is
6 -- it under the terms of the GNU General Public License as published by
7
7 -- the Free Software Foundation; either version 3 of the License, or
8
8 -- (at your option) any later version.
9 --===========================================================|
9 --
10 --================= Valeurs Sinus 1Khz ======================|
10 -- This program is distributed in the hope that it will be useful,
11 --===========================================================|
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
13 -- GNU General Public License for more details.
14
14 --
15 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
15 -- You should have received a copy of the GNU General Public License
16
16 -- along with this program; if not, write to the Free Software
17
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 --===========================================================|
18 -------------------------------------------------------------------------------
19 --============= Fr�quence de s�rialisation ==================|
19 library IEEE;
20 --===========================================================|
20 use IEEE.std_logic_1164.all;
21 constant Freq_serial : integer := 1_000_000;
21 use IEEE.numeric_std.all;
22 constant nb_serial : integer := 40_000_000 / Freq_serial;
22
23
23 Package Convertisseur_config is
24 end; No newline at end of file
24
25
26 --===========================================================|
27 --================= Valeurs Sinus 1Khz ======================|
28 --===========================================================|
29 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
30 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
31
32 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
33
34
35 --===========================================================|
36 --============= Fr�quence de s�rialisation ==================|
37 --===========================================================|
38 constant Freq_serial : integer := 1_000_000;
39 constant nb_serial : integer := 40_000_000 / Freq_serial;
40
41 end;
Show file before | Show file after | Hide comments
@@ -1,94 +1,111
1 -- GeneSYNC_flag.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.std_logic_1164.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.numeric_std.all;
4 --
5
5 -- This program is free software; you can redistribute it and/or modify
6 entity GeneSYNC_flag is
6 -- it under the terms of the GNU General Public License as published by
7
7 -- the Free Software Foundation; either version 3 of the License, or
8 port(
8 -- (at your option) any later version.
9 clk,raz : in std_logic;
9 --
10 flag_nw : in std_logic;
10 -- This program is distributed in the hope that it will be useful,
11 Sysclk : in std_logic;
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 OKAI_send : out std_logic;
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 SYNC : out std_logic
13 -- GNU General Public License for more details.
14 );
14 --
15
15 -- You should have received a copy of the GNU General Public License
16 end GeneSYNC_flag;
16 -- along with this program; if not, write to the Free Software
17
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
18 -------------------------------------------------------------------------------
19 architecture ar_GeneSYNC_flag of GeneSYNC_flag is
19 library IEEE;
20
20 use IEEE.std_logic_1164.all;
21 signal Sysclk_reg : std_logic;
21 use IEEE.numeric_std.all;
22 signal flag_nw_reg : std_logic;
22
23 signal count : integer;
23 entity GeneSYNC_flag is
24
24
25 port(
26 clk,raz : in std_logic;
27 flag_nw : in std_logic;
28 Sysclk : in std_logic;
29 OKAI_send : out std_logic;
30 SYNC : out std_logic
31 );
32
33 end GeneSYNC_flag;
34
35
36 architecture ar_GeneSYNC_flag of GeneSYNC_flag is
37
38 signal Sysclk_reg : std_logic;
39 signal flag_nw_reg : std_logic;
40 signal count : integer;
41
25 type etat is (e0,e1,e2,eX);
42 type etat is (e0,e1,e2,eX);
26 signal ect : etat;
43 signal ect : etat;
27
44
28 begin
45 begin
29 process (clk,raz)
46 process (clk,raz)
30 begin
47 begin
31 if(raz='0')then
48 if(raz='0')then
32 SYNC <= '0';
49 SYNC <= '0';
33 Sysclk_reg <= '0';
50 Sysclk_reg <= '0';
34 flag_nw_reg <= '0';
51 flag_nw_reg <= '0';
35 count <= 14;
52 count <= 14;
36 OKAI_send <= '0';
53 OKAI_send <= '0';
37 ect <= e0;
54 ect <= e0;
38
55
39 elsif(clk' event and clk='1')then
56 elsif(clk' event and clk='1')then
40 Sysclk_reg <= Sysclk;
57 Sysclk_reg <= Sysclk;
41 flag_nw_reg <= flag_nw;
58 flag_nw_reg <= flag_nw;
42
59
43 case ect is
60 case ect is
44 when e0 =>
61 when e0 =>
45 if(flag_nw_reg='0' and flag_nw='1')then
62 if(flag_nw_reg='0' and flag_nw='1')then
46 ect <= e1;
63 ect <= e1;
47 else
64 else
48 count <= 14;
65 count <= 14;
49 ect <= e0;
66 ect <= e0;
50 end if;
67 end if;
51
68
52
69
53 when e1 =>
70 when e1 =>
54 if(Sysclk_reg='1' and Sysclk='0')then
71 if(Sysclk_reg='1' and Sysclk='0')then
55 if(count=15)then
72 if(count=15)then
56 SYNC <= '1';
73 SYNC <= '1';
57 count <= count+1;
74 count <= count+1;
58 ect <= e2;
75 ect <= e2;
59 elsif(count=16)then
76 elsif(count=16)then
60 count <= 0;
77 count <= 0;
61 OKAI_send <= '1';
78 OKAI_send <= '1';
62 ect <= eX;
79 ect <= eX;
63 else
80 else
64 count <= count+1;
81 count <= count+1;
65 OKAI_send <= '0';
82 OKAI_send <= '0';
66 ect <= e1;
83 ect <= e1;
67 end if;
84 end if;
68 end if;
85 end if;
69
86
70
87
71 when e2 =>
88 when e2 =>
72 if(Sysclk_reg='0' and Sysclk='1')then
89 if(Sysclk_reg='0' and Sysclk='1')then
73 if(count=16)then
90 if(count=16)then
74 SYNC <= '0';
91 SYNC <= '0';
75 ect <= e1;
92 ect <= e1;
76 end if;
93 end if;
77 end if;
94 end if;
78
95
79 when eX =>
96 when eX =>
80 if(Sysclk_reg='0' and Sysclk='1')then
97 if(Sysclk_reg='0' and Sysclk='1')then
81 if(count=15)then
98 if(count=15)then
82 OKAI_send <= '0';
99 OKAI_send <= '0';
83 ect <= e0;
100 ect <= e0;
84 else
101 else
85 count <= count+1;
102 count <= count+1;
86 ect <= eX;
103 ect <= eX;
87 end if;
104 end if;
88 end if;
105 end if;
89
106
90 end case;
107 end case;
91 end if;
108 end if;
92
109
93 end process;
110 end process;
94 end ar_GeneSYNC_flag; No newline at end of file
111 end ar_GeneSYNC_flag;
Show file before | Show file after | Hide comments
@@ -1,86 +1,103
1 -- Serialize.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
2 library IEEE;
19 library IEEE;
3 use IEEE.numeric_std.all;
20 use IEEE.numeric_std.all;
4 use IEEE.std_logic_1164.all;
21 use IEEE.std_logic_1164.all;
5
22
6 entity Serialize is
23 entity Serialize is
7
24
8 port(
25 port(
9 clk,raz : in std_logic;
26 clk,raz : in std_logic;
10 sclk : in std_logic;
27 sclk : in std_logic;
11 vectin : in std_logic_vector(15 downto 0);
28 vectin : in std_logic_vector(15 downto 0);
12 send : in std_logic;
29 send : in std_logic;
13 sended : out std_logic;
30 sended : out std_logic;
14 Data : out std_logic);
31 Data : out std_logic);
15
32
16 end Serialize;
33 end Serialize;
17
34
18
35
19 architecture ar_Serialize of Serialize is
36 architecture ar_Serialize of Serialize is
20
37
21 type etat is (attente,serialize);
38 type etat is (attente,serialize);
22 signal ect : etat;
39 signal ect : etat;
23
40
24 signal vector_int : std_logic_vector(16 downto 0);
41 signal vector_int : std_logic_vector(16 downto 0);
25 signal vectin_reg : std_logic_vector(15 downto 0);
42 signal vectin_reg : std_logic_vector(15 downto 0);
26 signal load : std_logic;
43 signal load : std_logic;
27 signal N : integer range 0 to 16;
44 signal N : integer range 0 to 16;
28 signal CPT_ended : std_logic:='0';
45 signal CPT_ended : std_logic:='0';
29
46
30 begin
47 begin
31 process(clk,raz)
48 process(clk,raz)
32 begin
49 begin
33 if(raz='0')then
50 if(raz='0')then
34 ect <= attente;
51 ect <= attente;
35 vectin_reg <= (others=> '0');
52 vectin_reg <= (others=> '0');
36 load <= '0';
53 load <= '0';
37 sended <= '1';
54 sended <= '1';
38
55
39 elsif(clk'event and clk='1')then
56 elsif(clk'event and clk='1')then
40 vectin_reg <= vectin;
57 vectin_reg <= vectin;
41
58
42 case ect is
59 case ect is
43 when attente =>
60 when attente =>
44 if (send='1') then
61 if (send='1') then
45 sended <= '0';
62 sended <= '0';
46 load <= '1';
63 load <= '1';
47 ect <= serialize;
64 ect <= serialize;
48 else
65 else
49 ect <= attente;
66 ect <= attente;
50 end if;
67 end if;
51
68
52 when serialize =>
69 when serialize =>
53 load <= '0';
70 load <= '0';
54 if(CPT_ended='1')then
71 if(CPT_ended='1')then
55 ect <= attente;
72 ect <= attente;
56 sended <= '1';
73 sended <= '1';
57 end if;
74 end if;
58
75
59 end case;
76 end case;
60 end if;
77 end if;
61 end process;
78 end process;
62
79
63 process(sclk,load,raz)
80 process(sclk,load,raz)
64 begin
81 begin
65 if (raz='0')then
82 if (raz='0')then
66 vector_int <= (others=> '0');
83 vector_int <= (others=> '0');
67 N <= 16;
84 N <= 16;
68 elsif(load='1')then
85 elsif(load='1')then
69 vector_int <= vectin & '0';
86 vector_int <= vectin & '0';
70 N <= 0;
87 N <= 0;
71 elsif(sclk'event and sclk='0')then
88 elsif(sclk'event and sclk='0')then
72 if (CPT_ended='0') then
89 if (CPT_ended='0') then
73 vector_int <= vector_int(15 downto 0) & '0';
90 vector_int <= vector_int(15 downto 0) & '0';
74 N <= N+1;
91 N <= N+1;
75 end if;
92 end if;
76 end if;
93 end if;
77 end process;
94 end process;
78
95
79 CPT_ended <= '1' when N = 16 else '0';
96 CPT_ended <= '1' when N = 16 else '0';
80
97
81 with ect select
98 with ect select
82 Data <= vector_int(16) when serialize,
99 Data <= vector_int(16) when serialize,
83 '0' when others;
100 '0' when others;
84
101
85 end ar_Serialize;
102 end ar_Serialize;
86
103
Show file before | Show file after | Hide comments
@@ -1,41 +1,58
1 -- clock.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.std_logic_1164.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.numeric_std.all;
4 --
5
5 -- This program is free software; you can redistribute it and/or modify
6
6 -- it under the terms of the GNU General Public License as published by
7 entity Clock_Serie is
7 -- the Free Software Foundation; either version 3 of the License, or
8
8 -- (at your option) any later version.
9 generic(N :integer := 695);
9 --
10
10 -- This program is distributed in the hope that it will be useful,
11 port(
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 clk, raz : in std_logic ;
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 clock : out std_logic);
13 -- GNU General Public License for more details.
14
14 --
15 end Clock_Serie;
15 -- You should have received a copy of the GNU General Public License
16
16 -- along with this program; if not, write to the Free Software
17
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 architecture ar_Clock_Serie of Clock_Serie is
18 -------------------------------------------------------------------------------
19
19 library IEEE;
20 signal clockint : std_logic;
20 use IEEE.std_logic_1164.all;
21 signal countint : integer range 0 to N/2-1;
21 use IEEE.numeric_std.all;
22
22
23 begin
23
24 process (clk,raz)
24 entity Clock_Serie is
25 begin
25
26 if(raz = '0') then
26 generic(N :integer := 695);
27 countint <= 0;
27
28 clockint <= '0';
28 port(
29 elsif (clk' event and clk='1') then
29 clk, raz : in std_logic ;
30 if (countint = N/2-1) then
30 clock : out std_logic);
31 countint <= 0;
31
32 clockint <= not clockint;
32 end Clock_Serie;
33 else
33
34 countint <= countint+1;
34
35 end if;
35 architecture ar_Clock_Serie of Clock_Serie is
36 end if;
36
37 end process;
37 signal clockint : std_logic;
38
38 signal countint : integer range 0 to N/2-1;
39 clock <= clockint;
39
40
40 begin
41 end ar_Clock_Serie; No newline at end of file
41 process (clk,raz)
42 begin
43 if(raz = '0') then
44 countint <= 0;
45 clockint <= '0';
46 elsif (clk' event and clk='1') then
47 if (countint = N/2-1) then
48 countint <= 0;
49 clockint <= not clockint;
50 else
51 countint <= countint+1;
52 end if;
53 end if;
54 end process;
55
56 clock <= clockint;
57
58 end ar_Clock_Serie;
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@@ -1,52 +1,51
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 library grlib;
21 library grlib;
23 use grlib.amba.all;
22 use grlib.amba.all;
24 -- pragma translate_off
23 -- pragma translate_off
25 use std.textio.all;
24 use std.textio.all;
26 -- pragma translate_on
25 -- pragma translate_on
27 library lpp;
26 library lpp;
28 use lpp.lpp_amba.all;
27 use lpp.lpp_amba.all;
29
28
30
29
31 package lpp_CNA_amba is
30 package lpp_CNA_amba is
32
31
33
32
34 component APB_CNA is
33 component APB_CNA is
35 generic (
34 generic (
36 pindex : integer := 0;
35 pindex : integer := 0;
37 paddr : integer := 0;
36 paddr : integer := 0;
38 pmask : integer := 16#fff#;
37 pmask : integer := 16#fff#;
39 pirq : integer := 0;
38 pirq : integer := 0;
40 abits : integer := 8);
39 abits : integer := 8);
41 port (
40 port (
42 clk : in std_logic;
41 clk : in std_logic;
43 rst : in std_logic;
42 rst : in std_logic;
44 apbi : in apb_slv_in_type;
43 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
44 apbo : out apb_slv_out_type;
46 SYNC : out std_logic;
45 SYNC : out std_logic;
47 SCLK : out std_logic;
46 SCLK : out std_logic;
48 DATA : out std_logic
47 DATA : out std_logic
49 );
48 );
50 end component;
49 end component;
51
50
52 end;
51 end;
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@@ -1,106 +1,104
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- APB_MULTI_DIODE.vhd
19 library ieee;
20
20 use ieee.std_logic_1164.all;
21 library ieee;
21 --use ieee.numeric_std.all;
22 use ieee.std_logic_1164.all;
22 library grlib;
23 --use ieee.numeric_std.all;
23 use grlib.amba.all;
24 library grlib;
24 use grlib.stdlib.all;
25 use grlib.amba.all;
25 use grlib.devices.all;
26 use grlib.stdlib.all;
26 library lpp;
27 use grlib.devices.all;
27 use lpp.lpp_amba.all;
28 library lpp;
28
29 use lpp.lpp_amba.all;
29
30
30 entity APB_MULTI_DIODE is
31
31 generic (
32 entity APB_MULTI_DIODE is
32 pindex : integer := 0;
33 generic (
33 paddr : integer := 0;
34 pindex : integer := 0;
34 pmask : integer := 16#fff#;
35 paddr : integer := 0;
35 pirq : integer := 0;
36 pmask : integer := 16#fff#;
36 abits : integer := 8);
37 pirq : integer := 0;
37 port (
38 abits : integer := 8);
38 rst : in std_ulogic;
39 port (
39 clk : in std_ulogic;
40 rst : in std_ulogic;
40 apbi : in apb_slv_in_type;
41 clk : in std_ulogic;
41 apbo : out apb_slv_out_type;
42 apbi : in apb_slv_in_type;
42 LED : out std_logic_vector(2 downto 0)
43 apbo : out apb_slv_out_type;
43 );
44 LED : out std_logic_vector(2 downto 0)
44 end;
45 );
45
46 end;
46
47
47 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
48
48
49 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
49 constant REVISION : integer := 1;
50
50
51 constant REVISION : integer := 1;
51 constant pconfig : apb_config_type := (
52
52 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
53 constant pconfig : apb_config_type := (
53 1 => apb_iobar(paddr, pmask));
54 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
54
55 1 => apb_iobar(paddr, pmask));
55
56
56
57
57 type LEDregs is record
58
58 DATAin : std_logic_vector(31 downto 0);
59 type LEDregs is record
59 DATAout : std_logic_vector(31 downto 0);
60 DATAin : std_logic_vector(31 downto 0);
60 end record;
61 DATAout : std_logic_vector(31 downto 0);
61
62 end record;
62 signal r : LEDregs;
63
63
64 signal r : LEDregs;
64
65
65 begin
66
66
67 begin
67 r.DATAout <= r.DATAin xor X"FFFFFFFF";
68
68
69 r.DATAout <= r.DATAin xor X"FFFFFFFF";
69 process(rst,clk)
70
70 begin
71 process(rst,clk)
71 if rst = '0' then
72 begin
72 LED <= "000";
73 if rst = '0' then
73 r.DATAin <= (others => '0');
74 LED <= "000";
74 apbo.prdata <= (others => '0');
75 r.DATAin <= (others => '0');
75 elsif clk'event and clk = '1' then
76 apbo.prdata <= (others => '0');
76
77 elsif clk'event and clk = '1' then
77 LED <= r.DATAin(2 downto 0);
78
78
79 LED <= r.DATAin(2 downto 0);
79 --APB Write OP
80
80 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
81 --APB Write OP
81 case apbi.paddr(abits-1 downto 2) is
82 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
82 when "000000" =>
83 case apbi.paddr(abits-1 downto 2) is
83 r.DATAin <= apbi.pwdata;
84 when "000000" =>
84 when others =>
85 r.DATAin <= apbi.pwdata;
85 null;
86 when others =>
86 end case;
87 null;
87 end if;
88 end case;
88
89 end if;
89 --APB READ OP
90
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
91 --APB READ OP
91 case apbi.paddr(abits-1 downto 2) is
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
92 when "000000" =>
93 case apbi.paddr(abits-1 downto 2) is
93 apbo.prdata <= r.DATAin;
94 when "000000" =>
94 when others =>
95 apbo.prdata <= r.DATAin;
95 apbo.prdata <= r.DATAout;
96 when others =>
96 end case;
97 apbo.prdata <= r.DATAout;
97 end if;
98 end case;
98
99 end if;
99 end if;
100
100 apbo.pconfig <= pconfig;
101 end if;
101 end process;
102 apbo.pconfig <= pconfig;
102
103 end process;
103
104
104 end ar_APB_MULTI_DIODE;
105
106 end ar_APB_MULTI_DIODE; No newline at end of file
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@@ -1,129 +1,127
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- APB_SIMPLE_DIODE.vhd
19 library ieee;
20
20 use ieee.std_logic_1164.all;
21 library ieee;
21 --use ieee.numeric_std.all;
22 use ieee.std_logic_1164.all;
22 library grlib;
23 --use ieee.numeric_std.all;
23 use grlib.amba.all;
24 library grlib;
24 use grlib.stdlib.all;
25 use grlib.amba.all;
25 use grlib.devices.all;
26 use grlib.stdlib.all;
26 library lpp;
27 use grlib.devices.all;
27 use lpp.lpp_amba.all;
28 library lpp;
28
29 use lpp.lpp_amba.all;
29
30
30 entity APB_SIMPLE_DIODE is
31
31 generic (
32 entity APB_SIMPLE_DIODE is
32 pindex : integer := 0;
33 generic (
33 paddr : integer := 0;
34 pindex : integer := 0;
34 pmask : integer := 16#fff#;
35 paddr : integer := 0;
35 pirq : integer := 0;
36 pmask : integer := 16#fff#;
36 abits : integer := 8);
37 pirq : integer := 0;
37 port (
38 abits : integer := 8);
38 rst : in std_ulogic;
39 port (
39 clk : in std_ulogic;
40 rst : in std_ulogic;
40 apbi : in apb_slv_in_type;
41 clk : in std_ulogic;
41 apbo : out apb_slv_out_type;
42 apbi : in apb_slv_in_type;
42 LED : out std_ulogic
43 apbo : out apb_slv_out_type;
43 );
44 LED : out std_ulogic
44 end;
45 );
45
46 end;
46
47
47 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
48
48
49 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
49 constant REVISION : integer := 1;
50
50
51 constant REVISION : integer := 1;
51 constant pconfig : apb_config_type := (
52
52 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
53 constant pconfig : apb_config_type := (
53 1 => apb_iobar(paddr, pmask));
54 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
54
55 1 => apb_iobar(paddr, pmask));
55
56
56
57
57 type LEDregs is record
58
58 DATAin : std_logic_vector(31 downto 0);
59 type LEDregs is record
59 DATAout : std_logic_vector(31 downto 0);
60 DATAin : std_logic_vector(31 downto 0);
60 end record;
61 DATAout : std_logic_vector(31 downto 0);
61
62 end record;
62 signal r : LEDregs;
63
63
64 signal r : LEDregs;
64
65
65 begin
66
66
67 begin
67 r.DATAout <= r.DATAin xor X"FFFFFFFF";
68
68
69 r.DATAout <= r.DATAin xor X"FFFFFFFF";
69 process(rst,clk)
70
70 begin
71 process(rst,clk)
71 if rst = '0' then
72 begin
72 LED <= '0';
73 if rst = '0' then
73 r.DATAin <= (others => '0');
74 LED <= '0';
74 apbo.prdata <= (others => '0');
75 r.DATAin <= (others => '0');
75 elsif clk'event and clk = '1' then
76 apbo.prdata <= (others => '0');
76
77 elsif clk'event and clk = '1' then
77 LED <= r.DATAin(0);
78
78
79 LED <= r.DATAin(0);
79 --APB Write OP
80
80 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
81 --APB Write OP
81 case apbi.paddr(abits-1 downto 2) is
82 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
82 when "000000" =>
83 case apbi.paddr(abits-1 downto 2) is
83 r.DATAin <= apbi.pwdata;
84 when "000000" =>
84 when others =>
85 r.DATAin <= apbi.pwdata;
85 null;
86 when others =>
86 end case;
87 null;
87 end if;
88 end case;
88
89 end if;
89 --APB READ OP
90
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
91 --APB READ OP
91 case apbi.paddr(abits-1 downto 2) is
92 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
92 when "000000" =>
93 case apbi.paddr(abits-1 downto 2) is
93 apbo.prdata <= r.DATAin;
94 when "000000" =>
94 when others =>
95 apbo.prdata <= r.DATAin;
95 apbo.prdata <= r.DATAout;
96 when others =>
96 end case;
97 apbo.prdata <= r.DATAout;
97 end if;
98 end case;
98
99 end if;
99 end if;
100
100 apbo.pconfig <= pconfig;
101 end if;
101 end process;
102 apbo.pconfig <= pconfig;
102
103 end process;
103
104
104
105
105 -- pragma translate_off
106
106 -- bootmsg : report_version
107 -- pragma translate_off
107 -- generic map ("apbuart" & tost(pindex) &
108 -- bootmsg : report_version
108 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
109 -- generic map ("apbuart" & tost(pindex) &
109 -- ", irq " & tost(pirq));
110 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
110 -- pragma translate_on
111 -- ", irq " & tost(pirq));
111
112 -- pragma translate_on
112
113
113
114
114 end ar_APB_SIMPLE_DIODE;
115
115
116 end ar_APB_SIMPLE_DIODE;
116
117
117
118
118
119
119
120
120
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@@ -1,78 +1,77
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
20 library ieee;
19 library ieee;
21 use ieee.std_logic_1164.all;
20 use ieee.std_logic_1164.all;
22 library grlib;
21 library grlib;
23 use grlib.amba.all;
22 use grlib.amba.all;
24 -- pragma translate_off
23 -- pragma translate_off
25 use std.textio.all;
24 use std.textio.all;
26 -- pragma translate_on
25 -- pragma translate_on
27
26
28
27
29
28
30 package lpp_amba is
29 package lpp_amba is
31
30
32 constant VENDOR_LPP : amba_vendor_type := 16#19#;
31 constant VENDOR_LPP : amba_vendor_type := 16#19#;
33
32
34 -- LPP device ids
33 -- LPP device ids
35
34
36 constant ROCKET_TM : amba_device_type := 16#001#;
35 constant ROCKET_TM : amba_device_type := 16#001#;
37 constant otherCore : amba_device_type := 16#002#;
36 constant otherCore : amba_device_type := 16#002#;
38 constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#;
37 constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#;
39 constant LPP_MULTI_DIODE : amba_device_type := 16#004#;
38 constant LPP_MULTI_DIODE : amba_device_type := 16#004#;
40 constant LPP_LCD_CTRLR : amba_device_type := 16#005#;
39 constant LPP_LCD_CTRLR : amba_device_type := 16#005#;
41 constant LPP_UART : amba_device_type := 16#006#;
40 constant LPP_UART : amba_device_type := 16#006#;
42 constant LPP_CNA : amba_device_type := 16#007#;
41 constant LPP_CNA : amba_device_type := 16#007#;
43
42
44
43
45 component APB_SIMPLE_DIODE is
44 component APB_SIMPLE_DIODE is
46 generic (
45 generic (
47 pindex : integer := 0;
46 pindex : integer := 0;
48 paddr : integer := 0;
47 paddr : integer := 0;
49 pmask : integer := 16#fff#;
48 pmask : integer := 16#fff#;
50 pirq : integer := 0;
49 pirq : integer := 0;
51 abits : integer := 8);
50 abits : integer := 8);
52 port (
51 port (
53 rst : in std_ulogic;
52 rst : in std_ulogic;
54 clk : in std_ulogic;
53 clk : in std_ulogic;
55 apbi : in apb_slv_in_type;
54 apbi : in apb_slv_in_type;
56 apbo : out apb_slv_out_type;
55 apbo : out apb_slv_out_type;
57 LED : out std_ulogic
56 LED : out std_ulogic
58 );
57 );
59 end component;
58 end component;
60
59
61
60
62 component APB_MULTI_DIODE is
61 component APB_MULTI_DIODE is
63 generic (
62 generic (
64 pindex : integer := 0;
63 pindex : integer := 0;
65 paddr : integer := 0;
64 paddr : integer := 0;
66 pmask : integer := 16#fff#;
65 pmask : integer := 16#fff#;
67 pirq : integer := 0;
66 pirq : integer := 0;
68 abits : integer := 8);
67 abits : integer := 8);
69 port (
68 port (
70 rst : in std_ulogic;
69 rst : in std_ulogic;
71 clk : in std_ulogic;
70 clk : in std_ulogic;
72 apbi : in apb_slv_in_type;
71 apbi : in apb_slv_in_type;
73 apbo : out apb_slv_out_type;
72 apbo : out apb_slv_out_type;
74 LED : out std_logic_vector(2 downto 0)
73 LED : out std_logic_vector(2 downto 0)
75 );
74 );
76 end component;
75 end component;
77
76
78 end;
77 end;
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@@ -1,128 +1,126
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- APB_UART.vhd
19 library ieee;
20
20 use ieee.std_logic_1164.all;
21 library ieee;
21 library grlib;
22 use ieee.std_logic_1164.all;
22 use grlib.amba.all;
23 library grlib;
23 use grlib.stdlib.all;
24 use grlib.amba.all;
24 use grlib.devices.all;
25 use grlib.stdlib.all;
25 library lpp;
26 use grlib.devices.all;
26 use lpp.lpp_amba.all;
27 library lpp;
27 use lpp.lpp_uart.all;
28 use lpp.lpp_amba.all;
28
29 use lpp.lpp_uart.all;
29 entity APB_UART is
30
30 generic (
31 entity APB_UART is
31 pindex : integer := 0;
32 generic (
32 paddr : integer := 0;
33 pindex : integer := 0;
33 pmask : integer := 16#fff#;
34 paddr : integer := 0;
34 pirq : integer := 0;
35 pmask : integer := 16#fff#;
35 abits : integer := 8;
36 pirq : integer := 0;
36 Data_sz : integer := 8);
37 abits : integer := 8;
37 port (
38 Data_sz : integer := 8);
38 clk : in std_logic;
39 port (
39 rst : in std_logic;
40 clk : in std_logic;
40 apbi : in apb_slv_in_type;
41 rst : in std_logic;
41 apbo : out apb_slv_out_type;
42 apbi : in apb_slv_in_type;
42 TXD : out std_logic;
43 apbo : out apb_slv_out_type;
43 RXD : in std_logic
44 TXD : out std_logic;
44 );
45 RXD : in std_logic
45 end APB_UART;
46 );
46
47 end APB_UART;
47
48
48 architecture ar_APB_UART of APB_UART is
49
49
50 architecture ar_APB_UART of APB_UART is
50 constant REVISION : integer := 1;
51
51
52 constant REVISION : integer := 1;
52 constant pconfig : apb_config_type := (
53
53 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
54 constant pconfig : apb_config_type := (
54 1 => apb_iobar(paddr, pmask));
55 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
55
56 1 => apb_iobar(paddr, pmask));
56 signal NwData : std_logic;
57
57 signal ACK : std_logic;
58 signal NwData : std_logic;
58 signal Capture : std_logic;
59 signal ACK : std_logic;
59 signal Send : std_logic;
60 signal Capture : std_logic;
60 signal Sended : std_logic;
61 signal Send : std_logic;
61
62 signal Sended : std_logic;
62 type UART_ctrlr_Reg is record
63
63 UART_Cfg : std_logic_vector(4 downto 0);
64 type UART_ctrlr_Reg is record
64 UART_Wdata : std_logic_vector(7 downto 0);
65 UART_Cfg : std_logic_vector(4 downto 0);
65 UART_Rdata : std_logic_vector(7 downto 0);
66 UART_Wdata : std_logic_vector(7 downto 0);
66 UART_BTrig : std_logic_vector(11 downto 0);
67 UART_Rdata : std_logic_vector(7 downto 0);
67 end record;
68 UART_BTrig : std_logic_vector(11 downto 0);
68
69 end record;
69 signal Rec : UART_ctrlr_Reg;
70
70
71 signal Rec : UART_ctrlr_Reg;
71 begin
72
72
73 begin
73 Capture <= Rec.UART_Cfg(0);
74
74 ACK <= Rec.UART_Cfg(1);
75 Capture <= Rec.UART_Cfg(0);
75 Send <= Rec.UART_Cfg(2);
76 ACK <= Rec.UART_Cfg(1);
76 Rec.UART_Cfg(3) <= Sended;
77 Send <= Rec.UART_Cfg(2);
77 Rec.UART_Cfg(4) <= NwData;
78 Rec.UART_Cfg(3) <= Sended;
78
79 Rec.UART_Cfg(4) <= NwData;
79
80
80 COM0 : entity work.UART
81
81 generic map (Data_sz)
82 COM0 : entity work.UART
82 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
83 generic map (Data_sz)
83
84 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
84
85
85 process(rst,clk)
86
86 begin
87 process(rst,clk)
87 if(rst='0')then
88 begin
88 Rec.UART_Wdata <= (others => '0');
89 if(rst='0')then
89 apbo.prdata <= (others => '0');
90 Rec.UART_Wdata <= (others => '0');
90
91 apbo.prdata <= (others => '0');
91 elsif(clk'event and clk='1')then
92
92
93 elsif(clk'event and clk='1')then
93
94
94 --APB Write OP
95
95 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 --APB Write OP
96 case apbi.paddr(abits-1 downto 2) is
97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 when "000000" =>
98 case apbi.paddr(abits-1 downto 2) is
98 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
99 when "000000" =>
99 when "000001" =>
100 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
100 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
101 when "000001" =>
101 when others =>
102 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
102 null;
103 when others =>
103 end case;
104 null;
104 end if;
105 end case;
105
106 end if;
106 --APB READ OP
107
107 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
108 --APB READ OP
108 case apbi.paddr(abits-1 downto 2) is
109 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
109 when "000000" =>
110 case apbi.paddr(abits-1 downto 2) is
110 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
111 when "000000" =>
111 apbo.prdata(26 downto 12) <= (others => '0');
112 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
112 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
113 apbo.prdata(26 downto 12) <= (others => '0');
113 when "000001" =>
114 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
114 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
115 when "000001" =>
115 when "000010" =>
116 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
116 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
117 when "000010" =>
117 when others =>
118 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
118 apbo.prdata <= (others => '0');
119 when others =>
119 end case;
120 apbo.prdata <= (others => '0');
120 end if;
121 end case;
121
122 end if;
122 end if;
123
123 apbo.pconfig <= pconfig;
124 end if;
124 end process;
125 apbo.pconfig <= pconfig;
125
126 end process;
126 end ar_APB_UART;
127
128 end ar_APB_UART; No newline at end of file
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@@ -1,82 +1,99
1 -- BaudGen.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.numeric_std.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.std_logic_1164.all;
4 --
5
5 -- This program is free software; you can redistribute it and/or modify
6 --! Generateur de Bauds
6 -- it under the terms of the GNU General Public License as published by
7
7 -- the Free Software Foundation; either version 3 of the License, or
8 entity BaudGen is
8 -- (at your option) any later version.
9
9 --
10 port(
10 -- This program is distributed in the hope that it will be useful,
11 clk : in std_logic;
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 reset : in std_logic;
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 Capture : in std_logic;
13 -- GNU General Public License for more details.
14 Bclk : out std_logic;
14 --
15 RXD : in std_logic;
15 -- You should have received a copy of the GNU General Public License
16 BTrigger : out std_logic_vector(11 downto 0)
16 -- along with this program; if not, write to the Free Software
17 );
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 end BaudGen;
18 -------------------------------------------------------------------------------
19
19 library IEEE;
20
20 use IEEE.numeric_std.all;
21 architecture ar_BaudGen of BaudGen is
21 use IEEE.std_logic_1164.all;
22 signal cpt : std_logic_vector(11 downto 0) := (others => '0');
22
23 signal errorFlag : std_logic;
23 --! Generateur de Bauds
24 signal triger : std_logic_vector(11 downto 0) := (others => '0');
24
25 signal RX_reg : std_logic:='1';
25 entity BaudGen is
26
26
27 begin
27 port(
28
28 clk : in std_logic;
29
29 reset : in std_logic;
30 BTrigger <= triger;
30 Capture : in std_logic;
31
31 Bclk : out std_logic;
32
32 RXD : in std_logic;
33 BaudGeneration:
33 BTrigger : out std_logic_vector(11 downto 0)
34 process(clk,reset)
34 );
35 begin
35 end BaudGen;
36 if reset = '0' then
36
37 cpt <= (others => '0');
37
38 triger <= (others => '1');
38 architecture ar_BaudGen of BaudGen is
39 errorFlag <= '0';
39 signal cpt : std_logic_vector(11 downto 0) := (others => '0');
40 elsif clk'event and clk = '1'then
40 signal errorFlag : std_logic;
41 RX_reg <= RXD;
41 signal triger : std_logic_vector(11 downto 0) := (others => '0');
42 if capture = '1' then
42 signal RX_reg : std_logic:='1';
43 cpt <= (others => '0');
43
44 triger <= (others => '1');
44 begin
45 errorFlag <= '0';
45
46 else
46
47 if RX_reg /= RXD then
47 BTrigger <= triger;
48 cpt <= (others => '0');
48
49 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
49
50 errorFlag <= '1';
50 BaudGeneration:
51 elsif errorFlag = '1' then
51 process(clk,reset)
52 triger <= cpt;
52 begin
53 errorFlag <= '0';
53 if reset = '0' then
54 else
54 cpt <= (others => '0');
55 errorFlag <= '1';
55 triger <= (others => '1');
56 end if;
56 errorFlag <= '0';
57 else
57 elsif clk'event and clk = '1'then
58 if cpt = triger then
58 RX_reg <= RXD;
59 cpt <= (others => '0');
59 if capture = '1' then
60 errorFlag <= '0';
60 cpt <= (others => '0');
61 else
61 triger <= (others => '1');
62 cpt <= std_logic_vector(unsigned(cpt) + 1);
62 errorFlag <= '0';
63 end if;
63 else
64 end if;
64 if RX_reg /= RXD then
65 end if;
65 cpt <= (others => '0');
66 end if;
66 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
67 end process;
67 errorFlag <= '1';
68
68 elsif errorFlag = '1' then
69
69 triger <= cpt;
70 process(clk)
70 errorFlag <= '0';
71 begin
71 else
72 if clk'event and clk = '1' then
72 errorFlag <= '1';
73 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
73 end if;
74 Bclk <= '0';
74 else
75 elsif cpt = '0' & triger(11 downto 1) then
75 if cpt = triger then
76 Bclk <= '1';
76 cpt <= (others => '0');
77 end if;
77 errorFlag <= '0';
78 end if;
78 else
79 end process;
79 cpt <= std_logic_vector(unsigned(cpt) + 1);
80
80 end if;
81
81 end if;
82 end ar_BaudGen; No newline at end of file
82 end if;
83 end if;
84 end process;
85
86
87 process(clk)
88 begin
89 if clk'event and clk = '1' then
90 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then
91 Bclk <= '0';
92 elsif cpt = '0' & triger(11 downto 1) then
93 Bclk <= '1';
94 end if;
95 end if;
96 end process;
97
98
99 end ar_BaudGen;
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@@ -1,94 +1,111
1 -- Shift_REG.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.numeric_std.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.std_logic_1164.all;
4 --
5
5 -- This program is free software; you can redistribute it and/or modify
6 --! Gestion Reception/Transmission
6 -- it under the terms of the GNU General Public License as published by
7
7 -- the Free Software Foundation; either version 3 of the License, or
8 entity Shift_REG is
8 -- (at your option) any later version.
9 generic(Data_sz : integer := 10);
9 --
10 port(
10 -- This program is distributed in the hope that it will be useful,
11 clk : in std_logic;
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 Sclk : in std_logic;
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 reset : in std_logic;
13 -- GNU General Public License for more details.
14 SIN : in std_logic;
14 --
15 SOUT : out std_logic;
15 -- You should have received a copy of the GNU General Public License
16 Serialize : in std_logic;
16 -- along with this program; if not, write to the Free Software
17 Serialized : out std_logic;
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 D : in std_logic_vector(Data_sz-1 downto 0);
18 -------------------------------------------------------------------------------
19 Q : out std_logic_vector(Data_sz-1 downto 0)
19 library IEEE;
20
20 use IEEE.numeric_std.all;
21 );
21 use IEEE.std_logic_1164.all;
22 end entity;
22
23
23 --! Gestion Reception/Transmission
24
24
25 architecture ar_Shift_REG of Shift_REG is
25 entity Shift_REG is
26
26 generic(Data_sz : integer := 10);
27 signal REG : std_logic_vector(Data_sz-1 downto 0);
27 port(
28 signal Serialized_int : std_logic;
28 clk : in std_logic;
29 signal Serialize_reg : std_logic;
29 Sclk : in std_logic;
30 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
30 reset : in std_logic;
31 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
31 SIN : in std_logic;
32 signal CptBits_flag : std_logic;
32 SOUT : out std_logic;
33 signal CptBits_flag_reg : std_logic;
33 Serialize : in std_logic;
34
34 Serialized : out std_logic;
35 begin
35 D : in std_logic_vector(Data_sz-1 downto 0);
36
36 Q : out std_logic_vector(Data_sz-1 downto 0)
37 Serialized <= Serialized_int;
37
38 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
38 );
39
39 end entity;
40 process(reset,clk)
40
41 begin
41
42 if reset = '0' then
42 architecture ar_Shift_REG of Shift_REG is
43 Serialized_int <= '1';
43
44 CptBits_flag_reg <= '0';
44 signal REG : std_logic_vector(Data_sz-1 downto 0);
45 Q <= (others => '0');
45 signal Serialized_int : std_logic;
46 elsif clk'event and clk = '1' then
46 signal Serialize_reg : std_logic;
47 CptBits_flag_reg <= CptBits_flag;
47 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
48
48 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
49 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
49 signal CptBits_flag : std_logic;
50 Serialized_int <= '1';
50 signal CptBits_flag_reg : std_logic;
51 Q <= REG;
51
52 elsif Serialize = '1' then
52 begin
53 Serialized_int <= '0';
53
54 end if;
54 Serialized <= Serialized_int;
55 end if;
55 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
56 end process;
56
57
57 process(reset,clk)
58
58 begin
59 process(reset,Sclk)
59 if reset = '0' then
60 begin
60 Serialized_int <= '1';
61 if reset = '0' then
61 CptBits_flag_reg <= '0';
62 CptBits <= (others => '0');
62 Q <= (others => '0');
63 REG <= (others => '0');
63 elsif clk'event and clk = '1' then
64 SOUT <= '1';
64 CptBits_flag_reg <= CptBits_flag;
65 Serialize_reg <= '0';
65
66 elsif Sclk'event and Sclk = '1' then
66 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
67 Serialize_reg <= Serialized_int;
67 Serialized_int <= '1';
68 if (Serialized_int = '0' and Serialize_reg ='1') then
68 Q <= REG;
69 REG <= SIN & D(Data_sz-1 downto 1);
69 elsif Serialize = '1' then
70 SOUT <= D(0);
70 Serialized_int <= '0';
71 elsif CptBits_flag ='1' then
71 end if;
72 REG <= SIN & D(Data_sz-1 downto 1);
72 end if;
73 SOUT <= D(0);
73 end process;
74 elsif Serialized_int = '0' then
74
75 REG <= SIN & REG(Data_sz-1 downto 1);
75
76 SOUT <= REG(0);
76 process(reset,Sclk)
77 else
77 begin
78 SOUT <= '1';
78 if reset = '0' then
79 end if;
79 CptBits <= (others => '0');
80 if Serialized_int = '0' then
80 REG <= (others => '0');
81 if CptBits_flag = '1' then
81 SOUT <= '1';
82 CptBits <= (others => '0');
82 Serialize_reg <= '0';
83 else
83 elsif Sclk'event and Sclk = '1' then
84 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
84 Serialize_reg <= Serialized_int;
85 end if;
85 if (Serialized_int = '0' and Serialize_reg ='1') then
86
86 REG <= SIN & D(Data_sz-1 downto 1);
87 else
87 SOUT <= D(0);
88 CptBits <= (others => '0');
88 elsif CptBits_flag ='1' then
89 end if;
89 REG <= SIN & D(Data_sz-1 downto 1);
90
90 SOUT <= D(0);
91 end if;
91 elsif Serialized_int = '0' then
92 end process;
92 REG <= SIN & REG(Data_sz-1 downto 1);
93
93 SOUT <= REG(0);
94 end ar_Shift_REG; No newline at end of file
94 else
95 SOUT <= '1';
96 end if;
97 if Serialized_int = '0' then
98 if CptBits_flag = '1' then
99 CptBits <= (others => '0');
100 else
101 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
102 end if;
103
104 else
105 CptBits <= (others => '0');
106 end if;
107
108 end if;
109 end process;
110
111 end ar_Shift_REG;
Show file before | Show file after | Hide comments
@@ -1,81 +1,98
1 -- UART.vhd
1 ------------------------------------------------------------------------------
2 library IEEE;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 use IEEE.numeric_std.all;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use IEEE.std_logic_1164.all;
4 --
5 library lpp;
5 -- This program is free software; you can redistribute it and/or modify
6 use lpp.lpp_uart.all;
6 -- it under the terms of the GNU General Public License as published by
7
7 -- the Free Software Foundation; either version 3 of the License, or
8 --! Programme qui va gerer toute la communication entre le PC et le FPGA
8 -- (at your option) any later version.
9
9 --
10 entity UART is
10 -- This program is distributed in the hope that it will be useful,
11 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 port(
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 clk : in std_logic; --! Horloge a 25Mhz du systeme
13 -- GNU General Public License for more details.
14 reset : in std_logic; --! Reset du systeme
14 --
15 TXD : out std_logic; --! Transmission, cote PC
15 -- You should have received a copy of the GNU General Public License
16 RXD : in std_logic; --! Reception, cote PC
16 -- along with this program; if not, write to the Free Software
17 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
18 -------------------------------------------------------------------------------
19 ACK : in std_logic; --! Flag, Reponse au flag precedent
19 library IEEE;
20 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
20 use IEEE.numeric_std.all;
21 Sended : out std_logic; --! Flag, Envoi termine
21 use IEEE.std_logic_1164.all;
22 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
22 library lpp;
23 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
23 use lpp.lpp_uart.all;
24 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
24
25 );
25 --! Programme qui va gerer toute la communication entre le PC et le FPGA
26 end entity;
26
27
27 entity UART is
28
28 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
29 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
29 port(
30 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
30 clk : in std_logic; --! Horloge a 25Mhz du systeme
31 architecture ar_UART of UART is
31 reset : in std_logic; --! Reset du systeme
32 signal Bclk : std_logic;
32 TXD : out std_logic; --! Transmission, cote PC
33
33 RXD : in std_logic; --! Reception, cote PC
34 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
34 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
35 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
35 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
36
36 ACK : in std_logic; --! Flag, Reponse au flag precedent
37 signal TXD_Dummy : std_logic;
37 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
38 signal NwDat_int : std_logic;
38 Sended : out std_logic; --! Flag, Envoi termine
39 signal NwDat_int_reg : std_logic;
39 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
40 signal receive : std_logic;
40 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
41
41 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
42 begin
42 );
43
43 end entity;
44
44
45 RDATA <= RDATA_int(8 downto 1);
45
46 WDATA_int <= '1' & WDATA & '0';
46 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
47
47 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
48 BaudGenerator : BaudGen
48 architecture ar_UART of UART is
49 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
49 signal Bclk : std_logic;
50
50
51
51 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
52 RX_REG : Shift_REG
52 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
53 generic map(Data_sz+2)
53
54 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,(others => '0'),RDATA_int);
54 signal TXD_Dummy : std_logic;
55
55 signal NwDat_int : std_logic;
56 TX_REG : Shift_REG
56 signal NwDat_int_reg : std_logic;
57 generic map(Data_sz+2)
57 signal receive : std_logic;
58 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
58
59
59 begin
60
60
61
61
62 process(clk,reset)
62 RDATA <= RDATA_int(8 downto 1);
63 begin
63 WDATA_int <= '1' & WDATA & '0';
64 if reset = '0' then
64
65 NwDat <= '0';
65 BaudGenerator : BaudGen
66 elsif clk'event and clk = '1' then
66 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
67 NwDat_int_reg <= NwDat_int;
67
68 if RXD = '1' and NwDat_int = '1' then
68
69 receive <= '0';
69 RX_REG : Shift_REG
70 elsif RXD = '0' then
70 generic map(Data_sz+2)
71 receive <= '1';
71 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,(others => '0'),RDATA_int);
72 end if;
72
73 if NwDat_int_reg = '0' and NwDat_int = '1' then
73 TX_REG : Shift_REG
74 NwDat <= '1';
74 generic map(Data_sz+2)
75 elsif ack = '1' then
75 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
76 NwDat <= '0';
76
77 end if;
77
78 end if;
78
79 end process;
79 process(clk,reset)
80
80 begin
81 end ar_UART; No newline at end of file
81 if reset = '0' then
82 NwDat <= '0';
83 elsif clk'event and clk = '1' then
84 NwDat_int_reg <= NwDat_int;
85 if RXD = '1' and NwDat_int = '1' then
86 receive <= '0';
87 elsif RXD = '0' then
88 receive <= '1';
89 end if;
90 if NwDat_int_reg = '0' and NwDat_int = '1' then
91 NwDat <= '1';
92 elsif ack = '1' then
93 NwDat <= '0';
94 end if;
95 end if;
96 end process;
97
98 end ar_UART;
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@@ -1,79 +1,97
1 library ieee;
1 ------------------------------------------------------------------------------
2 use ieee.std_logic_1164.all;
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 library grlib;
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 use grlib.amba.all;
4 --
5 -- pragma translate_off
5 -- This program is free software; you can redistribute it and/or modify
6 use std.textio.all;
6 -- it under the terms of the GNU General Public License as published by
7 -- pragma translate_on
7 -- the Free Software Foundation; either version 3 of the License, or
8 library lpp;
8 -- (at your option) any later version.
9 use lpp.lpp_amba.all;
9 --
10
10 -- This program is distributed in the hope that it will be useful,
11 package lpp_uart is
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 component UART is
13 -- GNU General Public License for more details.
14 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
14 --
15 port(
15 -- You should have received a copy of the GNU General Public License
16 clk : in std_logic; --! Horloge a 25Mhz du systeme
16 -- along with this program; if not, write to the Free Software
17 reset : in std_logic; --! Reset du systeme
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 TXD : out std_logic; --! Transmission, cote PC
18 -------------------------------------------------------------------------------
19 RXD : in std_logic; --! Reception, cote PC
19 library ieee;
20 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
20 use ieee.std_logic_1164.all;
21 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
21 library grlib;
22 ACK : in std_logic; --! Flag, Reponse au flag precedent
22 use grlib.amba.all;
23 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
23 -- pragma translate_off
24 Sended : out std_logic; --! Flag, Envoi termine
24 use std.textio.all;
25 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
25 -- pragma translate_on
26 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
26 library lpp;
27 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
27 use lpp.lpp_amba.all;
28 );
28
29 end component;
29 package lpp_uart is
30
30
31
31 component UART is
32 component Shift_REG is
32 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
33 generic(Data_sz : integer := 10);
33 port(
34 port(
34 clk : in std_logic; --! Horloge a 25Mhz du systeme
35 clk : in std_logic;
35 reset : in std_logic; --! Reset du systeme
36 Sclk : in std_logic;
36 TXD : out std_logic; --! Transmission, cote PC
37 reset : in std_logic;
37 RXD : in std_logic; --! Reception, cote PC
38 SIN : in std_logic;
38 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
39 SOUT : out std_logic;
39 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
40 Serialize : in std_logic;
40 ACK : in std_logic; --! Flag, Reponse au flag precedent
41 Serialized : out std_logic;
41 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
42 D : in std_logic_vector(Data_sz-1 downto 0);
42 Sended : out std_logic; --! Flag, Envoi termine
43 Q : out std_logic_vector(Data_sz-1 downto 0)
43 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
44
44 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
45 );
45 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
46 end component;
46 );
47
47 end component;
48
48
49 component BaudGen is
49
50 port(
50 component Shift_REG is
51 clk : in std_logic;
51 generic(Data_sz : integer := 10);
52 reset : in std_logic;
52 port(
53 Capture : in std_logic;
53 clk : in std_logic;
54 Bclk : out std_logic;
54 Sclk : in std_logic;
55 RXD : in std_logic;
55 reset : in std_logic;
56 BTrigger : out std_logic_vector(11 downto 0)
56 SIN : in std_logic;
57 );
57 SOUT : out std_logic;
58 end component;
58 Serialize : in std_logic;
59
59 Serialized : out std_logic;
60 component APB_UART is
60 D : in std_logic_vector(Data_sz-1 downto 0);
61 generic (
61 Q : out std_logic_vector(Data_sz-1 downto 0)
62 pindex : integer := 0;
62
63 paddr : integer := 0;
63 );
64 pmask : integer := 16#fff#;
64 end component;
65 pirq : integer := 0;
65
66 abits : integer := 8;
66
67 Data_sz : integer := 8);
67 component BaudGen is
68 port (
68 port(
69 clk : in std_logic;
69 clk : in std_logic;
70 rst : in std_logic;
70 reset : in std_logic;
71 apbi : in apb_slv_in_type;
71 Capture : in std_logic;
72 apbo : out apb_slv_out_type;
72 Bclk : out std_logic;
73 TXD : out std_logic;
73 RXD : in std_logic;
74 RXD : in std_logic
74 BTrigger : out std_logic_vector(11 downto 0)
75 );
75 );
76 end component;
76 end component;
77
77
78
78 component APB_UART is
79 end lpp_uart; No newline at end of file
79 generic (
80 pindex : integer := 0;
81 paddr : integer := 0;
82 pmask : integer := 16#fff#;
83 pirq : integer := 0;
84 abits : integer := 8;
85 Data_sz : integer := 8);
86 port (
87 clk : in std_logic;
88 rst : in std_logic;
89 apbi : in apb_slv_in_type;
90 apbo : out apb_slv_out_type;
91 TXD : out std_logic;
92 RXD : in std_logic
93 );
94 end component;
95
96
97 end lpp_uart;
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@@ -1,674 +1,339
1 GNU GENERAL PUBLIC LICENSE
1 GNU GENERAL PUBLIC LICENSE
2 Version 3, 29 June 2007
2 Version 2, June 1991
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3
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71 TERMS AND CONDITIONS
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279 Corresponding Source along with the object code. If the place to
280 copy the object code is a network server, the Corresponding Source
281 may be on a different server (operated by you or a third party)
282 that supports equivalent copying facilities, provided you maintain
283 clear directions next to the object code saying where to find the
284 Corresponding Source. Regardless of what server hosts the
285 Corresponding Source, you remain obligated to ensure that it is
286 available for as long as needed to satisfy these requirements.
287
288 e) Convey the object code using peer-to-peer transmission, provided
289 you inform other peers where the object code and Corresponding
290 Source of the work are being offered to the general public at no
291 charge under subsection 6d.
292
128
293 A separable portion of the object code, whose source code is excluded
129 In addition, mere aggregation of another work not based on the Program
294 from the Corresponding Source as a System Library, need not be
130 with the Program (or with a work based on the Program) on a volume of
295 included in conveying the object code work.
131 a storage or distribution medium does not bring the other work under
132 the scope of this License.
296
133
297 A "User Product" is either (1) a "consumer product", which means any
134 3. You may copy and distribute the Program (or a work based on it,
298 tangible personal property which is normally used for personal, family,
135 under Section 2) in object code or executable form under the terms of
299 or household purposes, or (2) anything designed or sold for incorporation
136 Sections 1 and 2 above provided that you also do one of the following:
300 into a dwelling. In determining whether a product is a consumer product,
301 doubtful cases shall be resolved in favor of coverage. For a particular
302 product received by a particular user, "normally used" refers to a
303 typical or common use of that class of product, regardless of the status
304 of the particular user or of the way in which the particular user
305 actually uses, or expects or is expected to use, the product. A product
306 is a consumer product regardless of whether the product has substantial
307 commercial, industrial or non-consumer uses, unless such uses represent
308 the only significant mode of use of the product.
309
310 "Installation Information" for a User Product means any methods,
311 procedures, authorization keys, or other information required to install
312 and execute modified versions of a covered work in that User Product from
313 a modified version of its Corresponding Source. The information must
314 suffice to ensure that the continued functioning of the modified object
315 code is in no case prevented or interfered with solely because
316 modification has been made.
317
137
318 If you convey an object code work under this section in, or with, or
138 a) Accompany it with the complete corresponding machine-readable
319 specifically for use in, a User Product, and the conveying occurs as
139 source code, which must be distributed under the terms of Sections
320 part of a transaction in which the right of possession and use of the
140 1 and 2 above on a medium customarily used for software interchange; or,
321 User Product is transferred to the recipient in perpetuity or for a
322 fixed term (regardless of how the transaction is characterized), the
323 Corresponding Source conveyed under this section must be accompanied
324 by the Installation Information. But this requirement does not apply
325 if neither you nor any third party retains the ability to install
326 modified object code on the User Product (for example, the work has
327 been installed in ROM).
328
329 The requirement to provide Installation Information does not include a
330 requirement to continue to provide support service, warranty, or updates
331 for a work that has been modified or installed by the recipient, or for
332 the User Product in which it has been modified or installed. Access to a
333 network may be denied when the modification itself materially and
334 adversely affects the operation of the network or violates the rules and
335 protocols for communication across the network.
336
337 Corresponding Source conveyed, and Installation Information provided,
338 in accord with this section must be in a format that is publicly
339 documented (and with an implementation available to the public in
340 source code form), and must require no special password or key for
341 unpacking, reading or copying.
342
343 7. Additional Terms.
344
141
345 "Additional permissions" are terms that supplement the terms of this
142 b) Accompany it with a written offer, valid for at least three
346 License by making exceptions from one or more of its conditions.
143 years, to give any third party, for a charge no more than your
347 Additional permissions that are applicable to the entire Program shall
144 cost of physically performing source distribution, a complete
348 be treated as though they were included in this License, to the extent
145 machine-readable copy of the corresponding source code, to be
349 that they are valid under applicable law. If additional permissions
146 distributed under the terms of Sections 1 and 2 above on a medium
350 apply only to part of the Program, that part may be used separately
147 customarily used for software interchange; or,
351 under those permissions, but the entire Program remains governed by
352 this License without regard to the additional permissions.
353
354 When you convey a copy of a covered work, you may at your option
355 remove any additional permissions from that copy, or from any part of
356 it. (Additional permissions may be written to require their own
357 removal in certain cases when you modify the work.) You may place
358 additional permissions on material, added by you to a covered work,
359 for which you have or can give appropriate copyright permission.
360
148
361 Notwithstanding any other provision of this License, for material you
149 c) Accompany it with the information you received as to the offer
362 add to a covered work, you may (if authorized by the copyright holders of
150 to distribute corresponding source code. (This alternative is
363 that material) supplement the terms of this License with terms:
151 allowed only for noncommercial distribution and only if you
364
152 received the program in object code or executable form with such
365 a) Disclaiming warranty or limiting liability differently from the
153 an offer, in accord with Subsection b above.)
366 terms of sections 15 and 16 of this License; or
367
368 b) Requiring preservation of specified reasonable legal notices or
369 author attributions in that material or in the Appropriate Legal
370 Notices displayed by works containing it; or
371
372 c) Prohibiting misrepresentation of the origin of that material, or
373 requiring that modified versions of such material be marked in
374 reasonable ways as different from the original version; or
375
376 d) Limiting the use for publicity purposes of names of licensors or
377 authors of the material; or
378
154
379 e) Declining to grant rights under trademark law for use of some
155 The source code for a work means the preferred form of the work for
380 trade names, trademarks, or service marks; or
156 making modifications to it. For an executable work, complete source
381
157 code means all the source code for all modules it contains, plus any
382 f) Requiring indemnification of licensors and authors of that
158 associated interface definition files, plus the scripts used to
383 material by anyone who conveys the material (or modified versions of
159 control compilation and installation of the executable. However, as a
384 it) with contractual assumptions of liability to the recipient, for
160 special exception, the source code distributed need not include
385 any liability that these contractual assumptions directly impose on
161 anything that is normally distributed (in either source or binary
386 those licensors and authors.
162 form) with the major components (compiler, kernel, and so on) of the
387
163 operating system on which the executable runs, unless that component
388 All other non-permissive additional terms are considered "further
164 itself accompanies the executable.
389 restrictions" within the meaning of section 10. If the Program as you
390 received it, or any part of it, contains a notice stating that it is
391 governed by this License along with a term that is a further
392 restriction, you may remove that term. If a license document contains
393 a further restriction but permits relicensing or conveying under this
394 License, you may add to a covered work material governed by the terms
395 of that license document, provided that the further restriction does
396 not survive such relicensing or conveying.
397
398 If you add terms to a covered work in accord with this section, you
399 must place, in the relevant source files, a statement of the
400 additional terms that apply to those files, or a notice indicating
401 where to find the applicable terms.
402
165
403 Additional terms, permissive or non-permissive, may be stated in the
166 If distribution of executable or object code is made by offering
404 form of a separately written license, or stated as exceptions;
167 access to copy from a designated place, then offering equivalent
405 the above requirements apply either way.
168 access to copy the source code from the same place counts as
406
169 distribution of the source code, even though third parties are not
407 8. Termination.
170 compelled to copy the source along with the object code.
408
409 You may not propagate or modify a covered work except as expressly
410 provided under this License. Any attempt otherwise to propagate or
411 modify it is void, and will automatically terminate your rights under
412 this License (including any patent licenses granted under the third
413 paragraph of section 11).
414
415 However, if you cease all violation of this License, then your
416 license from a particular copyright holder is reinstated (a)
417 provisionally, unless and until the copyright holder explicitly and
418 finally terminates your license, and (b) permanently, if the copyright
419 holder fails to notify you of the violation by some reasonable means
420 prior to 60 days after the cessation.
421
422 Moreover, your license from a particular copyright holder is
423 reinstated permanently if the copyright holder notifies you of the
424 violation by some reasonable means, this is the first time you have
425 received notice of violation of this License (for any work) from that
426 copyright holder, and you cure the violation prior to 30 days after
427 your receipt of the notice.
428
171
429 Termination of your rights under this section does not terminate the
172 4. You may not copy, modify, sublicense, or distribute the Program
430 licenses of parties who have received copies or rights from you under
173 except as expressly provided under this License. Any attempt
431 this License. If your rights have been terminated and not permanently
174 otherwise to copy, modify, sublicense or distribute the Program is
432 reinstated, you do not qualify to receive new licenses for the same
175 void, and will automatically terminate your rights under this License.
433 material under section 10.
176 However, parties who have received copies, or rights, from you under
434
177 this License will not have their licenses terminated so long as such
435 9. Acceptance Not Required for Having Copies.
178 parties remain in full compliance.
436
437 You are not required to accept this License in order to receive or
438 run a copy of the Program. Ancillary propagation of a covered work
439 occurring solely as a consequence of using peer-to-peer transmission
440 to receive a copy likewise does not require acceptance. However,
441 nothing other than this License grants you permission to propagate or
442 modify any covered work. These actions infringe copyright if you do
443 not accept this License. Therefore, by modifying or propagating a
444 covered work, you indicate your acceptance of this License to do so.
445
446 10. Automatic Licensing of Downstream Recipients.
447
448 Each time you convey a covered work, the recipient automatically
449 receives a license from the original licensors, to run, modify and
450 propagate that work, subject to this License. You are not responsible
451 for enforcing compliance by third parties with this License.
452
179
453 An "entity transaction" is a transaction transferring control of an
180 5. You are not required to accept this License, since you have not
454 organization, or substantially all assets of one, or subdividing an
181 signed it. However, nothing else grants you permission to modify or
455 organization, or merging organizations. If propagation of a covered
182 distribute the Program or its derivative works. These actions are
456 work results from an entity transaction, each party to that
183 prohibited by law if you do not accept this License. Therefore, by
457 transaction who receives a copy of the work also receives whatever
184 modifying or distributing the Program (or any work based on the
458 licenses to the work the party's predecessor in interest had or could
185 Program), you indicate your acceptance of this License to do so, and
459 give under the previous paragraph, plus a right to possession of the
186 all its terms and conditions for copying, distributing or modifying
460 Corresponding Source of the work from the predecessor in interest, if
187 the Program or works based on it.
461 the predecessor has it or can get it with reasonable efforts.
462
188
463 You may not impose any further restrictions on the exercise of the
189 6. Each time you redistribute the Program (or any work based on the
464 rights granted or affirmed under this License. For example, you may
190 Program), the recipient automatically receives a license from the
465 not impose a license fee, royalty, or other charge for exercise of
191 original licensor to copy, distribute or modify the Program subject to
466 rights granted under this License, and you may not initiate litigation
192 these terms and conditions. You may not impose any further
467 (including a cross-claim or counterclaim in a lawsuit) alleging that
193 restrictions on the recipients' exercise of the rights granted herein.
468 any patent claim is infringed by making, using, selling, offering for
194 You are not responsible for enforcing compliance by third parties to
469 sale, or importing the Program or any portion of it.
470
471 11. Patents.
472
473 A "contributor" is a copyright holder who authorizes use under this
474 License of the Program or a work on which the Program is based. The
475 work thus licensed is called the contributor's "contributor version".
476
477 A contributor's "essential patent claims" are all patent claims
478 owned or controlled by the contributor, whether already acquired or
479 hereafter acquired, that would be infringed by some manner, permitted
480 by this License, of making, using, or selling its contributor version,
481 but do not include claims that would be infringed only as a
482 consequence of further modification of the contributor version. For
483 purposes of this definition, "control" includes the right to grant
484 patent sublicenses in a manner consistent with the requirements of
485 this License.
195 this License.
486
196
487 Each contributor grants you a non-exclusive, worldwide, royalty-free
197 7. If, as a consequence of a court judgment or allegation of patent
488 patent license under the contributor's essential patent claims, to
198 infringement or for any other reason (not limited to patent issues),
489 make, use, sell, offer for sale, import and otherwise run, modify and
199 conditions are imposed on you (whether by court order, agreement or
490 propagate the contents of its contributor version.
200 otherwise) that contradict the conditions of this License, they do not
491
201 excuse you from the conditions of this License. If you cannot
492 In the following three paragraphs, a "patent license" is any express
202 distribute so as to satisfy simultaneously your obligations under this
493 agreement or commitment, however denominated, not to enforce a patent
203 License and any other pertinent obligations, then as a consequence you
494 (such as an express permission to practice a patent or covenant not to
204 may not distribute the Program at all. For example, if a patent
495 sue for patent infringement). To "grant" such a patent license to a
205 license would not permit royalty-free redistribution of the Program by
496 party means to make such an agreement or commitment not to enforce a
206 all those who receive copies directly or indirectly through you, then
497 patent against the party.
207 the only way you could satisfy both it and this License would be to
208 refrain entirely from distribution of the Program.
498
209
499 If you convey a covered work, knowingly relying on a patent license,
210 If any portion of this section is held invalid or unenforceable under
500 and the Corresponding Source of the work is not available for anyone
211 any particular circumstance, the balance of the section is intended to
501 to copy, free of charge and under the terms of this License, through a
212 apply and the section as a whole is intended to apply in other
502 publicly available network server or other readily accessible means,
213 circumstances.
503 then you must either (1) cause the Corresponding Source to be so
504 available, or (2) arrange to deprive yourself of the benefit of the
505 patent license for this particular work, or (3) arrange, in a manner
506 consistent with the requirements of this License, to extend the patent
507 license to downstream recipients. "Knowingly relying" means you have
508 actual knowledge that, but for the patent license, your conveying the
509 covered work in a country, or your recipient's use of the covered work
510 in a country, would infringe one or more identifiable patents in that
511 country that you have reason to believe are valid.
512
513 If, pursuant to or in connection with a single transaction or
514 arrangement, you convey, or propagate by procuring conveyance of, a
515 covered work, and grant a patent license to some of the parties
516 receiving the covered work authorizing them to use, propagate, modify
517 or convey a specific copy of the covered work, then the patent license
518 you grant is automatically extended to all recipients of the covered
519 work and works based on it.
520
214
521 A patent license is "discriminatory" if it does not include within
215 It is not the purpose of this section to induce you to infringe any
522 the scope of its coverage, prohibits the exercise of, or is
216 patents or other property right claims or to contest validity of any
523 conditioned on the non-exercise of one or more of the rights that are
217 such claims; this section has the sole purpose of protecting the
524 specifically granted under this License. You may not convey a covered
218 integrity of the free software distribution system, which is
525 work if you are a party to an arrangement with a third party that is
219 implemented by public license practices. Many people have made
526 in the business of distributing software, under which you make payment
220 generous contributions to the wide range of software distributed
527 to the third party based on the extent of your activity of conveying
221 through that system in reliance on consistent application of that
528 the work, and under which the third party grants, to any of the
222 system; it is up to the author/donor to decide if he or she is willing
529 parties who would receive the covered work from you, a discriminatory
223 to distribute software through any other system and a licensee cannot
530 patent license (a) in connection with copies of the covered work
224 impose that choice.
531 conveyed by you (or copies made from those copies), or (b) primarily
532 for and in connection with specific products or compilations that
533 contain the covered work, unless you entered into that arrangement,
534 or that patent license was granted, prior to 28 March 2007.
535
536 Nothing in this License shall be construed as excluding or limiting
537 any implied license or other defenses to infringement that may
538 otherwise be available to you under applicable patent law.
539
540 12. No Surrender of Others' Freedom.
541
225
542 If conditions are imposed on you (whether by court order, agreement or
226 This section is intended to make thoroughly clear what is believed to
543 otherwise) that contradict the conditions of this License, they do not
227 be a consequence of the rest of this License.
544 excuse you from the conditions of this License. If you cannot convey a
545 covered work so as to satisfy simultaneously your obligations under this
546 License and any other pertinent obligations, then as a consequence you may
547 not convey it at all. For example, if you agree to terms that obligate you
548 to collect a royalty for further conveying from those to whom you convey
549 the Program, the only way you could satisfy both those terms and this
550 License would be to refrain entirely from conveying the Program.
551
552 13. Use with the GNU Affero General Public License.
553
228
554 Notwithstanding any other provision of this License, you have
229 8. If the distribution and/or use of the Program is restricted in
555 permission to link or combine any covered work with a work licensed
230 certain countries either by patents or by copyrighted interfaces, the
556 under version 3 of the GNU Affero General Public License into a single
231 original copyright holder who places the Program under this License
557 combined work, and to convey the resulting work. The terms of this
232 may add an explicit geographical distribution limitation excluding
558 License will continue to apply to the part which is the covered work,
233 those countries, so that distribution is permitted only in or among
559 but the special requirements of the GNU Affero General Public License,
234 countries not thus excluded. In such case, this License incorporates
560 section 13, concerning interaction through a network will apply to the
235 the limitation as if written in the body of this License.
561 combination as such.
562
236
563 14. Revised Versions of this License.
237 9. The Free Software Foundation may publish revised and/or new versions
564
238 of the General Public License from time to time. Such new versions will
565 The Free Software Foundation may publish revised and/or new versions of
566 the GNU General Public License from time to time. Such new versions will
567 be similar in spirit to the present version, but may differ in detail to
239 be similar in spirit to the present version, but may differ in detail to
568 address new problems or concerns.
240 address new problems or concerns.
569
241
570 Each version is given a distinguishing version number. If the
242 Each version is given a distinguishing version number. If the Program
571 Program specifies that a certain numbered version of the GNU General
243 specifies a version number of this License which applies to it and "any
572 Public License "or any later version" applies to it, you have the
244 later version", you have the option of following the terms and conditions
573 option of following the terms and conditions either of that numbered
245 either of that version or of any later version published by the Free
574 version or of any later version published by the Free Software
246 Software Foundation. If the Program does not specify a version number of
575 Foundation. If the Program does not specify a version number of the
247 this License, you may choose any version ever published by the Free Software
576 GNU General Public License, you may choose any version ever published
248 Foundation.
577 by the Free Software Foundation.
578
249
579 If the Program specifies that a proxy can decide which future
250 10. If you wish to incorporate parts of the Program into other free
580 versions of the GNU General Public License can be used, that proxy's
251 programs whose distribution conditions are different, write to the author
581 public statement of acceptance of a version permanently authorizes you
252 to ask for permission. For software which is copyrighted by the Free
582 to choose that version for the Program.
253 Software Foundation, write to the Free Software Foundation; we sometimes
254 make exceptions for this. Our decision will be guided by the two goals
255 of preserving the free status of all derivatives of our free software and
256 of promoting the sharing and reuse of software generally.
583
257
584 Later license versions may give you additional or different
258 NO WARRANTY
585 permissions. However, no additional obligations are imposed on any
586 author or copyright holder as a result of your choosing to follow a
587 later version.
588
589 15. Disclaimer of Warranty.
590
259
591 THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
260 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
592 APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
261 FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
593 HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
262 OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
594 OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
263 PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
595 THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
264 OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
596 PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
265 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
597 IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
266 TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
598 ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
267 PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
599
268 REPAIR OR CORRECTION.
600 16. Limitation of Liability.
601
269
602 IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
270 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
603 WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
271 WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
604 THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
272 REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
605 GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
273 INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
606 USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
274 OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
607 DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
275 TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
608 PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
276 YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
609 EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
277 PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
610 SUCH DAMAGES.
278 POSSIBILITY OF SUCH DAMAGES.
611
612 17. Interpretation of Sections 15 and 16.
613
614 If the disclaimer of warranty and limitation of liability provided
615 above cannot be given local legal effect according to their terms,
616 reviewing courts shall apply local law that most closely approximates
617 an absolute waiver of all civil liability in connection with the
618 Program, unless a warranty or assumption of liability accompanies a
619 copy of the Program in return for a fee.
620
279
621 END OF TERMS AND CONDITIONS
280 END OF TERMS AND CONDITIONS
622
281
623 How to Apply These Terms to Your New Programs
282 How to Apply These Terms to Your New Programs
624
283
625 If you develop a new program, and you want it to be of the greatest
284 If you develop a new program, and you want it to be of the greatest
626 possible use to the public, the best way to achieve this is to make it
285 possible use to the public, the best way to achieve this is to make it
627 free software which everyone can redistribute and change under these terms.
286 free software which everyone can redistribute and change under these terms.
628
287
629 To do so, attach the following notices to the program. It is safest
288 To do so, attach the following notices to the program. It is safest
630 to attach them to the start of each source file to most effectively
289 to attach them to the start of each source file to most effectively
631 state the exclusion of warranty; and each file should have at least
290 convey the exclusion of warranty; and each file should have at least
632 the "copyright" line and a pointer to where the full notice is found.
291 the "copyright" line and a pointer to where the full notice is found.
633
292
634 <one line to give the program's name and a brief idea of what it does.>
293 <one line to give the program's name and a brief idea of what it does.>
635 Copyright (C) <year> <name of author>
294 Copyright (C) <year> <name of author>
636
295
637 This program is free software: you can redistribute it and/or modify
296 This program is free software; you can redistribute it and/or modify
638 it under the terms of the GNU General Public License as published by
297 it under the terms of the GNU General Public License as published by
639 the Free Software Foundation, either version 3 of the License, or
298 the Free Software Foundation; either version 2 of the License, or
640 (at your option) any later version.
299 (at your option) any later version.
641
300
642 This program is distributed in the hope that it will be useful,
301 This program is distributed in the hope that it will be useful,
643 but WITHOUT ANY WARRANTY; without even the implied warranty of
302 but WITHOUT ANY WARRANTY; without even the implied warranty of
644 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
303 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
645 GNU General Public License for more details.
304 GNU General Public License for more details.
646
305
647 You should have received a copy of the GNU General Public License
306 You should have received a copy of the GNU General Public License along
648 along with this program. If not, see <http://www.gnu.org/licenses/>.
307 with this program; if not, write to the Free Software Foundation, Inc.,
308 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
649
309
650 Also add information on how to contact you by electronic and paper mail.
310 Also add information on how to contact you by electronic and paper mail.
651
311
652 If the program does terminal interaction, make it output a short
312 If the program is interactive, make it output a short notice like this
653 notice like this when it starts in an interactive mode:
313 when it starts in an interactive mode:
654
314
655 <program> Copyright (C) <year> <name of author>
315 Gnomovision version 69, Copyright (C) year name of author
656 This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
316 Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
657 This is free software, and you are welcome to redistribute it
317 This is free software, and you are welcome to redistribute it
658 under certain conditions; type `show c' for details.
318 under certain conditions; type `show c' for details.
659
319
660 The hypothetical commands `show w' and `show c' should show the appropriate
320 The hypothetical commands `show w' and `show c' should show the appropriate
661 parts of the General Public License. Of course, your program's commands
321 parts of the General Public License. Of course, the commands you use may
662 might be different; for a GUI interface, you would use an "about box".
322 be called something other than `show w' and `show c'; they could even be
323 mouse-clicks or menu items--whatever suits your program.
324
325 You should also get your employer (if you work as a programmer) or your
326 school, if any, to sign a "copyright disclaimer" for the program, if
327 necessary. Here is a sample; alter the names:
663
328
664 You should also get your employer (if you work as a programmer) or school,
329 Yoyodyne, Inc., hereby disclaims all copyright interest in the program
665 if any, to sign a "copyright disclaimer" for the program, if necessary.
330 `Gnomovision' (which makes passes at compilers) written by James Hacker.
666 For more information on this, and how to apply and follow the GNU GPL, see
331
667 <http://www.gnu.org/licenses/>.
332 <signature of Ty Coon>, 1 April 1989
333 Ty Coon, President of Vice
668
334
669 The GNU General Public License does not permit incorporating your program
335 This General Public License does not permit incorporating your program into
670 into proprietary programs. If your program is a subroutine library, you
336 proprietary programs. If your program is a subroutine library, you may
671 may consider it more useful to permit linking proprietary applications with
337 consider it more useful to permit linking proprietary applications with the
672 the library. If this is what you want to do, use the GNU Lesser General
338 library. If this is what you want to do, use the GNU Lesser General
673 Public License instead of this License. But first, please read
339 Public License instead of this License.
674 <http://www.gnu.org/philosophy/why-not-lgpl.html>.
Show file before | Show file after | Hide comments
@@ -1,72 +1,72
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP GPL PATCHER "
3 echo " LPP GPL PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28 # Absolute path to this script. /home/user/bin/foo.sh
28 # Absolute path to this script. /home/user/bin/foo.sh
29 #SCRIPT=$(readlink -f $0)
29 #SCRIPT=$(readlink -f $0)
30 # Absolute path this script is in. /home/user/bin
30 # Absolute path this script is in. /home/user/bin
31
31
32 #LPP_PATCHPATH=`dirname $SCRIPT`
32 #LPP_PATCHPATH=`dirname $SCRIPT`
33 LPP_PATCHPATH=`pwd -L`
33 LPP_PATCHPATH=`pwd -L`
34
34
35
35
36 case $1 in
36 case $1 in
37 -R | --recursive )
37 -R | --recursive )
38 for file in $(find . -name '*.vhd')
38 for file in $(find . -name '*.vhd')
39 do
39 do
40 if(grep -q "This program is free software" $file); then
40 if(grep -q "This program is free software" $file); then
41 echo "$file already contains GPL HEADER"
41 echo "$file already contains GPL HEADER"
42 else
42 else
43 echo "Modifying file : $file"
43 echo "Modifying file : $file"
44 more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
44 more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
45 cat $file >> $file.tmp
45 cat $file >> $file.tmp
46 mv $file.tmp $file
46 mv $file.tmp $file
47 fi
47 fi
48 done
48 done
49 ;;
49 ;;
50 -h | --help | --h | -help)
50 -h | --help | --h | -help)
51 echo 'Help:
51 echo 'Help:
52 This script add a GPL HEADER in all vhdl files.
52 This script add a GPL HEADER in all vhdl files.
53
53
54 -R or --recurcive:
54 -R or --recurcive:
55 Analyse recurcively folders starting from $LPP_PATCHPATH'
55 Analyse recurcively folders starting from $LPP_PATCHPATH'
56 ;;
56 ;;
57 * )
57 * )
58 for file in $(ls *.vhd)
58 for file in $(ls *.vhd)
59 do
59 do
60 if(grep -q "This program is free software" $file); then
60 if(grep -q "This program is free software" $file); then
61 echo "$file already contains GPL HEADER"
61 echo "$file already contains GPL HEADER"
62 else
62 else
63 echo "Modifying file : $file"
63 echo "Modifying file : $file"
64 more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
64 more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
65 cat $file >> $file.tmp
65 cat $file >> $file.tmp
66 mv $file.tmp $file
66 mv $file.tmp $file
67 fi
67 fi
68 done
68 done
69 ;;
69 ;;
70
70
71 esac
71 esac
72
72
Show file before | Show file after | Hide comments
@@ -1,72 +1,82
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP GPL PATCHER "
3 echo " LPP GPL PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28 # Absolute path to this script. /home/user/bin/foo.sh
28 # Absolute path to this script. /home/user/bin/foo.sh
29 #SCRIPT=$(readlink -f $0)
29 #SCRIPT=$(readlink -f $0)
30 # Absolute path this script is in. /home/user/bin
30 # Absolute path this script is in. /home/user/bin
31
31
32 #LPP_PATCHPATH=`dirname $SCRIPT`
32 #LPP_PATCHPATH=`dirname $SCRIPT`
33 LPP_PATCHPATH=`pwd -L`
33 LPP_PATCHPATH=`pwd -L`
34
34
35
35
36 cd $LPP_PATCHPATH/$3
37
38 echo $LPP_PATCHPATH/$3
39 echo $LPP_PATCHPATH
40
36 case $1 in
41 case $1 in
37 -R | --recursive )
42 -R | --recursive )
38 for file in $(find . -name '*.vhd')
43 for file in $(find . -name *.$2)
39 do
44 do
40 if(grep -q "This program is free software" $file); then
45 if(grep -q "This program is free software" $file); then
41 echo "$file already contains GPL HEADER"
46 echo "$file already contains GPL HEADER"
42 else
47 else
43 echo "Modifying file : $file"
48 echo "Modifying file : $file"
44 more $LPP_PATCHPATH/licenses/GPL_V2/HEADER >> $file.tmp
49 more $LPP_PATCHPATH/licenses/GPL_V3/${2}HEADER >> $file.tmp
45 cat $file >> $file.tmp
50 cat $file >> $file.tmp
46 mv $file.tmp $file
51 mv $file.tmp $file
47 fi
52 fi
48 done
53 done
49 ;;
54 ;;
50 -h | --help | --h | -help)
55 -h | --help | --h | -help)
51 echo 'Help:
56 echo 'Help:
52 This script add a GPL HEADER in all vhdl files.
57 This script add a GPL HEADER in all vhdl files.
53
58 usage: sh GPL_Patcher.sh [-R] [extension] [path]
54 -R or --recurcive:
59 -R or --recurcive:
55 Analyse recurcively folders starting from $LPP_PATCHPATH'
60 Analyse recurcively folders starting from $LPP_PATCHPATH
61 extension
62 for example vhd,h,c
63 path
64 starting path'
56 ;;
65 ;;
57 * )
66 * )
58 for file in $(ls *.vhd)
67 for file in $(ls *.$2)
59 do
68 do
60 if(grep -q "This program is free software" $file); then
69 if(grep -q "This program is free software" $file); then
61 echo "$file already contains GPL HEADER"
70 echo "$file already contains GPL HEADER"
62 else
71 else
63 echo "Modifying file : $file"
72 echo "Modifying file : $file"
64 more $LPP_PATCHPATH/licenses/GPL_V2/HEADER >> $file.tmp
73 more $LPP_PATCHPATH/licenses/GPL_V3/${2}HEADER >> $file.tmp
65 cat $file >> $file.tmp
74 cat $file >> $file.tmp
66 mv $file.tmp $file
75 mv $file.tmp $file
67 fi
76 fi
68 done
77 done
69 ;;
78 ;;
70
79
71 esac
80 esac
72
81
82 cd $LPP_PATCHPATH
Show file before | Show file after | Hide comments
@@ -1,50 +1,50
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP VHDL lib makeDirs "
3 echo " LPP VHDL lib makeDirs "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28
28
29
29
30 LPP_PATCHPATH=`pwd -L`
30 LPP_PATCHPATH=`pwd -L`
31
31
32 cd $LPP_PATCHPATH/lib/lpp
32 cd $LPP_PATCHPATH/lib/lpp
33
33
34
34
35 #find . -type d|grep ./>$LPP_PATCHPATH/lib/lpp/dirs.txt
35 #find . -type d|grep ./>$LPP_PATCHPATH/lib/lpp/dirs.txt
36
36
37 rm $LPP_PATCHPATH/lib/lpp/dirs.txt
37 rm $LPP_PATCHPATH/lib/lpp/dirs.txt
38
38
39 for folders in $(find . -type d|grep ./)
39 for folders in $(find . -type d|grep ./)
40 do
40 do
41 echo "enter folder : $folders"
41 echo "enter folder : $folders"
42 files=$(ls $folders|grep .vhd)
42 files=$(ls $folders|grep .vhd)
43 if(ls $folders|grep .vhd|grep -i -v .html|grep -i -v .tex); then
43 if(ls $folders|grep .vhd|grep -i -v .html|grep -i -v .tex); then
44 echo "found $files"
44 echo "found $files"
45 echo $folders>>$LPP_PATCHPATH/lib/lpp/dirs.txt
45 echo $folders>>$LPP_PATCHPATH/lib/lpp/dirs.txt
46 fi
46 fi
47 done
47 done
48
48
49
49
50 cd $LPP_PATCHPATH
50 cd $LPP_PATCHPATH
Show file before | Show file after | Hide comments
@@ -1,89 +1,89
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP's GRLIB GLOBAL PATCHER "
3 echo " LPP's GRLIB GLOBAL PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '------------------------------------------------------------------------------
6 echo '------------------------------------------------------------------------------
7 -- This file is a part of the LPP VHDL IP LIBRARY
7 -- This file is a part of the LPP VHDL IP LIBRARY
8 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
8 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
9 --
9 --
10 -- This program is free software; you can redistribute it and/or modify
10 -- This program is free software; you can redistribute it and/or modify
11 -- it under the terms of the GNU General Public License as published by
11 -- it under the terms of the GNU General Public License as published by
12 -- the Free Software Foundation; either version 2 of the License, or
12 -- the Free Software Foundation; either version 3 of the License, or
13 -- (at your option) any later version.
13 -- (at your option) any later version.
14 --
14 --
15 -- This program is distributed in the hope that it will be useful,
15 -- This program is distributed in the hope that it will be useful,
16 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
17 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 -- GNU General Public License for more details.
18 -- GNU General Public License for more details.
19 --
19 --
20 -- You should have received a copy of the GNU General Public License
20 -- You should have received a copy of the GNU General Public License
21 -- along with this program; if not, write to the Free Software
21 -- along with this program; if not, write to the Free Software
22 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 -------------------------------------------------------------------------------'
23 -------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28 # Absolute path to this script. /home/user/bin/foo.sh
28 # Absolute path to this script. /home/user/bin/foo.sh
29 #SCRIPT=$(readlink -f $0)
29 #SCRIPT=$(readlink -f $0)
30 # Absolute path this script is in. /home/user/bin
30 # Absolute path this script is in. /home/user/bin
31
31
32 #LPP_PATCHPATH=`dirname $SCRIPT`
32 #LPP_PATCHPATH=`dirname $SCRIPT`
33 LPP_PATCHPATH=`pwd -L`
33 LPP_PATCHPATH=`pwd -L`
34
34
35 GRLIBPATH=$1
35 GRLIBPATH=$1
36
36
37
37
38 if [ -d "$GRLIBPATH" ]; then
38 if [ -d "$GRLIBPATH" ]; then
39 if [ -d "$GRLIBPATH/lib" ]; then
39 if [ -d "$GRLIBPATH/lib" ]; then
40 if [ -d "$GRLIBPATH/designs" ]; then
40 if [ -d "$GRLIBPATH/designs" ]; then
41 if [ -d "$GRLIBPATH/boards" ]; then
41 if [ -d "$GRLIBPATH/boards" ]; then
42 #PATCH /lib
42 #PATCH /lib
43 echo "patch /lib"
43 echo "patch /lib"
44 echo
44 echo
45
45
46 sh scripts/patchlibs.sh $GRLIBPATH
46 sh scripts/patchlibs.sh $GRLIBPATH
47
47
48 #PATCH /boards
48 #PATCH /boards
49 echo "patch /boards"
49 echo "patch /boards"
50 echo
50 echo
51 sh scripts/patchboards.sh $GRLIBPATH
51 sh scripts/patchboards.sh $GRLIBPATH
52
52
53 #PATCH /designs
53 #PATCH /designs
54 echo "patch /designs"
54 echo "patch /designs"
55 echo
55 echo
56 sh scripts/patchdesigns.sh $GRLIBPATH
56 sh scripts/patchdesigns.sh $GRLIBPATH
57
57
58 echo
58 echo
59 echo
59 echo
60
60
61 #CLEAN
61 #CLEAN
62 echo "CLEANING .."
62 echo "CLEANING .."
63 rm -v $1/lib/*.sh
63 rm -v $1/lib/*.sh
64 rm -v $1/lib/TODO
64 rm -v $1/lib/TODO
65 rm -v $1/lib/Makefile
65 rm -v $1/lib/Makefile
66 rm -v $1/lib/log.txt
66 rm -v $1/lib/log.txt
67 echo
67 echo
68 echo
68 echo
69 echo
69 echo
70 else
70 else
71 echo "I can't find GRLIB in $1"
71 echo "I can't find GRLIB in $1"
72 fi
72 fi
73
73
74 else
74 else
75 echo "I can't find GRLIB in $1"
75 echo "I can't find GRLIB in $1"
76 fi
76 fi
77 else
77 else
78 echo "I can't find GRLIB in $1"
78 echo "I can't find GRLIB in $1"
79 fi
79 fi
80
80
81 else
81 else
82 echo "I can't find GRLIB in $1"
82 echo "I can't find GRLIB in $1"
83 fi
83 fi
84
84
85
85
86
86
87
87
88
88
89
89
Show file before | Show file after | Hide comments
@@ -1,48 +1,48
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP's GRLIB Boards PATCHER "
3 echo " LPP's GRLIB Boards PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28
28
29 LPP_LIBPATH=`pwd -L`
29 LPP_LIBPATH=`pwd -L`
30
30
31 echo "Patching boards..."
31 echo "Patching boards..."
32 echo
32 echo
33 echo
33 echo
34
34
35 #COPY
35 #COPY
36 echo "Copy boards Files..."
36 echo "Copy boards Files..."
37 cp -R -v $LPP_LIBPATH/boards $1
37 cp -R -v $LPP_LIBPATH/boards $1
38 echo
38 echo
39 echo
39 echo
40 echo
40 echo
41
41
42
42
43 #CLEAN
43 #CLEAN
44 echo "CLEANING .."
44 echo "CLEANING .."
45 rm -v $1/boards/*.sh
45 rm -v $1/boards/*.sh
46 echo
46 echo
47 echo
47 echo
48 echo
48 echo
Show file before | Show file after | Hide comments
@@ -1,49 +1,49
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP's GRLIB Designs PATCHER "
3 echo " LPP's GRLIB Designs PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28
28
29 LPP_LIBPATH=`pwd -L`
29 LPP_LIBPATH=`pwd -L`
30
30
31 echo "Patching designs..."
31 echo "Patching designs..."
32 echo
32 echo
33 echo
33 echo
34
34
35 #COPY
35 #COPY
36 echo "Copy designs Files..."
36 echo "Copy designs Files..."
37 cp -R -v $LPP_LIBPATH/designs $1
37 cp -R -v $LPP_LIBPATH/designs $1
38 echo
38 echo
39 echo
39 echo
40 echo
40 echo
41
41
42
42
43 #CLEAN
43 #CLEAN
44 echo "CLEANING .."
44 echo "CLEANING .."
45 rm -v $1/designs/*.sh
45 rm -v $1/designs/*.sh
46 echo
46 echo
47 echo
47 echo
48 echo
48 echo
49
49
Show file before | Show file after | Hide comments
@@ -1,64 +1,64
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP's GRLIB IPs PATCHER "
3 echo " LPP's GRLIB IPs PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28
28
29 LPP_LIBPATH=`pwd -L`
29 LPP_LIBPATH=`pwd -L`
30
30
31 echo "Patching Grlib..."
31 echo "Patching Grlib..."
32 echo
32 echo
33 echo
33 echo
34
34
35 #COPY
35 #COPY
36 echo "Remove old lib Files..."
36 echo "Remove old lib Files..."
37 rm -R -v $1/lib/lpp
37 rm -R -v $1/lib/lpp
38 echo "Copy lib Files..."
38 echo "Copy lib Files..."
39 cp -R -v $LPP_LIBPATH/lib $1
39 cp -R -v $LPP_LIBPATH/lib $1
40 echo
40 echo
41 echo
41 echo
42 echo
42 echo
43
43
44
44
45 #PATCH libs.txt
45 #PATCH libs.txt
46 echo "Patch $1/lib/libs.txt..."
46 echo "Patch $1/lib/libs.txt..."
47 if(grep -q lpp $1/lib/libs.txt); then
47 if(grep -q lpp $1/lib/libs.txt); then
48 echo "No need to Patch $1/lib/libs.txt..."
48 echo "No need to Patch $1/lib/libs.txt..."
49 else
49 else
50 echo lpp>>$1/lib/libs.txt
50 echo lpp>>$1/lib/libs.txt
51 fi
51 fi
52
52
53 echo
53 echo
54 echo
54 echo
55 echo
55 echo
56
56
57 #CLEAN
57 #CLEAN
58 echo "CLEANING .."
58 echo "CLEANING .."
59 rm -v $1/lib/*.sh
59 rm -v $1/lib/*.sh
60 rm -v $1/lib/GPL_HEADER
60 rm -v $1/lib/GPL_HEADER
61 echo
61 echo
62 echo
62 echo
63 echo
63 echo
64
64
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@@ -1,61 +1,61
1 echo "======================================================================================="
1 echo "======================================================================================="
2 echo "---------------------------------------------------------------------------------------"
2 echo "---------------------------------------------------------------------------------------"
3 echo " LPP vhdlsyn PATCHER "
3 echo " LPP vhdlsyn PATCHER "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 echo "======================================================================================="
5 echo "======================================================================================="
6 echo '----------------------------------------------------------------------------------------
6 echo '----------------------------------------------------------------------------------------
7 This file is a part of the LPP VHDL IP LIBRARY
7 This file is a part of the LPP VHDL IP LIBRARY
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9
9
10 This program is free software; you can redistribute it and/or modify
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
13 (at your option) any later version.
14
14
15 This program is distributed in the hope that it will be useful,
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
18 GNU General Public License for more details.
19
19
20 You should have received a copy of the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 ----------------------------------------------------------------------------------------'
23 ----------------------------------------------------------------------------------------'
24 echo
24 echo
25 echo
25 echo
26 echo
26 echo
27
27
28 # Absolute path to this script. /home/user/bin/foo.sh
28 # Absolute path to this script. /home/user/bin/foo.sh
29 #SCRIPT=$(readlink -f $0)
29 #SCRIPT=$(readlink -f $0)
30 # Absolute path this script is in. /home/user/bin
30 # Absolute path this script is in. /home/user/bin
31
31
32 #LPP_PATCHPATH=`dirname $SCRIPT`
32 #LPP_PATCHPATH=`dirname $SCRIPT`
33 LPP_PATCHPATH=`pwd -L`
33 LPP_PATCHPATH=`pwd -L`
34
34
35 cd $LPP_PATCHPATH/lib/lpp
35 cd $LPP_PATCHPATH/lib/lpp
36
36
37 echo `pwd -L`
37 echo `pwd -L`
38
38
39 case $1 in
39 case $1 in
40 -h | --help | --h | -help)
40 -h | --help | --h | -help)
41 echo 'Help:
41 echo 'Help:
42 This script add all non testbensh VHDL files in vhdlsyn.txt file of each folder.'
42 This script add all non testbensh VHDL files in vhdlsyn.txt file of each folder.'
43 ;;
43 ;;
44 * )
44 * )
45 for folders in $(find . -type d|grep ./)
45 for folders in $(find . -type d|grep ./)
46 do
46 do
47 echo "enter folder : $folders"
47 echo "enter folder : $folders"
48 files=$(ls $folders | grep .vhd | grep -i -v "test")
48 files=$(ls $folders | grep .vhd | grep -i -v "test")
49 echo "found $files"
49 echo "found $files"
50 rm $folders/vhdlsyn.txt
50 rm $folders/vhdlsyn.txt
51 for file in $files
51 for file in $files
52 do
52 do
53 echo "$file">>$folders/vhdlsyn.txt
53 echo "$file">>$folders/vhdlsyn.txt
54 done
54 done
55 done
55 done
56 ;;
56 ;;
57
57
58 esac
58 esac
59
59
60 cd $LPP_PATCHPATH
60 cd $LPP_PATCHPATH
61
61
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1 NO CONTENT: file was removed
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1 NO CONTENT: file was removed
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1 NO CONTENT: file was removed
NO CONTENT: file was removed
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1 NO CONTENT: file was removed
NO CONTENT: file was removed
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