@@ -0,0 +1,209 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more Cdetails. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Paul LEROY | |||
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | ||||
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23 | LIBRARY IEEE; | |||
|
24 | USE IEEE.numeric_std.ALL; | |||
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25 | USE IEEE.std_logic_1164.ALL; | |||
|
26 | ||||
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27 | LIBRARY staging_lpp; | |||
|
28 | --USE lpp.general_purpose.ALL; | |||
|
29 | use staging_lpp.PLE_general_purpose.all; | |||
|
30 | use staging_lpp.PLE_lpp_fft.all; | |||
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31 | ||||
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32 | ENTITY BUTTERFLY_CTRL IS | |||
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33 | PORT ( | |||
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34 | rstn : IN STD_LOGIC; | |||
|
35 | clk : IN STD_LOGIC; | |||
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36 | ||||
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37 | sample_in_val : IN STD_LOGIC; | |||
|
38 | sample_out_val : OUT STD_LOGIC; | |||
|
39 | ||||
|
40 | sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z | |||
|
41 | sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in | |||
|
42 | sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z | |||
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43 | sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); | |||
|
44 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
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45 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) | |||
|
46 | ); | |||
|
47 | END BUTTERFLY_CTRL; | |||
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48 | ||||
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49 | ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS | |||
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50 | ||||
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51 | TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC, | |||
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52 | waiting, | |||
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53 | add1, | |||
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54 | add2, | |||
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55 | add3, | |||
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56 | add4, | |||
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57 | mult5, | |||
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58 | mac6, | |||
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59 | mac7, | |||
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60 | mult8, | |||
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61 | mac9, | |||
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62 | last10, | |||
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63 | last11); | |||
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64 | SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T; | |||
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65 | ||||
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66 | BEGIN | |||
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67 | ||||
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68 | PROCESS (clk, rstn) | |||
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69 | ||||
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70 | BEGIN -- PROCESS | |||
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71 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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72 | --REG ------------------------------------------------------------------- | |||
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73 | sel_xyz <= (OTHERS => '0'); | |||
|
74 | sel_out <= (OTHERS => '0'); | |||
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75 | --ALU ------------------------------------------------------------------- | |||
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76 | sel_op1 <= (OTHERS => '0'); | |||
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77 | sel_op2 <= (OTHERS => '0'); | |||
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78 | alu_ctrl <= ctrl_IDLE; | |||
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79 | alu_comp <= (OTHERS => '0'); | |||
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80 | --OUT | |||
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81 | sample_out_val <= '0'; | |||
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82 | ||||
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83 | BUTTERFLY_CTRL_STATE <= clearMAC; | |||
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84 | ||||
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85 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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86 | ||||
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87 | CASE BUTTERFLY_CTRL_STATE IS | |||
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88 | ||||
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89 | WHEN clearMAC => | |||
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90 | IF sample_in_val = '1' THEN | |||
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91 | alu_ctrl <= ctrl_CLRMAC; | |||
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92 | BUTTERFLY_CTRL_STATE <= waiting; | |||
|
93 | END IF; | |||
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94 | ||||
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95 | WHEN waiting => | |||
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96 | sel_op1 <= "10000"; -- Are | |||
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97 | sel_op2 <= "10000"; -- Bre | |||
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98 | alu_comp <= "10"; | |||
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99 | BUTTERFLY_CTRL_STATE <= add1; | |||
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100 | ||||
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101 | WHEN add1 => | |||
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102 | sample_out_val <= '0'; | |||
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103 | sel_op1 <= "01000"; -- Aim | |||
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104 | sel_op2 <= "01000"; -- Bim | |||
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105 | alu_comp <= "10"; | |||
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106 | alu_ctrl <= ctrl_ADD; | |||
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107 | sel_out <= "10000"; | |||
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108 | BUTTERFLY_CTRL_STATE <= add2; | |||
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109 | ||||
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110 | WHEN add2 => | |||
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111 | sample_out_val <= '0'; | |||
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112 | sel_op1 <= "10000"; -- Are | |||
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113 | sel_op2 <= "10000"; -- Bre | |||
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114 | alu_comp <= "00"; | |||
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115 | alu_ctrl <= ctrl_ADD; | |||
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116 | sel_out <= "10000"; | |||
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117 | BUTTERFLY_CTRL_STATE <= add3; | |||
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118 | ||||
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119 | WHEN add3 => | |||
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120 | sample_out_val <= '0'; | |||
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121 | sel_op1 <= "01000"; -- Aim | |||
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122 | sel_op2 <= "01000"; -- Bim | |||
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123 | alu_comp <= "00"; | |||
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124 | alu_ctrl <= ctrl_ADD; | |||
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125 | sel_out <= "10000"; | |||
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126 | sel_xyz <= "100"; -- X | |||
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127 | BUTTERFLY_CTRL_STATE <= add4; | |||
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128 | ||||
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129 | WHEN add4 => | |||
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130 | sample_out_val <= '0'; | |||
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131 | sel_op1 <= "00100"; -- X | |||
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132 | sel_op2 <= "00100"; -- c | |||
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133 | alu_comp <= "00"; | |||
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134 | alu_ctrl <= ctrl_ADD; | |||
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135 | sel_out <= "00000"; | |||
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136 | sel_xyz <= "010"; | |||
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137 | BUTTERFLY_CTRL_STATE <= mult5; | |||
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138 | ||||
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139 | WHEN mult5 => | |||
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140 | sample_out_val <= '0'; | |||
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141 | alu_ctrl <= ctrl_MULT; | |||
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142 | sel_op1 <= "00010"; -- Y | |||
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143 | sel_op2 <= "00100"; -- c | |||
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144 | alu_comp <= "10"; | |||
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145 | sel_out <= "00100"; | |||
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146 | BUTTERFLY_CTRL_STATE <= mac6; | |||
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147 | ||||
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148 | WHEN mac6 => | |||
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149 | sample_out_val <= '0'; | |||
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150 | sel_op1 <= "00010"; -- Y | |||
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151 | sel_op2 <= "00001"; -- cms | |||
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152 | alu_comp <= "00"; | |||
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153 | alu_ctrl <= ctrl_MAC; | |||
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154 | sel_out <= "10000"; | |||
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155 | BUTTERFLY_CTRL_STATE <= mac7; | |||
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156 | ||||
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157 | WHEN mac7 => | |||
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158 | sample_out_val <= '0'; | |||
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159 | sel_op1 <= "00100"; -- X | |||
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160 | sel_op2 <= "00010"; -- cps | |||
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161 | alu_ctrl <= ctrl_MAC; | |||
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162 | alu_comp <= "00"; | |||
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163 | sel_out <= "10000"; | |||
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164 | BUTTERFLY_CTRL_STATE <= mult8; | |||
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165 | ||||
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166 | WHEN mult8 => | |||
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167 | sample_out_val <= '0'; | |||
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168 | alu_ctrl <= ctrl_MULT; | |||
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169 | sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU | |||
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170 | sel_op2 <= "00000"; -- 1 | |||
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171 | alu_comp <= "00"; | |||
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172 | sel_out <= "10000"; | |||
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173 | BUTTERFLY_CTRL_STATE <= mac9; | |||
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174 | ||||
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175 | WHEN mac9 => | |||
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176 | sample_out_val <= '0'; | |||
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177 | sel_op1 <= "10000"; | |||
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178 | sel_op2 <= "10000"; | |||
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179 | alu_ctrl <= ctrl_MAC; | |||
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180 | alu_comp <= "10"; | |||
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181 | sel_out <= "10000"; | |||
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182 | BUTTERFLY_CTRL_STATE <= last10; | |||
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183 | ||||
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184 | WHEN last10 => | |||
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185 | sample_out_val <= '0'; | |||
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186 | sel_op1 <= "10000"; | |||
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187 | sel_op2 <= "10000"; | |||
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188 | alu_ctrl <= ctrl_IDLE; | |||
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189 | alu_comp <= "10"; | |||
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190 | sel_out <= "10000"; | |||
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191 | BUTTERFLY_CTRL_STATE <= last11; | |||
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192 | ||||
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193 | WHEN last11 => | |||
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194 | sample_out_val <= '0'; | |||
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195 | alu_ctrl <= ctrl_IDLE; | |||
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196 | alu_comp <= "10"; | |||
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197 | sel_out <= "10000"; | |||
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198 | BUTTERFLY_CTRL_STATE <= waiting; | |||
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199 | ||||
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200 | WHEN OTHERS => | |||
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201 | NULL; | |||
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202 | ||||
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203 | END CASE; | |||
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204 | ||||
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205 | END IF; | |||
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206 | ||||
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207 | END PROCESS; | |||
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208 | ||||
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209 | END ar_BUTTERFLY_CTRL; No newline at end of file |
@@ -0,0 +1,115 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more Cdetails. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Paul LEROY | |||
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | ||||
|
23 | LIBRARY IEEE; | |||
|
24 | USE IEEE.numeric_std.ALL; | |||
|
25 | USE IEEE.std_logic_1164.ALL; | |||
|
26 | ||||
|
27 | LIBRARY staging_lpp; | |||
|
28 | USE staging_lpp.PLE_general_purpose.ALL; | |||
|
29 | use staging_lpp.PLE_lpp_fft.all; | |||
|
30 | ||||
|
31 | ENTITY BUTTERFLY_TOP IS | |||
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32 | GENERIC ( | |||
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33 | Sample_SZ : INTEGER := 16); | |||
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34 | PORT ( | |||
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35 | rstn : IN STD_LOGIC; | |||
|
36 | clk : IN STD_LOGIC; | |||
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37 | ||||
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38 | sample_in_val : IN STD_LOGIC; | |||
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39 | sample_out_val : OUT STD_LOGIC; | |||
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40 | ||||
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41 | Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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42 | Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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43 | Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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44 | Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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45 | c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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46 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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47 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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48 | ||||
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49 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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50 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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51 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
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52 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |||
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53 | ||||
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54 | butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |||
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55 | sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) | |||
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56 | ); | |||
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57 | END BUTTERFLY_TOP; | |||
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58 | ||||
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59 | ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS | |||
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60 | ||||
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61 | SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z | |||
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62 | SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in | |||
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63 | SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z | |||
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64 | SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
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65 | SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |||
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66 | ||||
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67 | BEGIN | |||
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68 | ||||
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69 | alu_ctrl <= alu_ctrl_sig; | |||
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70 | alu_comp <= alu_comp_sig; | |||
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71 | ||||
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72 | BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW | |||
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73 | GENERIC MAP ( | |||
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74 | Sample_SZ => 16) | |||
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75 | PORT MAP ( | |||
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76 | rstn => rstn, | |||
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77 | clk => clk, | |||
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78 | ||||
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79 | Are => Are, | |||
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80 | Aim => Aim, | |||
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81 | Bre => Bre, | |||
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82 | Bim => Bim, | |||
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83 | c_in => c_in, | |||
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84 | cps_in => cps_in, | |||
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85 | cms_in => cms_in, | |||
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86 | ||||
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87 | op1 => op1, | |||
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88 | op2 => op2, | |||
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89 | ||||
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90 | out_alu => butterfly_out, | |||
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91 | ||||
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92 | sel_op1 => sel_op1, | |||
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93 | sel_op2 => sel_op2, | |||
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94 | sel_xyz => sel_xyz, | |||
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95 | alu_ctrl => alu_ctrl_sig, | |||
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96 | alu_comp => alu_comp_sig | |||
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97 | ); | |||
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98 | ||||
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99 | BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL | |||
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100 | PORT MAP( | |||
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101 | rstn => rstn, | |||
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102 | clk => clk, | |||
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103 | ||||
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104 | sample_in_val => sample_in_val, | |||
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105 | sample_out_val => sample_out_val, | |||
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106 | ||||
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107 | sel_op1 => sel_op1, | |||
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108 | sel_op2 => sel_op2, | |||
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109 | sel_xyz => sel_xyz, | |||
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110 | sel_out => sel_out, | |||
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111 | alu_ctrl => alu_ctrl_sig, | |||
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112 | alu_comp => alu_comp_sig | |||
|
113 | ); | |||
|
114 | ||||
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115 | END ar_BUTTERFLY_TOP; No newline at end of file |
@@ -0,0 +1,129 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more Cdetails. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Paul LEROY | |||
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | ||||
|
23 | LIBRARY IEEE; | |||
|
24 | USE IEEE.numeric_std.ALL; | |||
|
25 | USE IEEE.std_logic_1164.ALL; | |||
|
26 | LIBRARY staging_lpp; | |||
|
27 | USE staging_lpp.PLE_general_purpose.ALL; | |||
|
28 | ||||
|
29 | ENTITY BUTTERFLY_DATAFLOW IS | |||
|
30 | GENERIC ( | |||
|
31 | Sample_SZ : INTEGER := 16 | |||
|
32 | ); | |||
|
33 | PORT ( | |||
|
34 | rstn : IN STD_LOGIC; | |||
|
35 | clk : IN STD_LOGIC; | |||
|
36 | ||||
|
37 | Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
38 | Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
39 | Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
40 | Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
41 | c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
42 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
43 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
44 | ||||
|
45 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
46 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
47 | ||||
|
48 | out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |||
|
49 | ||||
|
50 | sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z | |||
|
51 | sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in | |||
|
52 | sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z | |||
|
53 | alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
|
54 | alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) | |||
|
55 | ); | |||
|
56 | END BUTTERFLY_DATAFLOW; | |||
|
57 | ||||
|
58 | ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS | |||
|
59 | ||||
|
60 | SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); | |||
|
61 | SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); | |||
|
62 | SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); | |||
|
63 | ||||
|
64 | SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); | |||
|
65 | SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); | |||
|
66 | ||||
|
67 | SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |||
|
68 | ||||
|
69 | BEGIN | |||
|
70 | ||||
|
71 | out_alu <= OUT_ALU_SIG; | |||
|
72 | ||||
|
73 | PROCESS (clk, rstn) | |||
|
74 | ||||
|
75 | BEGIN -- PROCESS | |||
|
76 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
77 | X <= (OTHERS => '0'); | |||
|
78 | Y <= (OTHERS => '0'); | |||
|
79 | Z <= (OTHERS => '0'); | |||
|
80 | ||||
|
81 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
82 | ||||
|
83 | if sel_xyz = "100" THEN | |||
|
84 | X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); | |||
|
85 | elsif sel_xyz = "010" THEN | |||
|
86 | Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); | |||
|
87 | elsif sel_xyz = "001" THEN | |||
|
88 | Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); | |||
|
89 | end if; | |||
|
90 | ||||
|
91 | END IF; | |||
|
92 | ||||
|
93 | END PROCESS; | |||
|
94 | ||||
|
95 | op1 <= ALU_OP1; | |||
|
96 | op2 <= ALU_OP2; | |||
|
97 | ||||
|
98 | ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE | |||
|
99 | Aim WHEN sel_op1 = "01000" ELSE | |||
|
100 | X WHEN sel_op1 = "00100" ELSE | |||
|
101 | Y WHEN sel_op1 = "00010" ELSE | |||
|
102 | Z WHEN sel_op1 = "00001" ELSE | |||
|
103 | STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE | |||
|
104 | (OTHERS => '0'); | |||
|
105 | ||||
|
106 | ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE | |||
|
107 | Bim WHEN sel_op2 = "01000" ELSE | |||
|
108 | c_in WHEN sel_op2 = "00100" ELSE | |||
|
109 | cps_in WHEN sel_op2 = "00010" ELSE | |||
|
110 | cms_in WHEN sel_op2 = "00001" ELSE | |||
|
111 | std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE | |||
|
112 | (OTHERS => '0'); | |||
|
113 | ||||
|
114 | ALU_1: ALU | |||
|
115 | GENERIC MAP ( | |||
|
116 | Arith_en => 1, | |||
|
117 | Input_SZ_1 => Sample_SZ, | |||
|
118 | Input_SZ_2 => Sample_SZ, | |||
|
119 | COMP_EN => 0) -- comp is enable when COMP_EN is 0 | |||
|
120 | PORT MAP ( | |||
|
121 | clk => clk, | |||
|
122 | reset => rstn, | |||
|
123 | ctrl => alu_ctrl, | |||
|
124 | comp => alu_comp, | |||
|
125 | OP1 => ALU_OP1, | |||
|
126 | OP2 => ALU_OP2, | |||
|
127 | RES => OUT_ALU_SIG); | |||
|
128 | ||||
|
129 | END ar_BUTTERFLY_DATAFLOW; No newline at end of file |
@@ -0,0 +1,102 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Paul Leroy | |||
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | ||||
|
23 | ||||
|
24 | LIBRARY ieee; | |||
|
25 | USE ieee.std_logic_1164.ALL; | |||
|
26 | ||||
|
27 | PACKAGE PLE_lpp_fft IS | |||
|
28 | ||||
|
29 | COMPONENT BUTTERFLY_DATAFLOW | |||
|
30 | GENERIC ( | |||
|
31 | Sample_SZ : INTEGER := 16); | |||
|
32 | PORT ( | |||
|
33 | rstn : IN STD_LOGIC; | |||
|
34 | clk : IN STD_LOGIC; | |||
|
35 | ||||
|
36 | Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
37 | Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
38 | Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
39 | Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
40 | c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
41 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
42 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
43 | ||||
|
44 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
45 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
46 | ||||
|
47 | out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |||
|
48 | ||||
|
49 | sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z | |||
|
50 | sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in | |||
|
51 | sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z | |||
|
52 | alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
|
53 | alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) | |||
|
54 | ); | |||
|
55 | END COMPONENT; | |||
|
56 | ||||
|
57 | COMPONENT BUTTERFLY_CTRL | |||
|
58 | PORT ( | |||
|
59 | rstn : IN STD_LOGIC; | |||
|
60 | clk : IN STD_LOGIC; | |||
|
61 | ||||
|
62 | sample_in_val : IN STD_LOGIC; | |||
|
63 | sample_out_val : OUT STD_LOGIC; | |||
|
64 | ||||
|
65 | sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z | |||
|
66 | sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in | |||
|
67 | sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z | |||
|
68 | sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); | |||
|
69 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
|
70 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) | |||
|
71 | ); | |||
|
72 | END COMPONENT; | |||
|
73 | ||||
|
74 | COMPONENT BUTTERFLY_TOP | |||
|
75 | GENERIC ( | |||
|
76 | Sample_SZ : INTEGER := 16); | |||
|
77 | PORT ( | |||
|
78 | rstn : IN STD_LOGIC; | |||
|
79 | clk : IN STD_LOGIC; | |||
|
80 | ||||
|
81 | sample_in_val : IN STD_LOGIC; | |||
|
82 | sample_out_val : OUT STD_LOGIC; | |||
|
83 | ||||
|
84 | Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
85 | Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
86 | Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
87 | Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
88 | c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
89 | cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
90 | cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
91 | ||||
|
92 | op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
93 | op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
|
94 | alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
|
95 | alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |||
|
96 | ||||
|
97 | butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); | |||
|
98 | sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) | |||
|
99 | ); | |||
|
100 | END COMPONENT; | |||
|
101 | ||||
|
102 | END; No newline at end of file |
@@ -0,0 +1,337 | |||||
|
1 | ; Copyright 1991-2010 Mentor Graphics Corporation | |||
|
2 | ; | |||
|
3 | ; All Rights Reserved. | |||
|
4 | ; | |||
|
5 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF | |||
|
6 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. | |||
|
7 | ; | |||
|
8 | ||||
|
9 | [Library] | |||
|
10 | others = $MODEL_TECH/../modelsim.ini | |||
|
11 | ||||
|
12 | ; Actel Primitive Libraries | |||
|
13 | ; | |||
|
14 | ; VHDL Section | |||
|
15 | ; | |||
|
16 | ;aact1 = $MODEL_TECH/../actel/vhdl/aact1 | |||
|
17 | ;aact2 = $MODEL_TECH/../actel/vhdl/aact2 | |||
|
18 | ;aact3 = $MODEL_TECH/../actel/vhdl/aact3 | |||
|
19 | ;a3200dx = $MODEL_TECH/../actel/vhdl/a3200dx | |||
|
20 | ;a40mx = $MODEL_TECH/../actel/vhdl/a40mx | |||
|
21 | ;a42mx = $MODEL_TECH/../actel/vhdl/a42mx | |||
|
22 | ;a54sxa = $MODEL_TECH/../actel/vhdl/a54sxa | |||
|
23 | ; | |||
|
24 | ; Verilog Section | |||
|
25 | ; | |||
|
26 | ;act1 = $MODEL_TECH/../actel/verilog/act1 | |||
|
27 | ;act2 = $MODEL_TECH/../actel/verilog/act2 | |||
|
28 | ;act3 = $MODEL_TECH/../actel/verilog/act3 | |||
|
29 | ;3200dx = $MODEL_TECH/../actel/verilog/3200dx | |||
|
30 | ;40mx = $MODEL_TECH/../actel/verilog/40mx | |||
|
31 | ;42mx = $MODEL_TECH/../actel/verilog/42mx | |||
|
32 | ;54sxa = $MODEL_TECH/../actel/verilog/54sxa | |||
|
33 | ||||
|
34 | staging_lpp = staging_lpp | |||
|
35 | [vcom] | |||
|
36 | ; VHDL93 variable selects language version as the default. | |||
|
37 | ; Default is VHDL-2002. | |||
|
38 | ; Value of 0 or 1987 for VHDL-1987. | |||
|
39 | ; Value of 1 or 1993 for VHDL-1993. | |||
|
40 | ; Default or value of 2 or 2002 for VHDL-2002. | |||
|
41 | VHDL93 = 2002 | |||
|
42 | ||||
|
43 | ; Show source line containing error. Default is off. | |||
|
44 | ; Show_source = 1 | |||
|
45 | ||||
|
46 | ; Turn off unbound-component warnings. Default is on. | |||
|
47 | ; Show_Warning1 = 0 | |||
|
48 | ||||
|
49 | ; Turn off process-without-a-wait-statement warnings. Default is on. | |||
|
50 | ; Show_Warning2 = 0 | |||
|
51 | ||||
|
52 | ; Turn off null-range warnings. Default is on. | |||
|
53 | ; Show_Warning3 = 0 | |||
|
54 | ||||
|
55 | ; Turn off no-space-in-time-literal warnings. Default is on. | |||
|
56 | ; Show_Warning4 = 0 | |||
|
57 | ||||
|
58 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. | |||
|
59 | ; Show_Warning5 = 0 | |||
|
60 | ||||
|
61 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. | |||
|
62 | ; Optimize_1164 = 0 | |||
|
63 | ||||
|
64 | ; Turn on resolving of ambiguous function overloading in favor of the | |||
|
65 | ; "explicit" function declaration (not the one automatically created by | |||
|
66 | ; the compiler for each type declaration). Default is off. | |||
|
67 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned | |||
|
68 | ; will match the behavior of synthesis tools. | |||
|
69 | Explicit = 1 | |||
|
70 | ||||
|
71 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. | |||
|
72 | ; NoVital = 1 | |||
|
73 | ||||
|
74 | ; Turn off VITAL compliance checking. Default is checking on. | |||
|
75 | ; NoVitalCheck = 1 | |||
|
76 | ||||
|
77 | ; Ignore VITAL compliance checking errors. Default is to not ignore. | |||
|
78 | ; IgnoreVitalErrors = 1 | |||
|
79 | ||||
|
80 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. | |||
|
81 | ; Show_VitalChecksWarnings = 0 | |||
|
82 | ||||
|
83 | ; Keep silent about case statement static warnings. | |||
|
84 | ; Default is to give a warning. | |||
|
85 | ; NoCaseStaticError = 1 | |||
|
86 | ||||
|
87 | ; Keep silent about warnings caused by aggregates that are not locally static. | |||
|
88 | ; Default is to give a warning. | |||
|
89 | ; NoOthersStaticError = 1 | |||
|
90 | ||||
|
91 | ; Turn off inclusion of debugging info within design units. | |||
|
92 | ; Default is to include debugging info. | |||
|
93 | ; NoDebug = 1 | |||
|
94 | ||||
|
95 | ; Turn off "Loading..." messages. Default is messages on. | |||
|
96 | ; Quiet = 1 | |||
|
97 | ||||
|
98 | ; Turn on some limited synthesis rule compliance checking. Checks only: | |||
|
99 | ; -- signals used (read) by a process must be in the sensitivity list | |||
|
100 | ; CheckSynthesis = 1 | |||
|
101 | ||||
|
102 | ; Activate optimizations on expressions that do not involve signals, | |||
|
103 | ; waits, or function/procedure/task invocations. Default is off. | |||
|
104 | ; ScalarOpts = 1 | |||
|
105 | ||||
|
106 | ; Require the user to specify a configuration for all bindings, | |||
|
107 | ; and do not generate a compile time default binding for the | |||
|
108 | ; component. This will result in an elaboration error of | |||
|
109 | ; 'component not bound' if the user fails to do so. Avoids the rare | |||
|
110 | ; issue of a false dependency upon the unused default binding. | |||
|
111 | ; RequireConfigForAllDefaultBinding = 1 | |||
|
112 | ||||
|
113 | ; Inhibit range checking on subscripts of arrays. Range checking on | |||
|
114 | ; scalars defined with subtypes is inhibited by default. | |||
|
115 | ; NoIndexCheck = 1 | |||
|
116 | ||||
|
117 | ; Inhibit range checks on all (implicit and explicit) assignments to | |||
|
118 | ; scalar objects defined with subtypes. | |||
|
119 | ; NoRangeCheck = 1 | |||
|
120 | ||||
|
121 | [vlog] | |||
|
122 | ||||
|
123 | ; Turn off inclusion of debugging info within design units. | |||
|
124 | ; Default is to include debugging info. | |||
|
125 | ; NoDebug = 1 | |||
|
126 | ||||
|
127 | ; Turn off "loading..." messages. Default is messages on. | |||
|
128 | ; Quiet = 1 | |||
|
129 | ||||
|
130 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). | |||
|
131 | ; Default is off. | |||
|
132 | ; Hazard = 1 | |||
|
133 | ||||
|
134 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case | |||
|
135 | ; insensitivity for module names. Default is no conversion. | |||
|
136 | ; UpCase = 1 | |||
|
137 | ||||
|
138 | ; Turn on incremental compilation of modules. Default is off. | |||
|
139 | ; Incremental = 1 | |||
|
140 | ||||
|
141 | ; Turns on lint-style checking. | |||
|
142 | ; Show_Lint = 1 | |||
|
143 | ||||
|
144 | [vsim] | |||
|
145 | ; Simulator resolution | |||
|
146 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. | |||
|
147 | Resolution = ps | |||
|
148 | ||||
|
149 | ; User time unit for run commands | |||
|
150 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the | |||
|
151 | ; unit specified for Resolution. For example, if Resolution is 100ps, | |||
|
152 | ; then UserTimeUnit defaults to ps. | |||
|
153 | ; Should generally be set to default. | |||
|
154 | UserTimeUnit = default | |||
|
155 | ||||
|
156 | ; Default run length | |||
|
157 | RunLength = 100 | |||
|
158 | ||||
|
159 | ; Maximum iterations that can be run without advancing simulation time | |||
|
160 | IterationLimit = 5000 | |||
|
161 | ||||
|
162 | ; Directive to license manager: | |||
|
163 | ; vhdl Immediately reserve a VHDL license | |||
|
164 | ; vlog Immediately reserve a Verilog license | |||
|
165 | ; plus Immediately reserve a VHDL and Verilog license | |||
|
166 | ; nomgc Do not look for Mentor Graphics Licenses | |||
|
167 | ; nomti Do not look for Model Technology Licenses | |||
|
168 | ; noqueue Do not wait in the license queue when a license isn't available | |||
|
169 | ; viewsim Try for viewer license but accept simulator license(s) instead | |||
|
170 | ; of queuing for viewer license | |||
|
171 | ; License = plus | |||
|
172 | ||||
|
173 | ; Stop the simulator after a VHDL/Verilog assertion message | |||
|
174 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal | |||
|
175 | BreakOnAssertion = 3 | |||
|
176 | ||||
|
177 | ; Assertion Message Format | |||
|
178 | ; %S - Severity Level | |||
|
179 | ; %R - Report Message | |||
|
180 | ; %T - Time of assertion | |||
|
181 | ; %D - Delta | |||
|
182 | ; %I - Instance or Region pathname (if available) | |||
|
183 | ; %% - print '%' character | |||
|
184 | ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" | |||
|
185 | ||||
|
186 | ; Assertion File - alternate file for storing VHDL/Verilog assertion messages | |||
|
187 | ; AssertFile = assert.log | |||
|
188 | ||||
|
189 | ; Default radix for all windows and commands... | |||
|
190 | ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned | |||
|
191 | DefaultRadix = symbolic | |||
|
192 | ||||
|
193 | ; VSIM Startup command | |||
|
194 | ; Startup = do startup.do | |||
|
195 | ||||
|
196 | ; File for saving command transcript | |||
|
197 | TranscriptFile = transcript | |||
|
198 | ||||
|
199 | ; File for saving command history | |||
|
200 | ; CommandHistory = cmdhist.log | |||
|
201 | ||||
|
202 | ; Specify whether paths in simulator commands should be described | |||
|
203 | ; in VHDL or Verilog format. | |||
|
204 | ; For VHDL, PathSeparator = / | |||
|
205 | ; For Verilog, PathSeparator = . | |||
|
206 | ; Must not be the same character as DatasetSeparator. | |||
|
207 | PathSeparator = / | |||
|
208 | ||||
|
209 | ; Specify the dataset separator for fully rooted contexts. | |||
|
210 | ; The default is ':'. For example, sim:/top | |||
|
211 | ; Must not be the same character as PathSeparator. | |||
|
212 | DatasetSeparator = : | |||
|
213 | ||||
|
214 | ; Disable VHDL assertion messages | |||
|
215 | ; IgnoreNote = 1 | |||
|
216 | ; IgnoreWarning = 1 | |||
|
217 | ; IgnoreError = 1 | |||
|
218 | ; IgnoreFailure = 1 | |||
|
219 | ||||
|
220 | ; Default force kind. May be freeze, drive, deposit, or default | |||
|
221 | ; or in other terms, fixed, wired, or charged. | |||
|
222 | ; A value of "default" will use the signal kind to determine the | |||
|
223 | ; force kind, drive for resolved signals, freeze for unresolved signals | |||
|
224 | ; DefaultForceKind = freeze | |||
|
225 | ||||
|
226 | ; If zero, open files when elaborated; otherwise, open files on | |||
|
227 | ; first read or write. Default is 0. | |||
|
228 | ; DelayFileOpen = 1 | |||
|
229 | ||||
|
230 | ; Control VHDL files opened for write. | |||
|
231 | ; 0 = Buffered, 1 = Unbuffered | |||
|
232 | UnbufferedOutput = 0 | |||
|
233 | ||||
|
234 | ; Control the number of VHDL files open concurrently. | |||
|
235 | ; This number should always be less than the current ulimit | |||
|
236 | ; setting for max file descriptors. | |||
|
237 | ; 0 = unlimited | |||
|
238 | ConcurrentFileLimit = 40 | |||
|
239 | ||||
|
240 | ; Control the number of hierarchical regions displayed as | |||
|
241 | ; part of a signal name shown in the Wave window. | |||
|
242 | ; A value of zero tells VSIM to display the full name. | |||
|
243 | ; The default is 0. | |||
|
244 | ; WaveSignalNameWidth = 0 | |||
|
245 | ||||
|
246 | ; Turn off warnings from the std_logic_arith, std_logic_unsigned | |||
|
247 | ; and std_logic_signed packages. | |||
|
248 | ; StdArithNoWarnings = 1 | |||
|
249 | ||||
|
250 | ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. | |||
|
251 | ; NumericStdNoWarnings = 1 | |||
|
252 | ||||
|
253 | ; Control the format of the (VHDL) FOR generate statement label | |||
|
254 | ; for each iteration. Do not quote it. | |||
|
255 | ; The format string here must contain the conversion codes %s and %d, | |||
|
256 | ; in that order, and no other conversion codes. The %s represents | |||
|
257 | ; the generate_label; the %d represents the generate parameter value | |||
|
258 | ; at a particular generate iteration (this is the position number if | |||
|
259 | ; the generate parameter is of an enumeration type). Embedded whitespace | |||
|
260 | ; is allowed (but discouraged); leading and trailing whitespace is ignored. | |||
|
261 | ; Application of the format must result in a unique scope name over all | |||
|
262 | ; such names in the design so that name lookup can function properly. | |||
|
263 | ; GenerateFormat = %s__%d | |||
|
264 | ||||
|
265 | ; Specify whether checkpoint files should be compressed. | |||
|
266 | ; The default is 1 (compressed). | |||
|
267 | ; CheckpointCompressMode = 0 | |||
|
268 | ||||
|
269 | ; List of dynamically loaded objects for Verilog PLI applications | |||
|
270 | ; Veriuser = veriuser.sl | |||
|
271 | ||||
|
272 | ; Specify default options for the restart command. Options can be one | |||
|
273 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave | |||
|
274 | ; DefaultRestartOptions = -force | |||
|
275 | ||||
|
276 | ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs | |||
|
277 | ; (> 500 megabyte memory footprint). Default is disabled. | |||
|
278 | ; Specify number of megabytes to lock. | |||
|
279 | ; LockedMemory = 1000 | |||
|
280 | ||||
|
281 | ; Turn on (1) or off (0) WLF file compression. | |||
|
282 | ; The default is 1 (compress WLF file). | |||
|
283 | ; WLFCompress = 0 | |||
|
284 | ||||
|
285 | ; Specify whether to save all design hierarchy (1) in the WLF file | |||
|
286 | ; or only regions containing logged signals (0). | |||
|
287 | ; The default is 0 (save only regions with logged signals). | |||
|
288 | ; WLFSaveAllRegions = 1 | |||
|
289 | ||||
|
290 | ; WLF file time limit. Limit WLF file by time, as closely as possible, | |||
|
291 | ; to the specified amount of simulation time. When the limit is exceeded | |||
|
292 | ; the earliest times get truncated from the file. | |||
|
293 | ; If both time and size limits are specified the most restrictive is used. | |||
|
294 | ; UserTimeUnits are used if time units are not specified. | |||
|
295 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} | |||
|
296 | ; WLFTimeLimit = 0 | |||
|
297 | ||||
|
298 | ; WLF file size limit. Limit WLF file size, as closely as possible, | |||
|
299 | ; to the specified number of megabytes. If both time and size limits | |||
|
300 | ; are specified then the most restrictive is used. | |||
|
301 | ; The default is 0 (no limit). | |||
|
302 | ; WLFSizeLimit = 1000 | |||
|
303 | ||||
|
304 | ; Specify whether or not a WLF file should be deleted when the | |||
|
305 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. | |||
|
306 | ; The default is 0 (do not delete WLF file when simulation ends). | |||
|
307 | ; WLFDeleteOnQuit = 1 | |||
|
308 | ||||
|
309 | ; Automatic SDF compilation | |||
|
310 | ; Disables automatic compilation of SDF files in flows that support it. | |||
|
311 | ; Default is on, uncomment to turn off. | |||
|
312 | ; NoAutoSDFCompile = 1 | |||
|
313 | ||||
|
314 | [lmc] | |||
|
315 | ||||
|
316 | [msg_system] | |||
|
317 | ; Change a message severity or suppress a message. | |||
|
318 | ; The format is: <msg directive> = <msg number>[,<msg number>...] | |||
|
319 | ; Examples: | |||
|
320 | ; note = 3009 | |||
|
321 | ; warning = 3033 | |||
|
322 | ; error = 3010,3016 | |||
|
323 | ; fatal = 3016,3033 | |||
|
324 | ; suppress = 3009,3016,3043 | |||
|
325 | ; The command verror <msg number> can be used to get the complete | |||
|
326 | ; description of a message. | |||
|
327 | ||||
|
328 | ; Control transcripting of elaboration/runtime messages. | |||
|
329 | ; The default is to have messages appear in the transcript and | |||
|
330 | ; recorded in the wlf file (messages that are recorded in the | |||
|
331 | ; wlf file can be viewed in the MsgViewer). The other settings | |||
|
332 | ; are to send messages only to the transcript or only to the | |||
|
333 | ; wlf file. The valid values are | |||
|
334 | ; both {default} | |||
|
335 | ; tran {transcript only} | |||
|
336 | ; wlf {wlf file only} | |||
|
337 | ; msgmode = both |
@@ -0,0 +1,30 | |||||
|
1 | vlib staging_lpp | |||
|
2 | vmap staging_lpp "staging_lpp" | |||
|
3 | ||||
|
4 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/general_purpose.vhd" | |||
|
5 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_CONTROLER.vhd" | |||
|
6 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/Multiplier.vhd" | |||
|
7 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/Adder.vhd" | |||
|
8 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/TwoComplementer.vhd" | |||
|
9 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_REG.vhd" | |||
|
10 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX.vhd" | |||
|
11 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX2.vhd" | |||
|
12 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC.vhd" | |||
|
13 | vcom -93 -explicit -work staging_lpp "../../../general_purpose/ALU.vhd" | |||
|
14 | ||||
|
15 | vcom -93 -explicit -work staging_lpp "../lpp_fft.vhd" | |||
|
16 | vcom -93 -explicit -work staging_lpp "../LPP_BUTTERFLY_DATAFLOW.vhd" | |||
|
17 | vcom -93 -explicit -work staging_lpp "../BUTTERFLY_CTRL.vhd" | |||
|
18 | vcom -93 -explicit -work staging_lpp "../BUTTERFLY_TOP.vhd" | |||
|
19 | vcom -93 -explicit -work staging_lpp "testBench_BUTTERFLY_TOP.vhd" | |||
|
20 | ||||
|
21 | vsim -L staging_lpp -t 1ps staging_lpp.TestBench_BUTTERFLY_TOP | |||
|
22 | ||||
|
23 | do wave.do | |||
|
24 | ||||
|
25 | log -R * | |||
|
26 | ||||
|
27 | run 1 us | |||
|
28 | # The following lines are commented because no testbench is associated with the project | |||
|
29 | # add wave /testbench/* | |||
|
30 | # run 1000ns |
@@ -0,0 +1,436 | |||||
|
1 | m255 | |||
|
2 | K3 | |||
|
3 | 13 | |||
|
4 | cModel Technology | |||
|
5 | Z0 dC:\VHDL\VHD_Lib-next\lib\staging\LPP\PLE\dsp\lpp_fft\test | |||
|
6 | Eadder | |||
|
7 | Z1 w1367492167 | |||
|
8 | Z2 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2 | |||
|
9 | Z3 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3 | |||
|
10 | Z4 dC:\VHDL\VHD_Lib-next\lib\staging\LPP\PLE\dsp\lpp_fft\test | |||
|
11 | Z5 8../../../general_purpose/Adder.vhd | |||
|
12 | Z6 F../../../general_purpose/Adder.vhd | |||
|
13 | l0 | |||
|
14 | L26 | |||
|
15 | VoFM@XeC8`dJE];FJ5EZS62 | |||
|
16 | Z7 OW;C;6.6d;45 | |||
|
17 | 31 | |||
|
18 | Z8 o-93 -explicit -work staging_lpp -O0 | |||
|
19 | Z9 tExplicit 1 | |||
|
20 | !s100 HIfJMPNI[=_daW0bOn4B93 | |||
|
21 | Aar_adder | |||
|
22 | R2 | |||
|
23 | R3 | |||
|
24 | DEx4 work 5 adder 0 22 oFM@XeC8`dJE];FJ5EZS62 | |||
|
25 | l52 | |||
|
26 | L47 | |||
|
27 | V76IAS<9VXz9KglW`AJ8Ld3 | |||
|
28 | R7 | |||
|
29 | 31 | |||
|
30 | Z10 Mx2 4 ieee 11 numeric_std | |||
|
31 | Z11 Mx1 4 ieee 14 std_logic_1164 | |||
|
32 | R8 | |||
|
33 | R9 | |||
|
34 | !s100 J=IZ]JXJGi7g8KE`DCYDk0 | |||
|
35 | Ealu | |||
|
36 | Z12 w1387453255 | |||
|
37 | Z13 DPx11 staging_lpp 19 ple_general_purpose 0 22 GgYZoG1iL[;Q6W7i9@@LK1 | |||
|
38 | R2 | |||
|
39 | R3 | |||
|
40 | R4 | |||
|
41 | Z14 8../../../general_purpose/ALU.vhd | |||
|
42 | Z15 F../../../general_purpose/ALU.vhd | |||
|
43 | l0 | |||
|
44 | L30 | |||
|
45 | VmEg_D0fVB_ZV1@FBk@aFd2 | |||
|
46 | R7 | |||
|
47 | 31 | |||
|
48 | R8 | |||
|
49 | R9 | |||
|
50 | !s100 1nho@1aIf]5_E]d?WEDL92 | |||
|
51 | Aar_alu | |||
|
52 | R13 | |||
|
53 | R2 | |||
|
54 | R3 | |||
|
55 | DEx4 work 3 alu 0 22 mEg_D0fVB_ZV1@FBk@aFd2 | |||
|
56 | l57 | |||
|
57 | L55 | |||
|
58 | VWjUk_]b@Sk^TfG4X_9Oc;2 | |||
|
59 | R7 | |||
|
60 | 31 | |||
|
61 | Z16 Mx3 4 ieee 11 numeric_std | |||
|
62 | Z17 Mx2 4 ieee 14 std_logic_1164 | |||
|
63 | Z18 Mx1 11 staging_lpp 19 ple_general_purpose | |||
|
64 | R8 | |||
|
65 | R9 | |||
|
66 | !s100 X]Y0>a4c6R:;@zlk5miIO2 | |||
|
67 | Ebutterfly_ctrl | |||
|
68 | Z19 w1387452436 | |||
|
69 | Z20 DPx11 staging_lpp 11 ple_lpp_fft 0 22 f<h7ZP]5PX4>R89[BSncW2 | |||
|
70 | R13 | |||
|
71 | R2 | |||
|
72 | R3 | |||
|
73 | R4 | |||
|
74 | Z21 8../BUTTERFLY_CTRL.vhd | |||
|
75 | Z22 F../BUTTERFLY_CTRL.vhd | |||
|
76 | l0 | |||
|
77 | L32 | |||
|
78 | VkQ?Y4JTf@DHzClk;BN8m?2 | |||
|
79 | R7 | |||
|
80 | 31 | |||
|
81 | R8 | |||
|
82 | R9 | |||
|
83 | !s100 OFBC17;8gEg8J^PPd26]^0 | |||
|
84 | Aar_butterfly_ctrl | |||
|
85 | R20 | |||
|
86 | R13 | |||
|
87 | R2 | |||
|
88 | R3 | |||
|
89 | DEx4 work 14 butterfly_ctrl 0 22 kQ?Y4JTf@DHzClk;BN8m?2 | |||
|
90 | l66 | |||
|
91 | L49 | |||
|
92 | VUOBVXO?RLc>P4cLYnIOJK3 | |||
|
93 | R7 | |||
|
94 | 31 | |||
|
95 | Z23 Mx4 4 ieee 11 numeric_std | |||
|
96 | Z24 Mx3 4 ieee 14 std_logic_1164 | |||
|
97 | Z25 Mx2 11 staging_lpp 19 ple_general_purpose | |||
|
98 | Z26 Mx1 11 staging_lpp 11 ple_lpp_fft | |||
|
99 | R8 | |||
|
100 | R9 | |||
|
101 | !s100 6jJJ^<^7KVK9YiOCAmAfk1 | |||
|
102 | Ebutterfly_dataflow | |||
|
103 | Z27 w1387454361 | |||
|
104 | R13 | |||
|
105 | R2 | |||
|
106 | R3 | |||
|
107 | R4 | |||
|
108 | Z28 8../LPP_BUTTERFLY_DATAFLOW.vhd | |||
|
109 | Z29 F../LPP_BUTTERFLY_DATAFLOW.vhd | |||
|
110 | l0 | |||
|
111 | L29 | |||
|
112 | VI`_;hfaYCNQ1Zkm5<`LHT3 | |||
|
113 | R7 | |||
|
114 | 31 | |||
|
115 | R8 | |||
|
116 | R9 | |||
|
117 | !s100 I>e@N:Zca9<ZOHLLWOFMc2 | |||
|
118 | Aar_butterfly_dataflow | |||
|
119 | R13 | |||
|
120 | R2 | |||
|
121 | R3 | |||
|
122 | DEx4 work 18 butterfly_dataflow 0 22 I`_;hfaYCNQ1Zkm5<`LHT3 | |||
|
123 | l69 | |||
|
124 | L58 | |||
|
125 | V9jb[@[oeF?z?6BZP=Db;:2 | |||
|
126 | R7 | |||
|
127 | 31 | |||
|
128 | R16 | |||
|
129 | R17 | |||
|
130 | R18 | |||
|
131 | R8 | |||
|
132 | R9 | |||
|
133 | !s100 ]RTo^ViMemeIA;L0:4EiO2 | |||
|
134 | Ebutterfly_top | |||
|
135 | Z30 w1387454433 | |||
|
136 | R20 | |||
|
137 | R13 | |||
|
138 | R2 | |||
|
139 | R3 | |||
|
140 | R4 | |||
|
141 | Z31 8../BUTTERFLY_TOP.vhd | |||
|
142 | Z32 F../BUTTERFLY_TOP.vhd | |||
|
143 | l0 | |||
|
144 | L31 | |||
|
145 | Vk:EL]Kgc6lPW6FVMb6M=c1 | |||
|
146 | R7 | |||
|
147 | 31 | |||
|
148 | R8 | |||
|
149 | R9 | |||
|
150 | !s100 zDSRB=<7mP`35NFaM3k;d2 | |||
|
151 | Aar_butterfly_top | |||
|
152 | R20 | |||
|
153 | R13 | |||
|
154 | R2 | |||
|
155 | R3 | |||
|
156 | DEx4 work 13 butterfly_top 0 22 k:EL]Kgc6lPW6FVMb6M=c1 | |||
|
157 | l67 | |||
|
158 | L59 | |||
|
159 | VJQVgjbV4Dbd?2l5^]><VR2 | |||
|
160 | !s100 1WiJUEMk^A1MjhRPz66P_1 | |||
|
161 | R7 | |||
|
162 | 31 | |||
|
163 | R23 | |||
|
164 | R24 | |||
|
165 | R25 | |||
|
166 | R26 | |||
|
167 | R8 | |||
|
168 | R9 | |||
|
169 | Emac | |||
|
170 | Z33 w1387453300 | |||
|
171 | R13 | |||
|
172 | R2 | |||
|
173 | R3 | |||
|
174 | R4 | |||
|
175 | Z34 8../../../general_purpose/MAC.vhd | |||
|
176 | Z35 F../../../general_purpose/MAC.vhd | |||
|
177 | l0 | |||
|
178 | L32 | |||
|
179 | Vz:J>WlmWN@nE@`EDad]Cf2 | |||
|
180 | R7 | |||
|
181 | 31 | |||
|
182 | R8 | |||
|
183 | R9 | |||
|
184 | !s100 22G:]MmP6`P]S5a<^zaIG3 | |||
|
185 | Aar_mac | |||
|
186 | R13 | |||
|
187 | R2 | |||
|
188 | R3 | |||
|
189 | DEx4 work 3 mac 0 22 z:J>WlmWN@nE@`EDad]Cf2 | |||
|
190 | l86 | |||
|
191 | L54 | |||
|
192 | V3nAA^GI7Ym8m@PF<9[<a_0 | |||
|
193 | R7 | |||
|
194 | 31 | |||
|
195 | R16 | |||
|
196 | R17 | |||
|
197 | R18 | |||
|
198 | R8 | |||
|
199 | R9 | |||
|
200 | !s100 [;@eekK>0=cIVS2X`8MPG0 | |||
|
201 | Emac_controler | |||
|
202 | R1 | |||
|
203 | R2 | |||
|
204 | R3 | |||
|
205 | R4 | |||
|
206 | Z36 8../../../general_purpose/MAC_CONTROLER.vhd | |||
|
207 | Z37 F../../../general_purpose/MAC_CONTROLER.vhd | |||
|
208 | l0 | |||
|
209 | L29 | |||
|
210 | V3F`]dJZY][ZC4@mMDbUjF1 | |||
|
211 | R7 | |||
|
212 | 31 | |||
|
213 | R8 | |||
|
214 | R9 | |||
|
215 | !s100 AEHI=CKBB^Y`BRI6Wkb653 | |||
|
216 | Aar_mac_controler | |||
|
217 | R2 | |||
|
218 | R3 | |||
|
219 | DEx4 work 13 mac_controler 0 22 3F`]dJZY][ZC4@mMDbUjF1 | |||
|
220 | l47 | |||
|
221 | L45 | |||
|
222 | VYKjYF<4O[WUG`U:VRF4<F1 | |||
|
223 | R7 | |||
|
224 | 31 | |||
|
225 | R10 | |||
|
226 | R11 | |||
|
227 | R8 | |||
|
228 | R9 | |||
|
229 | !s100 1L?0[RS=fbiUd8o?JRAiJ0 | |||
|
230 | Emac_mux | |||
|
231 | R1 | |||
|
232 | R2 | |||
|
233 | R3 | |||
|
234 | R4 | |||
|
235 | Z38 8../../../general_purpose/MAC_MUX.vhd | |||
|
236 | Z39 F../../../general_purpose/MAC_MUX.vhd | |||
|
237 | l0 | |||
|
238 | L26 | |||
|
239 | V=[k`JBkCz>0=MgDKG1ihL1 | |||
|
240 | R7 | |||
|
241 | 31 | |||
|
242 | R8 | |||
|
243 | R9 | |||
|
244 | !s100 VY:^W494N<Y1A=ES9nhFi3 | |||
|
245 | Aar_mac_mux | |||
|
246 | R2 | |||
|
247 | R3 | |||
|
248 | DEx4 work 7 mac_mux 0 22 =[k`JBkCz>0=MgDKG1ihL1 | |||
|
249 | l48 | |||
|
250 | L46 | |||
|
251 | VY>F?32o4EN<;M8QdcmA>e3 | |||
|
252 | R7 | |||
|
253 | 31 | |||
|
254 | R10 | |||
|
255 | R11 | |||
|
256 | R8 | |||
|
257 | R9 | |||
|
258 | !s100 <4^2O;J:P]mD1VL;cC1fD0 | |||
|
259 | Emac_mux2 | |||
|
260 | R1 | |||
|
261 | R2 | |||
|
262 | R3 | |||
|
263 | R4 | |||
|
264 | Z40 8../../../general_purpose/MAC_MUX2.vhd | |||
|
265 | Z41 F../../../general_purpose/MAC_MUX2.vhd | |||
|
266 | l0 | |||
|
267 | L27 | |||
|
268 | V^N``KIm1zV?_lMP8EliHk2 | |||
|
269 | R7 | |||
|
270 | 31 | |||
|
271 | R8 | |||
|
272 | R9 | |||
|
273 | !s100 TE[`n?T8Qd3^G^XaQFk5m1 | |||
|
274 | Aar_mac_mux2 | |||
|
275 | R2 | |||
|
276 | R3 | |||
|
277 | DEx4 work 8 mac_mux2 0 22 ^N``KIm1zV?_lMP8EliHk2 | |||
|
278 | l42 | |||
|
279 | L40 | |||
|
280 | VhnJjfYH]b0mK:U5e86_Y93 | |||
|
281 | R7 | |||
|
282 | 31 | |||
|
283 | R10 | |||
|
284 | R11 | |||
|
285 | R8 | |||
|
286 | R9 | |||
|
287 | !s100 k<jPd;^:@^bWDF>W7HO<H2 | |||
|
288 | Emac_reg | |||
|
289 | R1 | |||
|
290 | R2 | |||
|
291 | R3 | |||
|
292 | R4 | |||
|
293 | Z42 8../../../general_purpose/MAC_REG.vhd | |||
|
294 | Z43 F../../../general_purpose/MAC_REG.vhd | |||
|
295 | l0 | |||
|
296 | L26 | |||
|
297 | V2ciJdFnYB6EEZEC2GLc_z1 | |||
|
298 | R7 | |||
|
299 | 31 | |||
|
300 | R8 | |||
|
301 | R9 | |||
|
302 | !s100 kXk_2M@5koRY^4=;=B5n<2 | |||
|
303 | Aar_mac_reg | |||
|
304 | R2 | |||
|
305 | R3 | |||
|
306 | DEx4 work 7 mac_reg 0 22 2ciJdFnYB6EEZEC2GLc_z1 | |||
|
307 | l39 | |||
|
308 | L38 | |||
|
309 | VB[9zMRU>Q26jFZ8lM42Fj3 | |||
|
310 | R7 | |||
|
311 | 31 | |||
|
312 | R10 | |||
|
313 | R11 | |||
|
314 | R8 | |||
|
315 | R9 | |||
|
316 | !s100 7LMbI<5IG<5UVHOI:=m>Y2 | |||
|
317 | Emultiplier | |||
|
318 | R1 | |||
|
319 | R2 | |||
|
320 | R3 | |||
|
321 | R4 | |||
|
322 | Z44 8../../../general_purpose/Multiplier.vhd | |||
|
323 | Z45 F../../../general_purpose/Multiplier.vhd | |||
|
324 | l0 | |||
|
325 | L26 | |||
|
326 | VGSdU:4<=H75L72@<e3jZY0 | |||
|
327 | R7 | |||
|
328 | 31 | |||
|
329 | R8 | |||
|
330 | R9 | |||
|
331 | !s100 5OhAd4m5P@V?>b^FY2MR80 | |||
|
332 | Aar_multiplier | |||
|
333 | R2 | |||
|
334 | R3 | |||
|
335 | DEx4 work 10 multiplier 0 22 GSdU:4<=H75L72@<e3jZY0 | |||
|
336 | l52 | |||
|
337 | L46 | |||
|
338 | Vj]Tio_1A9KeM65>kBeBz42 | |||
|
339 | R7 | |||
|
340 | 31 | |||
|
341 | R10 | |||
|
342 | R11 | |||
|
343 | R8 | |||
|
344 | R9 | |||
|
345 | !s100 1GiXjgO@4a3lmRe?YB9lz2 | |||
|
346 | Pple_general_purpose | |||
|
347 | R2 | |||
|
348 | w1387453210 | |||
|
349 | R4 | |||
|
350 | 8../../../general_purpose/general_purpose.vhd | |||
|
351 | F../../../general_purpose/general_purpose.vhd | |||
|
352 | l0 | |||
|
353 | L31 | |||
|
354 | VGgYZoG1iL[;Q6W7i9@@LK1 | |||
|
355 | R7 | |||
|
356 | 31 | |||
|
357 | R11 | |||
|
358 | R8 | |||
|
359 | R9 | |||
|
360 | !s100 bfW]gJ3gFYVT@iCLKo6Xm2 | |||
|
361 | Pple_lpp_fft | |||
|
362 | R2 | |||
|
363 | w1387452424 | |||
|
364 | R4 | |||
|
365 | 8../lpp_fft.vhd | |||
|
366 | F../lpp_fft.vhd | |||
|
367 | l0 | |||
|
368 | L27 | |||
|
369 | Vf<h7ZP]5PX4>R89[BSncW2 | |||
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376 | Etestbench_butterfly_top | |||
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382 | Z47 8testBench_BUTTERFLY_TOP.vhd | |||
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383 | Z48 FtestBench_BUTTERFLY_TOP.vhd | |||
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384 | l0 | |||
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385 | L29 | |||
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386 | V1NXi==_N]Mcd]D[Rf<oil3 | |||
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396 | Z49 DEx4 work 23 testbench_butterfly_top 0 22 1NXi==_N]Mcd]D[Rf<oil3 | |||
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414 | Z54 F../../../general_purpose/TwoComplementer.vhd | |||
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415 | l0 | |||
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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Paul Leroy | |||
|
20 | -- Mail : paul.leroy@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
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22 | library IEEE; | |||
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23 | use IEEE.numeric_std.all; | |||
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24 | use IEEE.std_logic_1164.all; | |||
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25 | ||||
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26 | library staging_lpp; | |||
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27 | use staging_lpp.PLE_lpp_fft.all; | |||
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28 | ||||
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29 | entity TestBench_BUTTERFLY_TOP is | |||
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30 | ||||
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31 | end TestBench_BUTTERFLY_TOP; | |||
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32 | ||||
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33 | architecture TestBench_BUTTERFLY_TOP of TestBench_BUTTERFLY_TOP is | |||
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34 | ||||
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35 | constant Sample_SZ : integer := 16; | |||
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36 | ||||
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37 | signal clk : std_logic:='0'; | |||
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38 | signal rstn : std_logic:='0'; | |||
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39 | ||||
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40 | signal Are : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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41 | signal Aim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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42 | signal Bre : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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43 | signal Bim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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44 | signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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45 | signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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46 | signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); | |||
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47 | ||||
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48 | signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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49 | signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); | |||
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50 | signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); | |||
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51 | signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); | |||
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52 | ||||
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53 | signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 ); | |||
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54 | ||||
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55 | signal sel_out : std_logic_vector( 4 downto 0 ); | |||
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56 | ||||
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57 | signal sample_in_val : std_logic := '0'; | |||
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58 | signal sample_out_val : std_logic; | |||
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59 | ||||
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60 | begin | |||
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61 | ||||
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62 | BUTTERFLY_TOP1 : BUTTERFLY_TOP | |||
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63 | generic map( | |||
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64 | Sample_SZ => Sample_SZ | |||
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65 | ) | |||
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66 | port map( | |||
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67 | rstn => rstn, | |||
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68 | clk => clk, | |||
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69 | ||||
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70 | sample_in_val => sample_in_val, | |||
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71 | sample_out_val => sample_out_val, | |||
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72 | ||||
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73 | Are => Are, | |||
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74 | Aim => Aim, | |||
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75 | Bre => Bre, | |||
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76 | Bim => Bim, | |||
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77 | c_in => c, | |||
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78 | cps_in => cps, | |||
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79 | cms_in => cms, | |||
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80 | ||||
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81 | op1 => op1, | |||
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82 | op2 => op2, | |||
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83 | alu_ctrl => alu_ctrl_sig, | |||
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84 | alu_comp => alu_comp_sig, | |||
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85 | ||||
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86 | butterfly_out => Resultat, | |||
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87 | sel_out => sel_out | |||
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88 | ); | |||
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89 | ||||
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90 | clk <= not clk after 25 ns; | |||
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91 | ||||
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92 | process | |||
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93 | begin | |||
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94 | ||||
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95 | wait for 40 ns; | |||
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96 | rstn <= '1'; | |||
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97 | ||||
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98 | wait for 11 ns; | |||
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99 | Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ)); | |||
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100 | Aim <= std_logic_vector(TO_SIGNED(110 ,Sample_SZ)); | |||
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101 | Bre <= std_logic_vector(TO_SIGNED(-40 ,Sample_SZ)); | |||
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102 | Bim <= std_logic_vector(TO_SIGNED(10 ,Sample_SZ)); | |||
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103 | c <= std_logic_vector(TO_SIGNED(121 ,Sample_SZ)); | |||
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104 | cps <= std_logic_vector(TO_SIGNED(160 ,Sample_SZ)); | |||
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105 | cms <= std_logic_vector(TO_SIGNED(82 ,Sample_SZ)); | |||
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106 | ||||
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107 | wait for 50 ns; | |||
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108 | sample_in_val <= '1'; | |||
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109 | ||||
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110 | end process; | |||
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111 | ||||
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112 | end TestBench_BUTTERFLY_TOP; |
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1 | onerror {resume} | |||
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2 | quietly WaveActivateNextPane {} 0 | |||
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3 | add wave -noupdate /testbench_butterfly_top/are | |||
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4 | add wave -noupdate -divider TOTO | |||
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5 | add wave -noupdate /testbench_butterfly_top/aim | |||
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6 | add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op2 | |||
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7 | add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op1 | |||
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8 | TreeUpdate [SetDefaultTree] | |||
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9 | WaveRestoreCursors {{Cursor 1} {0 ps} 0} | |||
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10 | configure wave -namecolwidth 226 | |||
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11 | configure wave -valuecolwidth 100 | |||
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12 | configure wave -justifyvalue left | |||
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13 | configure wave -signalnamewidth 0 | |||
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14 | configure wave -snapdistance 10 | |||
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15 | configure wave -datasetprefix 0 | |||
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16 | configure wave -rowmargin 4 | |||
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17 | configure wave -childrowmargin 2 | |||
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18 | configure wave -gridoffset 0 | |||
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19 | configure wave -gridperiod 1000 | |||
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20 | configure wave -griddelta 40 | |||
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21 | configure wave -timeline 0 | |||
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22 | configure wave -timelineunits ns | |||
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23 | update | |||
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24 | WaveRestoreZoom {0 ps} {1092 ps} |
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1 | --twiddle_factors_128.vhd | |||
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2 | ||||
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3 | constant Coef_SZ : integer := 16; | |||
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4 | constant NB_Coeffs : integer := 128; | |||
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5 | ||||
|
6 | --============================================================ | |||
|
7 | -- create each initial values for each coefs ============ | |||
|
8 | --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! | |||
|
9 | --============================================================ | |||
|
10 | ||||
|
11 | constant c_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
12 | constant c_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
13 | constant c_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
14 | constant c_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
15 | constant c_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
16 | constant c_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
17 | constant c_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
18 | constant c_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
19 | constant c_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
20 | constant c_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
21 | constant c_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
22 | constant c_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
23 | constant c_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
24 | constant c_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
25 | constant c_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
26 | constant c_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
27 | constant c_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
28 | constant c_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
29 | constant c_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
30 | constant c_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
31 | constant c_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
32 | constant c_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
33 | constant c_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
34 | constant c_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
35 | constant c_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
36 | constant c_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
37 | constant c_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
38 | constant c_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
39 | constant c_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
40 | constant c_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
41 | constant c_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
42 | constant c_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
43 | constant c_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
44 | constant c_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
45 | constant c_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
46 | constant c_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
47 | constant c_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
48 | constant c_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
49 | constant c_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
50 | constant c_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
51 | constant c_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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52 | constant c_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
53 | constant c_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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54 | constant c_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
55 | constant c_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
56 | constant c_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
57 | constant c_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
58 | constant c_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
59 | constant c_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
60 | constant c_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
61 | constant c_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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62 | constant c_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
63 | constant c_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
64 | constant c_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
65 | constant c_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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66 | constant c_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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67 | constant c_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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68 | constant c_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
69 | constant c_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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70 | constant c_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
71 | constant c_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
72 | constant c_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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73 | constant c_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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74 | constant c_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
75 | constant c_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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76 | constant c_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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77 | constant c_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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78 | constant c_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
79 | constant c_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
80 | constant c_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
81 | constant c_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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82 | constant c_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
83 | constant c_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
84 | constant c_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
85 | constant c_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
86 | constant c_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
87 | constant c_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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88 | constant c_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
89 | constant c_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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90 | constant c_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
91 | constant c_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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92 | constant c_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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93 | constant c_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
94 | constant c_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
95 | constant c_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
96 | constant c_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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97 | constant c_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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98 | constant c_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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99 | constant c_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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100 | constant c_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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101 | constant c_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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102 | constant c_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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103 | constant c_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
104 | constant c_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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105 | constant c_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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106 | constant c_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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107 | constant c_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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108 | constant c_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
109 | constant c_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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110 | constant c_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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111 | constant c_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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112 | constant c_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
113 | constant c_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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114 | constant c_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
115 | constant c_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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116 | constant c_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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117 | constant c_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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118 | constant c_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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119 | constant c_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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120 | constant c_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
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121 | constant c_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
122 | constant c_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
123 | constant c_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
124 | constant c_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
125 | constant c_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
126 | constant c_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
127 | constant c_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
128 | constant c_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
129 | constant c_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
130 | constant c_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
131 | constant c_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
132 | constant c_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
133 | constant c_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
134 | constant c_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
135 | constant c_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
136 | constant c_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
137 | constant c_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
138 | constant c_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ)); | |||
|
139 | ||||
|
140 | --************************************************-- | |||
|
141 | ||||
|
142 | constant cps_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
143 | constant cps_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
144 | constant cps_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
145 | constant cps_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
146 | constant cps_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
147 | constant cps_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
148 | constant cps_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
149 | constant cps_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
150 | constant cps_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
151 | constant cps_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
152 | constant cps_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
153 | constant cps_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
154 | constant cps_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
155 | constant cps_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
156 | constant cps_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
157 | constant cps_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
158 | constant cps_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
159 | constant cps_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
160 | constant cps_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
161 | constant cps_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
162 | constant cps_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
163 | constant cps_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
164 | constant cps_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
165 | constant cps_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
166 | constant cps_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
167 | constant cps_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
168 | constant cps_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
169 | constant cps_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
170 | constant cps_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
171 | constant cps_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
172 | constant cps_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
173 | constant cps_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
174 | constant cps_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
175 | constant cps_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
176 | constant cps_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
177 | constant cps_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
178 | constant cps_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
179 | constant cps_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
180 | constant cps_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
181 | constant cps_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
182 | constant cps_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
183 | constant cps_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
184 | constant cps_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
185 | constant cps_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
186 | constant cps_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
187 | constant cps_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
188 | constant cps_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
189 | constant cps_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
190 | constant cps_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
191 | constant cps_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
192 | constant cps_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
193 | constant cps_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
194 | constant cps_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
195 | constant cps_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
196 | constant cps_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
197 | constant cps_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
198 | constant cps_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
|
199 | constant cps_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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200 | constant cps_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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201 | constant cps_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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202 | constant cps_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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203 | constant cps_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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204 | constant cps_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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205 | constant cps_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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206 | constant cps_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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207 | constant cps_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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208 | constant cps_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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209 | constant cps_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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210 | constant cps_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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211 | constant cps_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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212 | constant cps_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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213 | constant cps_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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214 | constant cps_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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215 | constant cps_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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216 | constant cps_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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217 | constant cps_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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218 | constant cps_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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219 | constant cps_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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220 | constant cps_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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221 | constant cps_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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222 | constant cps_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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223 | constant cps_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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224 | constant cps_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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225 | constant cps_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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226 | constant cps_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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227 | constant cps_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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228 | constant cps_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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229 | constant cps_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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230 | constant cps_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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231 | constant cps_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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232 | constant cps_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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233 | constant cps_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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234 | constant cps_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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235 | constant cps_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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236 | constant cps_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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237 | constant cps_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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238 | constant cps_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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239 | constant cps_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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240 | constant cps_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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241 | constant cps_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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242 | constant cps_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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243 | constant cps_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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244 | constant cps_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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245 | constant cps_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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246 | constant cps_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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247 | constant cps_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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248 | constant cps_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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249 | constant cps_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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250 | constant cps_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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251 | constant cps_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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252 | constant cps_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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253 | constant cps_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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254 | constant cps_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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255 | constant cps_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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256 | constant cps_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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257 | constant cps_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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258 | constant cps_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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259 | constant cps_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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260 | constant cps_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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261 | constant cps_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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262 | constant cps_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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263 | constant cps_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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264 | constant cps_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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265 | constant cps_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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266 | constant cps_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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267 | constant cps_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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268 | constant cps_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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269 | constant cps_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ)); | |||
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270 | ||||
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271 | --************************************************-- | |||
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272 | ||||
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273 | constant cms_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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274 | constant cms_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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275 | constant cms_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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276 | constant cms_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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277 | constant cms_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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278 | constant cms_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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279 | constant cms_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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280 | constant cms_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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281 | constant cms_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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282 | constant cms_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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283 | constant cms_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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284 | constant cms_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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285 | constant cms_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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286 | constant cms_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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287 | constant cms_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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288 | constant cms_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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289 | constant cms_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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290 | constant cms_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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291 | constant cms_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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292 | constant cms_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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293 | constant cms_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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294 | constant cms_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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295 | constant cms_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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296 | constant cms_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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297 | constant cms_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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298 | constant cms_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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299 | constant cms_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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300 | constant cms_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
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301 | constant cms_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
302 | constant cms_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
303 | constant cms_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
304 | constant cms_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
305 | constant cms_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
306 | constant cms_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
307 | constant cms_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
308 | constant cms_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
309 | constant cms_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
310 | constant cms_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
311 | constant cms_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
312 | constant cms_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
313 | constant cms_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
314 | constant cms_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
315 | constant cms_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
316 | constant cms_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
317 | constant cms_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
318 | constant cms_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
319 | constant cms_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
320 | constant cms_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
321 | constant cms_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
322 | constant cms_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
323 | constant cms_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
324 | constant cms_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
325 | constant cms_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
326 | constant cms_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
327 | constant cms_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
328 | constant cms_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
329 | constant cms_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
330 | constant cms_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
331 | constant cms_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
332 | constant cms_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
333 | constant cms_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
334 | constant cms_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
335 | constant cms_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
336 | constant cms_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
337 | constant cms_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
338 | constant cms_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
339 | constant cms_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
340 | constant cms_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
341 | constant cms_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
342 | constant cms_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
343 | constant cms_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
344 | constant cms_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
345 | constant cms_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
346 | constant cms_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
347 | constant cms_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
348 | constant cms_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
349 | constant cms_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
350 | constant cms_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
351 | constant cms_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
352 | constant cms_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
353 | constant cms_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
354 | constant cms_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
355 | constant cms_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
356 | constant cms_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
357 | constant cms_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
358 | constant cms_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
359 | constant cms_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
360 | constant cms_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
361 | constant cms_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
362 | constant cms_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
363 | constant cms_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
364 | constant cms_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
365 | constant cms_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
366 | constant cms_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
367 | constant cms_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
368 | constant cms_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
369 | constant cms_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
370 | constant cms_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
371 | constant cms_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
372 | constant cms_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
373 | constant cms_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
374 | constant cms_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
375 | constant cms_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
376 | constant cms_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
377 | constant cms_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
378 | constant cms_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
379 | constant cms_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
380 | constant cms_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
381 | constant cms_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
382 | constant cms_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
383 | constant cms_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
384 | constant cms_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
385 | constant cms_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
386 | constant cms_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
387 | constant cms_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
388 | constant cms_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
389 | constant cms_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
390 | constant cms_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
391 | constant cms_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
392 | constant cms_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
393 | constant cms_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
394 | constant cms_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
395 | constant cms_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
396 | constant cms_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
397 | constant cms_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
398 | constant cms_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
399 | constant cms_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
400 | constant cms_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ)); | |||
|
401 | ||||
|
402 | --************************************************-- | |||
|
403 | ||||
|
404 | constant twiddleFactors_c : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := | |||
|
405 | ( | |||
|
406 | c_0 & c_1 & c_2 & c_3 & c_4 & c_5 & c_6 & c_7 & | |||
|
407 | c_8 & c_9 & c_10 & c_11 & c_12 & c_13 & c_14 & c_15 & | |||
|
408 | c_16 & c_17 & c_18 & c_19 & c_20 & c_21 & c_22 & c_23 & | |||
|
409 | c_24 & c_25 & c_26 & c_27 & c_28 & c_29 & c_30 & c_31 & | |||
|
410 | c_32 & c_33 & c_34 & c_35 & c_36 & c_37 & c_38 & c_39 & | |||
|
411 | c_40 & c_41 & c_42 & c_43 & c_44 & c_45 & c_46 & c_47 & | |||
|
412 | c_48 & c_49 & c_50 & c_51 & c_52 & c_53 & c_54 & c_55 & | |||
|
413 | c_56 & c_57 & c_58 & c_59 & c_60 & c_61 & c_62 & c_63 & | |||
|
414 | c_64 & c_65 & c_66 & c_67 & c_68 & c_69 & c_70 & c_71 & | |||
|
415 | c_72 & c_73 & c_74 & c_75 & c_76 & c_77 & c_78 & c_79 & | |||
|
416 | c_80 & c_81 & c_82 & c_83 & c_84 & c_85 & c_86 & c_87 & | |||
|
417 | c_88 & c_89 & c_90 & c_91 & c_92 & c_93 & c_94 & c_95 & | |||
|
418 | c_96 & c_97 & c_98 & c_99 & c_100 & c_101 & c_102 & c_103 & | |||
|
419 | c_104 & c_105 & c_106 & c_107 & c_108 & c_109 & c_110 & c_111 & | |||
|
420 | c_112 & c_113 & c_114 & c_115 & c_116 & c_117 & c_118 & c_119 & | |||
|
421 | c_120 & c_121 & c_122 & c_123 & c_124 & c_125 & c_126 & c_127 ); | |||
|
422 | ||||
|
423 | constant twiddleFactors_cps : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := | |||
|
424 | ( | |||
|
425 | cps_0 & cps_1 & cps_2 & cps_3 & cps_4 & cps_5 & cps_6 & cps_7 & | |||
|
426 | cps_8 & cps_9 & cps_10 & cps_11 & cps_12 & cps_13 & cps_14 & cps_15 & | |||
|
427 | cps_16 & cps_17 & cps_18 & cps_19 & cps_20 & cps_21 & cps_22 & cps_23 & | |||
|
428 | cps_24 & cps_25 & cps_26 & cps_27 & cps_28 & cps_29 & cps_30 & cps_31 & | |||
|
429 | cps_32 & cps_33 & cps_34 & cps_35 & cps_36 & cps_37 & cps_38 & cps_39 & | |||
|
430 | cps_40 & cps_41 & cps_42 & cps_43 & cps_44 & cps_45 & cps_46 & cps_47 & | |||
|
431 | cps_48 & cps_49 & cps_50 & cps_51 & cps_52 & cps_53 & cps_54 & cps_55 & | |||
|
432 | cps_56 & cps_57 & cps_58 & cps_59 & cps_60 & cps_61 & cps_62 & cps_63 & | |||
|
433 | cps_64 & cps_65 & cps_66 & cps_67 & cps_68 & cps_69 & cps_70 & cps_71 & | |||
|
434 | cps_72 & cps_73 & cps_74 & cps_75 & cps_76 & cps_77 & cps_78 & cps_79 & | |||
|
435 | cps_80 & cps_81 & cps_82 & cps_83 & cps_84 & cps_85 & cps_86 & cps_87 & | |||
|
436 | cps_88 & cps_89 & cps_90 & cps_91 & cps_92 & cps_93 & cps_94 & cps_95 & | |||
|
437 | cps_96 & cps_97 & cps_98 & cps_99 & cps_100 & cps_101 & cps_102 & cps_103 & | |||
|
438 | cps_104 & cps_105 & cps_106 & cps_107 & cps_108 & cps_109 & cps_110 & cps_111 & | |||
|
439 | cps_112 & cps_113 & cps_114 & cps_115 & cps_116 & cps_117 & cps_118 & cps_119 & | |||
|
440 | cps_120 & cps_121 & cps_122 & cps_123 & cps_124 & cps_125 & cps_126 & cps_127 ); | |||
|
441 | ||||
|
442 | constant twiddleFactors_cms : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) := | |||
|
443 | ( | |||
|
444 | cms_0 & cms_1 & cms_2 & cms_3 & cms_4 & cms_5 & cms_6 & cms_7 & | |||
|
445 | cms_8 & cms_9 & cms_10 & cms_11 & cms_12 & cms_13 & cms_14 & cms_15 & | |||
|
446 | cms_16 & cms_17 & cms_18 & cms_19 & cms_20 & cms_21 & cms_22 & cms_23 & | |||
|
447 | cms_24 & cms_25 & cms_26 & cms_27 & cms_28 & cms_29 & cms_30 & cms_31 & | |||
|
448 | cms_32 & cms_33 & cms_34 & cms_35 & cms_36 & cms_37 & cms_38 & cms_39 & | |||
|
449 | cms_40 & cms_41 & cms_42 & cms_43 & cms_44 & cms_45 & cms_46 & cms_47 & | |||
|
450 | cms_48 & cms_49 & cms_50 & cms_51 & cms_52 & cms_53 & cms_54 & cms_55 & | |||
|
451 | cms_56 & cms_57 & cms_58 & cms_59 & cms_60 & cms_61 & cms_62 & cms_63 & | |||
|
452 | cms_64 & cms_65 & cms_66 & cms_67 & cms_68 & cms_69 & cms_70 & cms_71 & | |||
|
453 | cms_72 & cms_73 & cms_74 & cms_75 & cms_76 & cms_77 & cms_78 & cms_79 & | |||
|
454 | cms_80 & cms_81 & cms_82 & cms_83 & cms_84 & cms_85 & cms_86 & cms_87 & | |||
|
455 | cms_88 & cms_89 & cms_90 & cms_91 & cms_92 & cms_93 & cms_94 & cms_95 & | |||
|
456 | cms_96 & cms_97 & cms_98 & cms_99 & cms_100 & cms_101 & cms_102 & cms_103 & | |||
|
457 | cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 & | |||
|
458 | cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 & | |||
|
459 | cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 ); |
@@ -0,0 +1,65 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | library staging_lpp; | |||
|
26 | use staging_lpp.PLE_general_purpose.all; | |||
|
27 | ||||
|
28 | --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration | |||
|
29 | ||||
|
30 | entity ALU is | |||
|
31 | generic( | |||
|
32 | Arith_en : integer := 1; | |||
|
33 | Logic_en : integer := 1; | |||
|
34 | Input_SZ_1 : integer := 16; | |||
|
35 | Input_SZ_2 : integer := 16; | |||
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
37 | ); | |||
|
38 | port( | |||
|
39 | clk : in std_logic; --! Horloge du composant | |||
|
40 | reset : in std_logic; --! Reset general du composant | |||
|
41 | ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e | |||
|
42 | comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes | |||
|
43 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande | |||
|
44 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande | |||
|
45 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration | |||
|
46 | ); | |||
|
47 | end ALU; | |||
|
48 | ||||
|
49 | --! @details S�lection grace a l'entr�e "ctrl" : | |||
|
50 | --! Pause : IDLE = 000 | |||
|
51 | --! Multiplieur/Accumulateur : MAC = 001 | |||
|
52 | --! Multiplication : MULT = 010 | |||
|
53 | --! Addition : ADD = 011 | |||
|
54 | --! Reset du MAC : CLRMAC = 100 | |||
|
55 | architecture ar_ALU of ALU is | |||
|
56 | ||||
|
57 | begin | |||
|
58 | ||||
|
59 | arith : if Arith_en = 1 generate | |||
|
60 | MACinst : MAC | |||
|
61 | generic map(Input_SZ_1,Input_SZ_2,COMP_EN) | |||
|
62 | port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); | |||
|
63 | end generate; | |||
|
64 | ||||
|
65 | end architecture; |
@@ -0,0 +1,71 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | LIBRARY IEEE; | |||
|
23 | USE IEEE.numeric_std.ALL; | |||
|
24 | USE IEEE.std_logic_1164.ALL; | |||
|
25 | ||||
|
26 | ENTITY Adder IS | |||
|
27 | GENERIC( | |||
|
28 | Input_SZ_A : INTEGER := 16; | |||
|
29 | Input_SZ_B : INTEGER := 16 | |||
|
30 | ||||
|
31 | ); | |||
|
32 | PORT( | |||
|
33 | clk : IN STD_LOGIC; | |||
|
34 | reset : IN STD_LOGIC; | |||
|
35 | clr : IN STD_LOGIC; | |||
|
36 | load : IN STD_LOGIC; | |||
|
37 | add : IN STD_LOGIC; | |||
|
38 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
39 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
40 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |||
|
41 | ); | |||
|
42 | END ENTITY; | |||
|
43 | ||||
|
44 | ||||
|
45 | ||||
|
46 | ||||
|
47 | ARCHITECTURE ar_Adder OF Adder IS | |||
|
48 | ||||
|
49 | SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
50 | SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
51 | ||||
|
52 | BEGIN | |||
|
53 | ||||
|
54 | RES <= REG; | |||
|
55 | RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A)); | |||
|
56 | ||||
|
57 | PROCESS(clk, reset) | |||
|
58 | BEGIN | |||
|
59 | IF reset = '0' THEN | |||
|
60 | REG <= (OTHERS => '0'); | |||
|
61 | ELSIF clk'EVENT AND clk = '1' then | |||
|
62 | IF clr = '1' THEN | |||
|
63 | REG <= (OTHERS => '0'); | |||
|
64 | ELSIF add = '1' THEN | |||
|
65 | REG <= RESADD; | |||
|
66 | ELSIF load = '1' THEN | |||
|
67 | REG <= OP2; | |||
|
68 | END IF; | |||
|
69 | END IF; | |||
|
70 | END PROCESS; | |||
|
71 | END ar_Adder; |
@@ -0,0 +1,301 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | LIBRARY IEEE; | |||
|
23 | USE IEEE.numeric_std.ALL; | |||
|
24 | USE IEEE.std_logic_1164.ALL; | |||
|
25 | LIBRARY staging_lpp; | |||
|
26 | USE staging_lpp.PLE_general_purpose.ALL; | |||
|
27 | --TODO | |||
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |||
|
29 | --par un resize sur un vecteur en combi | |||
|
30 | ||||
|
31 | ||||
|
32 | ENTITY MAC IS | |||
|
33 | GENERIC( | |||
|
34 | Input_SZ_A : INTEGER := 8; | |||
|
35 | Input_SZ_B : INTEGER := 8; | |||
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
37 | ||||
|
38 | ); | |||
|
39 | PORT( | |||
|
40 | clk : IN STD_LOGIC; | |||
|
41 | reset : IN STD_LOGIC; | |||
|
42 | clr_MAC : IN STD_LOGIC; | |||
|
43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |||
|
48 | ); | |||
|
49 | END MAC; | |||
|
50 | ||||
|
51 | ||||
|
52 | ||||
|
53 | ||||
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |||
|
55 | ||||
|
56 | SIGNAL add, mult : STD_LOGIC; | |||
|
57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
58 | ||||
|
59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
62 | ||||
|
63 | SIGNAL MACMUXsel : STD_LOGIC; | |||
|
64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
66 | ||||
|
67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
69 | ||||
|
70 | SIGNAL MACMUX2sel : STD_LOGIC; | |||
|
71 | ||||
|
72 | SIGNAL add_D : STD_LOGIC; | |||
|
73 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
74 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
75 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |||
|
76 | SIGNAL MACMUXsel_D : STD_LOGIC; | |||
|
77 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |||
|
78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |||
|
79 | SIGNAL clr_MAC_D : STD_LOGIC; | |||
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |||
|
81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
82 | ||||
|
83 | SIGNAL load_mult_result : STD_LOGIC; | |||
|
84 | SIGNAL load_mult_result_D : STD_LOGIC; | |||
|
85 | ||||
|
86 | BEGIN | |||
|
87 | ||||
|
88 | ||||
|
89 | ||||
|
90 | ||||
|
91 | --============================================================== | |||
|
92 | --=============M A C C O N T R O L E R========================= | |||
|
93 | --============================================================== | |||
|
94 | MAC_CONTROLER1 : MAC_CONTROLER | |||
|
95 | PORT MAP( | |||
|
96 | ctrl => MAC_MUL_ADD, | |||
|
97 | MULT => mult, | |||
|
98 | ADD => add, | |||
|
99 | LOAD_ADDER => load_mult_result, | |||
|
100 | MACMUX_sel => MACMUXsel, | |||
|
101 | MACMUX2_sel => MACMUX2sel | |||
|
102 | ||||
|
103 | ); | |||
|
104 | --============================================================== | |||
|
105 | ||||
|
106 | ||||
|
107 | ||||
|
108 | ||||
|
109 | --============================================================== | |||
|
110 | --=============M U L T I P L I E R============================== | |||
|
111 | --============================================================== | |||
|
112 | Multiplieri_nst : Multiplier | |||
|
113 | GENERIC MAP( | |||
|
114 | Input_SZ_A => Input_SZ_A, | |||
|
115 | Input_SZ_B => Input_SZ_B | |||
|
116 | ) | |||
|
117 | PORT MAP( | |||
|
118 | clk => clk, | |||
|
119 | reset => reset, | |||
|
120 | mult => mult, | |||
|
121 | OP1 => OP1_2C, | |||
|
122 | OP2 => OP2_2C, | |||
|
123 | RES => MULTout | |||
|
124 | ); | |||
|
125 | --============================================================== | |||
|
126 | ||||
|
127 | PROCESS (clk, reset) | |||
|
128 | BEGIN -- PROCESS | |||
|
129 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
|
130 | load_mult_result_D <= '0'; | |||
|
131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
132 | load_mult_result_D <= load_mult_result; | |||
|
133 | END IF; | |||
|
134 | END PROCESS; | |||
|
135 | ||||
|
136 | --============================================================== | |||
|
137 | --======================A D D E R ============================== | |||
|
138 | --============================================================== | |||
|
139 | adder_inst : Adder | |||
|
140 | GENERIC MAP( | |||
|
141 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |||
|
142 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |||
|
143 | ) | |||
|
144 | PORT MAP( | |||
|
145 | clk => clk, | |||
|
146 | reset => reset, | |||
|
147 | clr => clr_MAC_D, | |||
|
148 | load => load_mult_result_D, | |||
|
149 | add => add_D, | |||
|
150 | OP1 => ADDERinA, | |||
|
151 | OP2 => ADDERinB, | |||
|
152 | RES => ADDERout | |||
|
153 | ); | |||
|
154 | ||||
|
155 | --============================================================== | |||
|
156 | --===================TWO COMPLEMENTERS========================== | |||
|
157 | --============================================================== | |||
|
158 | gen_comp : IF COMP_EN = 0 GENERATE | |||
|
159 | TWO_COMPLEMENTER1 : TwoComplementer | |||
|
160 | GENERIC MAP( | |||
|
161 | Input_SZ => Input_SZ_A | |||
|
162 | ) | |||
|
163 | PORT MAP( | |||
|
164 | clk => clk, | |||
|
165 | reset => reset, | |||
|
166 | clr => clr_MAC, | |||
|
167 | TwoComp => Comp_2C(0), | |||
|
168 | OP => OP1, | |||
|
169 | RES => OP1_2C | |||
|
170 | ); | |||
|
171 | ||||
|
172 | TWO_COMPLEMENTER2 : TwoComplementer | |||
|
173 | GENERIC MAP( | |||
|
174 | Input_SZ => Input_SZ_B | |||
|
175 | ) | |||
|
176 | PORT MAP( | |||
|
177 | clk => clk, | |||
|
178 | reset => reset, | |||
|
179 | clr => clr_MAC, | |||
|
180 | TwoComp => Comp_2C(1), | |||
|
181 | OP => OP2, | |||
|
182 | RES => OP2_2C | |||
|
183 | ); | |||
|
184 | END GENERATE gen_comp; | |||
|
185 | ||||
|
186 | no_gen_comp : IF COMP_EN = 1 GENERATE | |||
|
187 | OP2_2C <= OP2; | |||
|
188 | OP1_2C <= OP1; | |||
|
189 | END GENERATE no_gen_comp; | |||
|
190 | --============================================================== | |||
|
191 | ||||
|
192 | clr_MACREG1 : MAC_REG | |||
|
193 | GENERIC MAP(size => 1) | |||
|
194 | PORT MAP( | |||
|
195 | reset => reset, | |||
|
196 | clk => clk, | |||
|
197 | D(0) => clr_MAC, | |||
|
198 | Q(0) => clr_MAC_D | |||
|
199 | ); | |||
|
200 | ||||
|
201 | addREG : MAC_REG | |||
|
202 | GENERIC MAP(size => 1) | |||
|
203 | PORT MAP( | |||
|
204 | reset => reset, | |||
|
205 | clk => clk, | |||
|
206 | D(0) => add, | |||
|
207 | Q(0) => add_D | |||
|
208 | ); | |||
|
209 | ||||
|
210 | OP1REG : MAC_REG | |||
|
211 | GENERIC MAP(size => Input_SZ_A) | |||
|
212 | PORT MAP( | |||
|
213 | reset => reset, | |||
|
214 | clk => clk, | |||
|
215 | D => OP1_2C, | |||
|
216 | Q => OP1_2C_D | |||
|
217 | ); | |||
|
218 | ||||
|
219 | ||||
|
220 | OP2REG : MAC_REG | |||
|
221 | GENERIC MAP(size => Input_SZ_B) | |||
|
222 | PORT MAP( | |||
|
223 | reset => reset, | |||
|
224 | clk => clk, | |||
|
225 | D => OP2_2C, | |||
|
226 | Q => OP2_2C_D | |||
|
227 | ); | |||
|
228 | ||||
|
229 | MULToutREG : MAC_REG | |||
|
230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |||
|
231 | PORT MAP( | |||
|
232 | reset => reset, | |||
|
233 | clk => clk, | |||
|
234 | D => MULTout, | |||
|
235 | Q => MULTout_D | |||
|
236 | ); | |||
|
237 | ||||
|
238 | MACMUXselREG : MAC_REG | |||
|
239 | GENERIC MAP(size => 1) | |||
|
240 | PORT MAP( | |||
|
241 | reset => reset, | |||
|
242 | clk => clk, | |||
|
243 | D(0) => MACMUXsel, | |||
|
244 | Q(0) => MACMUXsel_D | |||
|
245 | ); | |||
|
246 | ||||
|
247 | MACMUX2selREG : MAC_REG | |||
|
248 | GENERIC MAP(size => 1) | |||
|
249 | PORT MAP( | |||
|
250 | reset => reset, | |||
|
251 | clk => clk, | |||
|
252 | D(0) => MACMUX2sel, | |||
|
253 | Q(0) => MACMUX2sel_D | |||
|
254 | ); | |||
|
255 | ||||
|
256 | MACMUX2selREG2 : MAC_REG | |||
|
257 | GENERIC MAP(size => 1) | |||
|
258 | PORT MAP( | |||
|
259 | reset => reset, | |||
|
260 | clk => clk, | |||
|
261 | D(0) => MACMUX2sel_D, | |||
|
262 | Q(0) => MACMUX2sel_D_D | |||
|
263 | ); | |||
|
264 | ||||
|
265 | --============================================================== | |||
|
266 | --======================M A C M U X =========================== | |||
|
267 | --============================================================== | |||
|
268 | MACMUX_inst : MAC_MUX | |||
|
269 | GENERIC MAP( | |||
|
270 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |||
|
271 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |||
|
272 | ||||
|
273 | ) | |||
|
274 | PORT MAP( | |||
|
275 | sel => MACMUXsel_D, | |||
|
276 | INA1 => ADDERout, | |||
|
277 | INA2 => OP2_2C_D_Resz, | |||
|
278 | INB1 => MULTout, | |||
|
279 | INB2 => OP1_2C_D_Resz, | |||
|
280 | OUTA => ADDERinA, | |||
|
281 | OUTB => ADDERinB | |||
|
282 | ); | |||
|
283 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); | |||
|
284 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); | |||
|
285 | --============================================================== | |||
|
286 | ||||
|
287 | ||||
|
288 | --============================================================== | |||
|
289 | --======================M A C M U X2 ========================== | |||
|
290 | --============================================================== | |||
|
291 | MAC_MUX2_inst : MAC_MUX2 | |||
|
292 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) | |||
|
293 | PORT MAP( | |||
|
294 | sel => MACMUX2sel_D_D, | |||
|
295 | RES2 => MULTout_D, | |||
|
296 | RES1 => ADDERout, | |||
|
297 | RES => RES | |||
|
298 | ); | |||
|
299 | --============================================================== | |||
|
300 | ||||
|
301 | END ar_MAC; |
@@ -0,0 +1,71 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | --IDLE =00 MAC =01 MULT =10 ADD =11 | |||
|
27 | ||||
|
28 | ||||
|
29 | entity MAC_CONTROLER is | |||
|
30 | port( | |||
|
31 | ctrl : in std_logic_vector(1 downto 0); | |||
|
32 | MULT : out std_logic; | |||
|
33 | ADD : out std_logic; | |||
|
34 | LOAD_ADDER : out std_logic; | |||
|
35 | MACMUX_sel : out std_logic; | |||
|
36 | MACMUX2_sel : out std_logic | |||
|
37 | ||||
|
38 | ); | |||
|
39 | end MAC_CONTROLER; | |||
|
40 | ||||
|
41 | ||||
|
42 | ||||
|
43 | ||||
|
44 | ||||
|
45 | architecture ar_MAC_CONTROLER of MAC_CONTROLER is | |||
|
46 | ||||
|
47 | begin | |||
|
48 | ||||
|
49 | ||||
|
50 | ||||
|
51 | MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; | |||
|
52 | ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; | |||
|
53 | LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result | |||
|
54 | -- to permit to compute a | |||
|
55 | -- MULT follow by a MAC | |||
|
56 | --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; | |||
|
57 | MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1'; | |||
|
58 | MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1'; | |||
|
59 | ||||
|
60 | ||||
|
61 | end ar_MAC_CONTROLER; | |||
|
62 | ||||
|
63 | ||||
|
64 | ||||
|
65 | ||||
|
66 | ||||
|
67 | ||||
|
68 | ||||
|
69 | ||||
|
70 | ||||
|
71 |
@@ -0,0 +1,53 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | entity MAC_MUX is | |||
|
27 | generic( | |||
|
28 | Input_SZ_A : integer := 16; | |||
|
29 | Input_SZ_B : integer := 16 | |||
|
30 | ||||
|
31 | ); | |||
|
32 | port( | |||
|
33 | sel : in std_logic; | |||
|
34 | INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |||
|
35 | INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); | |||
|
36 | INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); | |||
|
37 | INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |||
|
38 | OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); | |||
|
39 | OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) | |||
|
40 | ); | |||
|
41 | end entity; | |||
|
42 | ||||
|
43 | ||||
|
44 | ||||
|
45 | ||||
|
46 | architecture ar_MAC_MUX of MAC_MUX is | |||
|
47 | ||||
|
48 | begin | |||
|
49 | ||||
|
50 | OUTA <= INA1 when sel = '0' else INA2; | |||
|
51 | OUTB <= INB1 when sel = '0' else INB2; | |||
|
52 | ||||
|
53 | end ar_MAC_MUX; |
@@ -0,0 +1,46 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | ||||
|
27 | entity MAC_MUX2 is | |||
|
28 | generic(Input_SZ : integer := 16); | |||
|
29 | port( | |||
|
30 | sel : in std_logic; | |||
|
31 | RES1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
32 | RES2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
33 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |||
|
34 | ); | |||
|
35 | end entity; | |||
|
36 | ||||
|
37 | ||||
|
38 | ||||
|
39 | ||||
|
40 | architecture ar_MAC_MUX2 of MAC_MUX2 is | |||
|
41 | ||||
|
42 | begin | |||
|
43 | ||||
|
44 | RES <= RES1 when sel = '0' else RES2; | |||
|
45 | ||||
|
46 | end ar_MAC_MUX2; |
@@ -0,0 +1,58 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | entity MAC_REG is | |||
|
27 | generic(size : integer := 16); | |||
|
28 | port( | |||
|
29 | reset : in std_logic; | |||
|
30 | clk : in std_logic; | |||
|
31 | D : in std_logic_vector(size-1 downto 0); | |||
|
32 | Q : out std_logic_vector(size-1 downto 0) | |||
|
33 | ); | |||
|
34 | end entity; | |||
|
35 | ||||
|
36 | ||||
|
37 | ||||
|
38 | architecture ar_MAC_REG of MAC_REG is | |||
|
39 | begin | |||
|
40 | process(clk,reset) | |||
|
41 | begin | |||
|
42 | if reset = '0' then | |||
|
43 | Q <= (others => '0'); | |||
|
44 | elsif clk'event and clk ='1' then | |||
|
45 | Q <= D; | |||
|
46 | end if; | |||
|
47 | end process; | |||
|
48 | end ar_MAC_REG; | |||
|
49 | ||||
|
50 | ||||
|
51 | ||||
|
52 | ||||
|
53 | ||||
|
54 | ||||
|
55 | ||||
|
56 | ||||
|
57 | ||||
|
58 |
@@ -0,0 +1,75 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | entity Multiplier is | |||
|
27 | generic( | |||
|
28 | Input_SZ_A : integer := 16; | |||
|
29 | Input_SZ_B : integer := 16 | |||
|
30 | ||||
|
31 | ); | |||
|
32 | port( | |||
|
33 | clk : in std_logic; | |||
|
34 | reset : in std_logic; | |||
|
35 | mult : in std_logic; | |||
|
36 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |||
|
37 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |||
|
38 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |||
|
39 | ); | |||
|
40 | end Multiplier; | |||
|
41 | ||||
|
42 | ||||
|
43 | ||||
|
44 | ||||
|
45 | ||||
|
46 | architecture ar_Multiplier of Multiplier is | |||
|
47 | ||||
|
48 | signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |||
|
49 | signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |||
|
50 | ||||
|
51 | ||||
|
52 | begin | |||
|
53 | ||||
|
54 | RES <= REG; | |||
|
55 | RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); | |||
|
56 | process(clk,reset) | |||
|
57 | begin | |||
|
58 | if reset = '0' then | |||
|
59 | REG <= (others => '0'); | |||
|
60 | elsif clk'event and clk ='1' then | |||
|
61 | if mult = '1' then | |||
|
62 | REG <= RESMULT; | |||
|
63 | end if; | |||
|
64 | end if; | |||
|
65 | end process; | |||
|
66 | ||||
|
67 | end ar_Multiplier; | |||
|
68 | ||||
|
69 | ||||
|
70 | ||||
|
71 | ||||
|
72 | ||||
|
73 | ||||
|
74 | ||||
|
75 |
@@ -0,0 +1,72 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | --! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs | |||
|
27 | ||||
|
28 | entity TwoComplementer is | |||
|
29 | generic( | |||
|
30 | Input_SZ : integer := 16); | |||
|
31 | port( | |||
|
32 | clk : in std_logic; --! Horloge du composant | |||
|
33 | reset : in std_logic; --! Reset general du composant | |||
|
34 | clr : in std_logic; --! Un reset sp�cifique au programme | |||
|
35 | TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment | |||
|
36 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e | |||
|
37 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non | |||
|
38 | ); | |||
|
39 | end TwoComplementer; | |||
|
40 | ||||
|
41 | ||||
|
42 | architecture ar_TwoComplementer of TwoComplementer is | |||
|
43 | ||||
|
44 | signal REG : std_logic_vector(Input_SZ-1 downto 0); | |||
|
45 | signal OPinteger : integer; | |||
|
46 | signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0); | |||
|
47 | ||||
|
48 | begin | |||
|
49 | ||||
|
50 | RES <= REG; | |||
|
51 | OPinteger <= to_integer(signed(OP)); | |||
|
52 | RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ)); | |||
|
53 | ||||
|
54 | process(clk,reset) | |||
|
55 | begin | |||
|
56 | ||||
|
57 | if(reset='0')then | |||
|
58 | REG <= (others => '0'); | |||
|
59 | elsif(clk'event and clk='1')then | |||
|
60 | ||||
|
61 | if(clr='1')then | |||
|
62 | REG <= (others => '0'); | |||
|
63 | elsif(TwoComp='1')then | |||
|
64 | REG <= RESCOMP; | |||
|
65 | else | |||
|
66 | REG <= OP; | |||
|
67 | end if; | |||
|
68 | ||||
|
69 | end if; | |||
|
70 | ||||
|
71 | end process; | |||
|
72 | end ar_TwoComplementer; No newline at end of file |
@@ -0,0 +1,185 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ---------------------------------------------------------------------------- | |||
|
22 | --UPDATE | |||
|
23 | ------------------------------------------------------------------------------- | |||
|
24 | -- 14-03-2013 - Jean-christophe Pellion | |||
|
25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) | |||
|
26 | ------------------------------------------------------------------------------- | |||
|
27 | ||||
|
28 | LIBRARY ieee; | |||
|
29 | USE ieee.std_logic_1164.ALL; | |||
|
30 | ||||
|
31 | PACKAGE PLE_general_purpose IS | |||
|
32 | ||||
|
33 | COMPONENT Adder IS | |||
|
34 | GENERIC( | |||
|
35 | Input_SZ_A : INTEGER := 16; | |||
|
36 | Input_SZ_B : INTEGER := 16 | |||
|
37 | ||||
|
38 | ); | |||
|
39 | PORT( | |||
|
40 | clk : IN STD_LOGIC; | |||
|
41 | reset : IN STD_LOGIC; | |||
|
42 | clr : IN STD_LOGIC; | |||
|
43 | load : IN STD_LOGIC; | |||
|
44 | add : IN STD_LOGIC; | |||
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |||
|
48 | ); | |||
|
49 | END COMPONENT; | |||
|
50 | ||||
|
51 | COMPONENT ALU IS | |||
|
52 | GENERIC( | |||
|
53 | Arith_en : INTEGER := 1; | |||
|
54 | Logic_en : INTEGER := 1; | |||
|
55 | Input_SZ_1 : INTEGER := 16; | |||
|
56 | Input_SZ_2 : INTEGER := 9; | |||
|
57 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
58 | ||||
|
59 | ); | |||
|
60 | PORT( | |||
|
61 | clk : IN STD_LOGIC; | |||
|
62 | reset : IN STD_LOGIC; | |||
|
63 | ctrl : IN STD_LOGIC_VECTOR(2 downto 0); | |||
|
64 | comp : IN STD_LOGIC_VECTOR(1 downto 0); | |||
|
65 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |||
|
66 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |||
|
67 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |||
|
68 | ); | |||
|
69 | END COMPONENT; | |||
|
70 | ||||
|
71 | --------------------------------------------------------- | |||
|
72 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- | |||
|
73 | --------------------------------------------------------- | |||
|
74 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; | |||
|
75 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; | |||
|
76 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; | |||
|
77 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; | |||
|
78 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; | |||
|
79 | ||||
|
80 | ||||
|
81 | Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; | |||
|
82 | Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; | |||
|
83 | Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; | |||
|
84 | Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; | |||
|
85 | Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; | |||
|
86 | --------------------------------------------------------- | |||
|
87 | ||||
|
88 | COMPONENT MAC IS | |||
|
89 | GENERIC( | |||
|
90 | Input_SZ_A : INTEGER := 8; | |||
|
91 | Input_SZ_B : INTEGER := 8; | |||
|
92 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |||
|
93 | ); | |||
|
94 | PORT( | |||
|
95 | clk : IN STD_LOGIC; | |||
|
96 | reset : IN STD_LOGIC; | |||
|
97 | clr_MAC : IN STD_LOGIC; | |||
|
98 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
99 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
100 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
101 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
102 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |||
|
103 | ); | |||
|
104 | END COMPONENT; | |||
|
105 | ||||
|
106 | COMPONENT TwoComplementer is | |||
|
107 | generic( | |||
|
108 | Input_SZ : integer := 16); | |||
|
109 | port( | |||
|
110 | clk : in std_logic; --! Horloge du composant | |||
|
111 | reset : in std_logic; --! Reset general du composant | |||
|
112 | clr : in std_logic; --! Un reset spécifique au programme | |||
|
113 | TwoComp : in std_logic; --! Autorise l'utilisation du complément | |||
|
114 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée | |||
|
115 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non | |||
|
116 | ); | |||
|
117 | end COMPONENT; | |||
|
118 | ||||
|
119 | COMPONENT MAC_CONTROLER IS | |||
|
120 | PORT( | |||
|
121 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
122 | MULT : OUT STD_LOGIC; | |||
|
123 | ADD : OUT STD_LOGIC; | |||
|
124 | LOAD_ADDER : out std_logic; | |||
|
125 | MACMUX_sel : OUT STD_LOGIC; | |||
|
126 | MACMUX2_sel : OUT STD_LOGIC | |||
|
127 | ); | |||
|
128 | END COMPONENT; | |||
|
129 | ||||
|
130 | COMPONENT MAC_MUX IS | |||
|
131 | GENERIC( | |||
|
132 | Input_SZ_A : INTEGER := 16; | |||
|
133 | Input_SZ_B : INTEGER := 16 | |||
|
134 | ||||
|
135 | ); | |||
|
136 | PORT( | |||
|
137 | sel : IN STD_LOGIC; | |||
|
138 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
139 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
140 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
141 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
142 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
143 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) | |||
|
144 | ); | |||
|
145 | END COMPONENT; | |||
|
146 | ||||
|
147 | ||||
|
148 | COMPONENT MAC_MUX2 IS | |||
|
149 | GENERIC(Input_SZ : INTEGER := 16); | |||
|
150 | PORT( | |||
|
151 | sel : IN STD_LOGIC; | |||
|
152 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |||
|
153 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |||
|
154 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |||
|
155 | ); | |||
|
156 | END COMPONENT; | |||
|
157 | ||||
|
158 | ||||
|
159 | COMPONENT MAC_REG IS | |||
|
160 | GENERIC(size : INTEGER := 16); | |||
|
161 | PORT( | |||
|
162 | reset : IN STD_LOGIC; | |||
|
163 | clk : IN STD_LOGIC; | |||
|
164 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |||
|
165 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) | |||
|
166 | ); | |||
|
167 | END COMPONENT; | |||
|
168 | ||||
|
169 | COMPONENT Multiplier IS | |||
|
170 | GENERIC( | |||
|
171 | Input_SZ_A : INTEGER := 16; | |||
|
172 | Input_SZ_B : INTEGER := 16 | |||
|
173 | ||||
|
174 | ); | |||
|
175 | PORT( | |||
|
176 | clk : IN STD_LOGIC; | |||
|
177 | reset : IN STD_LOGIC; | |||
|
178 | mult : IN STD_LOGIC; | |||
|
179 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |||
|
180 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |||
|
181 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |||
|
182 | ); | |||
|
183 | END COMPONENT; | |||
|
184 | ||||
|
185 | END; |
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