@@ -1,123 +1,123 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
27 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_cna.all; |
|
31 | use lpp.lpp_cna.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba | |
34 |
|
34 | |||
35 | entity APB_CNA is |
|
35 | entity APB_CNA is | |
36 | generic ( |
|
36 | generic ( | |
37 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
38 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
39 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
40 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
41 | abits : integer := 8); |
|
41 | abits : integer := 8); | |
42 | port ( |
|
42 | port ( | |
43 | clk : in std_logic; --! Horloge du composant |
|
43 | clk : in std_logic; --! Horloge du composant | |
44 | rst : in std_logic; --! Reset general du composant |
|
44 | rst : in std_logic; --! Reset general du composant | |
45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
|
46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus | |
47 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
|
47 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
48 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
|
48 | SCLK : out std_logic; --! Horloge systeme du convertisseur | |
49 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
|
49 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ | |
50 | ); |
|
50 | ); | |
51 | end APB_CNA; |
|
51 | end APB_CNA; | |
52 |
|
52 | |||
53 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus |
|
53 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus | |
54 | --! et les sorties seront cablοΏ½es vers le convertisseur. |
|
54 | --! et les sorties seront cablοΏ½es vers le convertisseur. | |
55 |
|
55 | |||
56 | architecture ar_APB_CNA of APB_CNA is |
|
56 | architecture ar_APB_CNA of APB_CNA is | |
57 |
|
57 | |||
58 | constant REVISION : integer := 1; |
|
58 | constant REVISION : integer := 1; | |
59 |
|
59 | |||
60 | constant pconfig : apb_config_type := ( |
|
60 | constant pconfig : apb_config_type := ( | |
61 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
|
61 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |
62 | 1 => apb_iobar(paddr, pmask)); |
|
62 | 1 => apb_iobar(paddr, pmask)); | |
63 |
|
63 | |||
64 | signal enable : std_logic; |
|
64 | signal enable : std_logic; | |
65 | signal flag_sd : std_logic; |
|
65 | signal flag_sd : std_logic; | |
66 |
|
66 | |||
67 | type CNA_ctrlr_Reg is record |
|
67 | type CNA_ctrlr_Reg is record | |
68 | CNA_Cfg : std_logic_vector(1 downto 0); |
|
68 | CNA_Cfg : std_logic_vector(1 downto 0); | |
69 | CNA_Data : std_logic_vector(15 downto 0); |
|
69 | CNA_Data : std_logic_vector(15 downto 0); | |
70 | end record; |
|
70 | end record; | |
71 |
|
71 | |||
72 | signal Rec : CNA_ctrlr_Reg; |
|
72 | signal Rec : CNA_ctrlr_Reg; | |
73 | signal Rdata : std_logic_vector(31 downto 0); |
|
73 | signal Rdata : std_logic_vector(31 downto 0); | |
74 |
|
74 | |||
75 | begin |
|
75 | begin | |
76 |
|
76 | |||
77 | enable <= Rec.CNA_Cfg(0); |
|
77 | enable <= Rec.CNA_Cfg(0); | |
78 | Rec.CNA_Cfg(1) <= flag_sd; |
|
78 | Rec.CNA_Cfg(1) <= flag_sd; | |
79 |
|
79 | |||
80 | CONVERTER : entity Work.CNA_TabloC |
|
80 | CONVERTER : entity Work.CNA_TabloC | |
81 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); |
|
81 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
82 |
|
82 | |||
83 |
|
83 | |||
84 | process(rst,clk) |
|
84 | process(rst,clk) | |
85 | begin |
|
85 | begin | |
86 | if(rst='0')then |
|
86 | if(rst='0')then | |
87 | Rec.CNA_Data <= (others => '0'); |
|
87 | Rec.CNA_Data <= (others => '0'); | |
88 |
|
88 | |||
89 | elsif(clk'event and clk='1')then |
|
89 | elsif(clk'event and clk='1')then | |
90 |
|
90 | |||
91 |
|
91 | |||
92 | --APB Write OP |
|
92 | --APB Write OP | |
93 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
93 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
94 | case apbi.paddr(abits-1 downto 2) is |
|
94 | case apbi.paddr(abits-1 downto 2) is | |
95 | when "000000" => |
|
95 | when "000000" => | |
96 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); |
|
96 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
97 | when "000001" => |
|
97 | when "000001" => | |
98 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
|
98 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |
99 | when others => |
|
99 | when others => | |
100 | null; |
|
100 | null; | |
101 | end case; |
|
101 | end case; | |
102 | end if; |
|
102 | end if; | |
103 |
|
103 | |||
104 | --APB READ OP |
|
104 | --APB READ OP | |
105 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
105 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
106 | case apbi.paddr(abits-1 downto 2) is |
|
106 | case apbi.paddr(abits-1 downto 2) is | |
107 | when "000000" => |
|
107 | when "000000" => | |
108 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; |
|
108 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
109 | Rdata(1 downto 0) <= Rec.CNA_Cfg; |
|
109 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
110 | when "000001" => |
|
110 | when "000001" => | |
111 | Rdata(31 downto 16) <= X"FD18"; |
|
111 | Rdata(31 downto 16) <= X"FD18"; | |
112 | Rdata(15 downto 0) <= Rec.CNA_Data; |
|
112 | Rdata(15 downto 0) <= Rec.CNA_Data; | |
113 | when others => |
|
113 | when others => | |
114 | Rdata <= (others => '0'); |
|
114 | Rdata <= (others => '0'); | |
115 | end case; |
|
115 | end case; | |
116 | end if; |
|
116 | end if; | |
117 |
|
117 | |||
118 | end if; |
|
118 | end if; | |
119 | apbo.pconfig <= pconfig; |
|
119 | apbo.pconfig <= pconfig; | |
120 | end process; |
|
120 | end process; | |
121 |
|
121 | |||
122 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
122 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
123 | end ar_APB_CNA; |
|
123 | end ar_APB_CNA; |
@@ -1,152 +1,146 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
27 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_uart.all; |
|
31 | use lpp.lpp_uart.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba | |
34 |
|
34 | |||
35 | entity APB_UART is |
|
35 | entity APB_UART is | |
36 | generic ( |
|
36 | generic ( | |
37 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
38 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
39 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
40 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
41 | abits : integer := 8; |
|
41 | abits : integer := 8; | |
42 | Data_sz : integer := 8); |
|
42 | Data_sz : integer := 8); | |
43 | port ( |
|
43 | port ( | |
44 | clk : in std_logic; --! Horloge du composant |
|
44 | clk : in std_logic; --! Horloge du composant | |
45 | rst : in std_logic; --! Reset general du composant |
|
45 | rst : in std_logic; --! Reset general du composant | |
46 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
46 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
47 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
|
47 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus | |
48 | TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant |
|
48 | TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant | |
49 | RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant |
|
49 | RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant | |
50 | ); |
|
50 | ); | |
51 | end APB_UART; |
|
51 | end APB_UART; | |
52 |
|
52 | |||
53 |
|
53 | |||
54 | architecture ar_APB_UART of APB_UART is |
|
54 | architecture ar_APB_UART of APB_UART is | |
55 |
|
55 | |||
56 | constant REVISION : integer := 1; |
|
56 | constant REVISION : integer := 1; | |
57 |
|
57 | |||
58 | constant pconfig : apb_config_type := ( |
|
58 | constant pconfig : apb_config_type := ( | |
59 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), |
|
59 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), | |
60 | 1 => apb_iobar(paddr, pmask)); |
|
60 | 1 => apb_iobar(paddr, pmask)); | |
61 |
|
61 | |||
62 | signal NwData : std_logic; |
|
62 | signal NwData : std_logic; | |
63 | signal ACK : std_logic; |
|
63 | signal ACK : std_logic; | |
64 | signal Capture : std_logic; |
|
64 | signal Capture : std_logic; | |
65 | signal Send : std_logic; |
|
65 | signal Send : std_logic; | |
66 | signal Sended : std_logic; |
|
66 | signal Sended : std_logic; | |
67 |
|
67 | |||
68 | type UART_ctrlr_Reg is record |
|
68 | type UART_ctrlr_Reg is record | |
69 | UART_Cfg : std_logic_vector(2 downto 0); |
|
69 | UART_Cfg : std_logic_vector(2 downto 0); | |
70 | UART_Wdata : std_logic_vector(7 downto 0); |
|
70 | UART_Wdata : std_logic_vector(7 downto 0); | |
71 | UART_Rdata : std_logic_vector(7 downto 0); |
|
71 | UART_Rdata : std_logic_vector(7 downto 0); | |
72 | UART_BTrig : std_logic_vector(11 downto 0); |
|
72 | UART_BTrig : std_logic_vector(11 downto 0); | |
73 | end record; |
|
73 | end record; | |
74 |
|
74 | |||
75 | signal Rec : UART_ctrlr_Reg; |
|
75 | signal Rec : UART_ctrlr_Reg; | |
76 | signal Rdata : std_logic_vector(31 downto 0); |
|
76 | signal Rdata : std_logic_vector(31 downto 0); | |
77 | signal temp_ND : std_logic; |
|
77 | signal temp_ND : std_logic; | |
78 |
|
78 | |||
79 | begin |
|
79 | begin | |
80 |
|
80 | |||
81 | Capture <= Rec.UART_Cfg(0); |
|
81 | Capture <= Rec.UART_Cfg(0); | |
82 | --ACK <= Rec.UART_Cfg(1); |
|
|||
83 | --Send <= Rec.UART_Cfg(1); |
|
|||
84 | Rec.UART_Cfg(1) <= Sended; |
|
82 | Rec.UART_Cfg(1) <= Sended; | |
85 | Rec.UART_Cfg(2) <= NwData; |
|
83 | Rec.UART_Cfg(2) <= NwData; | |
86 |
|
84 | |||
87 |
|
85 | |||
88 | COM0 : entity work.UART |
|
86 | COM0 : entity work.UART | |
89 | generic map (Data_sz) |
|
87 | generic map (Data_sz) | |
90 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); |
|
88 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); | |
91 |
|
89 | |||
92 |
|
90 | |||
93 | process(rst,clk) |
|
91 | process(rst,clk) | |
94 | begin |
|
92 | begin | |
95 | if(rst='0')then |
|
93 | if(rst='0')then | |
96 | Rec.UART_Wdata <= (others => '0'); |
|
94 | Rec.UART_Wdata <= (others => '0'); | |
97 |
|
95 | |||
98 |
|
96 | |||
99 | elsif(clk'event and clk='1')then |
|
97 | elsif(clk'event and clk='1')then | |
100 | temp_ND <= NwData; |
|
98 | temp_ND <= NwData; | |
101 | if(NwData='1' and temp_ND='1')then |
|
99 | if(NwData='1' and temp_ND='1')then | |
102 | ACK <= '1'; |
|
100 | ACK <= '1'; | |
103 | else |
|
101 | else | |
104 | ACK <= '0'; |
|
102 | ACK <= '0'; | |
105 | end if; |
|
103 | end if; | |
106 |
|
104 | |||
107 | --APB Write OP |
|
105 | --APB Write OP | |
108 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
106 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
109 | case apbi.paddr(7 downto 2) is |
|
107 | case apbi.paddr(7 downto 2) is | |
110 | when "000000" => |
|
108 | when "000000" => | |
111 | Rec.UART_Cfg(0) <= apbi.pwdata(0); |
|
109 | Rec.UART_Cfg(0) <= apbi.pwdata(0); | |
112 | --Rec.UART_Cfg(1) <= apbi.pwdata(4); |
|
|||
113 | when "000001" => |
|
110 | when "000001" => | |
114 | Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); |
|
111 | Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); | |
115 | Send <= '1'; |
|
112 | Send <= '1'; | |
116 | when others => |
|
113 | when others => | |
117 | null; |
|
114 | null; | |
118 | end case; |
|
115 | end case; | |
119 | else |
|
116 | else | |
120 | Send <= '0'; |
|
117 | Send <= '0'; | |
121 | end if; |
|
118 | end if; | |
122 |
|
119 | |||
123 | --APB READ OP |
|
120 | --APB READ OP | |
124 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
121 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
125 | case apbi.paddr(7 downto 2) is |
|
122 | case apbi.paddr(7 downto 2) is | |
126 | when "000000" => |
|
123 | when "000000" => | |
127 | Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0); |
|
124 | Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0); | |
128 | Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1); |
|
125 | Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1); | |
129 | Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2); |
|
126 | Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2); | |
130 | Rdata(19 downto 12) <= X"EE"; |
|
127 | Rdata(19 downto 12) <= X"EE"; | |
131 | Rdata(31 downto 20) <= Rec.UART_BTrig; |
|
128 | Rdata(31 downto 20) <= Rec.UART_BTrig; | |
132 | when "000001" => |
|
129 | when "000001" => | |
133 | Rdata(31 downto 8) <= X"EEEEEE"; |
|
130 | Rdata(31 downto 8) <= X"EEEEEE"; | |
134 | Rdata(7 downto 0) <= Rec.UART_Wdata; |
|
131 | Rdata(7 downto 0) <= Rec.UART_Wdata; | |
135 | when "000010" => |
|
132 | when "000010" => | |
136 | Rdata(31 downto 8) <= X"EEEEEE"; |
|
133 | Rdata(31 downto 8) <= X"EEEEEE"; | |
137 | Rdata(7 downto 0) <= Rec.UART_Rdata; |
|
134 | Rdata(7 downto 0) <= Rec.UART_Rdata; | |
138 | --Ack <= '1'; |
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139 | when others => |
|
135 | when others => | |
140 | Rdata <= (others => '0'); |
|
136 | Rdata <= (others => '0'); | |
141 | end case; |
|
137 | end case; | |
142 | --else |
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143 | --Ack <= '0'; |
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144 | end if; |
|
138 | end if; | |
145 |
|
139 | |||
146 | end if; |
|
140 | end if; | |
147 | apbo.pconfig <= pconfig; |
|
141 | apbo.pconfig <= pconfig; | |
148 | end process; |
|
142 | end process; | |
149 |
|
143 | |||
150 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
144 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
151 |
|
145 | |||
152 | end ar_APB_UART; |
|
146 | end ar_APB_UART; |
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