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HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
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modif alexis - CNA
pellion -
r541:5b67570c5718 (LFR-EM) 1-1-63 JC
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@@ -391,7 +391,7 BEGIN -- beh
391 391 pirq_ms => 6,
392 392 pirq_wfp => 14,
393 393 hindex => 2,
394 top_lfr_version => X"01013E") -- aa.bb.cc version
394 top_lfr_version => X"01013F") -- aa.bb.cc version
395 395 -- AA : BOARD NUMBER
396 396 -- 0 => MINI_LFR
397 397 -- 1 => EM
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@@ -50,7 +50,6 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
50 50 SIGNAL shifting_R : STD_LOGIC := '0';
51 51 BEGIN
52 52
53 DOUT <= SHIFTREG(datawidth-1);
54 53
55 54 MSB : IF MSBFIRST = 1 GENERATE
56 55 INPUTREG <= DATA;
@@ -64,24 +63,26 BEGIN
64 63
65 64 PROCESS(clk, rstn)
66 65 BEGIN
67 IF rstn = '0' then
66 IF rstn = '0' THEN
68 67 -- shifting_R <= '0';
69 SMP_CLK_R <= '0';
70 ELSIF clk'EVENT AND clk = '1' then
71 SMP_CLK_R <= SMP_CLK;
68 SMP_CLK_R <= '0';
69 ELSIF clk'EVENT AND clk = '1' THEN
70 SMP_CLK_R <= SMP_CLK;
72 71 -- shifting_R <= shifting;
73 72 END IF;
74 73 END PROCESS;
75 74
76 75 PROCESS(clk, rstn)
77 76 BEGIN
78 IF rstn = '0' then
77 IF rstn = '0' THEN
79 78 shifting <= '0';
80 79 SHIFTREG <= (OTHERS => '0');
81 80 SYNC <= '0';
82 81 shiftcnt <= 0;
83 ELSIF clk'EVENT AND clk = '1' then
84 IF(SMP_CLK = '1' and SMP_CLK_R = '0') THEN
82 DOUT <= '0';
83 ELSIF clk'EVENT AND clk = '1' THEN
84 DOUT <= SHIFTREG(datawidth-1);
85 IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
85 86 SYNC <= '1';
86 87 shifting <= '1';
87 88 ELSE
@@ -90,9 +91,10 BEGIN
90 91 shifting <= '0';
91 92 END IF;
92 93 END IF;
93 IF shifting = '1' then
94 IF shifting = '1' THEN
94 95 shiftcnt <= shiftcnt + 1;
95 96 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
97
96 98 ELSE
97 99 SHIFTREG <= INPUTREG;
98 100 shiftcnt <= 0;
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