|
@@
-0,0
+1,354
|
|
|
1
|
LIBRARY ieee;
|
|
|
2
|
USE ieee.std_logic_1164.ALL;
|
|
|
3
|
LIBRARY lpp;
|
|
|
4
|
USE lpp.lpp_ad_conv.ALL;
|
|
|
5
|
USE lpp.iir_filter.ALL;
|
|
|
6
|
USE lpp.FILTERcfg.ALL;
|
|
|
7
|
USE lpp.lpp_memory.ALL;
|
|
|
8
|
USE lpp.lpp_top_lfr_pkg.ALL;
|
|
|
9
|
LIBRARY techmap;
|
|
|
10
|
USE techmap.gencomp.ALL;
|
|
|
11
|
|
|
|
12
|
ENTITY lpp_top_acq IS
|
|
|
13
|
GENERIC(
|
|
|
14
|
tech : INTEGER := 0
|
|
|
15
|
);
|
|
|
16
|
PORT (
|
|
|
17
|
-- ADS7886
|
|
|
18
|
cnv_run : IN STD_LOGIC;
|
|
|
19
|
cnv : OUT STD_LOGIC;
|
|
|
20
|
sck : OUT STD_LOGIC;
|
|
|
21
|
sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
|
22
|
--
|
|
|
23
|
cnv_clk : IN STD_LOGIC;
|
|
|
24
|
cnv_rstn : IN STD_LOGIC;
|
|
|
25
|
--
|
|
|
26
|
clk : IN STD_LOGIC;
|
|
|
27
|
rstn : IN STD_LOGIC;
|
|
|
28
|
--
|
|
|
29
|
sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
|
|
30
|
sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
|
|
31
|
sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
|
|
|
32
|
--
|
|
|
33
|
sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
|
|
34
|
sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
|
|
|
35
|
--
|
|
|
36
|
sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
|
|
37
|
sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
|
|
|
38
|
--
|
|
|
39
|
sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
|
|
|
40
|
sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)
|
|
|
41
|
);
|
|
|
42
|
END lpp_top_acq;
|
|
|
43
|
|
|
|
44
|
ARCHITECTURE tb OF lpp_top_acq IS
|
|
|
45
|
|
|
|
46
|
COMPONENT Downsampling
|
|
|
47
|
GENERIC (
|
|
|
48
|
ChanelCount : INTEGER;
|
|
|
49
|
SampleSize : INTEGER;
|
|
|
50
|
DivideParam : INTEGER);
|
|
|
51
|
PORT (
|
|
|
52
|
clk : IN STD_LOGIC;
|
|
|
53
|
rstn : IN STD_LOGIC;
|
|
|
54
|
sample_in_val : IN STD_LOGIC;
|
|
|
55
|
sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
|
|
|
56
|
sample_out_val : OUT STD_LOGIC;
|
|
|
57
|
sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
|
|
|
58
|
END COMPONENT;
|
|
|
59
|
|
|
|
60
|
-----------------------------------------------------------------------------
|
|
|
61
|
CONSTANT ChanelCount : INTEGER := 8;
|
|
|
62
|
CONSTANT ncycle_cnv_high : INTEGER := 79;
|
|
|
63
|
CONSTANT ncycle_cnv : INTEGER := 500;
|
|
|
64
|
|
|
|
65
|
-----------------------------------------------------------------------------
|
|
|
66
|
SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
|
|
|
67
|
SIGNAL sample_val : STD_LOGIC;
|
|
|
68
|
SIGNAL sample_val_delay : STD_LOGIC;
|
|
|
69
|
-----------------------------------------------------------------------------
|
|
|
70
|
CONSTANT Coef_SZ : INTEGER := 9;
|
|
|
71
|
CONSTANT CoefCntPerCel : INTEGER := 6;
|
|
|
72
|
CONSTANT CoefPerCel : INTEGER := 5;
|
|
|
73
|
CONSTANT Cels_count : INTEGER := 5;
|
|
|
74
|
|
|
|
75
|
-- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
|
|
|
76
|
SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
|
|
|
77
|
SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
78
|
-- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
79
|
--
|
|
|
80
|
SIGNAL sample_filter_JC_out_val : STD_LOGIC;
|
|
|
81
|
SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
82
|
--
|
|
|
83
|
SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
|
|
|
84
|
SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
85
|
-----------------------------------------------------------------------------
|
|
|
86
|
SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
|
87
|
SIGNAL sample_downsampling_out_val : STD_LOGIC;
|
|
|
88
|
SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
89
|
--
|
|
|
90
|
SIGNAL sample_f0_val : STD_LOGIC;
|
|
|
91
|
SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
92
|
--
|
|
|
93
|
SIGNAL sample_f0_0_val : STD_LOGIC;
|
|
|
94
|
SIGNAL sample_f0_1_val : STD_LOGIC;
|
|
|
95
|
SIGNAL counter_f0 : INTEGER;
|
|
|
96
|
-----------------------------------------------------------------------------
|
|
|
97
|
SIGNAL sample_f1_val : STD_LOGIC;
|
|
|
98
|
SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
99
|
--
|
|
|
100
|
SIGNAL sample_f2_val : STD_LOGIC;
|
|
|
101
|
SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
102
|
--
|
|
|
103
|
SIGNAL sample_f3_val : STD_LOGIC;
|
|
|
104
|
SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
|
|
|
105
|
|
|
|
106
|
BEGIN
|
|
|
107
|
|
|
|
108
|
-- component instantiation
|
|
|
109
|
-----------------------------------------------------------------------------
|
|
|
110
|
DIGITAL_acquisition : ADS7886_drvr
|
|
|
111
|
GENERIC MAP (
|
|
|
112
|
ChanelCount => ChanelCount,
|
|
|
113
|
ncycle_cnv_high => ncycle_cnv_high,
|
|
|
114
|
ncycle_cnv => ncycle_cnv)
|
|
|
115
|
PORT MAP (
|
|
|
116
|
cnv_clk => cnv_clk, --
|
|
|
117
|
cnv_rstn => cnv_rstn, --
|
|
|
118
|
cnv_run => cnv_run, --
|
|
|
119
|
cnv => cnv, --
|
|
|
120
|
clk => clk, --
|
|
|
121
|
rstn => rstn, --
|
|
|
122
|
sck => sck, --
|
|
|
123
|
sdo => sdo(ChanelCount-1 DOWNTO 0), --
|
|
|
124
|
sample => sample,
|
|
|
125
|
sample_val => sample_val);
|
|
|
126
|
|
|
|
127
|
-----------------------------------------------------------------------------
|
|
|
128
|
|
|
|
129
|
PROCESS (clk, rstn)
|
|
|
130
|
BEGIN -- PROCESS
|
|
|
131
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
132
|
sample_val_delay <= '0';
|
|
|
133
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
134
|
sample_val_delay <= sample_val;
|
|
|
135
|
END IF;
|
|
|
136
|
END PROCESS;
|
|
|
137
|
|
|
|
138
|
-----------------------------------------------------------------------------
|
|
|
139
|
ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
|
|
|
140
|
SampleLoop : FOR j IN 0 TO 15 GENERATE
|
|
|
141
|
sample_filter_in(i, j) <= sample(i)(j);
|
|
|
142
|
END GENERATE;
|
|
|
143
|
|
|
|
144
|
sample_filter_in(i, 16) <= sample(i)(15);
|
|
|
145
|
sample_filter_in(i, 17) <= sample(i)(15);
|
|
|
146
|
END GENERATE;
|
|
|
147
|
|
|
|
148
|
-- coefs <= CoefsInitValCst;
|
|
|
149
|
coefs_JC <= CoefsInitValCst_JC;
|
|
|
150
|
|
|
|
151
|
--FILTER : IIR_CEL_CTRLR
|
|
|
152
|
-- GENERIC MAP (
|
|
|
153
|
-- tech => 0,
|
|
|
154
|
-- Sample_SZ => 18,
|
|
|
155
|
-- ChanelsCount => ChanelCount,
|
|
|
156
|
-- Coef_SZ => Coef_SZ,
|
|
|
157
|
-- CoefCntPerCel => CoefCntPerCel,
|
|
|
158
|
-- Cels_count => Cels_count,
|
|
|
159
|
-- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
|
|
|
160
|
-- PORT MAP (
|
|
|
161
|
-- reset => rstn,
|
|
|
162
|
-- clk => clk,
|
|
|
163
|
-- sample_clk => sample_val_delay,
|
|
|
164
|
-- sample_in => sample_filter_in,
|
|
|
165
|
-- sample_out => sample_filter_out,
|
|
|
166
|
-- virg_pos => 7,
|
|
|
167
|
-- GOtest => OPEN,
|
|
|
168
|
-- coefs => coefs);
|
|
|
169
|
|
|
|
170
|
IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
|
|
|
171
|
GENERIC MAP (
|
|
|
172
|
tech => 0,
|
|
|
173
|
Mem_use => use_CEL,
|
|
|
174
|
Sample_SZ => 18,
|
|
|
175
|
Coef_SZ => Coef_SZ,
|
|
|
176
|
Coef_Nb => 25, -- TODO
|
|
|
177
|
Coef_sel_SZ => 5, -- TODO
|
|
|
178
|
Cels_count => Cels_count,
|
|
|
179
|
ChanelsCount => ChanelCount)
|
|
|
180
|
PORT MAP (
|
|
|
181
|
rstn => rstn,
|
|
|
182
|
clk => clk,
|
|
|
183
|
virg_pos => 7,
|
|
|
184
|
coefs => coefs_JC,
|
|
|
185
|
sample_in_val => sample_val_delay,
|
|
|
186
|
sample_in => sample_filter_in,
|
|
|
187
|
sample_out_val => sample_filter_JC_out_val,
|
|
|
188
|
sample_out => sample_filter_JC_out);
|
|
|
189
|
|
|
|
190
|
-----------------------------------------------------------------------------
|
|
|
191
|
PROCESS (clk, rstn)
|
|
|
192
|
BEGIN -- PROCESS
|
|
|
193
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
194
|
sample_filter_JC_out_r_val <= '0';
|
|
|
195
|
rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
|
|
|
196
|
rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
|
|
|
197
|
sample_filter_JC_out_r(I, J) <= '0';
|
|
|
198
|
END LOOP rst_all_bits;
|
|
|
199
|
END LOOP rst_all_chanel;
|
|
|
200
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
201
|
sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
|
|
|
202
|
IF sample_filter_JC_out_val = '1' THEN
|
|
|
203
|
sample_filter_JC_out_r <= sample_filter_JC_out;
|
|
|
204
|
END IF;
|
|
|
205
|
END IF;
|
|
|
206
|
END PROCESS;
|
|
|
207
|
|
|
|
208
|
-----------------------------------------------------------------------------
|
|
|
209
|
-- F0 -- @24.576 kHz
|
|
|
210
|
-----------------------------------------------------------------------------
|
|
|
211
|
Downsampling_f0 : Downsampling
|
|
|
212
|
GENERIC MAP (
|
|
|
213
|
ChanelCount => ChanelCount,
|
|
|
214
|
SampleSize => 18,
|
|
|
215
|
DivideParam => 4)
|
|
|
216
|
PORT MAP (
|
|
|
217
|
clk => clk,
|
|
|
218
|
rstn => rstn,
|
|
|
219
|
sample_in_val => sample_filter_JC_out_val ,
|
|
|
220
|
sample_in => sample_filter_JC_out,
|
|
|
221
|
sample_out_val => sample_f0_val,
|
|
|
222
|
sample_out => sample_f0);
|
|
|
223
|
|
|
|
224
|
all_bit_sample_f0 : FOR I IN 17 DOWNTO 0 GENERATE
|
|
|
225
|
sample_f0_wdata(I) <= sample_f0(0, I);
|
|
|
226
|
sample_f0_wdata(18*1+I) <= sample_f0(1, I);
|
|
|
227
|
sample_f0_wdata(18*2+I) <= sample_f0(2, I);
|
|
|
228
|
sample_f0_wdata(18*3+I) <= sample_f0(6, I);
|
|
|
229
|
sample_f0_wdata(18*4+I) <= sample_f0(7, I);
|
|
|
230
|
END GENERATE all_bit_sample_f0;
|
|
|
231
|
|
|
|
232
|
PROCESS (clk, rstn)
|
|
|
233
|
BEGIN -- PROCESS
|
|
|
234
|
IF rstn = '0' THEN -- asynchronous reset (active low)
|
|
|
235
|
counter_f0 <= 0;
|
|
|
236
|
ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
|
|
|
237
|
IF sample_f0_val = '1' THEN
|
|
|
238
|
IF counter_f0 = 511 THEN
|
|
|
239
|
counter_f0 <= 0;
|
|
|
240
|
ELSE
|
|
|
241
|
counter_f0 <= counter_f0 + 1;
|
|
|
242
|
END IF;
|
|
|
243
|
END IF;
|
|
|
244
|
END IF;
|
|
|
245
|
END PROCESS;
|
|
|
246
|
|
|
|
247
|
sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
|
|
|
248
|
sample_f0_0_wen <= NOT(sample_f0_0_val) &
|
|
|
249
|
NOT(sample_f0_0_val) &
|
|
|
250
|
NOT(sample_f0_0_val) &
|
|
|
251
|
NOT(sample_f0_0_val) &
|
|
|
252
|
NOT(sample_f0_0_val);
|
|
|
253
|
|
|
|
254
|
sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
|
|
|
255
|
sample_f0_1_wen <= NOT(sample_f0_1_val) &
|
|
|
256
|
NOT(sample_f0_1_val) &
|
|
|
257
|
NOT(sample_f0_1_val) &
|
|
|
258
|
NOT(sample_f0_1_val) &
|
|
|
259
|
NOT(sample_f0_1_val);
|
|
|
260
|
|
|
|
261
|
|
|
|
262
|
-----------------------------------------------------------------------------
|
|
|
263
|
-- F1 -- @4096 Hz
|
|
|
264
|
-----------------------------------------------------------------------------
|
|
|
265
|
Downsampling_f1 : Downsampling
|
|
|
266
|
GENERIC MAP (
|
|
|
267
|
ChanelCount => ChanelCount,
|
|
|
268
|
SampleSize => 18,
|
|
|
269
|
DivideParam => 6)
|
|
|
270
|
PORT MAP (
|
|
|
271
|
clk => clk,
|
|
|
272
|
rstn => rstn,
|
|
|
273
|
sample_in_val => sample_f0_val ,
|
|
|
274
|
sample_in => sample_f0,
|
|
|
275
|
sample_out_val => sample_f1_val,
|
|
|
276
|
sample_out => sample_f1);
|
|
|
277
|
|
|
|
278
|
sample_f1_wen <= NOT(sample_f1_val) &
|
|
|
279
|
NOT(sample_f1_val) &
|
|
|
280
|
NOT(sample_f1_val) &
|
|
|
281
|
NOT(sample_f1_val) &
|
|
|
282
|
NOT(sample_f1_val);
|
|
|
283
|
|
|
|
284
|
all_bit_sample_f1 : FOR I IN 17 DOWNTO 0 GENERATE
|
|
|
285
|
sample_f1_wdata(I) <= sample_f1(0, I);
|
|
|
286
|
sample_f1_wdata(18*1+I) <= sample_f1(1, I);
|
|
|
287
|
sample_f1_wdata(18*2+I) <= sample_f1(2, I);
|
|
|
288
|
sample_f1_wdata(18*3+I) <= sample_f1(6, I);
|
|
|
289
|
sample_f1_wdata(18*4+I) <= sample_f1(7, I);
|
|
|
290
|
END GENERATE all_bit_sample_f1;
|
|
|
291
|
|
|
|
292
|
-----------------------------------------------------------------------------
|
|
|
293
|
-- F2 -- @16 Hz
|
|
|
294
|
-----------------------------------------------------------------------------
|
|
|
295
|
Downsampling_f2 : Downsampling
|
|
|
296
|
GENERIC MAP (
|
|
|
297
|
ChanelCount => ChanelCount,
|
|
|
298
|
SampleSize => 18,
|
|
|
299
|
DivideParam => 256)
|
|
|
300
|
PORT MAP (
|
|
|
301
|
clk => clk,
|
|
|
302
|
rstn => rstn,
|
|
|
303
|
sample_in_val => sample_f1_val ,
|
|
|
304
|
sample_in => sample_f1,
|
|
|
305
|
sample_out_val => sample_f2_val,
|
|
|
306
|
sample_out => sample_f2);
|
|
|
307
|
|
|
|
308
|
sample_f2_wen <= NOT(sample_f2_val) &
|
|
|
309
|
NOT(sample_f2_val) &
|
|
|
310
|
NOT(sample_f2_val) &
|
|
|
311
|
NOT(sample_f2_val) &
|
|
|
312
|
NOT(sample_f2_val);
|
|
|
313
|
|
|
|
314
|
all_bit_sample_f2 : FOR I IN 17 DOWNTO 0 GENERATE
|
|
|
315
|
sample_f2_wdata(I) <= sample_f2(0, I);
|
|
|
316
|
sample_f2_wdata(18*1+I) <= sample_f2(1, I);
|
|
|
317
|
sample_f2_wdata(18*2+I) <= sample_f2(2, I);
|
|
|
318
|
sample_f2_wdata(18*3+I) <= sample_f2(6, I);
|
|
|
319
|
sample_f2_wdata(18*4+I) <= sample_f2(7, I);
|
|
|
320
|
END GENERATE all_bit_sample_f2;
|
|
|
321
|
|
|
|
322
|
-----------------------------------------------------------------------------
|
|
|
323
|
-- F3 -- @256 Hz
|
|
|
324
|
-----------------------------------------------------------------------------
|
|
|
325
|
Downsampling_f3 : Downsampling
|
|
|
326
|
GENERIC MAP (
|
|
|
327
|
ChanelCount => ChanelCount,
|
|
|
328
|
SampleSize => 18,
|
|
|
329
|
DivideParam => 96)
|
|
|
330
|
PORT MAP (
|
|
|
331
|
clk => clk,
|
|
|
332
|
rstn => rstn,
|
|
|
333
|
sample_in_val => sample_f0_val ,
|
|
|
334
|
sample_in => sample_f0,
|
|
|
335
|
sample_out_val => sample_f3_val,
|
|
|
336
|
sample_out => sample_f3);
|
|
|
337
|
|
|
|
338
|
sample_f3_wen <= (NOT sample_f3_val) &
|
|
|
339
|
(NOT sample_f3_val) &
|
|
|
340
|
(NOT sample_f3_val) &
|
|
|
341
|
(NOT sample_f3_val) &
|
|
|
342
|
(NOT sample_f3_val);
|
|
|
343
|
|
|
|
344
|
all_bit_sample_f3 : FOR I IN 17 DOWNTO 0 GENERATE
|
|
|
345
|
sample_f3_wdata(I) <= sample_f3(0, I);
|
|
|
346
|
sample_f3_wdata(18*1+I) <= sample_f3(1, I);
|
|
|
347
|
sample_f3_wdata(18*2+I) <= sample_f3(2, I);
|
|
|
348
|
sample_f3_wdata(18*3+I) <= sample_f3(6, I);
|
|
|
349
|
sample_f3_wdata(18*4+I) <= sample_f3(7, I);
|
|
|
350
|
END GENERATE all_bit_sample_f3;
|
|
|
351
|
|
|
|
352
|
|
|
|
353
|
|
|
|
354
|
END tb;
|