##// END OF EJS Templates
temp
pellion -
r398:51d54eefa77b JC
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@@ -138,6 +138,9 ARCHITECTURE beh OF LFR_em IS
138 138
139 139 -----------------------------------------------------------------------------
140 140 SIGNAL rstn : STD_LOGIC;
141
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
143
141 144 BEGIN -- beh
142 145
143 146 -----------------------------------------------------------------------------
@@ -371,6 +374,8 BEGIN -- beh
371 374 coarse_time => coarse_time,
372 375 fine_time => fine_time,
373 376 data_shaping_BW => bias_fail_sw,
377 observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
374 379 observation_reg => observation_reg);
375 380
376 381
@@ -389,7 +394,7 BEGIN -- beh
389 394 PORT MAP (
390 395 cnv_clk => clk_24, -- TODO : 49.152
391 396 cnv_rstn => rstn, -- ok
392 cnv => ADC_smpclk, -- ok
397 cnv => ADC_smpclk_s, -- ok
393 398 clk => clk_25, -- ok
394 399 rstn => rstn, -- ok
395 400 ADC_data => ADC_data, -- ok
@@ -397,6 +402,8 BEGIN -- beh
397 402 sample => sample, -- ok
398 403 sample_val => sample_val); -- ok
399 404
400 TAG8 <= ADC_smpclk;
405 ADC_smpclk <= ADC_smpclk_s;
406
407 TAG8 <= ADC_smpclk_s;
401 408
402 409 END beh;
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