HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r525:45bbe4445c14

temp (LFR-EM) WFP_MS_1-1-57...

pellion -

r525:45bbe4445c14 JC

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r525:45bbe4445c14

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designs/LFR-em-WFP_MS/LFR-em.vhd +2 -1

                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
+                  IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010138")  -- aa.bb.cc version
+                  top_lfr_version        => X"010139")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM

lib/lpp/lfr_management/apb_lfr_management.vhd +11 -2

               SIGNAL HK_temp_2_s          : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_sel_s             : STD_LOGIC_VECTOR(1 DOWNTO 0);
+              SIGNAL previous_fine_time_bit : STD_LOGIC;
               SIGNAL rstn_LFR_TM : STD_LOGIC;
             BEGIN
               -----------------------------------------------------------------------------
               PROCESS (clk25MHz, resetn)
+                CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11;  -- freq = 2^(16-BIT)
+                                                                -- for 11, the update frequency is 32Hz
+                                                                -- for each HK, the update frequency is freq/3
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   HK_sel_s <= "00";
+                  previous_fine_time_bit <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF HK_val = '1' THEN
+                    IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
+                      previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
                       CASE HK_sel_s IS
                         WHEN "00"   => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
                         WHEN "01"   => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
                         WHEN "10"   => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
                         WHEN OTHERS => NULL;
                       END CASE;
+                    END IF;
                   END IF;
                 END IF;
               HK_sel <= HK_sel_s;
-            END Behavioral;
+            END Behavioral;
  No newline at end of file

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +3 -2

                       PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                                 irqi(i), irqo(i), dbgi(i), dbgo(i));
                   END GENERATE leon3_non_radhard;
                   leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
-                    cpu : ENTITY gaisler.leon3ft
+                    cpu : leon3ft
                       GENERIC MAP (
                         HINDEX     => i,  --: integer;             --CPU_HINDEX,
                         FABTECH    => fabtech,        --CFG_TECH,
-            END Behavioral;
+            END Behavioral;
  No newline at end of file

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