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add MAC + MAC_CONTROLLER
pellion -
r122:0b9053df38a5 JC
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@@ -19,76 +19,68
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 27 --TODO
28 28 --terminer le testbensh puis changer le resize dans les instanciations
29 29 --par un resize sur un vecteur en combi
30 30
31 31
32
33
34
35 entity MAC is
36 generic(
37 Input_SZ_A : integer := 8;
38 Input_SZ_B : integer := 8
32 ENTITY MAC IS
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8
39 36
40 );
41 port(
42 clk : in std_logic;
43 reset : in std_logic;
44 clr_MAC : in std_logic;
45 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
46 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
47 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
48 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
49 );
50 end MAC;
51
52
53
54
55 architecture ar_MAC of MAC is
56
37 );
38 PORT(
39 clk : IN STD_LOGIC;
40 reset : IN STD_LOGIC;
41 clr_MAC : IN STD_LOGIC;
42 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
44 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
45 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
46 );
47 END MAC;
57 48
58 49
59 50
60 51
61 signal add,mult : std_logic;
62 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 ARCHITECTURE ar_MAC OF MAC IS
63 53
64 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
66 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
54 SIGNAL add, mult : STD_LOGIC;
55 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
56
57 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
59 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
67 60
68 61
69 signal MACMUXsel : std_logic;
70 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
71 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
62 SIGNAL MACMUXsel : STD_LOGIC;
63 SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
64 SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
72 65
73 66
74 67
75 signal MACMUX2sel : std_logic;
68 SIGNAL MACMUX2sel : STD_LOGIC;
76 69
77 signal add_D : std_logic;
78 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
79 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
80 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
81 signal MACMUXsel_D : std_logic;
82 signal MACMUX2sel_D : std_logic;
83 signal MACMUX2sel_D_D : std_logic;
84 signal clr_MAC_D : std_logic;
85 signal clr_MAC_D_D : std_logic;
70 SIGNAL add_D : STD_LOGIC;
71 SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
72 SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
73 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
74 SIGNAL MACMUXsel_D : STD_LOGIC;
75 SIGNAL MACMUX2sel_D : STD_LOGIC;
76 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
77 SIGNAL clr_MAC_D : STD_LOGIC;
78 SIGNAL clr_MAC_D_D : STD_LOGIC;
86 79
87
88
80 SIGNAL load_mult_result : STD_LOGIC;
81 SIGNAL load_mult_result_D : STD_LOGIC;
89 82
90
91 begin
83 BEGIN
92 84
93 85
94 86
@@ -96,15 +88,16 begin
96 88 --==============================================================
97 89 --=============M A C C O N T R O L E R=========================
98 90 --==============================================================
99 MAC_CONTROLER1 : MAC_CONTROLER
100 port map(
101 ctrl => MAC_MUL_ADD,
102 MULT => mult,
103 ADD => add,
104 MACMUX_sel => MACMUXsel,
105 MACMUX2_sel => MACMUX2sel
91 MAC_CONTROLER1 : MAC_CONTROLER
92 PORT MAP(
93 ctrl => MAC_MUL_ADD,
94 MULT => mult,
95 ADD => add,
96 LOAD_ADDER => load_mult_result,
97 MACMUX_sel => MACMUXsel,
98 MACMUX2_sel => MACMUX2sel
106 99
107 );
100 );
108 101 --==============================================================
109 102
110 103
@@ -113,166 +106,157 port map(
113 106 --==============================================================
114 107 --=============M U L T I P L I E R==============================
115 108 --==============================================================
116 Multiplieri_nst : Multiplier
117 generic map(
118 Input_SZ_A => Input_SZ_A,
119 Input_SZ_B => Input_SZ_B
120 )
121 port map(
122 clk => clk,
123 reset => reset,
124 mult => mult,
125 OP1 => OP1,
126 OP2 => OP2,
127 RES => MULTout
128 );
129
109 Multiplieri_nst : Multiplier
110 GENERIC MAP(
111 Input_SZ_A => Input_SZ_A,
112 Input_SZ_B => Input_SZ_B
113 )
114 PORT MAP(
115 clk => clk,
116 reset => reset,
117 mult => mult,
118 OP1 => OP1,
119 OP2 => OP2,
120 RES => MULTout
121 );
130 122 --==============================================================
131 123
132
133
134
124 PROCESS (clk, reset)
125 BEGIN -- PROCESS
126 IF reset = '0' THEN -- asynchronous reset (active low)
127 load_mult_result_D <= '0';
128 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 load_mult_result_D <= load_mult_result;
130 END IF;
131 END PROCESS;
132
135 133 --==============================================================
136 134 --======================A D D E R ==============================
137 135 --==============================================================
138 adder_inst : Adder
139 generic map(
140 Input_SZ_A => Input_SZ_A+Input_SZ_B,
141 Input_SZ_B => Input_SZ_A+Input_SZ_B
142 )
143 port map(
144 clk => clk,
145 reset => reset,
146 clr => clr_MAC_D,
147 add => add_D,
148 OP1 => ADDERinA,
149 OP2 => ADDERinB,
150 RES => ADDERout
151 );
152
136 adder_inst : Adder
137 GENERIC MAP(
138 Input_SZ_A => Input_SZ_A+Input_SZ_B,
139 Input_SZ_B => Input_SZ_A+Input_SZ_B
140 )
141 PORT MAP(
142 clk => clk,
143 reset => reset,
144 clr => clr_MAC_D,
145 load => load_mult_result_D,
146 add => add_D,
147 OP1 => ADDERinA,
148 OP2 => ADDERinB,
149 RES => ADDERout
150 );
153 151 --==============================================================
154 152
155 153
156 clr_MACREG1 : MAC_REG
157 generic map(size => 1)
158 port map(
159 reset => reset,
160 clk => clk,
161 D(0) => clr_MAC,
162 Q(0) => clr_MAC_D
163 );
154 clr_MACREG1 : MAC_REG
155 GENERIC MAP(size => 1)
156 PORT MAP(
157 reset => reset,
158 clk => clk,
159 D(0) => clr_MAC,
160 Q(0) => clr_MAC_D
161 );
164 162
165 clr_MACREG2 : MAC_REG
166 generic map(size => 1)
167 port map(
168 reset => reset,
169 clk => clk,
170 D(0) => clr_MAC_D,
171 Q(0) => clr_MAC_D_D
172 );
163 addREG : MAC_REG
164 GENERIC MAP(size => 1)
165 PORT MAP(
166 reset => reset,
167 clk => clk,
168 D(0) => add,
169 Q(0) => add_D
170 );
173 171
174 addREG : MAC_REG
175 generic map(size => 1)
176 port map(
177 reset => reset,
178 clk => clk,
179 D(0) => add,
180 Q(0) => add_D
181 );
172 OP1REG : MAC_REG
173 GENERIC MAP(size => Input_SZ_A)
174 PORT MAP(
175 reset => reset,
176 clk => clk,
177 D => OP1,
178 Q => OP1_D
179 );
182 180
183 OP1REG : MAC_REG
184 generic map(size => Input_SZ_A)
185 port map(
186 reset => reset,
187 clk => clk,
188 D => OP1,
189 Q => OP1_D
190 );
191
181 OP2REG : MAC_REG
182 GENERIC MAP(size => Input_SZ_B)
183 PORT MAP(
184 reset => reset,
185 clk => clk,
186 D => OP2,
187 Q => OP2_D
188 );
192 189
193 OP2REG : MAC_REG
194 generic map(size => Input_SZ_B)
195 port map(
196 reset => reset,
197 clk => clk,
198 D => OP2,
199 Q => OP2_D
200 );
201
190 MULToutREG : MAC_REG
191 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
192 PORT MAP(
193 reset => reset,
194 clk => clk,
195 D => MULTout,
196 Q => MULTout_D
197 );
202 198
203 MULToutREG : MAC_REG
204 generic map(size => Input_SZ_A+Input_SZ_B)
205 port map(
206 reset => reset,
207 clk => clk,
208 D => MULTout,
209 Q => MULTout_D
210 );
211
199 MACMUXselREG : MAC_REG
200 GENERIC MAP(size => 1)
201 PORT MAP(
202 reset => reset,
203 clk => clk,
204 D(0) => MACMUXsel,
205 Q(0) => MACMUXsel_D
206 );
212 207
213 MACMUXselREG : MAC_REG
214 generic map(size => 1)
215 port map(
216 reset => reset,
217 clk => clk,
218 D(0) => MACMUXsel,
219 Q(0) => MACMUXsel_D
220 );
208 MACMUX2selREG : MAC_REG
209 GENERIC MAP(size => 1)
210 PORT MAP(
211 reset => reset,
212 clk => clk,
213 D(0) => MACMUX2sel,
214 Q(0) => MACMUX2sel_D
215 );
221 216
222 MACMUX2selREG : MAC_REG
223 generic map(size => 1)
224 port map(
225 reset => reset,
226 clk => clk,
227 D(0) => MACMUX2sel,
228 Q(0) => MACMUX2sel_D
229 );
230
231 MACMUX2selREG2 : MAC_REG
232 generic map(size => 1)
233 port map(
234 reset => reset,
235 clk => clk,
236 D(0) => MACMUX2sel_D,
237 Q(0) => MACMUX2sel_D_D
238 );
217 MACMUX2selREG2 : MAC_REG
218 GENERIC MAP(size => 1)
219 PORT MAP(
220 reset => reset,
221 clk => clk,
222 D(0) => MACMUX2sel_D,
223 Q(0) => MACMUX2sel_D_D
224 );
239 225
240 226 --==============================================================
241 227 --======================M A C M U X ===========================
242 228 --==============================================================
243 MACMUX_inst : MAC_MUX
244 generic map(
245 Input_SZ_A => Input_SZ_A+Input_SZ_B,
246 Input_SZ_B => Input_SZ_A+Input_SZ_B
229 MACMUX_inst : MAC_MUX
230 GENERIC MAP(
231 Input_SZ_A => Input_SZ_A+Input_SZ_B,
232 Input_SZ_B => Input_SZ_A+Input_SZ_B
247 233
248 )
249 port map(
250 sel => MACMUXsel_D,
251 INA1 => ADDERout,
252 INA2 => OP2_D_Resz,
253 INB1 => MULTout,
254 INB2 => OP1_D_Resz,
255 OUTA => ADDERinA,
256 OUTB => ADDERinB
257 );
258 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
259 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
234 )
235 PORT MAP(
236 sel => MACMUXsel_D,
237 INA1 => ADDERout,
238 INA2 => OP2_D_Resz,
239 INB1 => MULTout,
240 INB2 => OP1_D_Resz,
241 OUTA => ADDERinA,
242 OUTB => ADDERinB
243 );
244 OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B));
245 OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B));
260 246 --==============================================================
261 247
262 248
263 249 --==============================================================
264 250 --======================M A C M U X2 ==========================
265 251 --==============================================================
266 MAC_MUX2_inst : MAC_MUX2
267 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
268 port map(
269 sel => MACMUX2sel_D_D,
270 RES2 => MULTout_D,
271 RES1 => ADDERout,
272 RES => RES
273 );
274
275
252 MAC_MUX2_inst : MAC_MUX2
253 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
254 PORT MAP(
255 sel => MACMUX2sel_D_D,
256 RES2 => MULTout_D,
257 RES1 => ADDERout,
258 RES => RES
259 );
276 260 --==============================================================
277 261
278 end ar_MAC;
262 END ar_MAC;
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@@ -34,6 +34,7 port(
34 34 ctrl : in std_logic_vector(1 downto 0);
35 35 MULT : out std_logic;
36 36 ADD : out std_logic;
37 LOAD_ADDER : out std_logic;
37 38 MACMUX_sel : out std_logic;
38 39 MACMUX2_sel : out std_logic
39 40
@@ -52,8 +53,12 begin
52 53
53 54 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
54 55 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
55 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
56 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
56 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
57 -- to permit to compute a
58 -- MULT follow by a MAC
59 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
60 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
61 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
57 62
58 63
59 64 end ar_MAC_CONTROLER;
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