@@ -1,18 +1,19 | |||
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1 | TECHNOLOGY=PROASIC3 | |
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2 | 1 |
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3 | 2 | SPEED=Std |
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4 | 3 | SYNFREQ=50 |
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5 | 4 | |
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6 | PART=A3PE3000L | |
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5 | TECHNOLOGY=ProASIC3E | |
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6 | LIBERO_DIE=IT14X14M4 | |
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7 | PART=A3PE3000 | |
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8 | ||
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9 | DESIGNER_VOLTAGE=COM | |
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10 | DESIGNER_TEMP=COM | |
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7 | 11 | DESIGNER_PACKAGE=FBGA |
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8 | 12 | DESIGNER_PINS=324 |
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9 | DESIGNER_VOLTAGE=COM | |
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10 | DESIGNER_TEMP=COM | |
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11 | 13 | |
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12 | 14 | MANUFACTURER=Actel |
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15 | MGCTECHNOLOGY=Proasic3 | |
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13 | 16 | MGCPART=$(PART) |
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14 | MGCTECHNOLOGY=PROASIC3 | |
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15 | 17 | MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} |
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16 | LIBERO_DIE=IT14X14M4LDP | |
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17 | 18 | LIBERO_PACKAGE=fg$(DESIGNER_PINS) |
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18 | 19 |
@@ -1,261 +1,286 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; -- PLE |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | USE work.config.ALL; |
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39 | 39 | LIBRARY lpp; |
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40 | 40 | USE lpp.lpp_memory.ALL; |
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41 | 41 | USE lpp.lpp_ad_conv.ALL; |
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42 | 42 | USE lpp.lpp_lfr_pkg.ALL; |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | |
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47 | 47 | ENTITY MINI_LFR_top IS |
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48 | 48 | |
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49 | 49 | PORT ( |
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50 | 50 | clk_50 : IN STD_LOGIC; |
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51 | 51 | clk_49 : IN STD_LOGIC; |
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52 | 52 | reset : IN STD_LOGIC; |
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53 | 53 | --BPs |
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54 | 54 | BP0 : IN STD_LOGIC; |
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55 | 55 | BP1 : IN STD_LOGIC; |
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56 | 56 | --LEDs |
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57 | 57 | LED0 : OUT STD_LOGIC; |
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58 | 58 | LED1 : OUT STD_LOGIC; |
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59 | 59 | LED2 : OUT STD_LOGIC; |
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60 | 60 | --UARTs |
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61 | 61 | TXD1 : IN STD_LOGIC; |
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62 | 62 | RXD1 : OUT STD_LOGIC; |
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63 | 63 | nCTS1 : OUT STD_LOGIC; |
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64 | 64 | nRTS1 : IN STD_LOGIC; |
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65 | 65 | |
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66 | 66 | TXD2 : IN STD_LOGIC; |
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67 | 67 | RXD2 : OUT STD_LOGIC; |
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68 | 68 | nCTS2 : OUT STD_LOGIC; |
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69 | 69 | nDTR2 : IN STD_LOGIC; |
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70 | 70 | nRTS2 : IN STD_LOGIC; |
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71 | 71 | nDCD2 : OUT STD_LOGIC; |
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72 | 72 | |
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73 | 73 | --EXT CONNECTOR |
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74 | 74 | IO0 : INOUT STD_LOGIC; |
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75 | 75 | IO1 : INOUT STD_LOGIC; |
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76 | 76 | IO2 : INOUT STD_LOGIC; |
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77 | 77 | IO3 : INOUT STD_LOGIC; |
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78 | 78 | IO4 : INOUT STD_LOGIC; |
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79 | 79 | IO5 : INOUT STD_LOGIC; |
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80 | 80 | IO6 : INOUT STD_LOGIC; |
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81 | 81 | IO7 : INOUT STD_LOGIC; |
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82 | 82 | IO8 : INOUT STD_LOGIC; |
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83 | 83 | IO9 : INOUT STD_LOGIC; |
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84 | 84 | IO10 : INOUT STD_LOGIC; |
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85 | 85 | IO11 : INOUT STD_LOGIC; |
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86 | 86 | |
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87 | 87 | --SPACE WIRE |
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88 | 88 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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89 | 89 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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90 | 90 | SPW_NOM_SIN : IN STD_LOGIC; |
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91 | 91 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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92 | 92 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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94 | 94 | SPW_RED_SIN : IN STD_LOGIC; |
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95 | 95 | SPW_RED_DOUT : OUT STD_LOGIC; |
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96 | 96 | SPW_RED_SOUT : OUT STD_LOGIC; |
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97 | 97 | -- MINI LFR ADC INPUTS |
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98 | 98 | ADC_nCS : OUT STD_LOGIC; |
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99 | 99 | ADC_CLK : OUT STD_LOGIC; |
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100 | 100 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | 101 | |
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102 | 102 | -- SRAM |
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103 | 103 | SRAM_nWE : OUT STD_LOGIC; |
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104 | 104 | SRAM_CE : OUT STD_LOGIC; |
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105 | 105 | SRAM_nOE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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107 | 107 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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108 | 108 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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109 | 109 | ); |
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110 | 110 | |
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111 | 111 | END MINI_LFR_top; |
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112 | 112 | |
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113 | 113 | |
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114 | 114 | ARCHITECTURE beh OF MINI_LFR_top IS |
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115 | 115 | |
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116 | 116 | COMPONENT leon3_soc |
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117 | 117 | GENERIC ( |
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118 | 118 | fabtech : INTEGER; |
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119 | 119 | memtech : INTEGER; |
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120 | 120 | padtech : INTEGER; |
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121 | 121 | clktech : INTEGER; |
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122 | 122 | disas : INTEGER; |
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123 | 123 | dbguart : INTEGER; |
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124 | 124 | pclow : INTEGER); |
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125 | 125 | PORT ( |
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126 | 126 | clk100MHz : IN STD_ULOGIC; |
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127 | clk49_152MHz : IN STD_ULOGIC; | |
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128 | 127 | reset : IN STD_ULOGIC; |
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129 | 128 | errorn : OUT STD_ULOGIC; |
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130 | 129 | ahbrxd : IN STD_ULOGIC; |
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131 | 130 | ahbtxd : OUT STD_ULOGIC; |
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132 | 131 | urxd1 : IN STD_ULOGIC; |
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133 | 132 | utxd1 : OUT STD_ULOGIC; |
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134 | 133 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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135 | 134 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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136 | 135 | nSRAM_BE0 : OUT STD_LOGIC; |
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137 | 136 | nSRAM_BE1 : OUT STD_LOGIC; |
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138 | 137 | nSRAM_BE2 : OUT STD_LOGIC; |
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139 | 138 | nSRAM_BE3 : OUT STD_LOGIC; |
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140 | 139 | nSRAM_WE : OUT STD_LOGIC; |
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141 | 140 | nSRAM_CE : OUT STD_LOGIC; |
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142 | 141 | nSRAM_OE : OUT STD_LOGIC; |
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143 | 142 | spw1_din : IN STD_LOGIC; |
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144 | 143 | spw1_sin : IN STD_LOGIC; |
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145 | 144 | spw1_dout : OUT STD_LOGIC; |
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146 | 145 | spw1_sout : OUT STD_LOGIC; |
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147 | 146 | spw2_din : IN STD_LOGIC; |
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148 | 147 | spw2_sin : IN STD_LOGIC; |
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149 | 148 | spw2_dout : OUT STD_LOGIC; |
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150 | 149 | spw2_sout : OUT STD_LOGIC; |
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151 |
apbi_ |
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150 | apbi_ext : OUT apb_slv_in_type; | |
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152 | 151 | apbo_wfp : IN apb_slv_out_type; |
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153 |
a |
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154 |
ahb |
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155 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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156 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); | |
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152 | apbo_ltm : IN apb_slv_out_type; | |
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153 | ahbi_ext : OUT AHB_Mst_In_Type; | |
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154 | ahbo_wfp : IN AHB_Mst_Out_Type); | |
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157 | 155 | END COMPONENT; |
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158 | 156 | |
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157 | ----------------------------------------------------------------------------- | |
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158 | SIGNAL apbi : apb_slv_in_type; | |
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159 | SIGNAL apbo_wfp : apb_slv_out_type; | |
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160 | SIGNAL apbo_ltm : apb_slv_out_type; | |
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161 | SIGNAL ahbi : AHB_Mst_In_Type; | |
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162 | SIGNAL ahbo_wfp : AHB_Mst_Out_Type; | |
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163 | -- | |
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164 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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165 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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166 | -- | |
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167 | SIGNAL errorn : STD_LOGIC; | |
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168 | -- UART AHB --------------------------------------------------------------- | |
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169 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
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170 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
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171 | ||
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172 | -- UART APB --------------------------------------------------------------- | |
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173 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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174 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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175 | -- | |
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176 | SIGNAL I00_s : STD_LOGIC; | |
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177 | ||
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159 | 178 | BEGIN -- beh |
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160 | 179 | |
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161 | 180 | PROCESS (clk_50, reset) |
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162 | 181 | BEGIN -- PROCESS |
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163 | 182 | IF reset = '0' THEN -- asynchronous reset (active low) |
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164 | 183 | LED0 <= '0'; |
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165 | 184 | LED1 <= '0'; |
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166 | 185 | LED2 <= '0'; |
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186 | IO1 <= '0'; | |
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187 | IO2 <= '1'; | |
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188 | IO3 <= '0'; | |
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189 | IO4 <= '0'; | |
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190 | IO5 <= '0'; | |
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191 | IO6 <= '0'; | |
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192 | IO7 <= '0'; | |
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193 | IO8 <= '0'; | |
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194 | IO9 <= '0'; | |
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195 | IO10 <= '0'; | |
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196 | IO11 <= '0'; | |
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167 | 197 | ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge |
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168 | 198 | LED0 <= '0'; |
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169 | 199 | LED1 <= '1'; |
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170 | 200 | LED2 <= BP0; |
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171 | END IF; | |
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172 | END PROCESS; | |
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173 | ||
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174 | --UARTs | |
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175 | RXD1 <= '0'; | |
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176 | nCTS1 <= '0'; | |
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177 | RXD2 <= '0'; | |
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178 | nCTS2 <= '0'; | |
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179 | nDCD2 <= '0'; | |
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180 | ||
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181 | --EXT CONNECTOR | |
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182 | IO0 <= clk_49; | |
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183 | IO1 <= clk_50; | |
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184 | ||
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185 | IO2 <= SPW_NOM_DIN OR | |
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186 | SPW_NOM_SIN OR | |
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187 | SPW_RED_DIN OR | |
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188 | SPW_RED_SIN; | |
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189 | ||
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201 | IO1 <= '1'; | |
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202 | IO2 <= '0'; | |
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190 | 203 | IO3 <= ADC_SDO(0); |
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191 | 204 | IO4 <= ADC_SDO(1); |
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192 | 205 | IO5 <= ADC_SDO(2); |
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193 | 206 | IO6 <= ADC_SDO(3); |
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194 | 207 | IO7 <= ADC_SDO(4); |
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195 | 208 | IO8 <= ADC_SDO(5); |
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196 | 209 | IO9 <= ADC_SDO(6); |
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197 | 210 | IO10 <= ADC_SDO(7); |
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198 |
IO11 <= BP1 OR |
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211 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
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212 | END IF; | |
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213 | END PROCESS; | |
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214 | ||
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215 | PROCESS (clk_49, reset) | |
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216 | BEGIN -- PROCESS | |
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217 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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218 | I00_s <= '0'; | |
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219 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge | |
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220 | I00_s <= NOT I00_s; | |
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221 | END IF; | |
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222 | END PROCESS; | |
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223 | IO0 <= I00_s; | |
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224 | ||
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225 | --UARTs | |
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226 | nCTS1 <= '0'; | |
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227 | nCTS2 <= '0'; | |
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228 | nDCD2 <= '0'; | |
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229 | ||
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230 | --EXT CONNECTOR | |
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199 | 231 | |
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200 | 232 | --SPACE WIRE |
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201 | 233 | SPW_EN <= '0'; -- 0 => off |
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202 | SPW_NOM_DOUT <= '0'; | |
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203 | SPW_NOM_SOUT <= '0'; | |
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204 | SPW_RED_DOUT <= '0'; | |
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205 | SPW_RED_SOUT <= '0'; | |
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234 | ||
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206 | 235 |
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207 | 236 | ADC_CLK <= '0'; |
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208 | 237 | |
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209 | -- SRAM | |
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210 | SRAM_nWE <= '1'; | |
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211 | SRAM_CE <= '0'; | |
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212 | SRAM_nOE <= '1'; | |
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213 | SRAM_nBE <= (OTHERS => '1'); | |
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214 | SRAM_A <= (OTHERS => '0'); | |
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215 | SRAM_DQ <= (OTHERS => '0'); | |
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216 | ||
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217 | ||
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218 | 238 |
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219 | 239 | GENERIC MAP ( |
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220 |
fabtech => |
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221 |
memtech => |
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222 |
padtech => |
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223 |
clktech => |
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224 |
disas => |
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225 |
dbguart => |
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226 |
pclow => |
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240 | fabtech => CFG_FABTECH, | |
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241 | memtech => CFG_MEMTECH, | |
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242 | padtech => CFG_PADTECH, | |
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243 | clktech => CFG_CLKTECH, | |
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244 | disas => CFG_DISAS, | |
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245 | dbguart => CFG_DUART, | |
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246 | pclow => CFG_PCLOW) | |
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227 | 247 | PORT MAP ( |
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228 |
clk100MHz => clk |
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229 | clk49_152MHz => clk49_152MHz, | |
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230 | reset => reset, | |
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231 | errorn => errorn, | |
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232 | ahbrxd => ahbrxd, | |
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233 | ahbtxd => ahbtxd, | |
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234 | urxd1 => urxd1, | |
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235 | utxd1 => utxd1, | |
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236 | address => address, | |
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237 | data => data, | |
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238 | nSRAM_BE0 => nSRAM_BE0, | |
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239 | nSRAM_BE1 => nSRAM_BE1, | |
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240 | nSRAM_BE2 => nSRAM_BE2, | |
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241 | nSRAM_BE3 => nSRAM_BE3, | |
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242 | nSRAM_WE => nSRAM_WE, | |
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243 | nSRAM_CE => nSRAM_CE, | |
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244 | nSRAM_OE => nSRAM_OE, | |
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245 | spw1_din => spw1_din, | |
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246 | spw1_sin => spw1_sin, | |
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247 | spw1_dout => spw1_dout, | |
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248 | spw1_sout => spw1_sout, | |
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249 | spw2_din => spw2_din, | |
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250 | spw2_sin => spw2_sin, | |
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251 | spw2_dout => spw2_dout, | |
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252 | spw2_sout => spw2_sout, | |
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253 | apbi_wfp => apbi_wfp, | |
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254 | apbo_wfp => apbo_wfp, | |
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255 | ahbi_wfp => ahbi_wfp, | |
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256 | ahbo_wfp => ahbo_wfp, | |
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257 | coarse_time => coarse_time, | |
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258 | fine_time => fine_time); | |
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248 | clk100MHz => clk_50, -- | |
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249 | reset => reset, -- | |
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250 | errorn => errorn, -- | |
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259 | 251 | |
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252 | ahbrxd => TXD1, -- | |
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253 | ahbtxd => RXD1, -- | |
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254 | urxd1 => TXD2, -- | |
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255 | utxd1 => RXD2, -- | |
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256 | --RAM | |
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257 | address => SRAM_A, -- | |
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258 | data => SRAM_DQ, -- | |
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259 | nSRAM_BE0 => SRAM_nBE(0), -- | |
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260 | nSRAM_BE1 => SRAM_nBE(1), -- | |
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261 | nSRAM_BE2 => SRAM_nBE(2), -- | |
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262 | nSRAM_BE3 => SRAM_nBE(3), -- | |
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263 | nSRAM_WE => SRAM_nWE, -- | |
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264 | nSRAM_CE => SRAM_CE, -- | |
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265 | nSRAM_OE => SRAM_nOE, -- | |
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266 | --SPW | |
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267 | spw1_din => SPW_NOM_DIN, -- | |
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268 | spw1_sin => SPW_NOM_SIN, -- | |
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269 | spw1_dout => SPW_NOM_DOUT, -- | |
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270 | spw1_sout => SPW_NOM_SOUT, -- | |
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271 | spw2_din => SPW_RED_DIN, -- | |
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272 | spw2_sin => SPW_RED_SIN, -- | |
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273 | spw2_dout => SPW_RED_DOUT, -- | |
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274 | spw2_sout => SPW_RED_SOUT, -- | |
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260 | 275 | |
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261 | END beh; | |
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276 | apbi_ext => apbi, -- | |
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277 | apbo_wfp => apbo_wfp, -- | |
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278 | apbo_ltm => apbo_ltm, -- lfr time management | |
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279 | ahbi_ext => ahbi, -- | |
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280 | ahbo_wfp => ahbo_wfp); -- | |
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281 | ||
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282 | apbo_wfp <= apb_none; | |
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283 | apbo_ltm <= apb_none; | |
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284 | ahbo_wfp <= ahbm_none; | |
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285 | ||
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286 | END beh; No newline at end of file |
@@ -1,49 +1,52 | |||
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1 | 1 | VHDLIB=../.. |
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2 | 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
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3 | 3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
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4 | 4 | TOP=MINI_LFR_top |
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5 | 5 | BOARD=MINI-LFR |
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6 | 6 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc |
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7 | 7 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
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8 | 8 | UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf |
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9 | 9 | QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf |
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10 | 10 | EFFORT=high |
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11 | 11 | XSTOPT= |
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12 | 12 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
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13 |
VHDLSYNFILES= |
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14 | config.vhd \ | |
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13 | VHDLSYNFILES= config.vhd \ | |
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14 | MINI_LFR_top.vhd \ | |
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15 | 15 | leon3_soc.vhd |
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16 | 16 | |
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17 | 17 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc |
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18 | 18 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
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19 | 19 | CLEAN=soft-clean |
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20 | 20 | |
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21 | 21 | TECHLIBS = proasic3e |
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22 | 22 | |
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23 | 23 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
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24 | 24 | tmtc openchip hynix ihp gleichmann micron usbhc |
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25 | 25 | |
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26 | 26 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
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27 | 27 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
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28 | 28 | ./amba_lcd_16x2_ctrlr \ |
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29 | 29 | ./general_purpose/lpp_AMR \ |
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30 | 30 | ./general_purpose/lpp_balise \ |
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31 | 31 | ./general_purpose/lpp_delay \ |
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32 | 32 | ./dsp/lpp_fft \ |
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33 | 33 | ./lpp_bootloader \ |
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34 | 34 | ./lpp_cna \ |
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35 | 35 | ./lpp_demux \ |
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36 | 36 | ./lpp_matrix \ |
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37 | 37 | ./lpp_uart \ |
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38 | 38 | ./lpp_usb \ |
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39 | 39 | ./lpp_Header \ |
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40 | 40 | |
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41 |
FILESKIP = |
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41 | FILESKIP =lpp_lfr_ms.vhd \ | |
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42 | i2cmst.vhd \ | |
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42 | 43 | APB_MULTI_DIODE.vhd \ |
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43 | APB_SIMPLE_DIODE.vhd | |
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44 | APB_SIMPLE_DIODE.vhd \ | |
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45 | Top_MatrixSpec.vhd \ | |
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46 | APB_FFT.vhd | |
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44 | 47 | |
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45 | 48 | include $(GRLIB)/bin/Makefile |
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46 | 49 | include $(GRLIB)/software/leon3/Makefile |
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47 | 50 | |
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48 | 51 | ################## project specific targets ########################## |
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49 | 52 |
@@ -1,473 +1,452 | |||
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1 | 1 | ----------------------------------------------------------------------------- |
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2 | 2 | -- LEON3 Demonstration design |
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3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 2 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | 19 | |
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20 | 20 | |
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21 | 21 | LIBRARY ieee; |
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22 | 22 | USE ieee.std_logic_1164.ALL; |
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23 | 23 | LIBRARY grlib; |
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24 | 24 | USE grlib.amba.ALL; |
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25 | 25 | USE grlib.stdlib.ALL; |
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26 | 26 | LIBRARY techmap; |
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27 | 27 | USE techmap.gencomp.ALL; |
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28 | 28 | LIBRARY gaisler; |
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29 | 29 | USE gaisler.memctrl.ALL; |
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30 | 30 | USE gaisler.leon3.ALL; |
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31 | 31 | USE gaisler.uart.ALL; |
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32 | 32 | USE gaisler.misc.ALL; |
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33 | 33 | USE gaisler.spacewire.ALL; -- PLE |
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34 | 34 | LIBRARY esa; |
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35 | 35 | USE esa.memoryctrl.ALL; |
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36 | 36 | USE work.config.ALL; |
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37 | 37 | LIBRARY lpp; |
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38 | 38 | USE lpp.lpp_memory.ALL; |
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39 | 39 | USE lpp.lpp_ad_conv.ALL; |
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40 | 40 | USE lpp.lpp_lfr_pkg.ALL; |
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41 | 41 | USE lpp.iir_filter.ALL; |
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42 | 42 | USE lpp.general_purpose.ALL; |
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43 | 43 | USE lpp.lpp_lfr_time_management.ALL; |
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44 | 44 | |
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45 | 45 | ENTITY leon3_soc IS |
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46 | 46 | GENERIC ( |
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47 | 47 | fabtech : INTEGER := CFG_FABTECH; |
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48 | 48 | memtech : INTEGER := CFG_MEMTECH; |
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49 | 49 | padtech : INTEGER := CFG_PADTECH; |
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50 | 50 | clktech : INTEGER := CFG_CLKTECH; |
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51 | 51 | disas : INTEGER := CFG_DISAS; -- Enable disassembly to console |
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52 | 52 | dbguart : INTEGER := CFG_DUART; -- Print UART on console |
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53 | 53 | pclow : INTEGER := CFG_PCLOW |
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54 | 54 | ); |
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55 | 55 | PORT ( |
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56 | 56 | clk100MHz : IN STD_ULOGIC; |
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57 | clk49_152MHz : IN STD_ULOGIC; | |
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58 | 57 | reset : IN STD_ULOGIC; |
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59 | 58 | |
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60 | 59 | errorn : OUT STD_ULOGIC; |
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61 | 60 | |
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62 | 61 | -- UART AHB --------------------------------------------------------------- |
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63 | 62 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
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64 | 63 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
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65 | 64 | |
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66 | 65 | -- UART APB --------------------------------------------------------------- |
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67 | 66 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
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68 | 67 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
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69 | 68 | |
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70 | 69 | -- RAM -------------------------------------------------------------------- |
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71 | 70 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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72 | 71 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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73 | 72 | nSRAM_BE0 : OUT STD_LOGIC; |
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74 | 73 | nSRAM_BE1 : OUT STD_LOGIC; |
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75 | 74 | nSRAM_BE2 : OUT STD_LOGIC; |
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76 | 75 | nSRAM_BE3 : OUT STD_LOGIC; |
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77 | 76 | nSRAM_WE : OUT STD_LOGIC; |
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78 | 77 | nSRAM_CE : OUT STD_LOGIC; |
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79 | 78 | nSRAM_OE : OUT STD_LOGIC; |
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80 | 79 | |
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81 | 80 | -- SPW -------------------------------------------------------------------- |
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82 | 81 | spw1_din : IN STD_LOGIC; -- PLE |
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83 | 82 | spw1_sin : IN STD_LOGIC; -- PLE |
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84 | 83 | spw1_dout : OUT STD_LOGIC; -- PLE |
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85 | 84 | spw1_sout : OUT STD_LOGIC; -- PLE |
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86 | 85 | |
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87 | 86 | spw2_din : IN STD_LOGIC; -- JCPE --TODO |
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88 | 87 | spw2_sin : IN STD_LOGIC; -- JCPE --TODO |
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89 | 88 | spw2_dout : OUT STD_LOGIC; -- JCPE --TODO |
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90 | 89 | spw2_sout : OUT STD_LOGIC; |
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91 | 90 | |
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92 | 91 | -- WAVEFORM PICKER -------------------------------------------------------- |
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93 |
apbi_ |
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92 | apbi_ext : OUT apb_slv_in_type; | |
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94 | 93 | apbo_wfp : IN apb_slv_out_type; |
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95 | ahbi_wfp : OUT AHB_Mst_In_Type; | |
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96 |
ahb |
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97 | -- TIME ------------------------------------------------------------------- | |
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98 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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99 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) | |
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94 | apbo_ltm : IN apb_slv_out_type; | |
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95 | ahbi_ext : OUT AHB_Mst_In_Type; | |
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96 | ahbo_wfp : IN AHB_Mst_Out_Type | |
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100 | 97 | |
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101 | 98 | ); |
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102 | 99 | END; |
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103 | 100 | |
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104 | 101 | ARCHITECTURE Behavioral OF leon3_soc IS |
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105 | 102 | |
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106 | 103 | --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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107 | 104 | -- CFG_GRETH+CFG_AHB_JTAG; |
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108 | 105 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ |
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109 | 106 | CFG_AHB_UART |
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110 | 107 | +2; |
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111 | 108 | -- 1 is for the SpaceWire module grspw, which is a master |
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112 | 109 | -- 1 is for the LFR |
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113 | 110 | |
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114 | 111 | CONSTANT maxahbm : INTEGER := maxahbmsp; |
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115 | 112 | |
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116 | 113 | --Clk & Rst gοΏ½nοΏ½ |
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117 | 114 | SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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118 | 115 | SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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119 | 116 | SIGNAL resetnl : STD_ULOGIC; |
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120 | 117 | SIGNAL clk2x : STD_ULOGIC; |
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121 | 118 | SIGNAL lclk2x : STD_ULOGIC; |
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122 | 119 | SIGNAL lclk25MHz : STD_ULOGIC; |
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123 | 120 | SIGNAL lclk50MHz : STD_ULOGIC; |
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124 | 121 | SIGNAL lclk100MHz : STD_ULOGIC; |
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125 | 122 | SIGNAL clkm : STD_ULOGIC; |
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126 | 123 | SIGNAL rstn : STD_ULOGIC; |
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127 | 124 | SIGNAL rstraw : STD_ULOGIC; |
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128 | 125 | SIGNAL pciclk : STD_ULOGIC; |
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129 | 126 | SIGNAL sdclkl : STD_ULOGIC; |
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130 | 127 | SIGNAL cgi : clkgen_in_type; |
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131 | 128 | SIGNAL cgo : clkgen_out_type; |
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132 | 129 | --- AHB / APB |
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133 | 130 | SIGNAL apbi : apb_slv_in_type; |
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134 | 131 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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135 | 132 | SIGNAL ahbsi : ahb_slv_in_type; |
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136 | 133 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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137 | 134 | SIGNAL ahbmi : ahb_mst_in_type; |
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138 | 135 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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139 | 136 | --UART |
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140 | 137 | SIGNAL ahbuarti : uart_in_type; |
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141 | 138 | SIGNAL ahbuarto : uart_out_type; |
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142 | 139 | SIGNAL apbuarti : uart_in_type; |
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143 | 140 | SIGNAL apbuarto : uart_out_type; |
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144 | 141 | --MEM CTRLR |
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145 | 142 | SIGNAL memi : memory_in_type; |
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146 | 143 | SIGNAL memo : memory_out_type; |
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147 | 144 | SIGNAL wpo : wprot_out_type; |
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148 | 145 | SIGNAL sdo : sdram_out_type; |
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149 | 146 | SIGNAL ramcs : STD_ULOGIC; |
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150 | 147 | --IRQ |
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151 | 148 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
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152 | 149 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
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153 | 150 | --Timer |
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154 | 151 | SIGNAL gpti : gptimer_in_type; |
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155 | 152 | SIGNAL gpto : gptimer_out_type; |
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156 | 153 | --GPIO |
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157 | 154 | SIGNAL gpioi : gpio_in_type; |
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158 | 155 | SIGNAL gpioo : gpio_out_type; |
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159 | 156 | --DSU |
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160 | 157 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
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161 | 158 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
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162 | 159 | SIGNAL dsui : dsu_in_type; |
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163 | 160 | SIGNAL dsuo : dsu_out_type; |
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164 | 161 | |
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165 | 162 | --------------------------------------------------------------------- |
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166 | 163 | --- AJOUT TEST ------------------------Signaux---------------------- |
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167 | 164 | --------------------------------------------------------------------- |
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168 | 165 | |
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169 | 166 | --------------------------------------------------------------------- |
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170 | 167 | CONSTANT IOAEN : INTEGER := CFG_CAN; |
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171 | 168 | CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz |
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172 | 169 | |
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173 | 170 | -- Spacewire signals |
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174 | 171 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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175 | 172 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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176 | 173 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE |
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177 | 174 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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178 | 175 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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179 | 176 | SIGNAL spw_clk : STD_LOGIC; |
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180 | 177 | SIGNAL swni : grspw_in_type; -- PLE |
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181 | 178 | SIGNAL swno : grspw_out_type; -- PLE |
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182 | 179 | SIGNAL clkmn : STD_ULOGIC; -- PLE |
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183 | 180 | SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 |
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184 | 181 | ----------------------------------------------------------------------------- |
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185 | 182 | |
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186 | 183 | BEGIN |
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187 | 184 | |
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188 | 185 | |
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189 | 186 | ---------------------------------------------------------------------- |
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190 | 187 | --- Reset and Clock generation ------------------------------------- |
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191 | 188 | ---------------------------------------------------------------------- |
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192 | 189 | |
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193 | 190 | vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); |
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194 | 191 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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195 | 192 | |
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196 | 193 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
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197 | 194 | |
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198 | 195 | |
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199 | 196 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); |
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200 | 197 | |
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201 | 198 | clkgen0 : clkgen -- clock generator |
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202 | 199 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
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203 | 200 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
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204 | 201 | PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
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205 | 202 | |
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206 | 203 | PROCESS(lclk100MHz) |
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207 | 204 | BEGIN |
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208 | 205 | IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN |
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209 | 206 | lclk50MHz <= NOT lclk50MHz; |
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210 | 207 | END IF; |
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211 | 208 | END PROCESS; |
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212 | 209 | |
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213 | 210 | PROCESS(lclk50MHz) |
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214 | 211 | BEGIN |
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215 | 212 | IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN |
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216 | 213 | lclk25MHz <= NOT lclk25MHz; |
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217 | 214 | END IF; |
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218 | 215 | END PROCESS; |
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219 | 216 | |
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220 | 217 | lclk2x <= lclk50MHz; |
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221 | 218 | spw_clk <= lclk50MHz; |
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222 | 219 | |
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223 | 220 | ---------------------------------------------------------------------- |
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224 | 221 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
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225 | 222 | ---------------------------------------------------------------------- |
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226 | 223 | |
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227 | 224 | l3 : IF CFG_LEON3 = 1 GENERATE |
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228 | 225 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
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229 | 226 | u0 : leon3s -- LEON3 processor |
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230 | 227 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
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231 | 228 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
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232 | 229 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
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233 | 230 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
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234 | 231 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
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235 | 232 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
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236 | 233 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
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237 | 234 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
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238 | 235 | END GENERATE; |
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239 | 236 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
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240 | 237 | |
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241 | 238 | dsugen : IF CFG_DSU = 1 GENERATE |
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242 | 239 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
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243 | 240 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
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244 | 241 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
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245 | 242 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
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246 | 243 | dsui.enable <= '1'; |
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247 | 244 | dsui.break <= '0'; |
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248 | 245 | END GENERATE; |
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249 | 246 | END GENERATE; |
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250 | 247 | |
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251 | 248 | nodsu : IF CFG_DSU = 0 GENERATE |
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252 | 249 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
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253 | 250 | END GENERATE; |
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254 | 251 | |
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255 | 252 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
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256 | 253 | irqctrl0 : irqmp -- interrupt controller |
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257 | 254 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
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258 | 255 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
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259 | 256 | END GENERATE; |
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260 | 257 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
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261 | 258 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
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262 | 259 | irqi(i).irl <= "0000"; |
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263 | 260 | END GENERATE; |
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264 | 261 | apbo(2) <= apb_none; |
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265 | 262 | END GENERATE; |
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266 | 263 | |
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267 | 264 | ---------------------------------------------------------------------- |
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268 | 265 | --- Memory controllers --------------------------------------------- |
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269 | 266 | ---------------------------------------------------------------------- |
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270 | 267 | memctrlr : mctrl GENERIC MAP ( |
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271 | 268 | hindex => 0, |
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272 | 269 | pindex => 0, |
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273 | 270 | paddr => 0, |
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274 | 271 | srbanks => 1 |
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275 | 272 | ) |
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276 | 273 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
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277 | 274 | |
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278 | 275 | memi.brdyn <= '1'; |
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279 | 276 | memi.bexcn <= '1'; |
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280 | 277 | memi.writen <= '1'; |
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281 | 278 | memi.wrn <= "1111"; |
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282 | 279 | memi.bwidth <= "10"; |
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283 | 280 | |
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284 | 281 | bdr : FOR i IN 0 TO 3 GENERATE |
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285 | 282 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
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286 | 283 | PORT MAP ( |
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287 | 284 | data(31-i*8 DOWNTO 24-i*8), |
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288 | 285 | memo.data(31-i*8 DOWNTO 24-i*8), |
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289 | 286 | memo.bdrive(i), |
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290 | 287 | memi.data(31-i*8 DOWNTO 24-i*8)); |
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291 | 288 | END GENERATE; |
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292 | 289 | |
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293 | 290 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
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294 | 291 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
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295 | 292 | |
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296 | 293 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); |
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297 | 294 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
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298 | 295 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
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299 | 296 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
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300 | 297 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
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301 | 298 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
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302 | 299 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
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303 | 300 | |
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304 | 301 | ---------------------------------------------------------------------- |
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305 | 302 | --- AHB CONTROLLER ------------------------------------------------- |
|
306 | 303 | ---------------------------------------------------------------------- |
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307 | 304 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
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308 | 305 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
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309 | 306 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
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310 | 307 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
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311 | 308 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
312 | 309 | |
|
313 | 310 | ---------------------------------------------------------------------- |
|
314 | 311 | --- AHB UART ------------------------------------------------------- |
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315 | 312 | ---------------------------------------------------------------------- |
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316 | 313 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
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317 | 314 | dcom0 : ahbuart |
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318 | 315 | GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) |
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319 | 316 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); |
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320 | 317 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
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321 | 318 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
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322 | 319 | END GENERATE; |
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323 | 320 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
324 | 321 | |
|
325 | 322 | ---------------------------------------------------------------------- |
|
326 | 323 | --- APB Bridge ----------------------------------------------------- |
|
327 | 324 | ---------------------------------------------------------------------- |
|
328 | 325 | apb0 : apbctrl -- AHB/APB bridge |
|
329 | 326 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
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330 | 327 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
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331 | 328 | |
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332 | 329 | ---------------------------------------------------------------------- |
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333 | 330 | --- GPT Timer ------------------------------------------------------ |
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334 | 331 | ---------------------------------------------------------------------- |
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335 | 332 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
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336 | 333 | timer0 : gptimer -- timer unit |
|
337 | 334 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
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338 | 335 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
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339 | 336 | nbits => CFG_GPT_TW) |
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340 | 337 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
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341 | 338 | gpti.dhalt <= dsuo.tstop; |
|
342 | 339 | gpti.extclk <= '0'; |
|
343 | 340 | END GENERATE; |
|
344 | 341 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
345 | 342 | |
|
346 | 343 | |
|
347 | 344 | ---------------------------------------------------------------------- |
|
348 | 345 | --- APB UART ------------------------------------------------------- |
|
349 | 346 | ---------------------------------------------------------------------- |
|
350 | 347 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
351 | 348 | uart1 : apbuart -- UART 1 |
|
352 | 349 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
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353 | 350 | fifosize => CFG_UART1_FIFO) |
|
354 | 351 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
355 | 352 | apbuarti.rxd <= urxd1; |
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356 | 353 | apbuarti.extclk <= '0'; |
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357 | 354 | utxd1 <= apbuarto.txd; |
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358 | 355 | apbuarti.ctsn <= '0'; |
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359 | 356 | END GENERATE; |
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360 | 357 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
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361 | 358 | |
|
362 | ------------------------------------------------------------------------------- | |
|
363 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
|
364 | ------------------------------------------------------------------------------- | |
|
365 | apb_lfr_time_management_1: apb_lfr_time_management | |
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366 | GENERIC MAP ( | |
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367 | pindex => 6, | |
|
368 | paddr => 6, | |
|
369 | pmask => 16#fff#, | |
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370 | pirq => 12) | |
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371 | PORT MAP ( | |
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372 | clk25MHz => clkm, | |
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373 | clk49_152MHz => clk49_152MHz, | |
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374 | resetn => rstn, | |
|
375 | grspw_tick => swno.tickout, | |
|
376 | apbi => apbi, | |
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377 | apbo => apbo(6), | |
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378 | coarse_time => coarse_time, | |
|
379 | fine_time => fine_time); | |
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380 | ||
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381 | 359 | ----------------------------------------------------------------------- |
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382 | 360 | --- SpaceWire -------------------------------------------------------- |
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383 | 361 | ----------------------------------------------------------------------- |
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384 | 362 | |
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385 | 363 | spw_rxtxclk <= spw_clk; |
|
386 | 364 | spw_rxclkn <= NOT spw_rxtxclk; |
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387 | 365 | |
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388 | 366 | -- PADS for SPW1 |
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389 | 367 | spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) |
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390 | 368 | PORT MAP (spw1_din, dtmp(0)); |
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391 | 369 | spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) |
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392 | 370 | PORT MAP (spw1_sin, stmp(0)); |
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393 | 371 | spw1_txd_pad : outpad GENERIC MAP (tech => padtech) |
|
394 | 372 | PORT MAP (spw1_dout, swno.d(0)); |
|
395 | 373 | spw1_txs_pad : outpad GENERIC MAP (tech => padtech) |
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396 | 374 | PORT MAP (spw1_sout, swno.s(0)); |
|
397 | 375 | -- PADS FOR SPW2 |
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398 | 376 | spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) |
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399 | 377 | PORT MAP (spw2_din, dtmp(1)); |
|
400 | 378 | spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) |
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401 | 379 | PORT MAP (spw2_sin, stmp(1)); |
|
402 | 380 | spw2_txd_pad : outpad GENERIC MAP (tech => padtech) |
|
403 | 381 | PORT MAP (spw2_dout, swno.d(1)); |
|
404 | 382 | spw2_txs_pad : outpad GENERIC MAP (tech => padtech) |
|
405 | 383 | PORT MAP (spw2_sout, swno.s(1)); |
|
406 | 384 | |
|
407 | 385 | -- GRSPW PHY |
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408 | 386 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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409 | 387 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
410 | 388 | spw_phy0 : grspw_phy |
|
411 | 389 | GENERIC MAP( |
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412 | 390 | tech => fabtech, |
|
413 | 391 | rxclkbuftype => 1, |
|
414 | 392 | scantest => 0) |
|
415 | 393 | PORT MAP( |
|
416 | 394 | rxrst => swno.rxrst, |
|
417 | 395 | di => dtmp(j), |
|
418 | 396 | si => stmp(j), |
|
419 | 397 | rxclko => spw_rxclk(j), |
|
420 | 398 | do => swni.d(j), |
|
421 | 399 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
422 | 400 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
423 | 401 | END GENERATE spw_inputloop; |
|
424 | 402 | |
|
425 | 403 | -- SPW core |
|
426 | 404 | sw0 : grspwm |
|
427 | 405 | GENERIC MAP( |
|
428 | 406 | tech => apa3e, |
|
429 | 407 | hindex => 1, |
|
430 | 408 | pindex => 5, |
|
431 | 409 | paddr => 5, |
|
432 | 410 | pirq => 11, |
|
433 | 411 | sysfreq => 25000, -- CPU_FREQ |
|
434 | 412 | rmap => 1, |
|
435 | 413 | rmapcrc => 1, |
|
436 | 414 | fifosize1 => 16, |
|
437 | 415 | fifosize2 => 16, |
|
438 | 416 | rxclkbuftype => 1, |
|
439 | 417 | rxunaligned => 0, |
|
440 | 418 | rmapbufs => 4, |
|
441 | 419 | ft => 0, |
|
442 | 420 | netlist => 0, |
|
443 | 421 | ports => 2, |
|
444 | 422 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
445 | 423 | memtech => apa3e, |
|
446 | 424 | destkey => 2, |
|
447 | 425 | spwcore => 1 |
|
448 | 426 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
449 | 427 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
450 | 428 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
451 | 429 | ) |
|
452 | 430 | PORT MAP(rstn, clkm, spw_rxclk(0), |
|
453 | 431 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
454 | 432 | ahbmi, ahbmo(1), apbi, apbo(5), |
|
455 | 433 | swni, swno); |
|
456 | 434 | |
|
457 | 435 | swni.tickin <= '0'; |
|
458 | 436 | swni.rmapen <= '1'; |
|
459 | 437 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
460 | 438 | swni.tickinraw <= '0'; |
|
461 | 439 | swni.timein <= (OTHERS => '0'); |
|
462 | 440 | swni.dcrstval <= (OTHERS => '0'); |
|
463 | 441 | swni.timerrstval <= (OTHERS => '0'); |
|
464 | 442 | |
|
465 | 443 | ------------------------------------------------------------------------------- |
|
466 | 444 | -- LFR |
|
467 | 445 | ------------------------------------------------------------------------------- |
|
468 |
apbi_ |
|
|
446 | apbi_ext <= apbi; | |
|
469 | 447 | apbo(15) <= apbo_wfp; |
|
470 | ahbi_wfp <= ahbmi; | |
|
448 | apbo(6) <= apbo_ltm; | |
|
449 | ahbi_ext <= ahbmi; | |
|
471 | 450 | ahbmo(2) <= ahbo_wfp; |
|
472 | 451 | |
|
473 | 452 | END Behavioral; |
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