# HG changeset patch
# User Alexis Jeandet
# Date 2016-12-09 14:22:54
# Node ID f6e57cae6ba0b421281e6f49e593c5db2165df65
# Parent  f5c31dc5d20d2d3f9678ab895ed5290fa69c04e1

Updated SOLO_LFR_LFR-FM designs
        => added DATA_SHAPING_SATURATION in LPP_FILTER
        => changed boards number : LPP_LFR_BOARD_LFR_FM & X"015B"

diff --git a/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd b/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
--- a/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
+++ b/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd
@@ -450,14 +450,11 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"030159",  -- aa.bb.cc version
-                                            -- AA : BOARD NUMBER
-                                            --      0 => MINI_LFR
-                                            --      1 => EM
-                                            --      2 => EQM (with A3PE3000)
+      top_lfr_version        => LPP_LFR_BOARD_LFR_FM & X"015B",
       DEBUG_FORCE_DATA_DMA        => DEBUG_FORCE_DATA_DMA,
       RTL_DESIGN_LIGHT            =>0,
-      WINDOWS_HAANNING_PARAM_SIZE => 15)
+      WINDOWS_HAANNING_PARAM_SIZE => 15,
+      DATA_SHAPING_SATURATION     => 1)
     PORT MAP (
       clk             => clk_25,
       rstn            => LFR_rstn,
diff --git a/designs/SOLO_LFR_LFR-FM/Makefile b/designs/SOLO_LFR_LFR-FM/Makefile
--- a/designs/SOLO_LFR_LFR-FM/Makefile
+++ b/designs/SOLO_LFR_LFR-FM/Makefile
@@ -17,7 +17,7 @@ VHDLSYNFILES=LFR-FM.vhd
 VHDLSIMFILES=
 
 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX.pdc
-SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
+SDC=$(VHDLIB)/boards/$(BOARD)/LFR_FM_RTAX_layout.sdc
 
 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
 CLEAN=soft-clean