# HG changeset patch
# User Alexis
# Date 2010-10-26 17:59:33
# Node ID d63cd96dab77d75acee625fe1092de4d863c69a2
# Parent 98955b8fb9a7768df9705a206f99e8311dc06662
aded GRLIB Automated patcher
diff --git a/.hgignore b/.hgignore
new file mode 100644
--- /dev/null
+++ b/.hgignore
@@ -0,0 +1,15 @@
+# use glob syntax.
+syntax: glob
+
+*.tex
+*.html
+*log*
+*.png
+*.dot
+*.css
+*.md5
+*.eps
+*.pdf
+*.toc
+*~
+
diff --git a/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd b/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/FRAME_CLK.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:21:03 10/19/2010
--- Design Name:
--- Module Name: FRAME_CLK_GEN - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity FRAME_CLK_GEN is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- FRAME_CLK : out STD_LOGIC);
-end FRAME_CLK_GEN;
-
-architecture Behavioral of FRAME_CLK_GEN is
-
-Constant Goal_FRAME_CLK_FREQ : integer := 20;
-
-Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
-
-signal CPT : integer := 0;
-signal FRAME_CLK_reg : std_logic :='0';
-
-begin
-
-FRAME_CLK <= FRAME_CLK_reg;
-
-process(reset,clk)
-begin
- if reset = '0' then
- CPT <= 0;
- FRAME_CLK_reg <= '0';
- elsif clk'event and clk = '1' then
- if CPT = FRAME_CLK_TRIG then
- CPT <= 0;
- FRAME_CLK_reg <= not FRAME_CLK_reg;
- else
- CPT <= CPT + 1;
- end if;
- end if;
-end process;
-end Behavioral;
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_CFG.vhd
+++ /dev/null
@@ -1,57 +0,0 @@
--- Package File Template
---
--- Purpose: This package defines supplemental types, subtypes,
--- constants, and functions
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package LCD_16x2_CFG is
-
- type LCD_DRVR_CTRL_BUSS is
- record
- LCD_RW : std_logic;
- LCD_RS : std_logic;
- LCD_E : std_logic;
- LCD_DATA : std_logic_vector(7 downto 0);
- end record;
-
- type LCD_DRVR_SYNCH_BUSS is
- record
- DRVR_READY : std_logic;
- LCD_INITIALISED : std_logic;
- end record;
-
-
- type LCD_DRVR_CMD_BUSS is
- record
- Word : std_logic_vector(7 downto 0);
- CMD_Data : std_logic; --CMD = '0' and data = '1'
- Exec : std_logic;
- Duration : std_logic_vector(1 downto 0);
- end record;
- type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
-
-
-constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
-constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
-constant RetHome : std_logic_vector(7 downto 0):= X"02";
-constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
-constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C";
-
-constant CursorON : std_logic_vector(7 downto 0):= X"0E";
-constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
-
---===========================================================|
---======L C D D R I V E R T I M I N G C O D E=====|
---===========================================================|
-
-constant Duration_4us : std_logic_vector(1 downto 0) := "00";
-constant Duration_100us : std_logic_vector(1 downto 0) := "01";
-constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
-constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
-
-
-end LCD_16x2_CFG;
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/LCD_16x2_ENGINE.vhd
+++ /dev/null
@@ -1,206 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:32:21 10/19/2010
--- Design Name:
--- Module Name: LCD_16x2_ENGINE - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.LCD_16x2_CFG.all;
-
-entity LCD_16x2_ENGINE is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- DATA : in std_logic_vector(16*2*8-1 downto 0);
- CMD : in std_logic_vector(10 downto 0);
- Exec : in std_logic;
- Ready : out std_logic;
- LCD_CTRL : out LCD_DRVR_CTRL_BUSS
- );
-end LCD_16x2_ENGINE;
-
-architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
-
-constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
-
-
-
-signal SYNCH : LCD_DRVR_SYNCH_BUSS;
-signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
-signal FRAME_CLK : std_logic;
-
-signal FRAME_CLK_reg : std_logic;
-signal RefreshFlag : std_logic;
-signal CMD_Flag : std_logic;
-signal Exec_Reg : std_logic;
-
-type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
-signal state : state_t;
-signal i : integer range 0 to 32 := 0;
-
-
-
-begin
-
-Driver0 : entity work.LCD_16x2_DRIVER
- generic map(OSC_freqKHz)
- Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
-
-FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN
- generic map(OSC_freqKHz)
- Port map( clk,reset,FRAME_CLK);
-
-
-
-process(reset,clk)
-begin
- if reset = '0' then
- state <= INIT0;
- Ready <= '0';
- RefreshFlag <= '0';
- i <= 0;
- elsif clk'event and clk ='1' then
- FRAME_CLK_reg <= FRAME_CLK;
- Exec_Reg <= Exec;
-
- if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
- RefreshFlag <= '1';
- elsif state = Refresh or state = Refresh0 or state = Refresh1 then
- RefreshFlag <= '0';
- end if;
-
- if Exec_Reg = '0' and Exec = '1' then
- CMD_Flag <= '1';
- elsif state = ExecCMD0 or state = ExecCMD1 then
- CMD_Flag <= '0';
- end if;
-
- case state is
- when INIT0 =>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_20ms;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= ConfigTbl(i);
- i <= i + 1;
- state <= INIT1;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when INIT1 =>
- state <= INIT2;
- DRIVER_CMD.Exec <= '0';
- when INIT2 =>
- if SYNCH.DRVR_READY = '1' then
- if i = 5 then
- state <= Idle;
- else
- state <= INIT0;
- end if;
- end if;
- when Idle=>
- DRIVER_CMD.Exec <= '0';
- if RefreshFlag = '1' then
- Ready <= '0';
- state <= Refresh;
- elsif CMD_Flag = '1' then
- Ready <= '0';
- state <= ExecCMD0;
- else
- Ready <= '1';
- end if;
- i <= 0;
- when Refresh=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_100us;
- DRIVER_CMD.CMD_Data <= '1';
- DRIVER_CMD.Word <= DATA(i*8+7 downto i*8);
- i <= i + 1;
- state <= Refresh0;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when Refresh0=>
- state <= Refresh1;
- DRIVER_CMD.Exec <= '0';
- when Refresh1=>
- if SYNCH.DRVR_READY = '1' then
- if i = 32 then
- state <= ReturnHome;
- elsif i = 16 then
- state <= GoLine2;
- else
- state <= Refresh;
- end if;
- end if;
-
- when ExecCMD0=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= CMD(9 downto 8);
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= CMD(7 downto 0);
- state <= ExecCMD1;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
-
- when ExecCMD1=>
- state <= Idle;
- DRIVER_CMD.Exec <= '0';
-
- when GoLine2=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_100us;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= X"C0";
- state <= GoLine2_0;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when GoLine2_0=>
- state <= Refresh;
- DRIVER_CMD.Exec <= '0';
- when ReturnHome=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_4ms;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= X"02";
- state <= Idle;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- end case;
- end if;
-end process;
-
-
-end ar_LCD_16x2_ENGINE;
-
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/LCD_2x16_DRIVER.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 10:09:57 10/13/2010
--- Design Name:
--- Module Name: LCD_2x16_DRIVER - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.all;
-
-
-entity LCD_2x16_DRIVER is
- generic(
- OSC_Freq_MHz : integer:=60;
- Refresh_RateHz : integer:=5
- );
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
- LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
- LCD_RS : out STD_LOGIC;
- LCD_RW : out STD_LOGIC;
- LCD_E : out STD_LOGIC;
- LCD_RET : out STD_LOGIC;
- LCD_CS1 : out STD_LOGIC;
- LCD_CS2 : out STD_LOGIC;
- STATEOUT: out std_logic_vector(3 downto 0);
- refreshPulse : out std_logic
- );
-end LCD_2x16_DRIVER;
-
-architecture Behavioral of LCD_2x16_DRIVER is
-
-type stateT is(Rst,Configure,IDLE,RefreshScreen);
-signal state : stateT;
-
-signal ShortTimePulse : std_logic;
-signal MidleTimePulse : std_logic;
-signal Refresh_RatePulse : std_logic;
-signal Start : STD_LOGIC;
-
-signal CFGM_LCD_RS : std_logic;
-signal CFGM_LCD_RW : std_logic;
-signal CFGM_LCD_E : std_logic;
-signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
-signal CFGM_Enable : std_logic;
-signal CFGM_completed : std_logic;
-
-
-signal FRMW_LCD_RS : std_logic;
-signal FRMW_LCD_RW : std_logic;
-signal FRMW_LCD_E : std_logic;
-signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
-signal FRMW_Enable : std_logic;
-signal FRMW_completed : std_logic;
-
-begin
-
-
-Counter : entity work.LCD_Counter
-generic map(OSC_Freq_MHz,Refresh_RateHz)
-port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
-
-ConfigModule : entity work.Config_Module
-port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
-
-
-FrameWriter : entity work.FRAME_WRITER
-port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
-
-
-STATEOUT(0) <= '1' when state = Rst else '0';
-STATEOUT(1) <= '1' when state = Configure else '0';
-STATEOUT(2) <= '1' when state = IDLE else '0';
-STATEOUT(3) <= '1' when state = RefreshScreen else '0';
-
-
-
-refreshPulse <= Refresh_RatePulse;
-
-Start <= '1';
-
-process(reset,clk)
-begin
- if reset = '0' then
- LCD_data <= (others=>'0');
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_RET <= '0';
- LCD_CS1 <= '0';
- LCD_CS2 <= '0';
- LCD_E <= '0';
- state <= Rst;
- CFGM_Enable <= '0';
- FRMW_Enable <= '0';
- elsif clk'event and clk ='1' then
- case state is
- when Rst =>
- LCD_data <= (others=>'0');
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_E <= '0';
- CFGM_Enable <= '1';
- FRMW_Enable <= '0';
- if Refresh_RatePulse = '1' then
- state <= Configure;
- end if;
- when Configure =>
- LCD_data <= CFGM_LCD_data;
- LCD_RS <= CFGM_LCD_RS;
- LCD_RW <= CFGM_LCD_RW;
- LCD_E <= CFGM_LCD_E;
- CFGM_Enable <= '0';
- if CFGM_completed = '1' then
- state <= IDLE;
- end if;
- when IDLE =>
- if Refresh_RatePulse = '1' then
- state <= RefreshScreen;
- FRMW_Enable <= '1';
- end if;
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_E <= '0';
- LCD_data <= (others=>'0');
- when RefreshScreen =>
- LCD_data <= FRMW_LCD_data;
- LCD_RS <= FRMW_LCD_RS;
- LCD_RW <= FRMW_LCD_RW;
- LCD_E <= FRMW_LCD_E;
- FRMW_Enable <= '0';
- if FRMW_completed = '1' then
- state <= IDLE;
- end if;
- end case;
- end if;
-end process;
-end Behavioral;
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd b/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/LCD_CLK_GENERATOR.vhd
+++ /dev/null
@@ -1,72 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:52:25 10/18/2010
--- Design Name:
--- Module Name: LCD_CLK_GENERATOR - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity LCD_CLK_GENERATOR is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- clk_1us : out STD_LOGIC);
-end LCD_CLK_GENERATOR;
-
-architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
-
-Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
-
-
-signal cpt1 : integer;
-
-signal clk_1us_int : std_logic := '0';
-
-
-begin
-
-clk_1us <= clk_1us_int;
-
-
-process(reset,clk)
-begin
- if reset = '0' then
- cpt1 <= 0;
- clk_1us_int <= '0';
- elsif clk'event and clk = '1' then
- if cpt1 = clk_1usTRIGER then
- clk_1us_int <= not clk_1us_int;
- cpt1 <= 0;
- else
- cpt1 <= cpt1 + 1;
- end if;
- end if;
-end process;
-
-
-end ar_LCD_CLK_GENERATOR;
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd b/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/Top_LCD.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:44:41 10/14/2010
--- Design Name:
--- Module Name: Top_LCD - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.LCD_16x2_CFG.all;
-
-entity Top_LCD is
- Port ( reset : in STD_LOGIC;
- clk : in STD_LOGIC;
- Bp0 : in STD_LOGIC;
- Bp1 : in STD_LOGIC;
- Bp2 : in STD_LOGIC;
- LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
- LCD_RS : out STD_LOGIC;
- LCD_RW : out STD_LOGIC;
- LCD_E : out STD_LOGIC;
- LCD_RET : out STD_LOGIC;
- LCD_CS1 : out STD_LOGIC;
- LCD_CS2 : out STD_LOGIC;
- SF_CE0 : out std_logic
- );
-end Top_LCD;
-
-architecture Behavioral of Top_LCD is
-
-signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
-signal CMD : std_logic_vector(10 downto 0);
-signal Exec : std_logic;
-signal Ready : std_logic;
-signal rst : std_logic;
-signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
-
-begin
-
-LCD_data <= LCD_CTRL.LCD_DATA;
-LCD_RS <= LCD_CTRL.LCD_RS;
-LCD_RW <= LCD_CTRL.LCD_RW;
-LCD_E <= LCD_CTRL.LCD_E;
-
-
-LCD_RET <= '0';
-LCD_CS1 <= '0';
-LCD_CS2 <= '0';
-
-SF_CE0 <= '1';
-
-rst <= not reset;
-
-
-
-Driver0 : entity work.LCD_16x2_ENGINE
- generic map(50000)
- Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
-
-FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
- X"42" when Bp1 = '1' else
- X"43" when Bp2 = '1' else
- X"44";
-
-FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
- X"47" when Bp1 = '1' else
- X"48" when Bp2 = '1' else
- X"49";
-
-
-CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
- Duration_100us & CursorOFF;
-
-
-Exec <= Bp1;
-
-FramBUFF(2*8+7 downto 2*8) <= X"23";
-FramBUFF(3*8+7 downto 3*8) <= X"66";
-FramBUFF(4*8+7 downto 4*8) <= X"67";
-FramBUFF(5*8+7 downto 5*8) <= X"68";
-FramBUFF(17*8+7 downto 17*8) <= X"69";
---FramBUFF(16*2*8-1 downto 16) <= (others => '0');
-
-end Behavioral;
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf b/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf
deleted file mode 100755
--- a/LCD_16x2_DRIVER/With_AMBA/Top_LCDcst.ucf
+++ /dev/null
@@ -1,37 +0,0 @@
-
-NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I;
-
-NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
-
-net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33;
-net "clk" PERIOD = 20.0ns HIGH 40%;
-#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33;
-
-#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-
-#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
\ No newline at end of file
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/FRAME_CLK.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:21:03 10/19/2010
--- Design Name:
--- Module Name: FRAME_CLK_GEN - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity FRAME_CLK_GEN is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- FRAME_CLK : out STD_LOGIC);
-end FRAME_CLK_GEN;
-
-architecture Behavioral of FRAME_CLK_GEN is
-
-Constant Goal_FRAME_CLK_FREQ : integer := 20;
-
-Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
-
-signal CPT : integer := 0;
-signal FRAME_CLK_reg : std_logic :='0';
-
-begin
-
-FRAME_CLK <= FRAME_CLK_reg;
-
-process(reset,clk)
-begin
- if reset = '0' then
- CPT <= 0;
- FRAME_CLK_reg <= '0';
- elsif clk'event and clk = '1' then
- if CPT = FRAME_CLK_TRIG then
- CPT <= 0;
- FRAME_CLK_reg <= not FRAME_CLK_reg;
- else
- CPT <= CPT + 1;
- end if;
- end if;
-end process;
-end Behavioral;
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_CFG.vhd
+++ /dev/null
@@ -1,57 +0,0 @@
--- Package File Template
---
--- Purpose: This package defines supplemental types, subtypes,
--- constants, and functions
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-package LCD_16x2_CFG is
-
- type LCD_DRVR_CTRL_BUSS is
- record
- LCD_RW : std_logic;
- LCD_RS : std_logic;
- LCD_E : std_logic;
- LCD_DATA : std_logic_vector(7 downto 0);
- end record;
-
- type LCD_DRVR_SYNCH_BUSS is
- record
- DRVR_READY : std_logic;
- LCD_INITIALISED : std_logic;
- end record;
-
-
- type LCD_DRVR_CMD_BUSS is
- record
- Word : std_logic_vector(7 downto 0);
- CMD_Data : std_logic; --CMD = '0' and data = '1'
- Exec : std_logic;
- Duration : std_logic_vector(1 downto 0);
- end record;
- type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
-
-
-constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
-constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
-constant RetHome : std_logic_vector(7 downto 0):= X"02";
-constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
-constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C";
-
-constant CursorON : std_logic_vector(7 downto 0):= X"0E";
-constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
-
---===========================================================|
---======L C D D R I V E R T I M I N G C O D E=====|
---===========================================================|
-
-constant Duration_4us : std_logic_vector(1 downto 0) := "00";
-constant Duration_100us : std_logic_vector(1 downto 0) := "01";
-constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
-constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
-
-
-end LCD_16x2_CFG;
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_16x2_ENGINE.vhd
+++ /dev/null
@@ -1,206 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:32:21 10/19/2010
--- Design Name:
--- Module Name: LCD_16x2_ENGINE - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.LCD_16x2_CFG.all;
-
-entity LCD_16x2_ENGINE is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- DATA : in std_logic_vector(16*2*8-1 downto 0);
- CMD : in std_logic_vector(10 downto 0);
- Exec : in std_logic;
- Ready : out std_logic;
- LCD_CTRL : out LCD_DRVR_CTRL_BUSS
- );
-end LCD_16x2_ENGINE;
-
-architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
-
-constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
-
-
-
-signal SYNCH : LCD_DRVR_SYNCH_BUSS;
-signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
-signal FRAME_CLK : std_logic;
-
-signal FRAME_CLK_reg : std_logic;
-signal RefreshFlag : std_logic;
-signal CMD_Flag : std_logic;
-signal Exec_Reg : std_logic;
-
-type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
-signal state : state_t;
-signal i : integer range 0 to 32 := 0;
-
-
-
-begin
-
-Driver0 : entity work.LCD_16x2_DRIVER
- generic map(OSC_freqKHz)
- Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
-
-FRAME_CLK_GEN0 : entity work.FRAME_CLK_GEN
- generic map(OSC_freqKHz)
- Port map( clk,reset,FRAME_CLK);
-
-
-
-process(reset,clk)
-begin
- if reset = '0' then
- state <= INIT0;
- Ready <= '0';
- RefreshFlag <= '0';
- i <= 0;
- elsif clk'event and clk ='1' then
- FRAME_CLK_reg <= FRAME_CLK;
- Exec_Reg <= Exec;
-
- if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
- RefreshFlag <= '1';
- elsif state = Refresh or state = Refresh0 or state = Refresh1 then
- RefreshFlag <= '0';
- end if;
-
- if Exec_Reg = '0' and Exec = '1' then
- CMD_Flag <= '1';
- elsif state = ExecCMD0 or state = ExecCMD1 then
- CMD_Flag <= '0';
- end if;
-
- case state is
- when INIT0 =>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_20ms;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= ConfigTbl(i);
- i <= i + 1;
- state <= INIT1;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when INIT1 =>
- state <= INIT2;
- DRIVER_CMD.Exec <= '0';
- when INIT2 =>
- if SYNCH.DRVR_READY = '1' then
- if i = 5 then
- state <= Idle;
- else
- state <= INIT0;
- end if;
- end if;
- when Idle=>
- DRIVER_CMD.Exec <= '0';
- if RefreshFlag = '1' then
- Ready <= '0';
- state <= Refresh;
- elsif CMD_Flag = '1' then
- Ready <= '0';
- state <= ExecCMD0;
- else
- Ready <= '1';
- end if;
- i <= 0;
- when Refresh=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_100us;
- DRIVER_CMD.CMD_Data <= '1';
- DRIVER_CMD.Word <= DATA(i*8+7 downto i*8);
- i <= i + 1;
- state <= Refresh0;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when Refresh0=>
- state <= Refresh1;
- DRIVER_CMD.Exec <= '0';
- when Refresh1=>
- if SYNCH.DRVR_READY = '1' then
- if i = 32 then
- state <= ReturnHome;
- elsif i = 16 then
- state <= GoLine2;
- else
- state <= Refresh;
- end if;
- end if;
-
- when ExecCMD0=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= CMD(9 downto 8);
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= CMD(7 downto 0);
- state <= ExecCMD1;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
-
- when ExecCMD1=>
- state <= Idle;
- DRIVER_CMD.Exec <= '0';
-
- when GoLine2=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_100us;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= X"C0";
- state <= GoLine2_0;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- when GoLine2_0=>
- state <= Refresh;
- DRIVER_CMD.Exec <= '0';
- when ReturnHome=>
- if SYNCH.DRVR_READY = '1' then
- DRIVER_CMD.Exec <= '1';
- DRIVER_CMD.Duration <= Duration_4ms;
- DRIVER_CMD.CMD_Data <= '0';
- DRIVER_CMD.Word <= X"02";
- state <= Idle;
- else
- DRIVER_CMD.Exec <= '0';
- end if;
- end case;
- end if;
-end process;
-
-
-end ar_LCD_16x2_ENGINE;
-
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_2x16_DRIVER.vhd
+++ /dev/null
@@ -1,156 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 10:09:57 10/13/2010
--- Design Name:
--- Module Name: LCD_2x16_DRIVER - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.all;
-
-
-entity LCD_2x16_DRIVER is
- generic(
- OSC_Freq_MHz : integer:=60;
- Refresh_RateHz : integer:=5
- );
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
- LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
- LCD_RS : out STD_LOGIC;
- LCD_RW : out STD_LOGIC;
- LCD_E : out STD_LOGIC;
- LCD_RET : out STD_LOGIC;
- LCD_CS1 : out STD_LOGIC;
- LCD_CS2 : out STD_LOGIC;
- STATEOUT: out std_logic_vector(3 downto 0);
- refreshPulse : out std_logic
- );
-end LCD_2x16_DRIVER;
-
-architecture Behavioral of LCD_2x16_DRIVER is
-
-type stateT is(Rst,Configure,IDLE,RefreshScreen);
-signal state : stateT;
-
-signal ShortTimePulse : std_logic;
-signal MidleTimePulse : std_logic;
-signal Refresh_RatePulse : std_logic;
-signal Start : STD_LOGIC;
-
-signal CFGM_LCD_RS : std_logic;
-signal CFGM_LCD_RW : std_logic;
-signal CFGM_LCD_E : std_logic;
-signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
-signal CFGM_Enable : std_logic;
-signal CFGM_completed : std_logic;
-
-
-signal FRMW_LCD_RS : std_logic;
-signal FRMW_LCD_RW : std_logic;
-signal FRMW_LCD_E : std_logic;
-signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
-signal FRMW_Enable : std_logic;
-signal FRMW_completed : std_logic;
-
-begin
-
-
-Counter : entity work.LCD_Counter
-generic map(OSC_Freq_MHz,Refresh_RateHz)
-port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
-
-ConfigModule : entity work.Config_Module
-port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
-
-
-FrameWriter : entity work.FRAME_WRITER
-port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
-
-
-STATEOUT(0) <= '1' when state = Rst else '0';
-STATEOUT(1) <= '1' when state = Configure else '0';
-STATEOUT(2) <= '1' when state = IDLE else '0';
-STATEOUT(3) <= '1' when state = RefreshScreen else '0';
-
-
-
-refreshPulse <= Refresh_RatePulse;
-
-Start <= '1';
-
-process(reset,clk)
-begin
- if reset = '0' then
- LCD_data <= (others=>'0');
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_RET <= '0';
- LCD_CS1 <= '0';
- LCD_CS2 <= '0';
- LCD_E <= '0';
- state <= Rst;
- CFGM_Enable <= '0';
- FRMW_Enable <= '0';
- elsif clk'event and clk ='1' then
- case state is
- when Rst =>
- LCD_data <= (others=>'0');
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_E <= '0';
- CFGM_Enable <= '1';
- FRMW_Enable <= '0';
- if Refresh_RatePulse = '1' then
- state <= Configure;
- end if;
- when Configure =>
- LCD_data <= CFGM_LCD_data;
- LCD_RS <= CFGM_LCD_RS;
- LCD_RW <= CFGM_LCD_RW;
- LCD_E <= CFGM_LCD_E;
- CFGM_Enable <= '0';
- if CFGM_completed = '1' then
- state <= IDLE;
- end if;
- when IDLE =>
- if Refresh_RatePulse = '1' then
- state <= RefreshScreen;
- FRMW_Enable <= '1';
- end if;
- LCD_RS <= '0';
- LCD_RW <= '0';
- LCD_E <= '0';
- LCD_data <= (others=>'0');
- when RefreshScreen =>
- LCD_data <= FRMW_LCD_data;
- LCD_RS <= FRMW_LCD_RS;
- LCD_RW <= FRMW_LCD_RW;
- LCD_E <= FRMW_LCD_E;
- FRMW_Enable <= '0';
- if FRMW_completed = '1' then
- state <= IDLE;
- end if;
- end case;
- end if;
-end process;
-end Behavioral;
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/LCD_CLK_GENERATOR.vhd
+++ /dev/null
@@ -1,72 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:52:25 10/18/2010
--- Design Name:
--- Module Name: LCD_CLK_GENERATOR - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-
-entity LCD_CLK_GENERATOR is
- generic(OSC_freqKHz : integer := 50000);
- Port ( clk : in STD_LOGIC;
- reset : in STD_LOGIC;
- clk_1us : out STD_LOGIC);
-end LCD_CLK_GENERATOR;
-
-architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
-
-Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
-
-
-signal cpt1 : integer;
-
-signal clk_1us_int : std_logic := '0';
-
-
-begin
-
-clk_1us <= clk_1us_int;
-
-
-process(reset,clk)
-begin
- if reset = '0' then
- cpt1 <= 0;
- clk_1us_int <= '0';
- elsif clk'event and clk = '1' then
- if cpt1 = clk_1usTRIGER then
- clk_1us_int <= not clk_1us_int;
- cpt1 <= 0;
- else
- cpt1 <= cpt1 + 1;
- end if;
- end if;
-end process;
-
-
-end ar_LCD_CLK_GENERATOR;
-
-
-
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCD.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 08:44:41 10/14/2010
--- Design Name:
--- Module Name: Top_LCD - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use work.LCD_16x2_CFG.all;
-
-entity Top_LCD is
- Port ( reset : in STD_LOGIC;
- clk : in STD_LOGIC;
- Bp0 : in STD_LOGIC;
- Bp1 : in STD_LOGIC;
- Bp2 : in STD_LOGIC;
- LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
- LCD_RS : out STD_LOGIC;
- LCD_RW : out STD_LOGIC;
- LCD_E : out STD_LOGIC;
- LCD_RET : out STD_LOGIC;
- LCD_CS1 : out STD_LOGIC;
- LCD_CS2 : out STD_LOGIC;
- SF_CE0 : out std_logic
- );
-end Top_LCD;
-
-architecture Behavioral of Top_LCD is
-
-signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
-signal CMD : std_logic_vector(10 downto 0);
-signal Exec : std_logic;
-signal Ready : std_logic;
-signal rst : std_logic;
-signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
-
-begin
-
-LCD_data <= LCD_CTRL.LCD_DATA;
-LCD_RS <= LCD_CTRL.LCD_RS;
-LCD_RW <= LCD_CTRL.LCD_RW;
-LCD_E <= LCD_CTRL.LCD_E;
-
-
-LCD_RET <= '0';
-LCD_CS1 <= '0';
-LCD_CS2 <= '0';
-
-SF_CE0 <= '1';
-
-rst <= not reset;
-
-
-
-Driver0 : entity work.LCD_16x2_ENGINE
- generic map(50000)
- Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
-
-FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
- X"42" when Bp1 = '1' else
- X"43" when Bp2 = '1' else
- X"44";
-
-FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
- X"47" when Bp1 = '1' else
- X"48" when Bp2 = '1' else
- X"49";
-
-
-CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
- Duration_100us & CursorOFF;
-
-
-Exec <= Bp1;
-
-FramBUFF(2*8+7 downto 2*8) <= X"23";
-FramBUFF(3*8+7 downto 3*8) <= X"66";
-FramBUFF(4*8+7 downto 4*8) <= X"67";
-FramBUFF(5*8+7 downto 5*8) <= X"68";
-FramBUFF(17*8+7 downto 17*8) <= X"69";
---FramBUFF(16*2*8-1 downto 16) <= (others => '0');
-
-end Behavioral;
-
-
-
-
-
-
diff --git a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf b/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf
deleted file mode 100755
--- a/LCD_16x2_DRIVER/Without_AMBA/VHD/Top_LCDcst.ucf
+++ /dev/null
@@ -1,37 +0,0 @@
-
-NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I;
-
-NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
-
-net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33;
-net "clk" PERIOD = 20.0ns HIGH 40%;
-#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33;
-
-#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-
-#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
\ No newline at end of file
diff --git a/Makefile b/Makefile
new file mode 100644
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,36 @@
+all: help
+
+help:
+ @echo
+ @echo " batch targets:"
+ @echo
+ @echo " make Patch-GRLIB : install library into $(GRLIB)"
+ @echo " make dist : create a tar file for using into an other computer"
+ @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer"
+ @echo " make allGPL : add a GPL HEADER in all vhdl Files"
+ @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
+ @echo " make doc : make documentation for VHDL IPs"
+ @echo
+
+allGPL:
+ sh lib/GPL_Patcher.sh -R
+
+init: allGPL
+ sh lib/lpp/vhdlsynPatcher.sh
+ sh lib/lpp/makeDirs.sh lib/lpp
+
+
+Patch-GRLIB: init doc
+ sh patch.sh $(GRLIB)
+
+
+dist: init
+ tar -cvzf ./../lpp-lib.tgz ./../lib_lpp/*
+
+Patched-dist: Patch-GRLIB
+ tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
+
+
+doc:
+ doxygen lib/lpp/Doxyfile
+ make lib/lpp/doc/latex
diff --git a/TODO b/TODO
new file mode 100644
--- /dev/null
+++ b/TODO
@@ -0,0 +1,4 @@
+patch VENDOR Ids
+Write a README
+add app_simple_diode
+add LCD_16x2_DRIVER.vhd
diff --git a/boards/patchboards.sh b/boards/patchboards.sh
new file mode 100644
--- /dev/null
+++ b/boards/patchboards.sh
@@ -0,0 +1,48 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP's GRLIB Boards PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+
+LPP_LIBPATH=`pwd -L`
+
+echo "Patching boards..."
+echo
+echo
+
+#COPY
+echo "Copy boards Files..."
+cp -R -v $LPP_LIBPATH/boards $1
+echo
+echo
+echo
+
+
+#CLEAN
+echo "CLEANING .."
+rm -v $1/boards/*.sh
+echo
+echo
+echo
diff --git a/designs/patchdesigns.sh b/designs/patchdesigns.sh
new file mode 100644
--- /dev/null
+++ b/designs/patchdesigns.sh
@@ -0,0 +1,49 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP's GRLIB Designs PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+
+LPP_LIBPATH=`pwd -L`
+
+echo "Patching designs..."
+echo
+echo
+
+#COPY
+echo "Copy designs Files..."
+cp -R -v $LPP_LIBPATH/designs $1
+echo
+echo
+echo
+
+
+#CLEAN
+echo "CLEANING .."
+rm -v $1/designs/*.sh
+echo
+echo
+echo
+
diff --git a/lib/GPL_HEADER b/lib/GPL_HEADER
new file mode 100644
--- /dev/null
+++ b/lib/GPL_HEADER
@@ -0,0 +1,18 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
diff --git a/lib/GPL_Patcher.sh b/lib/GPL_Patcher.sh
new file mode 100644
--- /dev/null
+++ b/lib/GPL_Patcher.sh
@@ -0,0 +1,72 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP GPL PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+# Absolute path to this script. /home/user/bin/foo.sh
+#SCRIPT=$(readlink -f $0)
+# Absolute path this script is in. /home/user/bin
+
+#LPP_PATCHPATH=`dirname $SCRIPT`
+LPP_PATCHPATH=`pwd -L`
+
+
+case $1 in
+ -R | --recursive )
+ for file in $(find . -name '*.vhd')
+ do
+ if(grep -q "This program is free software" $file); then
+ echo "$file already contains GPL HEADER"
+ else
+ echo "Modifying file : $file"
+ more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
+ cat $file >> $file.tmp
+ mv $file.tmp $file
+ fi
+ done
+ ;;
+ -h | --help | --h | -help)
+ echo 'Help:
+ This script add a GPL HEADER in all vhdl files.
+
+ -R or --recurcive:
+ Analyse recurcively folders starting from $LPP_PATCHPATH'
+ ;;
+ * )
+ for file in $(ls *.vhd)
+ do
+ if(grep -q "This program is free software" $file); then
+ echo "$file already contains GPL HEADER"
+ else
+ echo "Modifying file : $file"
+ more $LPP_PATCHPATH/lib/GPL_HEADER >> $file.tmp
+ cat $file >> $file.tmp
+ mv $file.tmp $file
+ fi
+ done
+ ;;
+
+esac
+
diff --git a/lib/lpp/COPYING b/lib/lpp/COPYING
new file mode 100644
--- /dev/null
+++ b/lib/lpp/COPYING
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+ The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
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+
+ To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights. Therefore, you have
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+you modify it: responsibilities to respect the freedom of others.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
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+ Developers that use the GNU GPL protect your rights with two steps:
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+ d) Limiting the use for publicity purposes of names of licensors or
+ authors of the material; or
+
+ e) Declining to grant rights under trademark law for use of some
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+
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+ material by anyone who conveys the material (or modified versions of
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+ any liability that these contractual assumptions directly impose on
+ those licensors and authors.
+
+ All other non-permissive additional terms are considered "further
+restrictions" within the meaning of section 10. If the Program as you
+received it, or any part of it, contains a notice stating that it is
+governed by this License along with a term that is a further
+restriction, you may remove that term. If a license document contains
+a further restriction but permits relicensing or conveying under this
+License, you may add to a covered work material governed by the terms
+of that license document, provided that the further restriction does
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+
+ If you add terms to a covered work in accord with this section, you
+must place, in the relevant source files, a statement of the
+additional terms that apply to those files, or a notice indicating
+where to find the applicable terms.
+
+ Additional terms, permissive or non-permissive, may be stated in the
+form of a separately written license, or stated as exceptions;
+the above requirements apply either way.
+
+ 8. Termination.
+
+ You may not propagate or modify a covered work except as expressly
+provided under this License. Any attempt otherwise to propagate or
+modify it is void, and will automatically terminate your rights under
+this License (including any patent licenses granted under the third
+paragraph of section 11).
+
+ However, if you cease all violation of this License, then your
+license from a particular copyright holder is reinstated (a)
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+finally terminates your license, and (b) permanently, if the copyright
+holder fails to notify you of the violation by some reasonable means
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+
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+reinstated permanently if the copyright holder notifies you of the
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+your receipt of the notice.
+
+ Termination of your rights under this section does not terminate the
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+reinstated, you do not qualify to receive new licenses for the same
+material under section 10.
+
+ 9. Acceptance Not Required for Having Copies.
+
+ You are not required to accept this License in order to receive or
+run a copy of the Program. Ancillary propagation of a covered work
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+
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+any patent claim is infringed by making, using, selling, offering for
+sale, or importing the Program or any portion of it.
+
+ 11. Patents.
+
+ A "contributor" is a copyright holder who authorizes use under this
+License of the Program or a work on which the Program is based. The
+work thus licensed is called the contributor's "contributor version".
+
+ A contributor's "essential patent claims" are all patent claims
+owned or controlled by the contributor, whether already acquired or
+hereafter acquired, that would be infringed by some manner, permitted
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+but do not include claims that would be infringed only as a
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+patent license under the contributor's essential patent claims, to
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+
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+agreement or commitment, however denominated, not to enforce a patent
+(such as an express permission to practice a patent or covenant not to
+sue for patent infringement). To "grant" such a patent license to a
+party means to make such an agreement or commitment not to enforce a
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+
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+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
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+in a country, would infringe one or more identifiable patents in that
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+
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+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
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+
+ A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
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+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+ Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+ 12. No Surrender of Others' Freedom.
+
+ If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all. For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+ 13. Use with the GNU Affero General Public License.
+
+ Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work. The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+ 14. Revised Versions of this License.
+
+ The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+ Each version is given a distinguishing version number. If the
+Program specifies that a certain numbered version of the GNU General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation. If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+ If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+ Later license versions may give you additional or different
+permissions. However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+ 15. Disclaimer of Warranty.
+
+ THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
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+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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+IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+ 17. Interpretation of Sections 15 and 16.
+
+ If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+
+Also add information on how to contact you by electronic and paper mail.
+
+ If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+ Copyright (C)
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+.
+
+ The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License. But first, please read
+.
diff --git a/lib/lpp/Doxyfile b/lib/lpp/Doxyfile
new file mode 100644
--- /dev/null
+++ b/lib/lpp/Doxyfile
@@ -0,0 +1,1661 @@
+# Doxyfile 1.7.1
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project
+#
+# All text after a hash (#) is considered a comment and will be ignored
+# The format is:
+# TAG = value [value, ...]
+# For lists items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ")
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded
+# by quotes) that should identify the project.
+
+PROJECT_NAME = lib-lpp
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER = 1.0
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY = /opt/GRLIB/lib_lpp/lib/lpp/doc
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES = YES
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip.
+
+STRIP_FROM_PATH =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful is your file systems
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C = NO
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL = YES
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given extension.
+# Doxygen has a built-in mapping, but you can override or extend it using this
+# tag. The format is ext=language, where ext is a file extension, and language
+# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C,
+# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make
+# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C
+# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions
+# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen.
+
+EXTENSION_MAPPING =
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter
+# and setter methods for a property. Setting this option to YES (the default)
+# will make doxygen to replace the get and set methods by a property in the
+# documentation. This will only work if the methods are indeed getting or
+# setting a simple type. If this is not the case, or you want to show the
+# methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING = YES
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penality.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will rougly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols
+
+SYMBOL_CACHE_SIZE = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC = NO
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespace are hidden.
+
+EXTRACT_ANON_NSPACES = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or define consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and defines in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES = YES
+
+# If the sources in your project are distributed over multiple directories
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
+# in the documentation. The default is NO.
+
+SHOW_DIRECTORIES = NO
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page. This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command , where is the value of
+# the FILE_VERSION_FILTER tag, and is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. The create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR = YES
+
+# This WARN_NO_PARAMDOC option can be abled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT = /opt/GRLIB/lib_lpp/lib/lpp
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
+
+FILE_PATTERNS = *.c \
+ *.cc \
+ *.cxx \
+ *.cpp \
+ *.c++ \
+ *.d \
+ *.java \
+ *.ii \
+ *.ixx \
+ *.ipp \
+ *.i++ \
+ *.inl \
+ *.h \
+ *.hh \
+ *.hxx \
+ *.hpp \
+ *.h++ \
+ *.idl \
+ *.odl \
+ *.cs \
+ *.php \
+ *.php3 \
+ *.inc \
+ *.m \
+ *.mm \
+ *.dox \
+ *.py \
+ *.f90 \
+ *.f \
+ *.vhd \
+ *.vhdl
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE = YES
+
+# The EXCLUDE tag can be used to specify files and/or directories that should
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+
+EXCLUDE =
+
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
+# directories that are symbolic links (a Unix filesystem feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command , where
+# is the value of the INPUT_FILTER tag, and is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output. If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
+# is applied to all files.
+
+FILTER_PATTERNS =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C and C++ comments will always remain visible.
+
+STRIP_CODE_COMMENTS = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code. Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX = YES
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header.
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If the tag is left blank doxygen
+# will generate a default style sheet. Note that doxygen will try to copy
+# the style sheet file to the HTML output directory, so don't put your own
+# stylesheet in the HTML output directory as well, or it will be erased!
+
+HTML_STYLESHEET =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the stylesheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP = YES
+
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes,
+# files or namespaces will be aligned in HTML using tables. If set to
+# NO a bullet list will be used.
+
+HTML_ALIGN_MEMBERS = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded. For this to work a browser that supports
+# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox
+# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari).
+
+HTML_DYNAMIC_SECTIONS = NO
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+#
+# Qt Help Project / Custom Filters.
+
+QHP_CUST_FILTER_ATTRS =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+#
+# Qt Help Project / Filter Attributes.
+
+QHP_SECT_FILTER_ATTRS =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+# will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at
+# top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it.
+
+DISABLE_INDEX = NO
+
+# This tag can be used to set the number of enum values (range [1..20])
+# that doxygen will group on one line in the generated HTML documentation.
+
+ENUM_VALUES_PER_LINE = 4
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+
+GENERATE_TREEVIEW = NO
+
+# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
+# and Class Hierarchy pages using a tree view instead of an ordered list.
+
+USE_INLINE_TREES = NO
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT = YES
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvances is that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX = YES
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, a4wide, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE = a4wide
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader. This is useful
+# if you want to understand what is going on. On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION = NO
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF = NO
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# in the INCLUDE_PATH (see below) will be search if a #include is found.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED =
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all function-like macros that are alone
+# on a line, have an all uppercase name, and do not end with a semicolon. Such
+# function macros are typically used for boiler-plate code, and will confuse
+# the parser if not removed.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles.
+# Optionally an initial location of the external documentation
+# can be added for each tagfile. The format of a tag file without
+# this location is as follows:
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths or
+# URLs. If a location is present for each tag, the installdox tool
+# does not have to be run to correct the links.
+# Note that each tag file must have a unique name
+# (where the name does NOT include the path)
+# If a tag file is not located in the directory in which doxygen
+# is run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS = YES
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option is superseded by the HAVE_DOT option below. This is only a
+# fallback. It is recommended to install and use dot, since it yields more
+# powerful graphs.
+
+CLASS_DIAGRAMS = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT = NO
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
+# base this on the number of processors available in the system. You can set it
+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS = 0
+
+# By default doxygen will write a font called FreeSans.ttf to the output
+# directory and reference it in all dot files that doxygen generates. This
+# font does not include all possible unicode characters however, so when you need
+# these (or just want a differently looking font) you can specify the font name
+# using DOT_FONTNAME. You need need to make sure dot is able to find the font,
+# which can be done by putting it in a standard location or by setting the
+# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
+# containing the font.
+
+DOT_FONTNAME = FreeSans.ttf
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE = 10
+
+# By default doxygen will tell dot to use the output directory to look for the
+# FreeSans.ttf font (which doxygen will put there itself). If you specify a
+# different font using DOT_FONTNAME you can set the path where dot
+# can find it using this tag.
+
+DOT_FONTPATH =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# the CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK = NO
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH = NO
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH = NO
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY = YES
+
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are png, jpg, or gif
+# If left blank png will be used.
+
+DOT_IMAGE_FORMAT = png
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS = NO
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP = YES
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
@@ -0,0 +1,87 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 09:21:03 10/19/2010
+-- Design Name:
+-- Module Name: FRAME_CLK_GEN - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+
+entity FRAME_CLK_GEN is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ FRAME_CLK : out STD_LOGIC);
+end FRAME_CLK_GEN;
+
+architecture Behavioral of FRAME_CLK_GEN is
+
+Constant Goal_FRAME_CLK_FREQ : integer := 20;
+
+Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
+
+signal CPT : integer := 0;
+signal FRAME_CLK_reg : std_logic :='0';
+
+begin
+
+FRAME_CLK <= FRAME_CLK_reg;
+
+process(reset,clk)
+begin
+ if reset = '0' then
+ CPT <= 0;
+ FRAME_CLK_reg <= '0';
+ elsif clk'event and clk = '1' then
+ if CPT = FRAME_CLK_TRIG then
+ CPT <= 0;
+ FRAME_CLK_reg <= not FRAME_CLK_reg;
+ else
+ CPT <= CPT + 1;
+ end if;
+ end if;
+end process;
+end Behavioral;
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER b/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER
@@ -0,0 +1,18 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
@@ -0,0 +1,55 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- Package File Template
+--
+-- Purpose: This package defines supplemental types, subtypes,
+-- constants, and functions
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+
+
+
+package LCD_16x2_CFG is
+
+
+constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
+constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
+constant RetHome : std_logic_vector(7 downto 0):= X"02";
+constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
+constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C";
+
+constant CursorON : std_logic_vector(7 downto 0):= X"0E";
+constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
+
+--===========================================================|
+--======L C D D R I V E R T I M I N G C O D E=====|
+--===========================================================|
+
+constant Duration_4us : std_logic_vector(1 downto 0) := "00";
+constant Duration_100us : std_logic_vector(1 downto 0) := "01";
+constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
+constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
+
+
+end LCD_16x2_CFG;
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
@@ -0,0 +1,228 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:32:21 10/19/2010
+-- Design Name:
+-- Module Name: LCD_16x2_ENGINE - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+use lpp.LCD_16x2_CFG.all;
+
+
+entity LCD_16x2_ENGINE is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ DATA : in std_logic_vector(16*2*8-1 downto 0);
+ CMD : in std_logic_vector(10 downto 0);
+ Exec : in std_logic;
+ Ready : out std_logic;
+ LCD_CTRL : out LCD_DRVR_CTRL_BUSS
+ );
+end LCD_16x2_ENGINE;
+
+architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
+
+constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
+
+
+
+signal SYNCH : LCD_DRVR_SYNCH_BUSS;
+signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
+signal FRAME_CLK : std_logic;
+
+signal FRAME_CLK_reg : std_logic;
+signal RefreshFlag : std_logic;
+signal CMD_Flag : std_logic;
+signal Exec_Reg : std_logic;
+
+type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
+signal state : state_t;
+signal i : integer range 0 to 32 := 0;
+
+
+
+begin
+
+Driver0 : LCD_16x2_DRIVER
+ generic map(OSC_freqKHz)
+ Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
+
+FRAME_CLK_GEN0 : FRAME_CLK_GEN
+ generic map(OSC_freqKHz)
+ Port map( clk,reset,FRAME_CLK);
+
+
+
+process(reset,clk)
+begin
+ if reset = '0' then
+ state <= INIT0;
+ Ready <= '0';
+ RefreshFlag <= '0';
+ i <= 0;
+ elsif clk'event and clk ='1' then
+ FRAME_CLK_reg <= FRAME_CLK;
+ Exec_Reg <= Exec;
+
+ if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
+ RefreshFlag <= '1';
+ elsif state = Refresh or state = Refresh0 or state = Refresh1 then
+ RefreshFlag <= '0';
+ end if;
+
+ if Exec_Reg = '0' and Exec = '1' then
+ CMD_Flag <= '1';
+ elsif state = ExecCMD0 or state = ExecCMD1 then
+ CMD_Flag <= '0';
+ end if;
+
+ case state is
+ when INIT0 =>
+ if SYNCH.DRVR_READY = '1' then
+ DRIVER_CMD.Exec <= '1';
+ DRIVER_CMD.Duration <= Duration_20ms;
+ DRIVER_CMD.CMD_Data <= '0';
+ DRIVER_CMD.Word <= ConfigTbl(i);
+ i <= i + 1;
+ state <= INIT1;
+ else
+ DRIVER_CMD.Exec <= '0';
+ end if;
+ when INIT1 =>
+ state <= INIT2;
+ DRIVER_CMD.Exec <= '0';
+ when INIT2 =>
+ if SYNCH.DRVR_READY = '1' then
+ if i = 5 then
+ state <= Idle;
+ else
+ state <= INIT0;
+ end if;
+ end if;
+ when Idle=>
+ DRIVER_CMD.Exec <= '0';
+ if RefreshFlag = '1' then
+ Ready <= '0';
+ state <= Refresh;
+ elsif CMD_Flag = '1' then
+ Ready <= '0';
+ state <= ExecCMD0;
+ else
+ Ready <= '1';
+ end if;
+ i <= 0;
+ when Refresh=>
+ if SYNCH.DRVR_READY = '1' then
+ DRIVER_CMD.Exec <= '1';
+ DRIVER_CMD.Duration <= Duration_100us;
+ DRIVER_CMD.CMD_Data <= '1';
+ DRIVER_CMD.Word <= DATA(i*8+7 downto i*8);
+ i <= i + 1;
+ state <= Refresh0;
+ else
+ DRIVER_CMD.Exec <= '0';
+ end if;
+ when Refresh0=>
+ state <= Refresh1;
+ DRIVER_CMD.Exec <= '0';
+ when Refresh1=>
+ if SYNCH.DRVR_READY = '1' then
+ if i = 32 then
+ state <= ReturnHome;
+ elsif i = 16 then
+ state <= GoLine2;
+ else
+ state <= Refresh;
+ end if;
+ end if;
+
+ when ExecCMD0=>
+ if SYNCH.DRVR_READY = '1' then
+ DRIVER_CMD.Exec <= '1';
+ DRIVER_CMD.Duration <= CMD(9 downto 8);
+ DRIVER_CMD.CMD_Data <= '0';
+ DRIVER_CMD.Word <= CMD(7 downto 0);
+ state <= ExecCMD1;
+ else
+ DRIVER_CMD.Exec <= '0';
+ end if;
+
+ when ExecCMD1=>
+ state <= Idle;
+ DRIVER_CMD.Exec <= '0';
+
+ when GoLine2=>
+ if SYNCH.DRVR_READY = '1' then
+ DRIVER_CMD.Exec <= '1';
+ DRIVER_CMD.Duration <= Duration_100us;
+ DRIVER_CMD.CMD_Data <= '0';
+ DRIVER_CMD.Word <= X"C0";
+ state <= GoLine2_0;
+ else
+ DRIVER_CMD.Exec <= '0';
+ end if;
+ when GoLine2_0=>
+ state <= Refresh;
+ DRIVER_CMD.Exec <= '0';
+ when ReturnHome=>
+ if SYNCH.DRVR_READY = '1' then
+ DRIVER_CMD.Exec <= '1';
+ DRIVER_CMD.Duration <= Duration_4ms;
+ DRIVER_CMD.CMD_Data <= '0';
+ DRIVER_CMD.Word <= X"02";
+ state <= Idle;
+ else
+ DRIVER_CMD.Exec <= '0';
+ end if;
+ end case;
+ end if;
+end process;
+
+
+end ar_LCD_16x2_ENGINE;
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
@@ -0,0 +1,175 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 10:09:57 10/13/2010
+-- Design Name:
+-- Module Name: LCD_2x16_DRIVER - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.all;
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+
+entity LCD_2x16_DRIVER is
+ generic(
+ OSC_Freq_MHz : integer:=60;
+ Refresh_RateHz : integer:=5
+ );
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ STATEOUT: out std_logic_vector(3 downto 0);
+ refreshPulse : out std_logic
+ );
+end LCD_2x16_DRIVER;
+
+architecture Behavioral of LCD_2x16_DRIVER is
+
+type stateT is(Rst,Configure,IDLE,RefreshScreen);
+signal state : stateT;
+
+signal ShortTimePulse : std_logic;
+signal MidleTimePulse : std_logic;
+signal Refresh_RatePulse : std_logic;
+signal Start : STD_LOGIC;
+
+signal CFGM_LCD_RS : std_logic;
+signal CFGM_LCD_RW : std_logic;
+signal CFGM_LCD_E : std_logic;
+signal CFGM_LCD_DATA : std_logic_vector(7 downto 0);
+signal CFGM_Enable : std_logic;
+signal CFGM_completed : std_logic;
+
+
+signal FRMW_LCD_RS : std_logic;
+signal FRMW_LCD_RW : std_logic;
+signal FRMW_LCD_E : std_logic;
+signal FRMW_LCD_DATA : std_logic_vector(7 downto 0);
+signal FRMW_Enable : std_logic;
+signal FRMW_completed : std_logic;
+
+begin
+
+
+Counter : LCD_Counter
+generic map(OSC_Freq_MHz,Refresh_RateHz)
+port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
+
+ConfigModule : Config_Module
+port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
+
+
+FrameWriter : FRAME_WRITER
+port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
+
+
+STATEOUT(0) <= '1' when state = Rst else '0';
+STATEOUT(1) <= '1' when state = Configure else '0';
+STATEOUT(2) <= '1' when state = IDLE else '0';
+STATEOUT(3) <= '1' when state = RefreshScreen else '0';
+
+
+
+refreshPulse <= Refresh_RatePulse;
+
+Start <= '1';
+
+process(reset,clk)
+begin
+ if reset = '0' then
+ LCD_data <= (others=>'0');
+ LCD_RS <= '0';
+ LCD_RW <= '0';
+ LCD_RET <= '0';
+ LCD_CS1 <= '0';
+ LCD_CS2 <= '0';
+ LCD_E <= '0';
+ state <= Rst;
+ CFGM_Enable <= '0';
+ FRMW_Enable <= '0';
+ elsif clk'event and clk ='1' then
+ case state is
+ when Rst =>
+ LCD_data <= (others=>'0');
+ LCD_RS <= '0';
+ LCD_RW <= '0';
+ LCD_E <= '0';
+ CFGM_Enable <= '1';
+ FRMW_Enable <= '0';
+ if Refresh_RatePulse = '1' then
+ state <= Configure;
+ end if;
+ when Configure =>
+ LCD_data <= CFGM_LCD_data;
+ LCD_RS <= CFGM_LCD_RS;
+ LCD_RW <= CFGM_LCD_RW;
+ LCD_E <= CFGM_LCD_E;
+ CFGM_Enable <= '0';
+ if CFGM_completed = '1' then
+ state <= IDLE;
+ end if;
+ when IDLE =>
+ if Refresh_RatePulse = '1' then
+ state <= RefreshScreen;
+ FRMW_Enable <= '1';
+ end if;
+ LCD_RS <= '0';
+ LCD_RW <= '0';
+ LCD_E <= '0';
+ LCD_data <= (others=>'0');
+ when RefreshScreen =>
+ LCD_data <= FRMW_LCD_data;
+ LCD_RS <= FRMW_LCD_RS;
+ LCD_RW <= FRMW_LCD_RW;
+ LCD_E <= FRMW_LCD_E;
+ FRMW_Enable <= '0';
+ if FRMW_completed = '1' then
+ state <= IDLE;
+ end if;
+ end case;
+ end if;
+end process;
+end Behavioral;
+
+
+
+
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:52:25 10/18/2010
+-- Design Name:
+-- Module Name: LCD_CLK_GENERATOR - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+
+entity LCD_CLK_GENERATOR is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ clk_1us : out STD_LOGIC);
+end LCD_CLK_GENERATOR;
+
+architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
+
+Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1;
+
+
+signal cpt1 : integer;
+
+signal clk_1us_int : std_logic := '0';
+
+
+begin
+
+clk_1us <= clk_1us_int;
+
+
+process(reset,clk)
+begin
+ if reset = '0' then
+ cpt1 <= 0;
+ clk_1us_int <= '0';
+ elsif clk'event and clk = '1' then
+ if cpt1 = clk_1usTRIGER then
+ clk_1us_int <= not clk_1us_int;
+ cpt1 <= 0;
+ else
+ cpt1 <= cpt1 + 1;
+ end if;
+ end if;
+end process;
+
+
+end ar_LCD_CLK_GENERATOR;
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd
@@ -0,0 +1,124 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 08:44:41 10/14/2010
+-- Design Name:
+-- Module Name: Top_LCD - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library lpp;
+use lpp.amba_lcd_16x2_ctrlr.all;
+use lpp.LCD_16x2_CFG.all;
+
+
+entity AMBA_LCD_16x2_DRIVER is
+ Port ( reset : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ Bp0 : in STD_LOGIC;
+ Bp1 : in STD_LOGIC;
+ Bp2 : in STD_LOGIC;
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ SF_CE0 : out std_logic
+ );
+end AMBA_LCD_16x2_DRIVER;
+
+architecture Behavioral of AMBA_LCD_16x2_DRIVER is
+
+signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
+signal CMD : std_logic_vector(10 downto 0);
+signal Exec : std_logic;
+signal Ready : std_logic;
+signal rst : std_logic;
+signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
+
+begin
+
+LCD_data <= LCD_CTRL.LCD_DATA;
+LCD_RS <= LCD_CTRL.LCD_RS;
+LCD_RW <= LCD_CTRL.LCD_RW;
+LCD_E <= LCD_CTRL.LCD_E;
+
+
+LCD_RET <= '0';
+LCD_CS1 <= '0';
+LCD_CS2 <= '0';
+
+SF_CE0 <= '1';
+
+rst <= not reset;
+
+
+
+Driver0 : LCD_16x2_ENGINE
+ generic map(50000)
+ Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
+
+FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
+ X"42" when Bp1 = '1' else
+ X"43" when Bp2 = '1' else
+ X"44";
+
+FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
+ X"47" when Bp1 = '1' else
+ X"48" when Bp2 = '1' else
+ X"49";
+
+
+CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
+ Duration_100us & CursorOFF;
+
+
+Exec <= Bp1;
+
+FramBUFF(2*8+7 downto 2*8) <= X"23";
+FramBUFF(3*8+7 downto 3*8) <= X"66";
+FramBUFF(4*8+7 downto 4*8) <= X"67";
+FramBUFF(5*8+7 downto 5*8) <= X"68";
+FramBUFF(17*8+7 downto 17*8) <= X"69";
+--FramBUFF(16*2*8-1 downto 16) <= (others => '0');
+
+end Behavioral;
+
+
+
+
+
+
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf
@@ -0,0 +1,37 @@
+
+NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I;
+NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I;
+NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I;
+
+NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+
+NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
+NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
+NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
+NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
+
+net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33;
+net "clk" PERIOD = 20.0ns HIGH 40%;
+#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33;
+
+#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
+#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
+#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
+#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
+
+#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
\ No newline at end of file
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
@@ -0,0 +1,162 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package amba_lcd_16x2_ctrlr is
+
+
+type LCD_DRVR_CTRL_BUSS is
+ record
+ LCD_RW : std_logic;
+ LCD_RS : std_logic;
+ LCD_E : std_logic;
+ LCD_DATA : std_logic_vector(7 downto 0);
+ end record;
+
+ type LCD_DRVR_SYNCH_BUSS is
+ record
+ DRVR_READY : std_logic;
+ LCD_INITIALISED : std_logic;
+ end record;
+
+
+ type LCD_DRVR_CMD_BUSS is
+ record
+ Word : std_logic_vector(7 downto 0);
+ CMD_Data : std_logic; --CMD = '0' and data = '1'
+ Exec : std_logic;
+ Duration : std_logic_vector(1 downto 0);
+ end record;
+ type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
+
+
+
+
+
+
+component amba_lcd_16x2_driver is
+ Port ( reset : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ Bp0 : in STD_LOGIC;
+ Bp1 : in STD_LOGIC;
+ Bp2 : in STD_LOGIC;
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ SF_CE0 : out std_logic
+ );
+end component;
+
+
+
+component FRAME_CLK_GEN is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ FRAME_CLK : out STD_LOGIC);
+end component;
+
+
+
+component LCD_2x16_DRIVER is
+ generic(
+ OSC_Freq_MHz : integer:=60;
+ Refresh_RateHz : integer:=5
+ );
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0);
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ STATEOUT: out std_logic_vector(3 downto 0);
+ refreshPulse : out std_logic
+ );
+end component;
+
+
+component LCD_CLK_GENERATOR is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ clk_1us : out STD_LOGIC);
+end component;
+
+component AMBA_LCD_16x2_DRIVER is
+ Port ( reset : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ Bp0 : in STD_LOGIC;
+ Bp1 : in STD_LOGIC;
+ Bp2 : in STD_LOGIC;
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ SF_CE0 : out std_logic
+ );
+end component;
+
+component LCD_16x2_ENGINE is
+ generic(OSC_freqKHz : integer := 50000);
+ Port ( clk : in STD_LOGIC;
+ reset : in STD_LOGIC;
+ DATA : in std_logic_vector(16*2*8-1 downto 0);
+ CMD : in std_logic_vector(10 downto 0);
+ Exec : in std_logic;
+ Ready : out std_logic;
+ LCD_CTRL : out LCD_DRVR_CTRL_BUSS
+ );
+end component;
+
+
+component AMBA_LCD_16x2_DRIVER is
+ Port ( reset : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ Bp0 : in STD_LOGIC;
+ Bp1 : in STD_LOGIC;
+ Bp2 : in STD_LOGIC;
+ LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
+ LCD_RS : out STD_LOGIC;
+ LCD_RW : out STD_LOGIC;
+ LCD_E : out STD_LOGIC;
+ LCD_RET : out STD_LOGIC;
+ LCD_CS1 : out STD_LOGIC;
+ LCD_CS2 : out STD_LOGIC;
+ SF_CE0 : out std_logic
+ );
+end component;
+
+
+
+end;
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh b/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh
@@ -0,0 +1,1 @@
+ls|grep .vhd|grep -i -v test>vhdlsyn.txt
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt b/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt
@@ -0,0 +1,7 @@
+amba_lcd_16x2_ctrlr.vhd
+FRAME_CLK.vhd
+LCD_16x2_CFG.vhd
+LCD_16x2_ENGINE.vhd
+LCD_2x16_DRIVER.vhd
+LCD_CLK_GENERATOR.vhd
+Top_LCD.vhd
diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dirs.txt
@@ -0,0 +1,4 @@
+./general_purpose
+./lpp_amba
+./dsp/iir_filter
+./amba_lcd_16x2_ctrlr
diff --git a/lib/lpp/doc/html/installdox b/lib/lpp/doc/html/installdox
new file mode 100755
--- /dev/null
+++ b/lib/lpp/doc/html/installdox
@@ -0,0 +1,117 @@
+#!/usr/bin/perl
+
+%subst = ( );
+$quiet = 0;
+
+if (open(F,"search.cfg"))
+{
+ $_= ; s/[ \t\n]*$//g ; $subst{"_doc"} = $_;
+ $_= ; s/[ \t\n]*$//g ; $subst{"_cgi"} = $_;
+}
+
+while ( @ARGV ) {
+ $_ = shift @ARGV;
+ if ( s/^-// ) {
+ if ( /^l(.*)/ ) {
+ $v = ($1 eq "") ? shift @ARGV : $1;
+ ($v =~ /\/$/) || ($v .= "/");
+ $_ = $v;
+ if ( /(.+)\@(.+)/ ) {
+ if ( exists $subst{$1} ) {
+ $subst{$1} = $2;
+ } else {
+ print STDERR "Unknown tag file $1 given with option -l\n";
+ &usage();
+ }
+ } else {
+ print STDERR "Argument $_ is invalid for option -l\n";
+ &usage();
+ }
+ }
+ elsif ( /^q/ ) {
+ $quiet = 1;
+ }
+ elsif ( /^\?|^h/ ) {
+ &usage();
+ }
+ else {
+ print STDERR "Illegal option -$_\n";
+ &usage();
+ }
+ }
+ else {
+ push (@files, $_ );
+ }
+}
+
+foreach $sub (keys %subst)
+{
+ if ( $subst{$sub} eq "" )
+ {
+ print STDERR "No substitute given for tag file `$sub'\n";
+ &usage();
+ }
+ elsif ( ! $quiet && $sub ne "_doc" && $sub ne "_cgi" )
+ {
+ print "Substituting $subst{$sub} for each occurrence of tag file $sub\n";
+ }
+}
+
+if ( ! @files ) {
+ if (opendir(D,".")) {
+ foreach $file ( readdir(D) ) {
+ $match = ".html";
+ next if ( $file =~ /^\.\.?$/ );
+ ($file =~ /$match/) && (push @files, $file);
+ ($file =~ "tree.js") && (push @files, $file);
+ }
+ closedir(D);
+ }
+}
+
+if ( ! @files ) {
+ print STDERR "Warning: No input files given and none found!\n";
+}
+
+foreach $f (@files)
+{
+ if ( ! $quiet ) {
+ print "Editing: $f...\n";
+ }
+ $oldf = $f;
+ $f .= ".bak";
+ unless (rename $oldf,$f) {
+ print STDERR "Error: cannot rename file $oldf\n";
+ exit 1;
+ }
+ if (open(F,"<$f")) {
+ unless (open(G,">$oldf")) {
+ print STDERR "Error: opening file $oldf for writing\n";
+ exit 1;
+ }
+ if ($oldf ne "tree.js") {
+ while () {
+ s/doxygen\=\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\" (href|src)=\"\2/doxygen\=\"$1:$subst{$1}\" \3=\"$subst{$1}/g;
+ print G "$_";
+ }
+ }
+ else {
+ while () {
+ s/\"([^ \"\:\t\>\<]*)\:([^ \"\t\>\<]*)\", \"\2/\"$1:$subst{$1}\" ,\"$subst{$1}/g;
+ print G "$_";
+ }
+ }
+ }
+ else {
+ print STDERR "Warning file $f does not exist\n";
+ }
+ unlink $f;
+}
+
+sub usage {
+ print STDERR "Usage: installdox [options] [html-file [html-file ...]]\n";
+ print STDERR "Options:\n";
+ print STDERR " -l tagfile\@linkName tag file + URL or directory \n";
+ print STDERR " -q Quiet mode\n\n";
+ exit 1;
+}
diff --git a/lib/lpp/doc/html/search/search.js b/lib/lpp/doc/html/search/search.js
new file mode 100644
--- /dev/null
+++ b/lib/lpp/doc/html/search/search.js
@@ -0,0 +1,734 @@
+// Search script generated by doxygen
+// Copyright (C) 2009 by Dimitri van Heesch.
+
+// The code in this file is loosly based on main.js, part of Natural Docs,
+// which is Copyright (C) 2003-2008 Greg Valure
+// Natural Docs is licensed under the GPL.
+
+var indexSectionsWithContent =
+{
+ 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101001111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101101001100001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101001100001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101001111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
+};
+
+var indexSectionNames =
+{
+ 0: "all",
+ 1: "classes",
+ 2: "files",
+ 3: "functions",
+ 4: "variables"
+};
+
+function convertToId(search)
+{
+ var result = '';
+ for (i=0;i do a search
+ {
+ this.Search();
+ }
+ }
+
+ this.OnSearchSelectKey = function(evt)
+ {
+ var e = (evt) ? evt : window.event; // for IE
+ if (e.keyCode==40 && this.searchIndex0) // Up
+ {
+ this.searchIndex--;
+ this.OnSelectItem(this.searchIndex);
+ }
+ else if (e.keyCode==13 || e.keyCode==27)
+ {
+ this.OnSelectItem(this.searchIndex);
+ this.CloseSelectionWindow();
+ this.DOMSearchField().focus();
+ }
+ return false;
+ }
+
+ // --------- Actions
+
+ // Closes the results window.
+ this.CloseResultsWindow = function()
+ {
+ this.DOMPopupSearchResultsWindow().style.display = 'none';
+ this.DOMSearchClose().style.display = 'none';
+ this.Activate(false);
+ }
+
+ this.CloseSelectionWindow = function()
+ {
+ this.DOMSearchSelectWindow().style.display = 'none';
+ }
+
+ // Performs a search.
+ this.Search = function()
+ {
+ this.keyTimeout = 0;
+
+ // strip leading whitespace
+ var searchValue = this.DOMSearchField().value.replace(/^ +/, "");
+
+ var code = searchValue.toLowerCase().charCodeAt(0);
+ var hexCode;
+ if (code<16)
+ {
+ hexCode="0"+code.toString(16);
+ }
+ else
+ {
+ hexCode=code.toString(16);
+ }
+
+ var resultsPage;
+ var resultsPageWithSearch;
+ var hasResultsPage;
+
+ if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1')
+ {
+ resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';
+ resultsPageWithSearch = resultsPage+'?'+escape(searchValue);
+ hasResultsPage = true;
+ }
+ else // nothing available for this search term
+ {
+ resultsPage = this.resultsPath + '/nomatches.html';
+ resultsPageWithSearch = resultsPage;
+ hasResultsPage = false;
+ }
+
+ window.frames.MSearchResults.location.href = resultsPageWithSearch;
+ var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();
+
+ if (domPopupSearchResultsWindow.style.display!='block')
+ {
+ var domSearchBox = this.DOMSearchBox();
+ this.DOMSearchClose().style.display = 'inline';
+ if (this.insideFrame)
+ {
+ var domPopupSearchResults = this.DOMPopupSearchResults();
+ domPopupSearchResultsWindow.style.position = 'relative';
+ domPopupSearchResultsWindow.style.display = 'block';
+ var width = document.body.clientWidth - 8; // the -8 is for IE :-(
+ domPopupSearchResultsWindow.style.width = width + 'px';
+ domPopupSearchResults.style.width = width + 'px';
+ }
+ else
+ {
+ var domPopupSearchResults = this.DOMPopupSearchResults();
+ var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;
+ var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1;
+ domPopupSearchResultsWindow.style.display = 'block';
+ left -= domPopupSearchResults.offsetWidth;
+ domPopupSearchResultsWindow.style.top = top + 'px';
+ domPopupSearchResultsWindow.style.left = left + 'px';
+ }
+ }
+
+ this.lastSearchValue = searchValue;
+ this.lastResultsPage = resultsPage;
+ }
+
+ // -------- Activation Functions
+
+ // Activates or deactivates the search panel, resetting things to
+ // their default values if necessary.
+ this.Activate = function(isActive)
+ {
+ if (isActive || // open it
+ this.DOMPopupSearchResultsWindow().style.display == 'block'
+ )
+ {
+ this.DOMSearchBox().className = 'MSearchBoxActive';
+
+ var searchField = this.DOMSearchField();
+
+ if (searchField.value == this.searchLabel) // clear "Search" term upon entry
+ {
+ searchField.value = '';
+ this.searchActive = true;
+ }
+ }
+ else if (!isActive) // directly remove the panel
+ {
+ this.DOMSearchBox().className = 'MSearchBoxInactive';
+ this.DOMSearchField().value = this.searchLabel;
+ this.searchActive = false;
+ this.lastSearchValue = ''
+ this.lastResultsPage = '';
+ }
+ }
+}
+
+// -----------------------------------------------------------------------
+
+// The class that handles everything on the search results page.
+function SearchResults(name)
+{
+ // The number of matches from the last run of .
+ this.lastMatchCount = 0;
+ this.lastKey = 0;
+ this.repeatOn = false;
+
+ // Toggles the visibility of the passed element ID.
+ this.FindChildElement = function(id)
+ {
+ var parentElement = document.getElementById(id);
+ var element = parentElement.firstChild;
+
+ while (element && element!=parentElement)
+ {
+ if (element.nodeName == 'DIV' && element.className == 'SRChildren')
+ {
+ return element;
+ }
+
+ if (element.nodeName == 'DIV' && element.hasChildNodes())
+ {
+ element = element.firstChild;
+ }
+ else if (element.nextSibling)
+ {
+ element = element.nextSibling;
+ }
+ else
+ {
+ do
+ {
+ element = element.parentNode;
+ }
+ while (element && element!=parentElement && !element.nextSibling);
+
+ if (element && element!=parentElement)
+ {
+ element = element.nextSibling;
+ }
+ }
+ }
+ }
+
+ this.Toggle = function(id)
+ {
+ var element = this.FindChildElement(id);
+ if (element)
+ {
+ if (element.style.display == 'block')
+ {
+ element.style.display = 'none';
+ }
+ else
+ {
+ element.style.display = 'block';
+ }
+ }
+ }
+
+ // Searches for the passed string. If there is no parameter,
+ // it takes it from the URL query.
+ //
+ // Always returns true, since other documents may try to call it
+ // and that may or may not be possible.
+ this.Search = function(search)
+ {
+ if (!search) // get search word from URL
+ {
+ search = window.location.search;
+ search = search.substring(1); // Remove the leading '?'
+ search = unescape(search);
+ }
+
+ search = search.replace(/^ +/, ""); // strip leading spaces
+ search = search.replace(/ +$/, ""); // strip trailing spaces
+ search = search.toLowerCase();
+ search = convertToId(search);
+
+ var resultRows = document.getElementsByTagName("div");
+ var matches = 0;
+
+ var i = 0;
+ while (i < resultRows.length)
+ {
+ var row = resultRows.item(i);
+ if (row.className == "SRResult")
+ {
+ var rowMatchName = row.id.toLowerCase();
+ rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_'
+
+ if (search.length<=rowMatchName.length &&
+ rowMatchName.substr(0, search.length)==search)
+ {
+ row.style.display = 'block';
+ matches++;
+ }
+ else
+ {
+ row.style.display = 'none';
+ }
+ }
+ i++;
+ }
+ document.getElementById("Searching").style.display='none';
+ if (matches == 0) // no results
+ {
+ document.getElementById("NoMatches").style.display='block';
+ }
+ else // at least one result
+ {
+ document.getElementById("NoMatches").style.display='none';
+ }
+ this.lastMatchCount = matches;
+ return true;
+ }
+
+ // return the first item with index index or higher that is visible
+ this.NavNext = function(index)
+ {
+ var focusItem;
+ while (1)
+ {
+ var focusName = 'Item'+index;
+ focusItem = document.getElementById(focusName);
+ if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+ {
+ break;
+ }
+ else if (!focusItem) // last element
+ {
+ break;
+ }
+ focusItem=null;
+ index++;
+ }
+ return focusItem;
+ }
+
+ this.NavPrev = function(index)
+ {
+ var focusItem;
+ while (1)
+ {
+ var focusName = 'Item'+index;
+ focusItem = document.getElementById(focusName);
+ if (focusItem && focusItem.parentNode.parentNode.style.display=='block')
+ {
+ break;
+ }
+ else if (!focusItem) // last element
+ {
+ break;
+ }
+ focusItem=null;
+ index--;
+ }
+ return focusItem;
+ }
+
+ this.ProcessKeys = function(e)
+ {
+ if (e.type == "keydown")
+ {
+ this.repeatOn = false;
+ this.lastKey = e.keyCode;
+ }
+ else if (e.type == "keypress")
+ {
+ if (!this.repeatOn)
+ {
+ if (this.lastKey) this.repeatOn = true;
+ return false; // ignore first keypress after keydown
+ }
+ }
+ else if (e.type == "keyup")
+ {
+ this.lastKey = 0;
+ this.repeatOn = false;
+ }
+ return this.lastKey!=0;
+ }
+
+ this.Nav = function(evt,itemIndex)
+ {
+ var e = (evt) ? evt : window.event; // for IE
+ if (e.keyCode==13) return true;
+ if (!this.ProcessKeys(e)) return false;
+
+ if (this.lastKey==38) // Up
+ {
+ var newIndex = itemIndex-1;
+ var focusItem = this.NavPrev(newIndex);
+ if (focusItem)
+ {
+ var child = this.FindChildElement(focusItem.parentNode.parentNode.id);
+ if (child && child.style.display == 'block') // children visible
+ {
+ var n=0;
+ var tmpElem;
+ while (1) // search for last child
+ {
+ tmpElem = document.getElementById('Item'+newIndex+'_c'+n);
+ if (tmpElem)
+ {
+ focusItem = tmpElem;
+ }
+ else // found it!
+ {
+ break;
+ }
+ n++;
+ }
+ }
+ }
+ if (focusItem)
+ {
+ focusItem.focus();
+ }
+ else // return focus to search field
+ {
+ parent.document.getElementById("MSearchField").focus();
+ }
+ }
+ else if (this.lastKey==40) // Down
+ {
+ var newIndex = itemIndex+1;
+ var focusItem;
+ var item = document.getElementById('Item'+itemIndex);
+ var elem = this.FindChildElement(item.parentNode.parentNode.id);
+ if (elem && elem.style.display == 'block') // children visible
+ {
+ focusItem = document.getElementById('Item'+itemIndex+'_c0');
+ }
+ if (!focusItem) focusItem = this.NavNext(newIndex);
+ if (focusItem) focusItem.focus();
+ }
+ else if (this.lastKey==39) // Right
+ {
+ var item = document.getElementById('Item'+itemIndex);
+ var elem = this.FindChildElement(item.parentNode.parentNode.id);
+ if (elem) elem.style.display = 'block';
+ }
+ else if (this.lastKey==37) // Left
+ {
+ var item = document.getElementById('Item'+itemIndex);
+ var elem = this.FindChildElement(item.parentNode.parentNode.id);
+ if (elem) elem.style.display = 'none';
+ }
+ else if (this.lastKey==27) // Escape
+ {
+ parent.searchBox.CloseResultsWindow();
+ parent.document.getElementById("MSearchField").focus();
+ }
+ else if (this.lastKey==13) // Enter
+ {
+ return true;
+ }
+ return false;
+ }
+
+ this.NavChild = function(evt,itemIndex,childIndex)
+ {
+ var e = (evt) ? evt : window.event; // for IE
+ if (e.keyCode==13) return true;
+ if (!this.ProcessKeys(e)) return false;
+
+ if (this.lastKey==38) // Up
+ {
+ if (childIndex>0)
+ {
+ var newIndex = childIndex-1;
+ document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();
+ }
+ else // already at first child, jump to parent
+ {
+ document.getElementById('Item'+itemIndex).focus();
+ }
+ }
+ else if (this.lastKey==40) // Down
+ {
+ var newIndex = childIndex+1;
+ var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);
+ if (!elem) // last child, jump to parent next parent
+ {
+ elem = this.NavNext(itemIndex+1);
+ }
+ if (elem)
+ {
+ elem.focus();
+ }
+ }
+ else if (this.lastKey==27) // Escape
+ {
+ parent.searchBox.CloseResultsWindow();
+ parent.document.getElementById("MSearchField").focus();
+ }
+ else if (this.lastKey==13) // Enter
+ {
+ return true;
+ }
+ return false;
+ }
+}
diff --git a/lib/lpp/doc/latex/Makefile b/lib/lpp/doc/latex/Makefile
new file mode 100644
--- /dev/null
+++ b/lib/lpp/doc/latex/Makefile
@@ -0,0 +1,19 @@
+all: clean refman.pdf
+
+pdf: refman.pdf
+
+refman.pdf: refman.tex
+ pdflatex refman.tex
+ makeindex refman.idx
+ pdflatex refman.tex
+ latex_count=5 ; \
+ while egrep -s 'Rerun (LaTeX|to get cross-references right)' refman.log && [ $$latex_count -gt 0 ] ;\
+ do \
+ echo "Rerunning latex...." ;\
+ pdflatex refman.tex ;\
+ latex_count=`expr $$latex_count - 1` ;\
+ done
+
+
+clean:
+ rm -f *.ps *.dvi *.aux *.toc *.idx *.ind *.ilg *.log *.out refman.pdf
diff --git a/lib/lpp/doc/latex/doxygen.sty b/lib/lpp/doc/latex/doxygen.sty
new file mode 100644
--- /dev/null
+++ b/lib/lpp/doc/latex/doxygen.sty
@@ -0,0 +1,356 @@
+\NeedsTeXFormat{LaTeX2e}
+\ProvidesPackage{doxygen}
+
+% Packages used by this style file
+\RequirePackage{alltt}
+\RequirePackage{array}
+\RequirePackage{calc}
+\RequirePackage{color}
+\RequirePackage{fancyhdr}
+\RequirePackage{verbatim}
+
+% Setup fancy headings
+\pagestyle{fancyplain}
+\newcommand{\clearemptydoublepage}{%
+ \newpage{\pagestyle{empty}\cleardoublepage}%
+}
+\renewcommand{\chaptermark}[1]{%
+ \markboth{#1}{}%
+}
+\renewcommand{\sectionmark}[1]{%
+ \markright{\thesection\ #1}%
+}
+\lhead[\fancyplain{}{\bfseries\thepage}]{%
+ \fancyplain{}{\bfseries\rightmark}%
+}
+\rhead[\fancyplain{}{\bfseries\leftmark}]{%
+ \fancyplain{}{\bfseries\thepage}%
+}
+\rfoot[\fancyplain{}{\bfseries\scriptsize%
+ Generated on Tue Oct 26 2010 19:42:42 for lib-\/lpp by Doxygen }]{}
+\lfoot[]{\fancyplain{}{\bfseries\scriptsize%
+ Generated on Tue Oct 26 2010 19:42:42 for lib-\/lpp by Doxygen }}
+\cfoot{}
+
+%---------- Internal commands used in this style file ----------------
+
+% Generic environment used by all paragraph-based environments defined
+% below. Note that the command \title{...} needs to be defined inside
+% those environments!
+\newenvironment{DoxyDesc}[1]{%
+ \begin{list}{}%
+ {%
+ \settowidth{\labelwidth}{40pt}%
+ \setlength{\leftmargin}{\labelwidth}%
+ \setlength{\parsep}{0pt}%
+ \setlength{\itemsep}{-4pt}%
+ \renewcommand{\makelabel}{\entrylabel}%
+ }%
+ \item[#1]%
+}{%
+ \end{list}%
+}
+
+%---------- Commands used by doxygen LaTeX output generator ----------
+
+% Used by ...
+\newenvironment{DoxyPre}{%
+ \small%
+ \begin{alltt}%
+}{%
+ \end{alltt}%
+ \normalsize%
+}
+
+% Used by @code ... @endcode
+\newenvironment{DoxyCode}{%
+ \footnotesize%
+ \verbatim%
+}{%
+ \endverbatim%
+ \normalsize%
+}
+
+% Used by @example, @include, @includelineno and @dontinclude
+\newenvironment{DoxyCodeInclude}{%
+ \DoxyCode%
+}{%
+ \endDoxyCode%
+}
+
+% Used by @verbatim ... @endverbatim
+\newenvironment{DoxyVerb}{%
+ \footnotesize%
+ \verbatim%
+}{%
+ \endverbatim%
+ \normalsize%
+}
+
+% Used by @verbinclude
+\newenvironment{DoxyVerbInclude}{%
+ \DoxyVerb%
+}{%
+ \endDoxyVerb%
+}
+
+% Used by numbered lists (using '-#' or ...
)
+\newenvironment{DoxyEnumerate}{%
+ \enumerate%
+}{%
+ \endenumerate%
+}
+
+% Used by bullet lists (using '-', @li, @arg, or )
+\newenvironment{DoxyItemize}{%
+ \itemize%
+}{%
+ \enditemize%
+}
+
+% Used by description lists (using ...
)
+\newenvironment{DoxyDescription}{%
+ \description%
+}{%
+ \enddescription%
+}
+
+% Used by @image, @dotfile, and @dot ... @enddot
+% (only if caption is specified)
+\newenvironment{DoxyImage}{%
+ \begin{figure}[H]%
+ \begin{center}%
+}{%
+ \end{center}%
+ \end{figure}%
+}
+
+% Used by @image, @dotfile, @dot ... @enddot, and @msc ... @endmsc
+% (only if no caption is specified)
+\newenvironment{DoxyImageNoCaption}{%
+}{%
+}
+
+% Used by @attention
+\newenvironment{DoxyAttention}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @author and @authors
+\newenvironment{DoxyAuthor}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @date
+\newenvironment{DoxyDate}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @invariant
+\newenvironment{DoxyInvariant}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @note
+\newenvironment{DoxyNote}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @post
+\newenvironment{DoxyPostcond}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @pre
+\newenvironment{DoxyPrecond}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @remark
+\newenvironment{DoxyRemark}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @return
+\newenvironment{DoxyReturn}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @since
+\newenvironment{DoxySince}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @see
+\newenvironment{DoxySeeAlso}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @version
+\newenvironment{DoxyVersion}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @warning
+\newenvironment{DoxyWarning}[1]{%
+ \begin{DoxyDesc}{#1}%
+}{%
+ \end{DoxyDesc}%
+}
+
+% Used by @internal
+\newenvironment{DoxyInternal}[1]{%
+ \paragraph*{#1}%
+}{%
+}
+
+% Used by @par and @paragraph
+\newenvironment{DoxyParagraph}[1]{%
+ \begin{list}{}%
+ {%
+ \settowidth{\labelwidth}{40pt}%
+ \setlength{\leftmargin}{\labelwidth}%
+ \setlength{\parsep}{0pt}%
+ \setlength{\itemsep}{-4pt}%
+ \renewcommand{\makelabel}{\entrylabel}%
+ }%
+ \item[#1]%
+}{%
+ \end{list}%
+}
+
+% Used by parameter lists
+\newenvironment{DoxyParams}[1]{%
+ \begin{DoxyDesc}{#1}%
+ \begin{description}%
+}{%
+ \end{description}%
+ \end{DoxyDesc}%
+}
+
+% is used for parameters within a detailed function description
+\newenvironment{DoxyParamCaption}{%
+ \renewcommand{\item}[2][]{##1 {\em ##2}}%
+ }{%
+}
+
+% Used by return value lists
+\newenvironment{DoxyRetVals}[1]{%
+ \begin{DoxyDesc}{#1}%
+ \begin{description}%
+}{%
+ \end{description}%
+ \end{DoxyDesc}%
+}
+
+% Used by exception lists
+\newenvironment{DoxyExceptions}[1]{%
+ \begin{DoxyDesc}{#1}%
+ \begin{description}%
+}{%
+ \end{description}%
+ \end{DoxyDesc}%
+}
+
+% Used by template parameter lists
+\newenvironment{DoxyTemplParams}[1]{%
+ \begin{DoxyDesc}{#1}%
+ \begin{description}%
+}{%
+ \end{description}%
+ \end{DoxyDesc}%
+}
+
+\newcommand{\doxyref}[3]{\textbf{#1} (\textnormal{#2}\,\pageref{#3})}
+\newenvironment{DoxyCompactList}
+{\begin{list}{}{
+ \setlength{\leftmargin}{0.5cm}
+ \setlength{\itemsep}{0pt}
+ \setlength{\parsep}{0pt}
+ \setlength{\topsep}{0pt}
+ \renewcommand{\makelabel}{\hfill}}}
+{\end{list}}
+\newenvironment{DoxyCompactItemize}
+{
+ \begin{itemize}
+ \setlength{\itemsep}{-3pt}
+ \setlength{\parsep}{0pt}
+ \setlength{\topsep}{0pt}
+ \setlength{\partopsep}{0pt}
+}
+{\end{itemize}}
+\newcommand{\PBS}[1]{\let\temp=\\#1\let\\=\temp}
+\newlength{\tmplength}
+\newenvironment{TabularC}[1]
+{
+\setlength{\tmplength}
+ {\linewidth/(#1)-\tabcolsep*2-\arrayrulewidth*(#1+1)/(#1)}
+ \par\begin{tabular*}{\linewidth}
+ {*{#1}{|>{\PBS\raggedright\hspace{0pt}}p{\the\tmplength}}|}
+}
+{\end{tabular*}\par}
+\newcommand{\entrylabel}[1]{
+ {\parbox[b]{\labelwidth-4pt}{\makebox[0pt][l]{\textbf{#1}}\vspace{1.5\baselineskip}}}}
+\newenvironment{Desc}
+{\begin{list}{}
+ {
+ \settowidth{\labelwidth}{40pt}
+ \setlength{\leftmargin}{\labelwidth}
+ \setlength{\parsep}{0pt}
+ \setlength{\itemsep}{-4pt}
+ \renewcommand{\makelabel}{\entrylabel}
+ }
+}
+{\end{list}}
+\newenvironment{Indent}
+ {\begin{list}{}{\setlength{\leftmargin}{0.5cm}}
+ \item[]\ignorespaces}
+ {\unskip\end{list}}
+\setlength{\parindent}{0cm}
+\setlength{\parskip}{0.2cm}
+\addtocounter{secnumdepth}{1}
+\sloppy
+\usepackage[T1]{fontenc}
+\makeatletter
+\renewcommand{\paragraph}{\@startsection{paragraph}{4}{0ex}%
+ {-3.25ex plus -1ex minus -0.2ex}%
+ {1.5ex plus 0.2ex}%
+ {\normalfont\normalsize\bfseries}}
+\makeatother
+\stepcounter{secnumdepth}
+\stepcounter{tocdepth}
+\definecolor{comment}{rgb}{0.5,0.0,0.0}
+\definecolor{keyword}{rgb}{0.0,0.5,0.0}
+\definecolor{keywordtype}{rgb}{0.38,0.25,0.125}
+\definecolor{keywordflow}{rgb}{0.88,0.5,0.0}
+\definecolor{preprocessor}{rgb}{0.5,0.38,0.125}
+\definecolor{stringliteral}{rgb}{0.0,0.125,0.25}
+\definecolor{charliteral}{rgb}{0.0,0.5,0.5}
+\definecolor{vhdldigit}{rgb}{1.0,0.0,1.0}
+\definecolor{vhdlkeyword}{rgb}{0.43,0.0,0.43}
+\definecolor{vhdllogic}{rgb}{1.0,0.0,0.0}
+\definecolor{vhdlchar}{rgb}{0.0,0.0,0.0}
diff --git a/lib/lpp/doc/latex/refman.aux b/lib/lpp/doc/latex/refman.aux
new file mode 100644
--- /dev/null
+++ b/lib/lpp/doc/latex/refman.aux
@@ -0,0 +1,1866 @@
+\relax
+\ifx\hyper@anchor\@undefined
+\global \let \oldcontentsline\contentsline
+\gdef \contentsline#1#2#3#4{\oldcontentsline{#1}{#2}{#3}}
+\global \let \oldnewlabel\newlabel
+\gdef \newlabel#1#2{\newlabelxx{#1}#2}
+\gdef \newlabelxx#1#2#3#4#5#6{\oldnewlabel{#1}{{#2}{#3}}}
+\AtEndDocument{\let \contentsline\oldcontentsline
+\let \newlabel\oldnewlabel}
+\else
+\global \let \hyper@last\relax
+\fi
+
+\@writefile{toc}{\contentsline {chapter}{\numberline {1}Design Unit Index}{1}{chapter.1}}
+\@writefile{lof}{\addvspace {10\p@ }}
+\@writefile{lot}{\addvspace {10\p@ }}
+\@writefile{toc}{\contentsline {section}{\numberline {1.1}Design Unit Hierarchy}{1}{section.1.1}}
+\@writefile{toc}{\contentsline {chapter}{\numberline {2}Design Unit Index}{3}{chapter.2}}
+\@writefile{lof}{\addvspace {10\p@ }}
+\@writefile{lot}{\addvspace {10\p@ }}
+\@writefile{toc}{\contentsline {section}{\numberline {2.1}Design Unit List}{3}{section.2.1}}
+\@writefile{toc}{\contentsline {chapter}{\numberline {3}File Index}{5}{chapter.3}}
+\@writefile{lof}{\addvspace {10\p@ }}
+\@writefile{lot}{\addvspace {10\p@ }}
+\@writefile{toc}{\contentsline {section}{\numberline {3.1}File List}{5}{section.3.1}}
+\@writefile{toc}{\contentsline {chapter}{\numberline {4}Class Documentation}{7}{chapter.4}}
+\@writefile{lof}{\addvspace {10\p@ }}
+\@writefile{lot}{\addvspace {10\p@ }}
+\@writefile{toc}{\contentsline {section}{\numberline {4.1}Adder Entity Reference}{7}{section.4.1}}
+\newlabel{class_adder}{{4.1}{7}{Adder Entity Reference\relax }{section.4.1}{}}
+\@writefile{toc}{\contentsline {subsection}{\numberline {4.1.1}Member Data Documentation}{9}{subsection.4.1.1}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.1}add}{9}{subsubsection.4.1.1.1}}
+\newlabel{class_adder_a32a6650da83710066530c5095b459fac}{{4.1.1.1}{9}{add\relax }{subsubsection.4.1.1.1}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.2}clk}{9}{subsubsection.4.1.1.2}}
+\newlabel{class_adder_aeada434ddff982265d4a93768632e621}{{4.1.1.2}{9}{clk\relax }{subsubsection.4.1.1.2}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.3}clr}{9}{subsubsection.4.1.1.3}}
+\newlabel{class_adder_a6d72cbcfbbdab33537a5c43b160bf0f4}{{4.1.1.3}{9}{clr\relax }{subsubsection.4.1.1.3}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.4}general\_\discretionary {-}{}{}purpose}{9}{subsubsection.4.1.1.4}}
+\newlabel{class_adder_a63d2766a6c866f862cdeed31c8a0bdab}{{4.1.1.4}{9}{general\_\-purpose\relax }{subsubsection.4.1.1.4}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.5}IEEE}{9}{subsubsection.4.1.1.5}}
+\newlabel{class_adder_adc40931273a8420e6fb52edf643d8434}{{4.1.1.5}{9}{IEEE\relax }{subsubsection.4.1.1.5}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.6}Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}A}{9}{subsubsection.4.1.1.6}}
+\newlabel{class_adder_a809074e1b4c24cd7e29cdbccb59fbab5}{{4.1.1.6}{9}{Input\_\-SZ\_\-A\relax }{subsubsection.4.1.1.6}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.7}Input\_\discretionary {-}{}{}SZ\_\discretionary {-}{}{}B}{9}{subsubsection.4.1.1.7}}
+\newlabel{class_adder_a413a38e47e4d8bebbf888f22ad7df386}{{4.1.1.7}{9}{Input\_\-SZ\_\-B\relax }{subsubsection.4.1.1.7}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.8}lpp}{9}{subsubsection.4.1.1.8}}
+\newlabel{class_adder_aa7b2d89e49a7157b58499684cc228990}{{4.1.1.8}{9}{lpp\relax }{subsubsection.4.1.1.8}{}}
+\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1.9}numeric\_\discretionary {-}{}{}std}{9}{subsubsection.4.1.1.9}}
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diff --git a/lib/lpp/doc/latex/refman.idx b/lib/lpp/doc/latex/refman.idx
new file mode 100644
--- /dev/null
+++ b/lib/lpp/doc/latex/refman.idx
@@ -0,0 +1,1667 @@
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+\indexentry{ChanelsCNT@{ChanelsCNT}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{coefT@{coefT}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{DenCoefs\_\discretionary {-}{}{}cel@{DenCoefs\_\discretionary {-}{}{}cel}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
+\indexentry{FILTERcfg@{FILTERcfg}!DenominatorCoefs@{DenominatorCoefs}|hyperpage}{73}
+\indexentry{DenominatorCoefs@{DenominatorCoefs}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
+\indexentry{FILTERcfg@{FILTERcfg}!IDLE@{IDLE}|hyperpage}{73}
+\indexentry{IDLE@{IDLE}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{IEEE@{IEEE}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{NumCoefs\_\discretionary {-}{}{}cel@{NumCoefs\_\discretionary {-}{}{}cel}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
+\indexentry{FILTERcfg@{FILTERcfg}!NumeratorCoefs@{NumeratorCoefs}|hyperpage}{73}
+\indexentry{NumeratorCoefs@{NumeratorCoefs}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
+\indexentry{FILTERcfg@{FILTERcfg}!numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}|hyperpage}{73}
+\indexentry{numeric\_\discretionary {-}{}{}std@{numeric\_\discretionary {-}{}{}std}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{FILTERcfg@{FILTERcfg}!samplT@{samplT}|hyperpage}{73}
+\indexentry{samplT@{samplT}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{Scalefac\_\discretionary {-}{}{}SZ@{Scalefac\_\discretionary {-}{}{}SZ}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
+\indexentry{FILTERcfg@{FILTERcfg}!scaleValT@{scaleValT}|hyperpage}{73}
+\indexentry{scaleValT@{scaleValT}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{Smpl\_\discretionary {-}{}{}SZ@{Smpl\_\discretionary {-}{}{}SZ}!FILTERcfg@{FILTERcfg}|hyperpage}{73}
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+\indexentry{FilterCTRLR@{FilterCTRLR}!ALU\_\discretionary {-}{}{}Ctrl@{ALU\_\discretionary {-}{}{}Ctrl}|hyperpage}{75}
+\indexentry{ALU\_\discretionary {-}{}{}Ctrl@{ALU\_\discretionary {-}{}{}Ctrl}!FilterCTRLR@{FilterCTRLR}|hyperpage}{75}
+\indexentry{FilterCTRLR@{FilterCTRLR}!clk@{clk}|hyperpage}{75}
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+\indexentry{FilterCTRLR@{FilterCTRLR}!IEEE@{IEEE}|hyperpage}{75}
+\indexentry{IEEE@{IEEE}!FilterCTRLR@{FilterCTRLR}|hyperpage}{75}
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+\indexentry{reset@{reset}!FilterCTRLR@{FilterCTRLR}|hyperpage}{75}
+\indexentry{FilterCTRLR@{FilterCTRLR}!sample@{sample}|hyperpage}{75}
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+\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!FRAME_CLK_GEN@{FRAME\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GEN}|hyperpage}{77}
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+\indexentry{general\_\discretionary {-}{}{}purpose@{general\_\discretionary {-}{}{}purpose}|hyperpage}{78}
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+\indexentry{MAC\_\discretionary {-}{}{}CONTROLER@{MAC\_\discretionary {-}{}{}CONTROLER}!general_purpose@{general\_\discretionary {-}{}{}purpose}|hyperpage}{79}
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+\indexentry{MAC\_\discretionary {-}{}{}MUX2@{MAC\_\discretionary {-}{}{}MUX2}!general_purpose@{general\_\discretionary {-}{}{}purpose}|hyperpage}{79}
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+\indexentry{Multiplier@{Multiplier}!general_purpose@{general\_\discretionary {-}{}{}purpose}|hyperpage}{79}
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+\indexentry{REG@{REG}!general_purpose@{general\_\discretionary {-}{}{}purpose}|hyperpage}{79}
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+\indexentry{Duration\_\discretionary {-}{}{}20ms@{Duration\_\discretionary {-}{}{}20ms}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}4ms@{Duration\_\discretionary {-}{}{}4ms}|hyperpage}{90}
+\indexentry{Duration\_\discretionary {-}{}{}4ms@{Duration\_\discretionary {-}{}{}4ms}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!Duration\_\discretionary {-}{}{}4us@{Duration\_\discretionary {-}{}{}4us}|hyperpage}{90}
+\indexentry{Duration\_\discretionary {-}{}{}4us@{Duration\_\discretionary {-}{}{}4us}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!FunctionSet@{FunctionSet}|hyperpage}{90}
+\indexentry{FunctionSet@{FunctionSet}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!IEEE@{IEEE}|hyperpage}{90}
+\indexentry{IEEE@{IEEE}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl@{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl@{LCD\_\discretionary {-}{}{}CFG\_\discretionary {-}{}{}Tbl}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CMD\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}CTRL\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS@{LCD\_\discretionary {-}{}{}DRVR\_\discretionary {-}{}{}SYNCH\_\discretionary {-}{}{}BUSS}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!lpp@{lpp}|hyperpage}{90}
+\indexentry{lpp@{lpp}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!RetHome@{RetHome}|hyperpage}{90}
+\indexentry{RetHome@{RetHome}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!SetEntryMode@{SetEntryMode}|hyperpage}{90}
+\indexentry{SetEntryMode@{SetEntryMode}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
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+\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_16x2_CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{90}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{91}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}|hyperpage}{92}
+\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!clk@{clk}|hyperpage}{92}
+\indexentry{clk@{clk}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!CMD@{CMD}|hyperpage}{92}
+\indexentry{CMD@{CMD}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!DATA@{DATA}|hyperpage}{92}
+\indexentry{DATA@{DATA}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Exec@{Exec}|hyperpage}{92}
+\indexentry{Exec@{Exec}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
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+\indexentry{IEEE@{IEEE}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}CFG}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}CTRL@{LCD\_\discretionary {-}{}{}CTRL}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!lpp@{lpp}|hyperpage}{92}
+\indexentry{lpp@{lpp}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{92}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}|hyperpage}{93}
+\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}|hyperpage}{93}
+\indexentry{OSC\_\discretionary {-}{}{}freqKHz@{OSC\_\discretionary {-}{}{}freqKHz}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!Ready@{Ready}|hyperpage}{93}
+\indexentry{Ready@{Ready}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!reset@{reset}|hyperpage}{93}
+\indexentry{reset@{reset}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}|hyperpage}{93}
+\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_16x2_ENGINE@{LCD\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ENGINE}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{93}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}|hyperpage}{95}
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+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!clk@{clk}|hyperpage}{95}
+\indexentry{clk@{clk}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
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+\indexentry{FramBUFF@{FramBUFF}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!IEEE@{IEEE}|hyperpage}{95}
+\indexentry{IEEE@{IEEE}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}CS1@{LCD\_\discretionary {-}{}{}CS1}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}CS2@{LCD\_\discretionary {-}{}{}CS2}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}data@{LCD\_\discretionary {-}{}{}data}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}E@{LCD\_\discretionary {-}{}{}E}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}RET@{LCD\_\discretionary {-}{}{}RET}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}RS@{LCD\_\discretionary {-}{}{}RS}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}RW@{LCD\_\discretionary {-}{}{}RW}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!lpp@{lpp}|hyperpage}{95}
+\indexentry{lpp@{lpp}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}|hyperpage}{95}
+\indexentry{NUMERIC\_\discretionary {-}{}{}STD@{NUMERIC\_\discretionary {-}{}{}STD}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz@{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz}|hyperpage}{95}
+\indexentry{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz@{OSC\_\discretionary {-}{}{}Freq\_\discretionary {-}{}{}MHz}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!Refresh\_\discretionary {-}{}{}RateHz@{Refresh\_\discretionary {-}{}{}RateHz}|hyperpage}{95}
+\indexentry{Refresh\_\discretionary {-}{}{}RateHz@{Refresh\_\discretionary {-}{}{}RateHz}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!refreshPulse@{refreshPulse}|hyperpage}{95}
+\indexentry{refreshPulse@{refreshPulse}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!reset@{reset}|hyperpage}{95}
+\indexentry{reset@{reset}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!STATEOUT@{STATEOUT}|hyperpage}{95}
+\indexentry{STATEOUT@{STATEOUT}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}!STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}|hyperpage}{95}
+\indexentry{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164@{STD\_\discretionary {-}{}{}LOGIC\_\discretionary {-}{}{}1164}!LCD_2x16_DRIVER@{LCD\_\discretionary {-}{}{}2x16\_\discretionary {-}{}{}DRIVER}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}|hyperpage}{95}
+\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}|hyperpage}{97}
+\indexentry{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr@{amba\_\discretionary {-}{}{}lcd\_\discretionary {-}{}{}16x2\_\discretionary {-}{}{}ctrlr}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}|hyperpage}{97}
+\indexentry{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}!clk@{clk}|hyperpage}{97}
+\indexentry{clk@{clk}!LCD_CLK_GENERATOR@{LCD\_\discretionary {-}{}{}CLK\_\discretionary {-}{}{}GENERATOR}|hyperpage}{97}
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diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd
@@ -0,0 +1,193 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- APB_IIR_CEL.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+use lpp.lpp_amba.all;
+
+entity APB_IIR_CEL is
+ generic (
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ pirq : integer := 0;
+ abits : integer := 8;
+ Sample_SZ : integer := Smpl_SZ
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ sample_clk : in std_logic;
+ sample_clk_out : out std_logic;
+ sample_in : in samplT;
+ sample_out : out samplT
+ );
+end;
+
+
+architecture AR_APB_IIR_CEL of APB_IIR_CEL is
+
+constant REVISION : integer := 1;
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+
+
+type FILTERreg is record
+ regin : in_IIR_CEL_reg;
+ regout : out_IIR_CEL_reg;
+end record;
+
+signal r : FILTERreg;
+signal filter_reset : std_logic:='0';
+signal smp_cnt : integer :=0;
+signal sample_clk_out_R : std_logic;
+begin
+
+filter_reset <= rst and r.regin.config(0);
+sample_clk_out <= sample_clk_out_R;
+
+filter : IIR_CEL_FILTER
+generic map(Sample_SZ => Sample_SZ)
+port map(
+ reset => filter_reset,
+ clk => clk,
+ sample_clk => sample_clk,
+ regs_in => r.regin,
+ regs_out => r.regout,
+ sample_in => sample_in,
+ sample_out => sample_out
+ );
+
+process(rst,sample_clk)
+begin
+if rst = '0' then
+ smp_cnt <= 0;
+ sample_clk_out_R <= '0';
+elsif sample_clk'event and sample_clk = '1' then
+ if smp_cnt = 1 then
+ smp_cnt <= 0;
+ sample_clk_out_R <= not sample_clk_out_R;
+ else
+ smp_cnt <= smp_cnt +1;
+ end if;
+end if;
+end process;
+
+
+process(rst,clk)
+begin
+ if rst = '0' then
+ r.regin.coefsTB.NumCoefs <= NumCoefs_cel;
+ r.regin.coefsTB.DenCoefs <= DenCoefs_cel;
+ r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
+
+ elsif clk'event and clk = '1' then
+
+
+--APB Write OP
+ if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
+ case apbi.paddr(7 downto 2) is
+ when "000000" =>
+ r.regin.config(0) <= apbi.pwdata(0);
+ when "000001" =>
+ r.regin.virgPos <= apbi.pwdata(4 downto 0);
+ when others =>
+ for i in 0 to Cels_count-1 loop
+ if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
+ case apbi.paddr(4 downto 2) is
+ when "000" =>
+ r.regin.coefsTB.NumCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when "001" =>
+ r.regin.coefsTB.NumCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when "010" =>
+ r.regin.coefsTB.NumCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when "011" =>
+ r.regin.coefsTB.DenCoefs(i)(0) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when "100" =>
+ r.regin.coefsTB.DenCoefs(i)(1) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when "101" =>
+ r.regin.coefsTB.DenCoefs(i)(2) <= coefT(apbi.pwdata(Coef_SZ-1 downto 0));
+ when others =>
+ end case;
+ end if;
+ end loop;
+ end case;
+ end if;
+
+--APB READ OP
+ if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+ case apbi.paddr(7 downto 2) is
+ when "000000" =>
+
+ when "000001" =>
+ apbo.prdata(4 downto 0) <= r.regin.virgPos;
+ when others =>
+ for i in 0 to Cels_count-1 loop
+ if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
+ case apbi.paddr(4 downto 2) is
+ when "000" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(0));
+ when "001" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(1));
+ when "010" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.NumCoefs(i)(2));
+ when "011" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(0));
+ when "100" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(1));
+ when "101" =>
+ apbo.prdata(Coef_SZ-1 downto 0) <= std_logic_vector(r.regin.coefsTB.DenCoefs(i)(2));
+ when others =>
+ end case;
+ end if;
+ end loop;
+ end case;
+ end if;
+
+ end if;
+ apbo.pconfig <= pconfig;
+end process;
+
+
+
+-- pragma translate_off
+ bootmsg : report_version
+ generic map ("apbuart" & tost(pindex) &
+ ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
+ ", irq " & tost(pirq));
+-- pragma translate_on
+
+
+
+end ar_APB_IIR_CEL;
+
diff --git a/lib/lpp/dsp/iir_filter/DOC_APB_ROCKET_TM.odt b/lib/lpp/dsp/iir_filter/DOC_APB_ROCKET_TM.odt
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diff --git a/lib/lpp/dsp/iir_filter/FILTER.vhd b/lib/lpp/dsp/iir_filter/FILTER.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/FILTER.vhd
@@ -0,0 +1,102 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- FILTER.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+--Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
+--exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
+--Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
+
+entity FILTER is
+port(
+
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
+ Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
+);
+end entity;
+
+
+
+
+
+architecture ar_FILTER of FILTER is
+
+
+
+
+signal ALU_ctrl : std_logic_vector(3 downto 0);
+signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
+signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
+signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
+
+begin
+
+--==============================================================
+--=========================A L U================================
+--==============================================================
+ALU1 : entity ALU
+generic map(
+ Arith_en => 1,
+ Logic_en => 0,
+ Input_SZ_1 => Smpl_SZ,
+ Input_SZ_2 => Coef_SZ
+
+)
+port map(
+ clk => clk,
+ reset => reset,
+ ctrl => ALU_ctrl,
+ OP1 => Sample,
+ OP2 => Coef,
+ RES => ALU_OUT
+);
+--==============================================================
+
+--==============================================================
+--===============F I L T E R C O N T R O L E R================
+--==============================================================
+filterctrlr1 : FilterCTRLR
+port map(
+ reset => reset,
+ clk => clk,
+ sample_clk => sample_clk,
+ ALU_Ctrl => ALU_ctrl,
+ sample_in => sample_Tbl,
+ coef => Coef,
+ sample => Sample
+);
+--==============================================================
+
+chanelCut : for i in 0 to ChanelsCNT-1 generate
+ sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
+end generate;
+
+
+
+
+end ar_FILTER;
+
diff --git a/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd b/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd
@@ -0,0 +1,226 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- FILTER_RAM_CTRLR.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+
+--TODO am�liorer la flexibilit� de la config de la RAM.
+
+entity FILTER_RAM_CTRLR is
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ run : in std_logic;
+ GO_0 : in std_logic;
+ B_A : in std_logic;
+ writeForce : in std_logic;
+ next_blk : in std_logic;
+ sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
+ sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
+);
+end FILTER_RAM_CTRLR;
+
+
+architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is
+
+signal WD : std_logic_vector(35 downto 0);
+signal WD_D : std_logic_vector(35 downto 0);
+signal RD : std_logic_vector(35 downto 0);
+signal WEN, REN : std_logic;
+signal WADDR_back : std_logic_vector(7 downto 0);
+signal WADDR_back_D: std_logic_vector(7 downto 0);
+signal RADDR : std_logic_vector(7 downto 0);
+signal WADDR : std_logic_vector(7 downto 0);
+signal WADDR_D : std_logic_vector(7 downto 0);
+signal run_D : std_logic;
+signal run_D_inv : std_logic;
+signal run_inv : std_logic;
+signal next_blk_D : std_logic;
+signal MUX2_inst1_sel : std_logic;
+
+
+begin
+
+sample_out <= RD(Smpl_SZ-1 downto 0);
+
+MUX2_inst1_sel <= run_D and not next_blk;
+run_D_inv <= not run_D;
+run_inv <= not run;
+WEN <= run_D_inv and not writeForce;
+REN <= run_inv ;--and not next_blk;
+
+
+--==============================================================
+--=========================R A M================================
+--==============================================================
+memRAM : if Mem_use = use_RAM generate
+RAMblk :RAM
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN,
+ REN => REN,
+ WADDR => WADDR,
+ RADDR => RADDR,
+ RWCLK => clk,
+ RESET => reset
+ ) ;
+end generate;
+
+memCEL : if Mem_use = use_CEL generate
+RAMblk :RAM_CEL
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN,
+ REN => REN,
+ WADDR => WADDR,
+ RADDR => RADDR,
+ RWCLK => clk,
+ RESET => reset
+ ) ;
+end generate;
+--==============================================================
+--==============================================================
+
+
+ADDRcntr_inst : ADDRcntr
+port map(
+ clk => clk,
+ reset => reset,
+ count => run,
+ clr => GO_0,
+ Q => RADDR
+);
+
+
+
+MUX2_inst1 :MUX2
+generic map(Input_SZ => Smpl_SZ)
+port map(
+ sel => MUX2_inst1_sel,
+ IN1 => sample_in,
+ IN2 => RD(Smpl_SZ-1 downto 0),
+ RES => WD(Smpl_SZ-1 downto 0)
+);
+
+
+MUX2_inst2 :MUX2
+generic map(Input_SZ => 8)
+port map(
+ sel => next_blk_D,
+ IN1 => WADDR_D,
+ IN2 => WADDR_back_D,
+ RES => WADDR
+);
+
+
+next_blkRreg :REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => next_blk,
+ Q(0) => next_blk_D
+);
+
+WADDR_backreg :REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => B_A,
+ D => RADDR,
+ Q => WADDR_back
+);
+
+WADDR_backreg2 :REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => B_A,
+ D => WADDR_back,
+ Q => WADDR_back_D
+);
+
+WDRreg :REG
+generic map(size => Smpl_SZ)
+port map(
+ reset => reset,
+ clk => clk,
+ D => WD(Smpl_SZ-1 downto 0),
+ Q => WD_D(Smpl_SZ-1 downto 0)
+);
+
+RunRreg :REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => run,
+ Q(0) => run_D
+);
+
+
+
+ADDRreg :REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => clk,
+ D => RADDR,
+ Q => WADDR_D
+);
+
+
+
+end ar_FILTER_RAM_CTRLR;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
@@ -0,0 +1,242 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- FILTERcfg.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+
+package FILTERcfg is
+
+
+--===========================================================|
+--================A L U C O N T R O L======================|
+--===========================================================|
+constant IDLE : std_logic_vector(3 downto 0) := "0000";
+constant MAC_op : std_logic_vector(3 downto 0) := "0001";
+constant MULT : std_logic_vector(3 downto 0) := "0010";
+constant ADD : std_logic_vector(3 downto 0) := "0011";
+constant clr_mac : std_logic_vector(3 downto 0) := "0100";
+
+
+--===========================================================|
+--========F I L T E R C O N F I G V A L U E S=============|
+--===========================================================|
+--____________________________
+--Bus Width and chanels number|
+--____________________________|
+constant ChanelsCNT : integer := 6;
+constant Smpl_SZ : integer := 16;
+constant Coef_SZ : integer := 9;
+constant Scalefac_SZ: integer := 3;
+constant Cels_count : integer := 5;
+--____
+--RAM |
+--____|
+constant use_RAM : integer := 1;
+constant use_CEL : integer := 0;
+
+constant Mem_use : integer := 1;
+
+--===========================================================|
+--=============C O E F S ====================================|
+--===========================================================|
+-- create a specific type of data for coefs to avoid errors |
+--===========================================================|
+
+type coefT is array(Coef_SZ-1 downto 0) of std_logic;
+type scaleValT is array(natural range <>) of integer;
+
+type coef_celT is array(0 to 2) of coefT;
+
+type coefsT is array(natural range <>) of coefT ;
+
+type coefs_celT is array(natural range <>) of coef_celT;
+
+type samplT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
+
+
+
+
+type coefs_celsT is record
+ NumCoefs : coefs_celT(0 to Cels_count-1);
+ DenCoefs : coefs_celT(0 to Cels_count-1);
+end record;
+
+
+type in_IIR_CEL_reg is record
+ config : std_logic_vector(31 downto 0);
+ coefsTB : coefs_celsT;
+ virgPos : std_logic_vector(4 downto 0);
+end record;
+type out_IIR_CEL_reg is record
+ config : std_logic_vector(31 downto 0);
+ status : std_logic_vector(31 downto 0);
+end record;
+
+
+--============================================================
+-- create each initial values for each coefs ============
+--!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
+--============================================================
+constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ));
+constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
+constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
+constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
+constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
+constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
+constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
+
+constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
+constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ));
+constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
+constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ));
+
+
+constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
+constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ));
+constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
+
+constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
+constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ));
+constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ));
+
+constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
+constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ));
+constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ));
+
+constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
+constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ));
+constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
+
+constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
+constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ));
+constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ));
+
+constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
+constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ));
+constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ));
+
+constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ));
+constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ));
+constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ));
+
+
+constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ));
+constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ));
+
+constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ));
+constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ));
+
+constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ));
+constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ));
+
+constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ));
+constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ));
+
+constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ));
+constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ));
+
+constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
+constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
+constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ));
+constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ));
+constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ));
+
+
+constant celb0 : coef_celT := (b0_0,b0_1,b0_2);
+constant celb1 : coef_celT := (b1_0,b1_1,b1_2);
+constant celb2 : coef_celT := (b2_0,b2_1,b2_2);
+constant celb3 : coef_celT := (b3_0,b3_1,b3_2);
+constant celb4 : coef_celT := (b4_0,b4_1,b4_2);
+constant celb5 : coef_celT := (b5_0,b5_1,b5_2);
+constant celb6 : coef_celT := (b6_0,b6_1,b6_2);
+
+constant cela0 : coef_celT := (a0_0,a0_1,a0_2);
+constant cela1 : coef_celT := (a1_0,a1_1,a1_2);
+constant cela2 : coef_celT := (a2_0,a2_1,a2_2);
+constant cela3 : coef_celT := (a3_0,a3_1,a3_2);
+constant cela4 : coef_celT := (a4_0,a4_1,a4_2);
+constant cela5 : coef_celT := (a5_0,a5_1,a5_2);
+constant cela6 : coef_celT := (a6_0,a6_1,a6_2);
+
+
+
+constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4);
+constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4);
+constant virgPos : integer := 7;
+
+
+
+
+
+
+
+signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6);
+signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4);
+
+
+signal sample_Tbl : samplT;
+
+
+end;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd b/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd
@@ -0,0 +1,263 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- FilterCTRLR.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+
+--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
+
+entity FilterCTRLR is
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ ALU_Ctrl : out std_logic_vector(3 downto 0);
+ sample_in : in samplT;
+ coef : out std_logic_vector(Coef_SZ-1 downto 0);
+ sample : out std_logic_vector(Smpl_SZ-1 downto 0)
+);
+end FilterCTRLR;
+
+
+architecture ar_FilterCTRLR of FilterCTRLR is
+
+constant NUMCoefsCnt : integer:= NumeratorCoefs'high;
+constant DENCoefsCnt : integer:= DenominatorCoefs'high;
+
+signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0;
+signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0;
+
+signal chanelCnt : integer range 0 to 15:=0;
+
+signal WD : std_logic_vector(35 downto 0);
+signal WD_D : std_logic_vector(35 downto 0);
+signal RD : std_logic_vector(35 downto 0);
+signal WEN, REN,WEN_D : std_logic;
+signal WADDR_back : std_logic_vector(7 downto 0);
+signal ADDR : std_logic_vector(7 downto 0);
+signal ADDR_D : std_logic_vector(7 downto 0);
+signal clk_inv : std_logic;
+
+type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0);
+signal in_Rotate_Buff : Rotate_BuffT;
+signal out_Rotate_Buff : Rotate_BuffT;
+
+signal sample_clk_old : std_logic;
+
+type stateT is (waiting,computeNUM,computeDEN,NextChanel);
+signal state : stateT;
+
+begin
+clk_inv <= not clk;
+
+process(clk,reset)
+begin
+if reset = '0' then
+ state <= waiting;
+ WEN <= '1';
+ REN <= '1';
+ ADDR <= (others => '0');
+ WD <= (others => '0');
+ NcoefCnt <= 0;
+ DcoefCnt <= 0;
+ chanelCnt <= 0;
+ ALU_Ctrl <= clr_mac;
+ sample_clk_old <= '0';
+ coef <= (others => '0');
+ sample <= (others => '0');
+rst:for i in 0 to ChanelsCNT-1 loop
+ in_Rotate_Buff(i) <= (others => '0');
+ end loop;
+elsif clk'event and clk = '1' then
+
+ sample_clk_old <= sample_clk;
+
+--=================================================================
+--===============DATA processing===================================
+--=================================================================
+ case state is
+ when waiting=>
+
+ if sample_clk_old = '0' and sample_clk = '1' then
+ ALU_Ctrl <= MAC_op;
+ sample <= in_Rotate_Buff(0);
+ coef <= std_logic_vector(NumeratorCoefs(0));
+ else
+ ALU_Ctrl <= clr_mac;
+loadinput: for i in 0 to ChanelsCNT-1 loop
+ in_Rotate_Buff(i) <= sample_in(i);
+ end loop;
+ end if;
+
+ when computeNUM=>
+ ALU_Ctrl <= MAC_op;
+ sample <= RD(Smpl_SZ-1 downto 0);
+ coef <= std_logic_vector(NumeratorCoefs(NcoefCnt));
+
+ when computeDEN=>
+ ALU_Ctrl <= MAC_op;
+ sample <= RD(Smpl_SZ-1 downto 0);
+ coef <= std_logic_vector(DenominatorCoefs(DcoefCnt));
+
+ when NextChanel=>
+rotate : for i in 0 to ChanelsCNT-2 loop
+ in_Rotate_Buff(i) <= in_Rotate_Buff(i+1);
+ end loop;
+rotatetoo: if ChanelsCNT > 1 then
+ sample <= in_Rotate_Buff(1);
+ coef <= std_logic_vector(NumeratorCoefs(0));
+ end if;
+ end case;
+
+--=================================================================
+--===============RAM read write====================================
+--=================================================================
+ case state is
+ when waiting=>
+ if sample_clk_old = '0' and sample_clk = '1' then
+ REN <= '0';
+ else
+ REN <= '1';
+ end if;
+ ADDR <= (others => '0');
+ WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0);
+ WEN <= '1';
+
+ when computeNUM=>
+ WD <= RD;
+ REN <= '0';
+ WEN <= '0';
+ ADDR <= std_logic_vector(unsigned(ADDR)+1);
+ when computeDEN=>
+ WD <= RD;
+ REN <= '0';
+ WEN <= '0';
+ ADDR <= std_logic_vector(unsigned(ADDR)+1);
+ when NextChanel=>
+ REN <= '1';
+ WEN <= '1';
+ end case;
+--=================================================================
+
+
+--=================================================================
+--===============FSM Management====================================
+--=================================================================
+ case state is
+ when waiting=>
+ if sample_clk_old = '0' and sample_clk = '1' then
+ state <= computeNUM;
+ end if;
+ DcoefCnt <= 0;
+ NcoefCnt <= 1;
+ chanelCnt<= 0;
+ when computeNUM=>
+ if NcoefCnt = NumCoefsCnt then
+ state <= computeDEN;
+ NcoefCnt <= 1;
+ else
+ NcoefCnt <= NcoefCnt+1;
+ end if;
+ when computeDEN=>
+ if DcoefCnt = DENCoefsCnt then
+ state <= NextChanel;
+ DcoefCnt <= 0;
+ else
+ DcoefCnt <= DcoefCnt+1;
+ end if;
+ when NextChanel=>
+ if chanelCnt = (ChanelsCNT-1) then
+ state <= waiting;
+ else
+ chanelCnt<= chanelCnt+1;
+ state <= computeNUM;
+ end if;
+ end case;
+--=================================================================
+
+end if;
+end process;
+
+ADDRreg : REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => clk,
+ D => ADDR,
+ Q => ADDR_D
+);
+
+WDreg :REG
+generic map(size => 36)
+port map(
+ reset => reset,
+ clk => clk,
+ D => WD,
+ Q => WD_D
+);
+
+WRreg :REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => WEN,
+ Q(0) => WEN_D
+);
+--==============================================================
+--=========================R A M================================
+--==============================================================
+memRAM : if Mem_use = use_RAM generate
+RAMblk :RAM
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN_D,
+ REN => REN,
+ WADDR => ADDR_D,
+ RADDR => ADDR,
+ RWCLK => clk_inv,
+ RESET => reset
+ ) ;
+end generate;
+
+memCEL : if Mem_use = use_CEL generate
+RAMblk :RAM
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN_D,
+ REN => REN,
+ WADDR => ADDR_D,
+ RADDR => ADDR,
+ RWCLK => clk_inv,
+ RESET => reset
+ ) ;
+end generate;
+
+--==============================================================
+
+
+
+end ar_FilterCTRLR;
diff --git a/lib/lpp/dsp/iir_filter/GPL_HEADER b/lib/lpp/dsp/iir_filter/GPL_HEADER
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/GPL_HEADER
@@ -0,0 +1,18 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
@@ -0,0 +1,293 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- IIR_CEL_CTRLR.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+
+--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
+
+entity IIR_CEL_CTRLR is
+generic(Sample_SZ : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ sample_in : in samplT;
+ sample_out : out samplT;
+ virg_pos : in integer;
+ coefs : in coefs_celsT
+);
+end IIR_CEL_CTRLR;
+
+
+
+
+architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
+
+signal smpl_clk_old : std_logic := '0';
+signal WD_sel : std_logic := '0';
+signal Read : std_logic := '0';
+signal SVG_ADDR : std_logic := '0';
+signal count : std_logic := '0';
+signal Write : std_logic := '0';
+signal WADDR_sel : std_logic := '0';
+signal GO_0 : std_logic := '0';
+
+signal RAM_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
+signal RAM_sample_in_bk: std_logic_vector(Sample_SZ-1 downto 0);
+signal RAM_sample_out : std_logic_vector(Sample_SZ-1 downto 0);
+signal ALU_ctrl : std_logic_vector(3 downto 0);
+signal ALU_sample_in : std_logic_vector(Sample_SZ-1 downto 0);
+signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
+signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
+signal curentCel : integer range 0 to Cels_count-1 := 0;
+signal curentChan : integer range 0 to ChanelsCNT-1 := 0;
+
+signal sample_in_BUFF : samplT;
+signal sample_out_BUFF : samplT;
+
+
+
+type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
+
+signal IIR_CEL_STATE : fsmIIR_CEL_T;
+
+begin
+
+
+
+
+
+RAM_CTRLR2inst : RAM_CTRLR2
+generic map(Input_SZ_1 => Sample_SZ)
+port map(
+ reset => reset,
+ clk => clk,
+ WD_sel => WD_sel,
+ Read => Read,
+ WADDR_sel => WADDR_sel,
+ count => count,
+ SVG_ADDR => SVG_ADDR,
+ Write => Write,
+ GO_0 => GO_0,
+ sample_in => RAM_sample_in,
+ sample_out => RAM_sample_out
+);
+
+
+
+ALU_inst :ALU
+generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
+port map(
+ clk => clk,
+ reset => reset,
+ ctrl => ALU_ctrl,
+ OP1 => ALU_sample_in,
+ OP2 => ALU_coef_in,
+ RES => ALU_out
+);
+
+
+
+
+
+
+WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
+Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
+WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
+count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
+SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
+--Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
+Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
+
+GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
+
+
+
+
+
+
+
+process(clk,reset)
+variable result : std_logic_vector(Sample_SZ-1 downto 0);
+
+begin
+
+if reset = '0' then
+
+ smpl_clk_old <= '0';
+ RAM_sample_in <= (others=> '0');
+ ALU_ctrl <= IDLE;
+ ALU_sample_in <= (others=> '0');
+ ALU_Coef_in <= (others=> '0');
+ RAM_sample_in_bk<= (others=> '0');
+ curentCel <= 0;
+ curentChan <= 0;
+ IIR_CEL_STATE <= waiting;
+reset : for i in 0 to ChanelsCNT-1 loop
+ sample_in_BUFF(i) <= (others => '0');
+ sample_out_BUFF(i) <= (others => '0');
+ sample_out(i) <= (others => '0');
+ end loop;
+
+elsif clk'event and clk = '1' then
+
+ smpl_clk_old <= sample_clk;
+
+ case IIR_CEL_STATE is
+
+ when waiting =>
+ if sample_clk = '1' and smpl_clk_old = '0' then
+ IIR_CEL_STATE <= pipe1;
+ RAM_sample_in <= sample_in_BUFF(0);
+ ALU_sample_in <= sample_in_BUFF(0);
+
+ else
+ ALU_ctrl <= IDLE;
+ sample_in_BUFF <= sample_in;
+ sample_out <= sample_out_BUFF;
+
+ end if;
+ curentCel <= 0;
+ curentChan <= 0;
+
+ when pipe1 =>
+ IIR_CEL_STATE <= computeb1;
+ ALU_ctrl <= MAC_op;
+ ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(0));
+
+ when computeb1 =>
+
+ ALU_ctrl <= MAC_op;
+ ALU_sample_in <= RAM_sample_out;
+ ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(1));
+ IIR_CEL_STATE <= computeb2;
+ RAM_sample_in <= RAM_sample_in_bk;
+ when computeb2 =>
+ ALU_sample_in <= RAM_sample_out;
+ ALU_Coef_in <= std_logic_vector(coefs.NumCoefs(curentCel)(2));
+ IIR_CEL_STATE <= computea1;
+
+
+ when computea1 =>
+ ALU_sample_in <= RAM_sample_out;
+ ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(1));
+ IIR_CEL_STATE <= computea2;
+
+
+ when computea2 =>
+ ALU_sample_in <= RAM_sample_out;
+ ALU_Coef_in <= std_logic_vector(coefs.DenCoefs(curentCel)(2));
+ IIR_CEL_STATE <= next_cel;
+
+
+ when next_cel =>
+ ALU_ctrl <= clr_mac;
+ IIR_CEL_STATE <= pipe2;
+
+ when pipe2 =>
+ IIR_CEL_STATE <= pipe3;
+
+
+ when pipe3 =>
+
+ result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
+
+ sample_out_BUFF(0) <= result;
+ RAM_sample_in_bk <= result;
+ RAM_sample_in <= result;
+ if curentCel = Cels_count-1 then
+ IIR_CEL_STATE <= next_chan;
+ curentCel <= 0;
+ else
+ curentCel <= curentCel + 1;
+ IIR_CEL_STATE <= pipe1;
+ ALU_sample_in <= result;
+ end if;
+ when next_chan =>
+
+rotate : for i in 0 to ChanelsCNT-2 loop
+ sample_in_BUFF(i) <= sample_in_BUFF(i+1);
+ sample_out_BUFF(i) <= sample_out_BUFF(i+1);
+ end loop;
+ sample_in_BUFF(ChanelsCNT-1) <= sample_in_BUFF(0);
+ sample_out_BUFF(ChanelsCNT-1)<= sample_out_BUFF(0);
+
+ if curentChan = (ChanelsCNT-1) then
+ IIR_CEL_STATE <= waiting;
+ ALU_ctrl <= clr_mac;
+ else
+ curentChan <= curentChan + 1;
+ IIR_CEL_STATE <= pipe1;
+ ALU_sample_in <= sample_in_BUFF(1);
+ RAM_sample_in <= sample_in_BUFF(1);
+ end if;
+ end case;
+
+end if;
+end process;
+
+
+
+
+
+
+end ar_IIR_CEL_CTRLR;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd
@@ -0,0 +1,90 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- IIR_CEL_FILTER.vhd
+
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+
+--TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre
+
+entity IIR_CEL_FILTER is
+generic(Sample_SZ : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ regs_in : in in_IIR_CEL_reg;
+ regs_out : in out_IIR_CEL_reg;
+ sample_in : in samplT;
+ sample_out : out samplT
+
+);
+end IIR_CEL_FILTER;
+
+
+
+
+architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
+
+signal virg_pos : integer;
+begin
+
+virg_pos <= to_integer(unsigned(regs_in.virgPos));
+
+
+CTRLR : IIR_CEL_CTRLR
+generic map (Sample_SZ => Sample_SZ)
+port map(
+ reset => reset,
+ clk => clk,
+ sample_clk => sample_clk,
+ sample_in => sample_in,
+ sample_out => sample_out,
+ virg_pos => virg_pos,
+ coefs => regs_in.coefsTB
+);
+
+
+
+
+
+end ar_IIR_CEL_FILTER;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/RAM.vhd b/lib/lpp/dsp/iir_filter/RAM.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/RAM.vhd
@@ -0,0 +1,62 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- RAM.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity RAM is
+ port( WD : in std_logic_vector(35 downto 0); RD : out
+ std_logic_vector(35 downto 0);WEN, REN : in std_logic;
+ WADDR : in std_logic_vector(7 downto 0); RADDR : in
+ std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
+ ) ;
+end RAM;
+
+
+architecture DEF_ARCH of RAM is
+type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
+signal RAMarray : RAMarrayT:=(others => X"000000000");
+signal RD_int : std_logic_vector(35 downto 0);
+
+begin
+
+RD_int <= RAMarray(to_integer(unsigned(RADDR)));
+
+
+process(RWclk,reset)
+begin
+if reset = '0' then
+ RD <= (X"000000000");
+rst:for i in 0 to 255 loop
+ RAMarray(i) <= (others => '0');
+ end loop;
+
+elsif RWclk'event and RWclk = '1' then
+ if REN = '0' then
+ RD <= RD_int;
+ end if;
+
+ if WEN = '0' then
+ RAMarray(to_integer(unsigned(WADDR))) <= WD;
+ end if;
+
+end if;
+end process;
+end DEF_ARCH;
diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
@@ -0,0 +1,91 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- RAM_CEL.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity RAM_CEL is
+ port( WD : in std_logic_vector(35 downto 0); RD : out
+ std_logic_vector(35 downto 0);WEN, REN : in std_logic;
+ WADDR : in std_logic_vector(7 downto 0); RADDR : in
+ std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
+ ) ;
+end RAM_CEL;
+
+
+
+architecture ar_RAM_CEL of RAM_CEL is
+type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
+signal RAMarray : RAMarrayT:=(others => X"000000000");
+signal RD_int : std_logic_vector(35 downto 0);
+
+begin
+
+RD_int <= RAMarray(to_integer(unsigned(RADDR)));
+
+
+process(RWclk,reset)
+begin
+if reset = '0' then
+ RD <= (X"000000000");
+rst:for i in 0 to 255 loop
+ RAMarray(i) <= (others => '0');
+ end loop;
+
+elsif RWclk'event and RWclk = '1' then
+ if REN = '0' then
+ RD <= RD_int;
+ end if;
+
+ if WEN = '0' then
+ RAMarray(to_integer(unsigned(WADDR))) <= WD;
+ end if;
+
+end if;
+end process;
+end ar_RAM_CEL;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
@@ -0,0 +1,210 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- RAM_CTRLR2.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.FILTERcfg.all;
+use lpp.general_purpose.all;
+
+--TODO am�liorer la flexibilit� de la config de la RAM.
+
+entity RAM_CTRLR2 is
+generic(
+ Input_SZ_1 : integer := 16
+);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ WD_sel : in std_logic;
+ Read : in std_logic;
+ WADDR_sel : in std_logic;
+ count : in std_logic;
+ SVG_ADDR : in std_logic;
+ Write : in std_logic;
+ GO_0 : in std_logic;
+ sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
+ sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
+);
+end RAM_CTRLR2;
+
+
+architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
+
+signal WD : std_logic_vector(35 downto 0);
+signal WD_D : std_logic_vector(35 downto 0);
+signal RD : std_logic_vector(35 downto 0);
+signal WEN, REN : std_logic;
+signal WADDR_back : std_logic_vector(7 downto 0);
+signal WADDR_back_D: std_logic_vector(7 downto 0);
+signal RADDR : std_logic_vector(7 downto 0);
+signal WADDR : std_logic_vector(7 downto 0);
+signal WADDR_D : std_logic_vector(7 downto 0);
+
+
+
+begin
+
+sample_out <= RD(Smpl_SZ-1 downto 0);
+
+
+WEN <= not Write;
+REN <= not read;
+
+
+--==============================================================
+--=========================R A M================================
+--==============================================================
+memRAM : if Mem_use = use_RAM generate
+RAMblk :RAM
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN,
+ REN => REN,
+ WADDR => WADDR,
+ RADDR => RADDR,
+ RWCLK => clk,
+ RESET => reset
+ ) ;
+end generate;
+
+memCEL : if Mem_use = use_CEL generate
+RAMblk :RAM_CEL
+ port map(
+ WD => WD_D,
+ RD => RD,
+ WEN => WEN,
+ REN => REN,
+ WADDR => WADDR,
+ RADDR => RADDR,
+ RWCLK => clk,
+ RESET => reset
+ ) ;
+end generate;
+--==============================================================
+--==============================================================
+
+
+ADDRcntr_inst : ADDRcntr
+port map(
+ clk => clk,
+ reset => reset,
+ count => count,
+ clr => GO_0,
+ Q => RADDR
+);
+
+
+
+MUX2_inst1 :MUX2
+generic map(Input_SZ => Smpl_SZ)
+port map(
+ sel => WD_sel,
+ IN1 => sample_in,
+ IN2 => RD(Smpl_SZ-1 downto 0),
+ RES => WD(Smpl_SZ-1 downto 0)
+);
+
+
+MUX2_inst2 :MUX2
+generic map(Input_SZ => 8)
+port map(
+ sel => WADDR_sel,
+ IN1 => WADDR_D,
+ IN2 => WADDR_back_D,
+ RES => WADDR
+);
+
+
+
+
+WADDR_backreg :REG
+generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
+port map(
+ reset => reset,
+ clk => SVG_ADDR,
+ D => RADDR,
+ Q => WADDR_back
+);
+
+WADDR_backreg2 :REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => SVG_ADDR,
+ D => WADDR_back,
+ Q => WADDR_back_D
+);
+
+WDRreg :REG
+generic map(size => Smpl_SZ)
+port map(
+ reset => reset,
+ clk => clk,
+ D => WD(Smpl_SZ-1 downto 0),
+ Q => WD_D(Smpl_SZ-1 downto 0)
+);
+
+
+
+
+ADDRreg :REG
+generic map(size => 8)
+port map(
+ reset => reset,
+ clk => clk,
+ D => RADDR,
+ Q => WADDR_D
+);
+
+
+
+end ar_RAM_CTRLR2;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd b/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd
@@ -0,0 +1,114 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- TestbenshMAC.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+
+
+entity TestbenshMAC is
+end TestbenshMAC;
+
+
+
+
+architecture ar_TestbenshMAC of TestbenshMAC is
+
+
+
+constant OP1sz : integer := 16;
+constant OP2sz : integer := 12;
+--IDLE =00 MAC =01 MULT =10 ADD =11
+constant IDLE : std_logic_vector(1 downto 0) := "00";
+constant MAC : std_logic_vector(1 downto 0) := "01";
+constant MULT : std_logic_vector(1 downto 0) := "10";
+constant ADD : std_logic_vector(1 downto 0) := "11";
+
+signal clk : std_logic:='0';
+signal reset : std_logic:='0';
+signal clrMAC : std_logic:='0';
+signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE;
+signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
+signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
+signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
+
+
+
+
+begin
+
+
+MAC1 : entity LPP_IIR_FILTER.MAC
+generic map(
+ Input_SZ_A => OP1sz,
+ Input_SZ_B => OP2sz
+
+)
+port map(
+ clk => clk,
+ reset => reset,
+ clr_MAC => clrMAC,
+ MAC_MUL_ADD => MAC_MUL_ADD,
+ OP1 => Operand1,
+ OP2 => Operand2,
+ RES => Resultat
+);
+
+clk <= not clk after 25 ns;
+
+process
+begin
+wait for 40 ns;
+reset <= '1';
+wait for 11 ns;
+Operand1 <= X"0001";
+Operand2 <= X"001";
+MAC_MUL_ADD <= ADD;
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"100";
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"001";
+MAC_MUL_ADD <= MULT;
+wait for 50 ns;
+Operand1 <= X"0002";
+Operand2 <= X"002";
+wait for 50 ns;
+clrMAC <= '1';
+wait for 50 ns;
+clrMAC <= '0';
+Operand1 <= X"0001";
+Operand2 <= X"003";
+MAC_MUL_ADD <= MAC;
+wait;
+end process;
+end ar_TestbenshMAC;
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd b/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd
@@ -0,0 +1,19 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- Top_Filtre_IIR.vhd
\ No newline at end of file
diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd
@@ -0,0 +1,161 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library lpp;
+use lpp.FILTERcfg.all;
+
+
+
+package iir_filter is
+
+component APB_IIR_CEL is
+ generic (
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ pirq : integer := 0;
+ abits : integer := 8;
+ Sample_SZ : integer := Smpl_SZ
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ sample_clk : in std_logic;
+ sample_clk_out : out std_logic;
+ sample_in : in samplT;
+ sample_out : out samplT
+ );
+end component;
+
+
+component FILTER is
+port(
+
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
+ Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
+);
+end component;
+
+
+
+component FilterCTRLR is
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ ALU_Ctrl : out std_logic_vector(3 downto 0);
+ sample_in : in samplT;
+ coef : out std_logic_vector(Coef_SZ-1 downto 0);
+ sample : out std_logic_vector(Smpl_SZ-1 downto 0)
+);
+end component;
+
+
+component FILTER_RAM_CTRLR is
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ run : in std_logic;
+ GO_0 : in std_logic;
+ B_A : in std_logic;
+ writeForce : in std_logic;
+ next_blk : in std_logic;
+ sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
+ sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
+);
+end component;
+
+
+component IIR_CEL_CTRLR is
+generic(Sample_SZ : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ sample_in : in samplT;
+ sample_out : out samplT;
+ virg_pos : in integer;
+ coefs : in coefs_celsT
+);
+end component;
+
+
+component RAM is
+ port( WD : in std_logic_vector(35 downto 0); RD : out
+ std_logic_vector(35 downto 0);WEN, REN : in std_logic;
+ WADDR : in std_logic_vector(7 downto 0); RADDR : in
+ std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
+ ) ;
+end component;
+
+
+component RAM_CEL is
+ port( WD : in std_logic_vector(35 downto 0); RD : out
+ std_logic_vector(35 downto 0);WEN, REN : in std_logic;
+ WADDR : in std_logic_vector(7 downto 0); RADDR : in
+ std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
+ ) ;
+end component;
+
+component IIR_CEL_FILTER is
+generic(Sample_SZ : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ sample_clk : in std_logic;
+ regs_in : in in_IIR_CEL_reg;
+ regs_out : in out_IIR_CEL_reg;
+ sample_in : in samplT;
+ sample_out : out samplT
+
+);
+end component;
+
+
+component RAM_CTRLR2 is
+generic(
+ Input_SZ_1 : integer := 16
+);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ WD_sel : in std_logic;
+ Read : in std_logic;
+ WADDR_sel : in std_logic;
+ count : in std_logic;
+ SVG_ADDR : in std_logic;
+ Write : in std_logic;
+ GO_0 : in std_logic;
+ sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
+ sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
+);
+end component;
+
+
+end;
diff --git a/lib/lpp/dsp/iir_filter/temp.sh b/lib/lpp/dsp/iir_filter/temp.sh
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/temp.sh
@@ -0,0 +1,1 @@
+ls|grep .vhd|grep -i -v test>vhdlsyn.txt
diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt
@@ -0,0 +1,12 @@
+APB_IIR_CEL.vhd
+FILTERcfg.vhd
+FilterCTRLR.vhd
+FILTER_RAM_CTRLR.vhd
+FILTER.vhd
+IIR_CEL_CTRLR.vhd
+IIR_CEL_FILTER.vhd
+iir_filter.vhd
+RAM_CEL.vhd
+RAM_CTRLR2.vhd
+RAM.vhd
+Top_Filtre_IIR.vhd
diff --git a/lib/lpp/general_purpose/ADDRcntr.vhd b/lib/lpp/general_purpose/ADDRcntr.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/ADDRcntr.vhd
@@ -0,0 +1,62 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- ADDRcntr.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity ADDRcntr is
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ count : in std_logic;
+ clr : in std_logic;
+ Q : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_ADDRcntr of ADDRcntr is
+
+signal reg : std_logic_vector(7 downto 0);
+
+begin
+
+Q <= REG;
+
+process(clk,reset)
+begin
+if reset = '0' then
+ REG <= (others => '0');
+elsif clk'event and clk ='1' then
+ if clr = '1' then
+ REG <= (others => '0');
+ elsif count ='1' then
+ REG <= std_logic_vector(unsigned(REG)+1);
+ end if;
+end if;
+end process;
+
+end ar_ADDRcntr;
diff --git a/lib/lpp/general_purpose/ALU.vhd b/lib/lpp/general_purpose/ALU.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/ALU.vhd
@@ -0,0 +1,101 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- ALU.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+--IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
+--NOT =0101 AND =0110 OR =0111 XOR =1000
+--SHIFTleft =1001 SHIFTright =1010
+
+entity ALU is
+generic(
+ Arith_en : integer := 1;
+ Logic_en : integer := 1;
+ Input_SZ_1 : integer := 16;
+ Input_SZ_2 : integer := 9
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ ctrl : in std_logic_vector(3 downto 0);
+ OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
+);
+end entity;
+
+
+
+architecture ar_ALU of ALU is
+
+
+
+signal clr_MAC : std_logic:='1';
+
+
+begin
+
+clr_MAC <= '1' when ctrl = "0100" else '0';
+
+
+arith : if Arith_en = 1 generate
+
+
+MACinst : MAC
+generic map(
+ Input_SZ_A => Input_SZ_1,
+ Input_SZ_B => Input_SZ_2
+
+)
+port map(
+ clk => clk,
+ reset => reset,
+ clr_MAC => clr_MAC,
+ MAC_MUL_ADD => ctrl(1 downto 0),
+ OP1 => OP1,
+ OP2 => OP2,
+ RES => RES
+);
+
+end generate;
+
+process(clk,reset)
+begin
+if reset = '0' then
+elsif clk'event and clk ='1' then
+
+end if;
+end process;
+end architecture;
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/general_purpose/Adder.vhd b/lib/lpp/general_purpose/Adder.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/Adder.vhd
@@ -0,0 +1,70 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- Adder.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity Adder is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ clr : in std_logic;
+ add : in std_logic;
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_Adder of Adder is
+
+signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
+signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
+
+begin
+
+RES <= REG;
+RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
+
+process(clk,reset)
+begin
+if reset = '0' then
+ REG <= (others => '0');
+elsif clk'event and clk ='1' then
+ if clr = '1' then
+ REG <= (others => '0');
+ elsif add = '1' then
+ REG <= RESADD;
+ end if;
+end if;
+end process;
+end ar_Adder;
diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC.vhd
@@ -0,0 +1,276 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MAC.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+--TODO
+--terminer le testbensh puis changer le resize dans les instanciations
+--par un resize sur un vecteur en combi
+
+
+
+
+
+entity MAC is
+generic(
+ Input_SZ_A : integer := 8;
+ Input_SZ_B : integer := 8
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ clr_MAC : in std_logic;
+ MAC_MUL_ADD : in std_logic_vector(1 downto 0);
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end MAC;
+
+
+
+
+architecture ar_MAC of MAC is
+
+
+
+
+
+signal add,mult : std_logic;
+signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+
+signal MACMUXsel : std_logic;
+signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+
+
+signal MACMUX2sel : std_logic;
+
+signal add_D : std_logic;
+signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
+signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
+signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal MACMUXsel_D : std_logic;
+signal MACMUX2sel_D : std_logic;
+signal MACMUX2sel_D_D : std_logic;
+signal clr_MAC_D : std_logic;
+signal clr_MAC_D_D : std_logic;
+
+
+
+
+
+begin
+
+
+
+
+--==============================================================
+--=============M A C C O N T R O L E R=========================
+--==============================================================
+MAC_CONTROLER1 : MAC_CONTROLER
+port map(
+ ctrl => MAC_MUL_ADD,
+ MULT => mult,
+ ADD => add,
+ MACMUX_sel => MACMUXsel,
+ MACMUX2_sel => MACMUX2sel
+
+);
+--==============================================================
+
+
+
+
+--==============================================================
+--=============M U L T I P L I E R==============================
+--==============================================================
+Multiplieri_nst : Multiplier
+generic map(
+ Input_SZ_A => Input_SZ_A,
+ Input_SZ_B => Input_SZ_B
+)
+port map(
+ clk => clk,
+ reset => reset,
+ mult => mult,
+ OP1 => OP1,
+ OP2 => OP2,
+ RES => MULTout
+);
+
+--==============================================================
+
+
+
+
+--==============================================================
+--======================A D D E R ==============================
+--==============================================================
+adder_inst : Adder
+generic map(
+ Input_SZ_A => Input_SZ_A+Input_SZ_B,
+ Input_SZ_B => Input_SZ_A+Input_SZ_B
+)
+port map(
+ clk => clk,
+ reset => reset,
+ clr => clr_MAC_D,
+ add => add_D,
+ OP1 => ADDERinA,
+ OP2 => ADDERinB,
+ RES => ADDERout
+);
+
+--==============================================================
+
+
+clr_MACREG1 : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => clr_MAC,
+ Q(0) => clr_MAC_D
+);
+
+clr_MACREG2 : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => clr_MAC_D,
+ Q(0) => clr_MAC_D_D
+);
+
+addREG : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => add,
+ Q(0) => add_D
+);
+
+OP1REG : MAC_REG
+generic map(size => Input_SZ_A)
+port map(
+ reset => reset,
+ clk => clk,
+ D => OP1,
+ Q => OP1_D
+);
+
+
+OP2REG : MAC_REG
+generic map(size => Input_SZ_B)
+port map(
+ reset => reset,
+ clk => clk,
+ D => OP2,
+ Q => OP2_D
+);
+
+
+MULToutREG : MAC_REG
+generic map(size => Input_SZ_A+Input_SZ_B)
+port map(
+ reset => reset,
+ clk => clk,
+ D => MULTout,
+ Q => MULTout_D
+);
+
+
+MACMUXselREG : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => MACMUXsel,
+ Q(0) => MACMUXsel_D
+);
+
+MACMUX2selREG : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => MACMUX2sel,
+ Q(0) => MACMUX2sel_D
+);
+
+MACMUX2selREG2 : MAC_REG
+generic map(size => 1)
+port map(
+ reset => reset,
+ clk => clk,
+ D(0) => MACMUX2sel_D,
+ Q(0) => MACMUX2sel_D_D
+);
+
+--==============================================================
+--======================M A C M U X ===========================
+--==============================================================
+MACMUX_inst : MAC_MUX
+generic map(
+ Input_SZ_A => Input_SZ_A+Input_SZ_B,
+ Input_SZ_B => Input_SZ_A+Input_SZ_B
+
+)
+port map(
+ sel => MACMUXsel_D,
+ INA1 => ADDERout,
+ INA2 => OP2_D_Resz,
+ INB1 => MULTout,
+ INB2 => OP1_D_Resz,
+ OUTA => ADDERinA,
+ OUTB => ADDERinB
+);
+OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
+OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
+--==============================================================
+
+
+--==============================================================
+--======================M A C M U X2 ==========================
+--==============================================================
+MAC_MUX2_inst : MAC_MUX2
+generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
+port map(
+ sel => MACMUX2sel_D_D,
+ RES2 => MULTout_D,
+ RES1 => ADDERout,
+ RES => RES
+);
+
+
+--==============================================================
+
+end ar_MAC;
diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd
@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MAC_CONTROLER.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+--IDLE =00 MAC =01 MULT =10 ADD =11
+
+
+entity MAC_CONTROLER is
+port(
+ ctrl : in std_logic_vector(1 downto 0);
+ MULT : out std_logic;
+ ADD : out std_logic;
+ MACMUX_sel : out std_logic;
+ MACMUX2_sel : out std_logic
+
+);
+end MAC_CONTROLER;
+
+
+
+
+
+architecture ar_MAC_CONTROLER of MAC_CONTROLER is
+
+begin
+
+
+
+MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
+ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
+MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
+MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1';
+
+
+end ar_MAC_CONTROLER;
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/general_purpose/MAC_MUX.vhd b/lib/lpp/general_purpose/MAC_MUX.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC_MUX.vhd
@@ -0,0 +1,55 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MAC_MUX.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity MAC_MUX is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ sel : in std_logic;
+ INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
+ OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_MAC_MUX of MAC_MUX is
+
+begin
+
+OUTA <= INA1 when sel = '0' else INA2;
+OUTB <= INB1 when sel = '0' else INB2;
+
+end ar_MAC_MUX;
diff --git a/lib/lpp/general_purpose/MAC_MUX2.vhd b/lib/lpp/general_purpose/MAC_MUX2.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC_MUX2.vhd
@@ -0,0 +1,47 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MAC_MUX2.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity MAC_MUX2 is
+generic(Input_SZ : integer := 16);
+port(
+ sel : in std_logic;
+ RES1 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES2 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_MAC_MUX2 of MAC_MUX2 is
+
+begin
+
+RES <= RES1 when sel = '0' else RES2;
+
+end ar_MAC_MUX2;
diff --git a/lib/lpp/general_purpose/MAC_REG.vhd b/lib/lpp/general_purpose/MAC_REG.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MAC_REG.vhd
@@ -0,0 +1,60 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MAC_REG.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity MAC_REG is
+generic(size : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ D : in std_logic_vector(size-1 downto 0);
+ Q : out std_logic_vector(size-1 downto 0)
+);
+end entity;
+
+
+
+architecture ar_MAC_REG of MAC_REG is
+begin
+process(clk,reset)
+begin
+if reset = '0' then
+ Q <= (others => '0');
+elsif clk'event and clk ='1' then
+ Q <= D;
+end if;
+end process;
+end ar_MAC_REG;
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/general_purpose/MUX2.vhd b/lib/lpp/general_purpose/MUX2.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/MUX2.vhd
@@ -0,0 +1,47 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- MUX2.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity MUX2 is
+generic(Input_SZ : integer := 16);
+port(
+ sel : in std_logic;
+ IN1 : in std_logic_vector(Input_SZ-1 downto 0);
+ IN2 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_MUX2 of MUX2 is
+
+begin
+
+RES <= IN1 when sel = '0' else IN2;
+
+end ar_MUX2;
diff --git a/lib/lpp/general_purpose/Multiplier.vhd b/lib/lpp/general_purpose/Multiplier.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/Multiplier.vhd
@@ -0,0 +1,78 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- Multiplier.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity Multiplier is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ mult : in std_logic;
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end Multiplier;
+
+
+
+
+
+architecture ar_Multiplier of Multiplier is
+
+signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
+
+
+begin
+
+RES <= REG;
+RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
+process(clk,reset)
+begin
+if reset = '0' then
+ REG <= (others => '0');
+elsif clk'event and clk ='1' then
+ if mult = '1' then
+ REG <= RESMULT;
+ end if;
+end if;
+end process;
+
+end ar_Multiplier;
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/general_purpose/REG.vhd b/lib/lpp/general_purpose/REG.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/REG.vhd
@@ -0,0 +1,48 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- REG.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+entity REG is
+generic(size : integer := 16 ; initial_VALUE : integer := 0);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ D : in std_logic_vector(size-1 downto 0);
+ Q : out std_logic_vector(size-1 downto 0)
+);
+end entity;
+
+
+
+architecture ar_REG of REG is
+begin
+process(clk,reset)
+begin
+if reset = '0' then
+ Q <= std_logic_vector(to_unsigned(initial_VALUE,size));
+elsif clk'event and clk ='1' then
+ Q <= D;
+end if;
+end process;
+end ar_REG;
diff --git a/lib/lpp/general_purpose/Shifter.vhd b/lib/lpp/general_purpose/Shifter.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/Shifter.vhd
@@ -0,0 +1,66 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- Shifter.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+library lpp;
+use lpp.general_purpose.all;
+
+
+
+entity RShifter is
+generic(
+ Input_SZ : integer := 16;
+ shift_SZ : integer := 4
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ shift : in std_logic;
+ OP : in std_logic_vector(Input_SZ-1 downto 0);
+ cnt : in std_logic_vector(shift_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end entity;
+
+
+
+
+architecture ar_RShifter of RShifter is
+
+signal REG : std_logic_vector(Input_SZ-1 downto 0);
+signal RESSHIFT: std_logic_vector(Input_SZ-1 downto 0);
+
+begin
+
+RES <= REG;
+RESSHIFT <= std_logic_vector(SHIFT_RIGHT(signed(OP),to_integer(unsigned(cnt))));
+
+process(clk,reset)
+begin
+if reset = '0' then
+ REG <= (others => '0');
+elsif clk'event and clk ='1' then
+ if shift = '1' then
+ REG <= RESSHIFT;
+ end if;
+end if;
+end process;
+end ar_RShifter;
diff --git a/lib/lpp/general_purpose/TestbenshALU.vhd b/lib/lpp/general_purpose/TestbenshALU.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/TestbenshALU.vhd
@@ -0,0 +1,136 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- TestbenshALU.vhd
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+
+
+entity TestbenshALU is
+end TestbenshALU;
+
+
+
+
+architecture ar_TestbenshALU of TestbenshALU is
+
+
+
+constant OP1sz : integer := 16;
+constant OP2sz : integer := 12;
+--IDLE =00 MAC =01 MULT =10 ADD =11
+constant IDLE : std_logic_vector(3 downto 0) := "0000";
+constant MAC : std_logic_vector(3 downto 0) := "0001";
+constant MULT : std_logic_vector(3 downto 0) := "0010";
+constant ADD : std_logic_vector(3 downto 0) := "0011";
+constant clr_mac : std_logic_vector(3 downto 0) := "0100";
+
+signal clk : std_logic:='0';
+signal reset : std_logic:='0';
+signal ctrl : std_logic_vector(3 downto 0):=IDLE;
+signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0');
+signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0');
+signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0);
+
+
+
+
+begin
+
+ALU1 : entity LPP_IIR_FILTER.ALU
+generic map(
+ Arith_en => 1,
+ Logic_en => 0,
+ Input_SZ_1 => OP1sz,
+ Input_SZ_2 => OP2sz
+
+)
+port map(
+ clk => clk,
+ reset => reset,
+ ctrl => ctrl,
+ OP1 => Operand1,
+ OP2 => Operand2,
+ RES => Resultat
+);
+
+
+
+
+clk <= not clk after 25 ns;
+
+process
+begin
+wait for 40 ns;
+reset <= '1';
+wait for 11 ns;
+Operand1 <= X"0001";
+Operand2 <= X"001";
+ctrl <= ADD;
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"100";
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"001";
+ctrl <= MULT;
+wait for 50 ns;
+Operand1 <= X"0002";
+Operand2 <= X"002";
+wait for 50 ns;
+ctrl <= clr_mac;
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"003";
+ctrl <= MAC;
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"001";
+wait for 50 ns;
+Operand1 <= X"0011";
+Operand2 <= X"003";
+wait for 50 ns;
+Operand1 <= X"1001";
+Operand2 <= X"003";
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"000";
+wait for 50 ns;
+Operand1 <= X"0001";
+Operand2 <= X"003";
+wait for 50 ns;
+Operand1 <= X"0101";
+Operand2 <= X"053";
+wait for 50 ns;
+ctrl <= clr_mac;
+wait;
+end process;
+end ar_TestbenshALU;
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/general_purpose.vhd
@@ -0,0 +1,195 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package general_purpose is
+
+component Adder is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ clr : in std_logic;
+ add : in std_logic;
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A-1 downto 0)
+);
+end component;
+
+component ADDRcntr is
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ count : in std_logic;
+ clr : in std_logic;
+ Q : out std_logic_vector(7 downto 0)
+);
+end component;
+
+component ALU is
+generic(
+ Arith_en : integer := 1;
+ Logic_en : integer := 1;
+ Input_SZ_1 : integer := 16;
+ Input_SZ_2 : integer := 9
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ ctrl : in std_logic_vector(3 downto 0);
+ OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
+);
+end component;
+
+
+component MAC is
+generic(
+ Input_SZ_A : integer := 8;
+ Input_SZ_B : integer := 8
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ clr_MAC : in std_logic;
+ MAC_MUL_ADD : in std_logic_vector(1 downto 0);
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end component;
+
+
+component MAC_CONTROLER is
+port(
+ ctrl : in std_logic_vector(1 downto 0);
+ MULT : out std_logic;
+ ADD : out std_logic;
+ MACMUX_sel : out std_logic;
+ MACMUX2_sel : out std_logic
+
+);
+end component;
+
+component MAC_MUX is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ sel : in std_logic;
+ INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
+ OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
+);
+end component;
+
+
+component MAC_MUX2 is
+generic(Input_SZ : integer := 16);
+port(
+ sel : in std_logic;
+ RES1 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES2 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end component;
+
+
+component MAC_REG is
+generic(size : integer := 16);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ D : in std_logic_vector(size-1 downto 0);
+ Q : out std_logic_vector(size-1 downto 0)
+);
+end component;
+
+
+component MUX2 is
+generic(Input_SZ : integer := 16);
+port(
+ sel : in std_logic;
+ IN1 : in std_logic_vector(Input_SZ-1 downto 0);
+ IN2 : in std_logic_vector(Input_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end component;
+
+component Multiplier is
+generic(
+ Input_SZ_A : integer := 16;
+ Input_SZ_B : integer := 16
+
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ mult : in std_logic;
+ OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
+ OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
+ RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
+);
+end component;
+
+component REG is
+generic(size : integer := 16 ; initial_VALUE : integer := 0);
+port(
+ reset : in std_logic;
+ clk : in std_logic;
+ D : in std_logic_vector(size-1 downto 0);
+ Q : out std_logic_vector(size-1 downto 0)
+);
+end component;
+
+
+
+component RShifter is
+generic(
+ Input_SZ : integer := 16;
+ shift_SZ : integer := 4
+);
+port(
+ clk : in std_logic;
+ reset : in std_logic;
+ shift : in std_logic;
+ OP : in std_logic_vector(Input_SZ-1 downto 0);
+ cnt : in std_logic_vector(shift_SZ-1 downto 0);
+ RES : out std_logic_vector(Input_SZ-1 downto 0)
+);
+end component;
+
+end;
diff --git a/lib/lpp/general_purpose/temp.sh b/lib/lpp/general_purpose/temp.sh
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/temp.sh
@@ -0,0 +1,1 @@
+ls|grep .vhd|grep -i -v test>vhdlsyn.txt
diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/vhdlsyn.txt
@@ -0,0 +1,13 @@
+Adder.vhd
+ADDRcntr.vhd
+ALU.vhd
+general_purpose.vhd
+MAC_CONTROLER.vhd
+MAC_MUX2.vhd
+MAC_MUX.vhd
+MAC_REG.vhd
+MAC.vhd
+Multiplier.vhd
+MUX2.vhd
+REG.vhd
+Shifter.vhd
diff --git a/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd b/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd
@@ -0,0 +1,129 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+-- APB_SIMPLE_DIODE.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library lpp;
+use lpp.lpp_amba.all;
+
+
+entity APB_SIMPLE_DIODE is
+ generic (
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ pirq : integer := 0;
+ abits : integer := 8);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ LED : out std_ulogic
+ );
+end;
+
+
+architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
+
+constant REVISION : integer := 1;
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg (VENDOR_LPP, ROCKET_TM, 0, REVISION, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+
+
+type LEDregs is record
+ DATAin : std_logic_vector(31 downto 0);
+ DATAout : std_logic_vector(31 downto 0);
+end record;
+
+signal r : LEDregs;
+
+
+begin
+
+r.DATAout <= r.DATAin xor X"FFFFFFFF";
+
+process(rst,clk)
+begin
+ if rst = '0' then
+ LED <= '0';
+ r.DATAin <= (others => '0');
+ apbo.prdata <= (others => '0');
+ elsif clk'event and clk = '1' then
+
+ LED <= r.DATAin(0);
+
+--APB Write OP
+ if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
+ case apbi.paddr(abits-1 downto 2) is
+ when "000000" =>
+ r.DATAin <= apbi.pwdata;
+ when others =>
+ null;
+ end case;
+ end if;
+
+--APB READ OP
+ if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+ case apbi.paddr(abits-1 downto 2) is
+ when "000000" =>
+ apbo.prdata <= r.DATAin;
+ when others =>
+ apbo.prdata <= r.DATAout;
+ end case;
+ end if;
+
+ end if;
+ apbo.pconfig <= pconfig;
+end process;
+
+
+
+-- pragma translate_off
+ bootmsg : report_version
+ generic map ("apbuart" & tost(pindex) &
+ ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
+ ", irq " & tost(pirq));
+-- pragma translate_on
+
+
+
+end ar_APB_SIMPLE_DIODE;
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_amba/lpp_amba.vhd
@@ -0,0 +1,59 @@
+------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+-- pragma translate_off
+use std.textio.all;
+-- pragma translate_on
+
+
+
+
+
+package lpp_amba is
+
+constant VENDOR_LPP : amba_vendor_type := 16#19#;
+
+-- LPP device ids
+
+constant ROCKET_TM : amba_device_type := 16#001#;
+constant otherCore : amba_device_type := 16#002#;
+
+
+component APB_SIMPLE_DIODE is
+ generic (
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ pirq : integer := 0;
+ abits : integer := 8);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ LED : out std_ulogic
+ );
+end component;
+
+
+end;
diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_amba/vhdlsyn.txt
@@ -0,0 +1,2 @@
+APB_SIMPLE_DIODE.vhd
+lpp_amba.vhd
diff --git a/lib/lpp/makeDirs.sh b/lib/lpp/makeDirs.sh
new file mode 100644
--- /dev/null
+++ b/lib/lpp/makeDirs.sh
@@ -0,0 +1,50 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP VHDL lib makeDirs "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+
+
+LPP_PATCHPATH=`pwd -L`
+
+cd $LPP_PATCHPATH/lib/lpp
+
+
+#find . -type d|grep ./>$LPP_PATCHPATH/lib/lpp/dirs.txt
+
+rm $LPP_PATCHPATH/lib/lpp/dirs.txt
+
+for folders in $(find . -type d|grep ./)
+ do
+ echo "enter folder : $folders"
+ files=$(ls $folders|grep .vhd)
+ if(ls $folders|grep .vhd|grep -i -v .html|grep -i -v .tex); then
+ echo "found $files"
+ echo $folders>>$LPP_PATCHPATH/lib/lpp/dirs.txt
+ fi
+ done
+
+
+cd $LPP_PATCHPATH
diff --git a/lib/lpp/vhdlsynPatcher.sh b/lib/lpp/vhdlsynPatcher.sh
new file mode 100644
--- /dev/null
+++ b/lib/lpp/vhdlsynPatcher.sh
@@ -0,0 +1,61 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP vhdlsyn PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+# Absolute path to this script. /home/user/bin/foo.sh
+#SCRIPT=$(readlink -f $0)
+# Absolute path this script is in. /home/user/bin
+
+#LPP_PATCHPATH=`dirname $SCRIPT`
+LPP_PATCHPATH=`pwd -L`
+
+cd $LPP_PATCHPATH/lib/lpp
+
+echo `pwd -L`
+
+case $1 in
+ -h | --help | --h | -help)
+ echo 'Help:
+ This script add all non testbensh VHDL files in vhdlsyn.txt file of each folder.'
+ ;;
+ * )
+ for folders in $(find . -type d|grep ./)
+ do
+ echo "enter folder : $folders"
+ files=$(ls $folders | grep .vhd | grep -i -v "test")
+ echo "found $files"
+ rm $folders/vhdlsyn.txt
+ for file in $files
+ do
+ echo $file>>$folders/vhdlsyn.txt
+ done
+ done
+ ;;
+
+esac
+
+cd $LPP_PATCHPATH
+
diff --git a/lib/patchlibs.sh b/lib/patchlibs.sh
new file mode 100644
--- /dev/null
+++ b/lib/patchlibs.sh
@@ -0,0 +1,64 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP's GRLIB IPs PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '----------------------------------------------------------------------------------------
+ This file is a part of the LPP VHDL IP LIBRARY
+ Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+----------------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+
+LPP_LIBPATH=`pwd -L`
+
+echo "Patching Grlib..."
+echo
+echo
+
+#COPY
+echo "Remove old lib Files..."
+rm -R -v $1/lib/lpp
+echo "Copy lib Files..."
+cp -R -v $LPP_LIBPATH/lib $1
+echo
+echo
+echo
+
+
+#PATCH libs.txt
+echo "Patch $1/lib/libs.txt..."
+if(grep -q lpp $1/lib/libs.txt); then
+ echo "No need to Patch $1/lib/libs.txt..."
+else
+ echo lpp>>$1/lib/libs.txt
+fi
+
+echo
+echo
+echo
+
+#CLEAN
+echo "CLEANING .."
+rm -v $1/lib/*.sh
+rm -v $1/lib/GPL_HEADER
+echo
+echo
+echo
+
diff --git a/patch.sh b/patch.sh
new file mode 100644
--- /dev/null
+++ b/patch.sh
@@ -0,0 +1,89 @@
+echo "======================================================================================="
+echo "---------------------------------------------------------------------------------------"
+echo " LPP's GRLIB GLOBAL PATCHER "
+echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
+echo "======================================================================================="
+echo '------------------------------------------------------------------------------
+-- This file is a part of the LPP VHDL IP LIBRARY
+-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-------------------------------------------------------------------------------'
+echo
+echo
+echo
+
+# Absolute path to this script. /home/user/bin/foo.sh
+#SCRIPT=$(readlink -f $0)
+# Absolute path this script is in. /home/user/bin
+
+#LPP_PATCHPATH=`dirname $SCRIPT`
+LPP_PATCHPATH=`pwd -L`
+
+GRLIBPATH=$1
+
+
+if [ -d "$GRLIBPATH" ]; then
+ if [ -d "$GRLIBPATH/lib" ]; then
+ if [ -d "$GRLIBPATH/designs" ]; then
+ if [ -d "$GRLIBPATH/boards" ]; then
+ #PATCH /lib
+ echo "patch /lib"
+ echo
+
+ sh $LPP_PATCHPATH/lib/patchlibs.sh $GRLIBPATH
+
+ #PATCH /boards
+ echo "patch /boards"
+ echo
+ sh $LPP_PATCHPATH/boards/patchboards.sh $GRLIBPATH
+
+ #PATCH /designs
+ echo "patch /designs"
+ echo
+ sh $LPP_PATCHPATH/designs/patchdesigns.sh $GRLIBPATH
+
+ echo
+ echo
+
+ #CLEAN
+ echo "CLEANING .."
+ rm -v $1/lib/*.sh
+ rm -v $1/lib/TODO
+ rm -v $1/lib/Makefile
+ rm -v $1/lib/log.txt
+ echo
+ echo
+ echo
+ else
+ echo "I can't find GRLIB in $1"
+ fi
+
+ else
+ echo "I can't find GRLIB in $1"
+ fi
+ else
+ echo "I can't find GRLIB in $1"
+ fi
+
+else
+ echo "I can't find GRLIB in $1"
+fi
+
+
+
+
+
+