# HG changeset patch # User Alexis Jeandet # Date 2016-12-07 15:28:42 # Node ID d5eea55633d7d1adea20f6b336399a4358572867 # Parent 35f5f9f216cff6cf704f7ef67da77fd3541f3219 Deleted older LFR-EM's design diff --git a/designs/LFR-em-WFP_MS-EQM2test/LFR-em.vhd b/designs/LFR-em-WFP_MS-EQM2test/LFR-em.vhd deleted file mode 100644 --- a/designs/LFR-em-WFP_MS-EQM2test/LFR-em.vhd +++ /dev/null @@ -1,492 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY LFR_em IS - - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - TAG2 : IN STD_ULOGIC; -- UART1 rx data - TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - --------------------------------------------------------------------------- - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); - -END LFR_em; - - -ARCHITECTURE beh OF LFR_em IS - ---========================================================================== --- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board --- when enabled, chip enable polarity should be reversed and bank size also --- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 --- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 ---========================================================================== - CONSTANT USE_IAP_MEMCTRL : integer := 1; ---========================================================================== - - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - ---------------------------------------------------------------------------- - SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL nSRAM_READY : STD_LOGIC; - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); - - PROCESS(clk100MHz) - BEGIN - IF clk100MHz'EVENT AND clk100MHz = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - led(0) <= '0'; - led(1) <= '0'; - led(2) <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - led(0) <= '0'; - led(1) <= '1'; - led(2) <= '1'; - END IF; - END PROCESS; - - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 0, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 20, - USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 9, - SLOW_TIMING_EMULATION => 0 - ) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => OPEN, - ahbtxd => OPEN, - urxd1 => TAG2, - utxd1 => TAG4, - - address => address, - data => data, - nSRAM_BE0 => nSRAM_BE0, - nSRAM_BE1 => nSRAM_BE1, - nSRAM_BE2 => nSRAM_BE2, - nSRAM_BE3 => nSRAM_BE3, - nSRAM_WE => nSRAM_WE, - nSRAM_CE => nSRAM_CE_s, - nSRAM_OE => nSRAM_OE, - nSRAM_READY => nSRAM_READY, - SRAM_MBE => OPEN, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - nSRAM_READY <= '1'; - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - nSRAM_READY <= '1'; - END IF; - END PROCESS; - - IAP:if USE_IAP_MEMCTRL = 1 GENERATE - nSRAM_CE <= not nSRAM_CE_s(0); - END GENERATE; - - NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE - nSRAM_CE <= nSRAM_CE_s(0); - END GENERATE; - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => apa3e, - pindex => 6, - paddr => 6, - pmask => 16#fff#, --- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO --- clk24_576MHz => clk_24, -- 49.152MHz/2 --- resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - --- SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => use_RAM, - tech => inferred, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"010159", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - DEBUG_FORCE_DATA_DMA => 0, - RTL_DESIGN_LIGHT => 1, - WINDOWS_HAANNING_PARAM_SIZE => 10) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => OPEN, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - TAG8 <= ADC_smpclk_s; - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - -END beh; diff --git a/designs/LFR-em-WFP_MS-EQM2test/Makefile b/designs/LFR-em-WFP_MS-EQM2test/Makefile deleted file mode 100644 --- a/designs/LFR-em-WFP_MS-EQM2test/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=LFR_em -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -#VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSYNFILES=LFR-em.vhd -VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.pdc - -SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.sdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR-em_1.1.85.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft_rtax \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-em-WaveFormPicker/.config b/designs/LFR-em-WaveFormPicker/.config deleted file mode 100644 --- a/designs/LFR-em-WaveFormPicker/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/LFR-em-WaveFormPicker/LFR-em.vhd b/designs/LFR-em-WaveFormPicker/LFR-em.vhd deleted file mode 100644 --- a/designs/LFR-em-WaveFormPicker/LFR-em.vhd +++ /dev/null @@ -1,404 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY LFR_em IS - - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); - -END LFR_em; - - -ARCHITECTURE beh OF LFR_em IS - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - -- - -- UART AHB --------------------------------------------------------------- - --SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - --SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - --SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - --SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - -- - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; --- SIGNAL clkmn : STD_ULOGIC; --- SIGNAL txclk : STD_ULOGIC; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_nCS_sig : STD_LOGIC; - SIGNAL ADC_CLK_sig : STD_LOGIC; - SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); - - --SIGNAL bias_fail_sw_sig : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); - - PROCESS(clk100MHz) - BEGIN - IF clk100MHz'EVENT AND clk100MHz = '1' THEN - clk_50_s <= NOT clk_50_s; - END IF; - END PROCESS; - - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - PROCESS (clk_25, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - led(0) <= '0'; - led(1) <= '0'; - led(2) <= '0'; - ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge - led(0) <= '0'; - led(1) <= '1'; - led(2) <= '1'; - END IF; - END PROCESS; - - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) - PORT MAP ( - clk => clk_25, - reset => rstn, - errorn => errorn, - ahbrxd => ahbrxd, - ahbtxd => ahbtxd, - urxd1 => urxd1, - utxd1 => utxd1, - address => address, - data => data, - nSRAM_BE0 => nSRAM_BE0, - nSRAM_BE1 => nSRAM_BE1, - nSRAM_BE2 => nSRAM_BE2, - nSRAM_BE3 => nSRAM_BE3, - nSRAM_WE => nSRAM_WE, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_OE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - pirq => 12, - nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 - PORT MAP ( - clk25MHz => clk_25, - clk49_152MHz => clk_24, -- 49.152MHz/2 - resetn => rstn, - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - --- SPW_EN <= '1'; - - spw_clk <= clk_50_s; - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn, clk_25, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - lpp_lfr_1 : lpp_lfr_WFP_nMS - GENERIC MAP ( - Mem_use => use_RAM, - nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"010000") -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - PORT MAP ( - clk => clk_25, - rstn => rstn, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - observation_reg => observation_reg); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 40, -- TODO : 79 - ncycle_cnv => 250) -- TODO : 500 - PORT MAP ( - cnv_clk => clk_24, -- TODO : 49.152 - cnv_rstn => rstn, -- ok - cnv => ADC_smpclk, -- ok - clk => clk_25, -- ok - rstn => rstn, -- ok - ADC_data => ADC_data, -- ok - ADC_nOE => ADC_OEB_bar_CH, -- ok - sample => sample, -- ok - sample_val => sample_val); -- ok - -END beh; \ No newline at end of file diff --git a/designs/LFR-em-WaveFormPicker/Makefile b/designs/LFR-em-WaveFormPicker/Makefile deleted file mode 100644 --- a/designs/LFR-em-WaveFormPicker/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=LFR_em -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -#VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSYNFILES=LFR-em.vhd -#VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-em/.config b/designs/LFR-em/.config deleted file mode 100644 --- a/designs/LFR-em/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/LFR-em/Makefile b/designs/LFR-em/Makefile deleted file mode 100644 --- a/designs/LFR-em/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=leon3mp -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES=config.vhd leon3mp.vhd -#VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-em/config.vhd b/designs/LFR-em/config.vhd deleted file mode 100644 --- a/designs/LFR-em/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/LFR-em/leon3mp.vhd b/designs/LFR-em/leon3mp.vhd deleted file mode 100644 --- a/designs/LFR-em/leon3mp.vhd +++ /dev/null @@ -1,553 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -use lpp.lpp_cna.all; - - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; -- PLE - spw1_sin : IN STD_LOGIC; -- PLE - spw1_dout : OUT STD_LOGIC; -- PLE - spw1_sout : OUT STD_LOGIC; -- PLE - - spw2_din : IN STD_LOGIC; -- JCPE --TODO - spw2_sin : IN STD_LOGIC; -- JCPE --TODO - spw2_dout : OUT STD_LOGIC; -- JCPE --TODO - spw2_sout : OUT STD_LOGIC; -- JCPE --TODO - - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - - -- SCM CALIBRATION -------------------------------------------------------- - SCM_CAL_EN : OUT STD_LOGIC; -- TODO A6 - SCM_CAL_DIN : OUT STD_LOGIC; -- TODO A4 - SCM_CAL_SCLK : OUT STD_LOGIC; -- TODO A5 - SCM_CAL_nSYNC : OUT STD_LOGIC; -- TODO B6 - - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF leon3mp IS - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; - CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ - CFG_AHB_UART - +2; - -- 1 is for the SpaceWire module grspw, which is a master - -- 1 is for the LFR - - CONSTANT maxahbm : INTEGER := maxahbmsp; - ---Clk & Rst g�n� - SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL resetnl : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL lclk25MHz : STD_ULOGIC; - SIGNAL lclk50MHz : STD_ULOGIC; - SIGNAL lclk100MHz : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; ---- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - spw_clk <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - led(2) <= dsuo.active; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) - PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- APB_DAC -------------------------------------------------------------------- -------------------------------------------------------------------------------- - APB_DAC_1: APB_DAC - GENERIC MAP ( - pindex => 14, - paddr => 14, - pmask => 16#fff#, - pirq => 13, - abits => 8) - PORT MAP ( - clk => clk, - rst => rst, - apbi => apbi, - apbo => apbo(14), - - Cal_EN => SCM_CAL_EN, - SYNC => SCM_CAL_nSYNC, - SCLK => SCM_CAL_SCLK, - DATA => SCM_CAL_DIN); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_time_management_1: apb_lfr_time_management - GENERIC MAP ( - pindex => 6, - paddr => 6, - pmask => 16#fff#, - pirq => 12) - PORT MAP ( - clk25MHz => clkm, - clk49_152MHz => clk49_152MHz, - resetn => rstn, - grspw_tick => swno.tickout, - apbi => apbi, - apbo => apbo(6), - coarse_time => coarse_time, - fine_time => fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - spw_rxtxclk <= spw_clk; - spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => padtech) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => fabtech, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm - GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn, clkm, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbmi, ahbmo(1), apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR -------------------------------------------------------------------------------- - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => use_RAM, - nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"00000005") - PORT MAP ( - clk => clkm, - rstn => rstn, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi, - apbo => apbo(15), - ahbi => ahbmi, - ahbo => ahbmo(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw); - - top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - cnv => ADC_smpclk, - clk => clkm, - rstn => rstn, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH, - sample => sample, - sample_val => sample_val); - -END Behavioral; diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/.config b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/.config deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/Makefile b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/Makefile deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -GRLIB=../.. -TOP=leon3mp -BOARD=em-LeonLPP-A3PE3kL-v2 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES=config.vhd leon3mp.vhd -#VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./dsp/lpp_fft \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_demux \ - ./lpp_matrix \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_Header \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/config.vhd b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/config.vhd deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/history.txt b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/history.txt deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/history.txt +++ /dev/null @@ -1,27 +0,0 @@ -leon3mp_em_JCPE_02-07-2013.pdb - + UART ok - + SPW ok - + Leon3 ok - -leon3mp_em_JCPE_05-07-2013.pdb - + UART ok - + SPW ok - + Leon3 ok - + Waveform ok - -> No filter - -> Inverted ADC Input Channel - -leon3mp_em_JCPE_08-07-2013.pdb - + UART ?? - + SPW ?? - + Leon3 ?? - + Waveform ?? - -> No filter - -leon3mp_em_JCPE_09-07-2013.pdb - + UART ?? - + SPW ?? - + Leon3 ?? - + Waveform ?? - + Filter - diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/leon3mp_em_JCPE_02-07-2013.pdb b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/history/leon3mp_em_JCPE_02-07-2013.pdb deleted file mode 100644 index abb3bd31c723eeeaa5190e7ad548df1bcafac29f..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 GIT binary patch literal 0 Hc$@ apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_ULOGIC; -- PLE - SIGNAL stmp : STD_ULOGIC; -- PLE - SIGNAL rxclko : STD_ULOGIC; -- PLE - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - led(2) <= dsuo.active; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) - PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - lfrtimemanagement0 : apb_lfr_time_management - GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) - PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - spw_phy0 : grspw2_phy - GENERIC MAP( - scantest => 0, - tech => memtech, - input_type => 0) -- self_clocking mode - PORT MAP( - rstn => rstn, - rxclki => clkm, - rxclkin => clkmn, - nrxclki => clkm, -- not used in self-clocking - di => dtmp, - si => stmp, - do => swni.d(1 DOWNTO 0), - dov => swni.dv(1 DOWNTO 0), - dconnect => swni.dconnect(1 DOWNTO 0), - rxclko => rxclko); - - sw0 : grspwm - GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, - usegen => 1, -- sysfreq not used by the core version 2? usegen? - nsync => 1, -- nsync not used by the core version 2? - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 2, - rxunaligned => 0, - spwcore => 2, - memtech => apa3e, - nodeaddr => 254, - destkey => 2, -- added nodeaddr and destkey parameters - rmapbufs => 4, - netlist => 0, - ft => 0, - ports => 2) - PORT MAP( - rstn, clkm, - rxclko, rxclko, - txclk, txclk, - ahbmi, ahbmo(1), - apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00001001"; - - spw1_dout <= swno.d(0); - spw1_sout <= swno.s(0); - dtmp <= spw1_din; - stmp <= spw1_sin; - - txclk <= lclk100MHz; - - -------------------------------------------------------------------------------- --- WAVEFORM PICKER -------------------------------------------------------------------------------- - -- sdo_adc(4 DOWNTO 0) <= bias_adc(4 DOWNTO 0); - -- sdo_adc(7 DOWNTO 5) <= scm_adc(2 DOWNTO 0); - - waveform_picker0 : top_wf_picker - GENERIC MAP( - hindex => 2, - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq => 14, - tech => CFG_FABTECH, - nb_burst_available_size => 12, -- size of the register holding the nb of burst - nb_snapshot_param_size => 12, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot - ENABLE_FILTER => '1' - ) - PORT MAP( - sample => sample, - sample_val => sample_val, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(15), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => bias_fail_sw - ); - - top_ad_conv_RHF1401_1: top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - - cnv => ADC_smpclk, - - clk => clkm, - rstn => rstn, - ADC_data => ADC_data, - --ADC_smpclk => , - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1 - ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2 - ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3 - - ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1 - ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2 - ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3 - ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4 - ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5 - -END Behavioral; diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/tb_wf_picker.vhd b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/tb_wf_picker.vhd deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/tb_wf_picker.vhd +++ /dev/null @@ -1,253 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE - -LIBRARY esa; -USE esa.memoryctrl.ALL; ---USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; - -ENTITY tb_wf_picker IS -END; - -ARCHITECTURE Behavioral OF tb_wf_picker IS - - SIGNAL clk49_152MHz : STD_LOGIC := '0'; - SIGNAL clkm : STD_LOGIC := '0'; - SIGNAL rstn : STD_LOGIC := '0'; - SIGNAL coarse_time_0 : STD_LOGIC := '0'; - - -- ADC interface - SIGNAL bias_fail_sw : STD_LOGIC; -- OUT - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT - SIGNAL ADC_smpclk : STD_LOGIC; -- OUT - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN - - -- - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - - -- internal - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - -BEGIN - - ----------------------------------------------------------------------------- - - MODULE_RHF1401: FOR I IN 0 TO 7 GENERATE - TestModule_RHF1401_1: TestModule_RHF1401 - GENERIC MAP ( - freq => 24*(I+1), - amplitude => 8000/(I+1), - impulsion => 0) - PORT MAP ( - ADC_smpclk => ADC_smpclk, - ADC_OEB_bar => ADC_OEB_bar_CH(I), - ADC_data => ADC_data); - END GENERATE MODULE_RHF1401; - - ----------------------------------------------------------------------------- - - clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz - clkm <= NOT clkm AFTER 20 ns; -- 25 MHz - coarse_time_0 <= NOT coarse_time_0 AFTER 100 ms; - - ----------------------------------------------------------------------------- - -- waveform generation - WaveGen_Proc : PROCESS - BEGIN - -- insert signal assignments here - WAIT UNTIL clkm = '1'; - apbi <= apb_slv_in_none; - rstn <= '0'; --- cnv_rstn <= '0'; --- run_cnv <= '0'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - rstn <= '1'; --- cnv_rstn <= '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; --- run_cnv <= '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - apbi.psel(15) <= '1'; - apbi.penable <= '1'; - apbi.pwrite <= '1'; - -- 765432 - apbi.paddr(7 DOWNTO 2) <= "001000"; - apbi.pwdata(4 DOWNTO 0) <= "00000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001001"; - apbi.pwdata(6 DOWNTO 0) <= "0000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001010"; - apbi.pwdata <= "10000000000000000000000000000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001011"; - apbi.pwdata <= "10010000000000000000000000000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001100"; - apbi.pwdata <= "10100000000000000000000000000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001101"; - apbi.pwdata <= "10110000000000000000000000000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001110"; - apbi.pwdata(11 DOWNTO 0) <= "000000000000"; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001111"; - apbi.pwdata(15 DOWNTO 0) <= "0000000000000001"; -- A => 1 * 100 ms - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "010000"; -- delta_f2_f1 - apbi.pwdata(15 DOWNTO 0) <= "0000000001111000"; -- 0x78 = 120 - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "010001"; -- delta_f2_f0 - apbi.pwdata(19 DOWNTO 0) <= "00000000001011111000"; -- 0x2f8 = 760 - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "010010"; -- nb_burst_available - apbi.pwdata(11 DOWNTO 0) <= "000000001100"; -- 12 = 0xC - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "010011"; -- nb_snapshot_param - apbi.pwdata(11 DOWNTO 0) <= "000000001111"; -- 15 (+ 1) - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - WAIT UNTIL clkm = '1'; - apbi.paddr(7 DOWNTO 2) <= "001001"; - apbi.pwdata(6 DOWNTO 0) <= "0000111"; - WAIT UNTIL clkm = '1'; - apbi.psel(15) <= '1'; - apbi.penable <= '0'; - apbi.pwrite <= '0'; - WAIT UNTIL clkm = '1'; - - WAIT; - - END PROCESS WaveGen_Proc; - - - ahbmi.HGRANT(2) <= '1'; - ahbmi.HREADY <= '1'; - ahbmi.HRESP <= HRESP_OKAY; - - - -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --- DUT ------------------------------------------------------------------------ -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - - top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - - cnv => ADC_smpclk, - - clk => clkm, - rstn => rstn, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH, - sample => sample, - sample_val => sample_val); - - waveform_picker0 : top_wf_picker - GENERIC MAP( - hindex => 2, - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq => 14, - tech => inferred, - nb_burst_available_size => 12, -- size of the register holding the nb of burst - nb_snapshot_param_size => 12, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot - ENABLE_FILTER => '0' - ) - PORT MAP( - sample => sample, - sample_val => sample_val, - -- - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(15), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time_0, -- bit 0 of the coarse time - -- - data_shaping_BW => bias_fail_sw - ); -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- - -END Behavioral; diff --git a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/wave_tb.do b/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/wave_tb.do deleted file mode 100644 --- a/designs/em-2013-06-29-leon3_spw-A3PE3kL-v2/wave_tb.do +++ /dev/null @@ -1,65 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /tb_wf_picker/clk49_152mhz -add wave -noupdate /tb_wf_picker/clkm -add wave -noupdate /tb_wf_picker/rstn -add wave -noupdate /tb_wf_picker/coarse_time_0 -add wave -noupdate /tb_wf_picker/bias_fail_sw -add wave -noupdate /tb_wf_picker/adc_oeb_bar_ch -add wave -noupdate /tb_wf_picker/adc_smpclk -add wave -noupdate /tb_wf_picker/adc_data -add wave -noupdate /tb_wf_picker/apbi -add wave -noupdate /tb_wf_picker/apbo -add wave -noupdate /tb_wf_picker/ahbmi -add wave -noupdate /tb_wf_picker/sample -add wave -noupdate /tb_wf_picker/sample_val -add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk -add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/clk -add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/rstn -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_data -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/chanelcount -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe_reg_shift -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe_reg -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample_reg -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk_reg -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/start_readout -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/state -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_index -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/adc_noe -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample_val -add wave -noupdate -group RHF1401_DRIVER -radix hexadecimal /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/sample -add wave -noupdate -group RHF1401_DRIVER /tb_wf_picker/top_ad_conv_rhf1401_1/rhf1401_drvr_1/cnv_clk -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f3 -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f3_val -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f2 -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f2_val -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f1 -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f1_val -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f0 -add wave -noupdate -expand -group SAMPLE_VAL /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/sample_f0_val -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/time_ren -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/data_ren -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/ren -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/ready -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/rdata -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/data_wen -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/time_wen -add wave -noupdate -group WaveForm_fifo /tb_wf_picker/waveform_picker0/wf_picker_without_filter/lpp_top_lfr_wf_picker_ip_2/lpp_waveform_1/lpp_waveform_fifo_1/wdata -add wave -noupdate /tb_wf_picker/ahbmo(2) -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {27385336150 ps} 0} -configure wave -namecolwidth 644 -configure wave -valuecolwidth 534 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {2342005961 ps} {4381125074 ps} diff --git a/designs/em-2013-07-22-vhdlib202/.config b/designs/em-2013-07-22-vhdlib202/.config deleted file mode 100644 --- a/designs/em-2013-07-22-vhdlib202/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/em-2013-07-22-vhdlib202/Makefile b/designs/em-2013-07-22-vhdlib202/Makefile deleted file mode 100644 --- a/designs/em-2013-07-22-vhdlib202/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -GRLIB=../.. -TOP=leon3mp -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES=config.vhd leon3mp.vhd -#VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./dsp/lpp_fft \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_demux \ - ./lpp_matrix \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_Header \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_SIMPLE_DIODE.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/em-2013-07-22-vhdlib202/config.vhd b/designs/em-2013-07-22-vhdlib202/config.vhd deleted file mode 100644 --- a/designs/em-2013-07-22-vhdlib202/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/em-2013-07-22-vhdlib202/leon3mp.vhd b/designs/em-2013-07-22-vhdlib202/leon3mp.vhd deleted file mode 100644 --- a/designs/em-2013-07-22-vhdlib202/leon3mp.vhd +++ /dev/null @@ -1,542 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE work.config.ALL; -LIBRARY lpp; ---use lpp.lpp_amba.all; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; ---use lpp.lpp_uart.all; ---use lpp.lpp_matrix.all; ---use lpp.lpp_delay.all; ---use lpp.lpp_fft.all; ---use lpp.fft_components.all; -use lpp.iir_filter.all; -USE lpp.general_purpose.ALL; ---use lpp.Filtercfg.all; -USE lpp.lpp_lfr_time_management.ALL; -- PLE ---use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; -- PLE - spw1_sin : IN STD_LOGIC; -- PLE - spw1_dout : OUT STD_LOGIC; -- PLE - spw1_sout : OUT STD_LOGIC; -- PLE - - spw2_din : IN STD_LOGIC; -- JCPE --TODO - spw2_sin : IN STD_LOGIC; -- JCPE --TODO - spw2_dout : OUT STD_LOGIC; -- JCPE --TODO - spw2_sout : OUT STD_LOGIC; -- JCPE --TODO - - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF leon3mp IS - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; - CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ - CFG_AHB_UART+ - CFG_GRETH+ - CFG_AHB_JTAG - +2; -- 1 is for the SpaceWire module grspw2, which is a master - CONSTANT maxahbm : INTEGER := maxahbmsp; - ---Clk & Rst g�n� - SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL resetnl : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL lclk25MHz : STD_ULOGIC; - SIGNAL lclk50MHz : STD_ULOGIC; - SIGNAL lclk100MHz : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; ---- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - signal spw_rxtxclk : std_ulogic; - signal spw_rxclkn : std_ulogic; - SIGNAL spw_clk : std_logic; - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - spw_clk <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - led(2) <= dsuo.active; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) - PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - lfrtimemanagement0 : apb_lfr_time_management - GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) - PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - spw_rxtxclk <= spw_clk; - spw_rxclkn <= not spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad generic map (tech => padtech) - port map (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad generic map (tech => padtech) - port map (spw1_sin, stmp(0)); - spw1_txd_pad : outpad generic map (tech => padtech) - port map (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad generic map (tech => padtech) - port map (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad generic map (tech => padtech) - port map (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad generic map (tech => padtech) - port map (spw2_sin, stmp(1)); - spw2_txd_pad : outpad generic map (tech => padtech) - port map (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad generic map (tech => padtech) - port map (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop: for j in 0 to 1 generate - spw_phy0 : grspw_phy - generic map( - tech => fabtech, - rxclkbuftype => 1, - scantest => 0) - port map( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 downto j*5), - dconnect => swni.dconnect(j*2+1 downto j*2)); - end generate spw_inputloop; - - -- SPW core - sw0 : grspwm generic map( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - port map(rstn, clkm, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbmi, ahbmo(1), apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (others => '0'); - swni.dcrstval <= (others => '0'); - swni.timerrstval <= (others => '0'); - -------------------------------------------------------------------------------- --- WAVEFORM PICKER -------------------------------------------------------------------------------- - waveform_picker0 : top_wf_picker - GENERIC MAP( - hindex => 2, - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq => 14, - tech => CFG_FABTECH, - nb_burst_available_size => 12, -- size of the register holding the nb of burst - nb_snapshot_param_size => 12, -- size of the register holding the snapshots size - delta_snapshot_size => 16, -- snapshots period - delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts - delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot - ENABLE_FILTER => '1' - ) - PORT MAP( - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - -- - cnv_clk => clkm, - cnv_rstn => rstn, - -- AMBA AHB system signals - HCLK => clkm, - HRESETn => rstn, - -- AMBA APB Slave Interface - apbi => apbi, - apbo => apbo(15), - -- AMBA AHB Master Interface - AHB_Master_In => ahbmi, - AHB_Master_Out => ahbmo(2), - -- - coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time - -- - data_shaping_BW => bias_fail_sw - ); - - top_ad_conv_RHF1401_1: top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - - cnv => ADC_smpclk, - - clk => clkm, - rstn => rstn, - ADC_data => ADC_data, - --ADC_smpclk => , - ADC_nOE => ADC_OEB_bar_CH, - sample => sample, - sample_val => sample_val); - - -- ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1 - -- ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2 - -- ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3 - - -- ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1 - -- ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2 - -- ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3 - -- ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4 - -- ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5 - -END Behavioral; \ No newline at end of file diff --git a/designs/em-2013-07-24-vhdlib210/.config b/designs/em-2013-07-24-vhdlib210/.config deleted file mode 100644 --- a/designs/em-2013-07-24-vhdlib210/.config +++ /dev/null @@ -1,288 +0,0 @@ -# -# Automatically generated make config: don't edit -# - -# -# Synthesis -# -# CONFIG_SYN_INFERRED is not set -# CONFIG_SYN_STRATIX is not set -# CONFIG_SYN_STRATIXII is not set -# CONFIG_SYN_STRATIXIII is not set -# CONFIG_SYN_CYCLONEIII is not set -# CONFIG_SYN_ALTERA is not set -# CONFIG_SYN_AXCEL is not set -# CONFIG_SYN_PROASIC is not set -# CONFIG_SYN_PROASICPLUS is not set -CONFIG_SYN_PROASIC3=y -# CONFIG_SYN_UT025CRH is not set -# CONFIG_SYN_ATC18 is not set -# CONFIG_SYN_ATC18RHA is not set -# CONFIG_SYN_CUSTOM1 is not set -# CONFIG_SYN_EASIC90 is not set -# CONFIG_SYN_IHP25 is not set -# CONFIG_SYN_IHP25RH is not set -# CONFIG_SYN_LATTICE is not set -# CONFIG_SYN_ECLIPSE is not set -# CONFIG_SYN_PEREGRINE is not set -# CONFIG_SYN_RH_LIB18T is not set -# CONFIG_SYN_RHUMC is not set -# CONFIG_SYN_SMIC13 is not set -# CONFIG_SYN_SPARTAN2 is not set -# CONFIG_SYN_SPARTAN3 is not set -# CONFIG_SYN_SPARTAN3E is not set -# CONFIG_SYN_VIRTEX is not set -# CONFIG_SYN_VIRTEXE is not set -# CONFIG_SYN_VIRTEX2 is not set -# CONFIG_SYN_VIRTEX4 is not set -# CONFIG_SYN_VIRTEX5 is not set -# CONFIG_SYN_UMC is not set -# CONFIG_SYN_TSMC90 is not set -# CONFIG_SYN_INFER_RAM is not set -# CONFIG_SYN_INFER_PADS is not set -# CONFIG_SYN_NO_ASYNC is not set -# CONFIG_SYN_SCAN is not set - -# -# Clock generation -# -# CONFIG_CLK_INFERRED is not set -# CONFIG_CLK_HCLKBUF is not set -# CONFIG_CLK_ALTDLL is not set -# CONFIG_CLK_LATDLL is not set -CONFIG_CLK_PRO3PLL=y -# CONFIG_CLK_LIB18T is not set -# CONFIG_CLK_RHUMC is not set -# CONFIG_CLK_CLKDLL is not set -# CONFIG_CLK_DCM is not set -CONFIG_CLK_MUL=2 -CONFIG_CLK_DIV=8 -CONFIG_OCLK_DIV=2 -# CONFIG_PCI_SYSCLK is not set -CONFIG_LEON3=y -CONFIG_PROC_NUM=1 - -# -# Processor -# - -# -# Integer unit -# -CONFIG_IU_NWINDOWS=8 -# CONFIG_IU_V8MULDIV is not set -# CONFIG_IU_SVT is not set -CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=0 -# CONFIG_PWD is not set -CONFIG_IU_RSTADDR=00000 - -# -# Floating-point unit -# -# CONFIG_FPU_ENABLE is not set - -# -# Cache system -# -CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set -# CONFIG_ICACHE_ASSO3 is not set -# CONFIG_ICACHE_ASSO4 is not set -# CONFIG_ICACHE_SZ1 is not set -# CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set -# CONFIG_ICACHE_SZ16 is not set -# CONFIG_ICACHE_SZ32 is not set -# CONFIG_ICACHE_SZ64 is not set -# CONFIG_ICACHE_SZ128 is not set -# CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set -# CONFIG_DCACHE_ASSO3 is not set -# CONFIG_DCACHE_ASSO4 is not set -# CONFIG_DCACHE_SZ1 is not set -# CONFIG_DCACHE_SZ2 is not set -CONFIG_DCACHE_SZ4=y -# CONFIG_DCACHE_SZ8 is not set -# CONFIG_DCACHE_SZ16 is not set -# CONFIG_DCACHE_SZ32 is not set -# CONFIG_DCACHE_SZ64 is not set -# CONFIG_DCACHE_SZ128 is not set -# CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set -CONFIG_CACHE_FIXED=0 - -# -# MMU -# -CONFIG_MMU_ENABLE=y -# CONFIG_MMU_COMBINED is not set -CONFIG_MMU_SPLIT=y -# CONFIG_MMU_REPARRAY is not set -CONFIG_MMU_REPINCREMENT=y -# CONFIG_MMU_I2 is not set -# CONFIG_MMU_I4 is not set -CONFIG_MMU_I8=y -# CONFIG_MMU_I16 is not set -# CONFIG_MMU_I32 is not set -# CONFIG_MMU_D2 is not set -# CONFIG_MMU_D4 is not set -CONFIG_MMU_D8=y -# CONFIG_MMU_D16 is not set -# CONFIG_MMU_D32 is not set -CONFIG_MMU_FASTWB=y -CONFIG_MMU_PAGE_4K=y -# CONFIG_MMU_PAGE_8K is not set -# CONFIG_MMU_PAGE_16K is not set -# CONFIG_MMU_PAGE_32K is not set -# CONFIG_MMU_PAGE_PROG is not set - -# -# Debug Support Unit -# -# CONFIG_DSU_ENABLE is not set - -# -# Fault-tolerance -# - -# -# VHDL debug settings -# -# CONFIG_IU_DISAS is not set -# CONFIG_DEBUG_PC32 is not set - -# -# AMBA configuration -# -CONFIG_AHB_DEFMST=0 -CONFIG_AHB_RROBIN=y -# CONFIG_AHB_SPLIT is not set -CONFIG_AHB_IOADDR=FFF -CONFIG_APB_HADDR=800 -# CONFIG_AHB_MON is not set - -# -# Debug Link -# -CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set - -# -# Peripherals -# - -# -# Memory controllers -# - -# -# 8/32-bit PROM/SRAM controller -# -CONFIG_SRCTRL=y -# CONFIG_SRCTRL_8BIT is not set -CONFIG_SRCTRL_PROMWS=3 -CONFIG_SRCTRL_RAMWS=0 -CONFIG_SRCTRL_IOWS=0 -# CONFIG_SRCTRL_RMW is not set -CONFIG_SRCTRL_SRBANKS1=y -# CONFIG_SRCTRL_SRBANKS2 is not set -# CONFIG_SRCTRL_SRBANKS3 is not set -# CONFIG_SRCTRL_SRBANKS4 is not set -# CONFIG_SRCTRL_SRBANKS5 is not set -# CONFIG_SRCTRL_BANKSZ0 is not set -# CONFIG_SRCTRL_BANKSZ1 is not set -# CONFIG_SRCTRL_BANKSZ2 is not set -# CONFIG_SRCTRL_BANKSZ3 is not set -# CONFIG_SRCTRL_BANKSZ4 is not set -# CONFIG_SRCTRL_BANKSZ5 is not set -# CONFIG_SRCTRL_BANKSZ6 is not set -# CONFIG_SRCTRL_BANKSZ7 is not set -# CONFIG_SRCTRL_BANKSZ8 is not set -# CONFIG_SRCTRL_BANKSZ9 is not set -# CONFIG_SRCTRL_BANKSZ10 is not set -# CONFIG_SRCTRL_BANKSZ11 is not set -# CONFIG_SRCTRL_BANKSZ12 is not set -# CONFIG_SRCTRL_BANKSZ13 is not set -CONFIG_SRCTRL_ROMASEL=19 - -# -# Leon2 memory controller -# -CONFIG_MCTRL_LEON2=y -# CONFIG_MCTRL_8BIT is not set -# CONFIG_MCTRL_16BIT is not set -# CONFIG_MCTRL_5CS is not set -# CONFIG_MCTRL_SDRAM is not set - -# -# PC133 SDRAM controller -# -# CONFIG_SDCTRL is not set - -# -# On-chip RAM/ROM -# -# CONFIG_AHBROM_ENABLE is not set -# CONFIG_AHBRAM_ENABLE is not set - -# -# Ethernet -# -# CONFIG_GRETH_ENABLE is not set - -# -# CAN -# -# CONFIG_CAN_ENABLE is not set - -# -# PCI -# -# CONFIG_PCI_SIMPLE_TARGET is not set -# CONFIG_PCI_MASTER_TARGET is not set -# CONFIG_PCI_ARBITER is not set -# CONFIG_PCI_TRACE is not set - -# -# Spacewire -# -# CONFIG_SPW_ENABLE is not set - -# -# UARTs, timers and irq control -# -CONFIG_UART1_ENABLE=y -# CONFIG_UA1_FIFO1 is not set -# CONFIG_UA1_FIFO2 is not set -CONFIG_UA1_FIFO4=y -# CONFIG_UA1_FIFO8 is not set -# CONFIG_UA1_FIFO16 is not set -# CONFIG_UA1_FIFO32 is not set -# CONFIG_UART2_ENABLE is not set -CONFIG_IRQ3_ENABLE=y -# CONFIG_IRQ3_SEC is not set -CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 -CONFIG_GPT_SW=8 -CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=8 -CONFIG_GPT_SEPIRQ=y -CONFIG_GPT_WDOGEN=y -CONFIG_GPT_WDOG=FFFF -CONFIG_GRGPIO_ENABLE=y -CONFIG_GRGPIO_WIDTH=8 -CONFIG_GRGPIO_IMASK=0000 - -# -# VHDL Debugging -# -# CONFIG_DEBUG_UART is not set diff --git a/designs/em-2013-07-24-vhdlib210/Makefile b/designs/em-2013-07-24-vhdlib210/Makefile deleted file mode 100644 --- a/designs/em-2013-07-24-vhdlib210/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -GRLIB=../.. -TOP=leon3mp -BOARD=em-LeonLPP-A3PE3kL-v3-core1 -include $(GRLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES=config.vhd leon3mp.vhd -#VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc -PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/em-2013-07-24-vhdlib210/config.vhd b/designs/em-2013-07-24-vhdlib210/config.vhd deleted file mode 100644 --- a/designs/em-2013-07-24-vhdlib210/config.vhd +++ /dev/null @@ -1,182 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design test bench configuration --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. ------------------------------------------------------------------------------- - - -library techmap; -use techmap.gencomp.all; - -package config is - - --- Technology and synthesis options - constant CFG_FABTECH : integer := apa3e; - constant CFG_MEMTECH : integer := apa3e; - constant CFG_PADTECH : integer := inferred; - constant CFG_NOASYNC : integer := 0; - constant CFG_SCAN : integer := 0; - --- Clock generator - constant CFG_CLKTECH : integer := inferred; - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_PCIDLL : integer := 0; - constant CFG_PCISYSCLK: integer := 0; - constant CFG_CLK_NOFB : integer := 0; - --- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); - --constant CFG_NWIN : integer := (7); -- PLE - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist - --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE - constant CFG_GRFPUSH : integer := 0; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DFIXED : integer := 16#00F3#; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - constant CFG_LEON3FT_EN : integer := 0; - constant CFG_IUFT_EN : integer := 0; - constant CFG_FPUFT_EN : integer := 0; - constant CFG_RF_ERRINJ : integer := 0; - constant CFG_CACHE_FT_EN : integer := 0; - constant CFG_CACHE_ERRINJ : integer := 0; - constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; - constant CFG_PCLOW : integer := 2; - --- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - constant CFG_AHB_MON : integer := 0; - constant CFG_AHB_MONERR : integer := 0; - constant CFG_AHB_MONWAR : integer := 0; - --- DSU UART - constant CFG_AHB_UART : integer := 1; - --- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; - --- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0; - constant CFG_ETH_BUF : integer := 1; - constant CFG_ETH_IPM : integer := 16#C0A8#; - constant CFG_ETH_IPL : integer := 16#0033#; - constant CFG_ETH_ENM : integer := 16#00007A#; - constant CFG_ETH_ENL : integer := 16#CC0001#; - --- LEON2 memory controller - constant CFG_MCTRL_LEON2 : integer := 1; - constant CFG_MCTRL_RAM8BIT : integer := 0; - constant CFG_MCTRL_RAM16BIT : integer := 0; - constant CFG_MCTRL_5CS : integer := 0; - constant CFG_MCTRL_SDEN : integer := 0; - constant CFG_MCTRL_SEPBUS : integer := 0; - constant CFG_MCTRL_INVCLK : integer := 0; - constant CFG_MCTRL_SD64 : integer := 0; - constant CFG_MCTRL_PAGE : integer := 0 + 0; - --- SSRAM controller - constant CFG_SSCTRL : integer := 0; - constant CFG_SSCTRLP16 : integer := 0; - --- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; - constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; - --- AHB RAM - constant CFG_AHBRAMEN : integer := 0; - constant CFG_AHBRSZ : integer := 1; - constant CFG_AHBRADDR : integer := 16#A00#; - --- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; - constant CFG_GRETH1G : integer := 0; - constant CFG_ETH_FIFO : integer := 8; - --- CAN 2.0 interface - constant CFG_CAN : integer := 0; - constant CFG_CANIO : integer := 16#0#; - constant CFG_CANIRQ : integer := 0; - constant CFG_CANLOOP : integer := 0; - constant CFG_CAN_SYNCRST : integer := 0; - constant CFG_CANFT : integer := 0; - --- UART 1 - constant CFG_UART1_ENABLE : integer := 1; - constant CFG_UART1_FIFO : integer := 1; - --- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := 1; - --- Modular timer - constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (3); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - --- GPIO port - constant CFG_GRGPIO_ENABLE : integer := 1; - constant CFG_GRGPIO_IMASK : integer := 16#0000#; - constant CFG_GRGPIO_WIDTH : integer := (7); - --- GRLIB debugging - constant CFG_DUART : integer := 0; - - -end; diff --git a/designs/em-2013-07-24-vhdlib210/leon3mp.vhd b/designs/em-2013-07-24-vhdlib210/leon3mp.vhd deleted file mode 100644 --- a/designs/em-2013-07-24-vhdlib210/leon3mp.vhd +++ /dev/null @@ -1,520 +0,0 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -USE work.config.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -use lpp.iir_filter.all; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; - -ENTITY leon3mp IS - GENERIC ( - fabtech : INTEGER := CFG_FABTECH; - memtech : INTEGER := CFG_MEMTECH; - padtech : INTEGER := CFG_PADTECH; - clktech : INTEGER := CFG_CLKTECH; - disas : INTEGER := CFG_DISAS; -- Enable disassembly to console - dbguart : INTEGER := CFG_DUART; -- Print UART on console - pclow : INTEGER := CFG_PCLOW - ); - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- SPW -------------------------------------------------------------------- - spw1_din : IN STD_LOGIC; -- PLE - spw1_sin : IN STD_LOGIC; -- PLE - spw1_dout : OUT STD_LOGIC; -- PLE - spw1_sout : OUT STD_LOGIC; -- PLE - - spw2_din : IN STD_LOGIC; -- JCPE --TODO - spw2_sin : IN STD_LOGIC; -- JCPE --TODO - spw2_dout : OUT STD_LOGIC; -- JCPE --TODO - spw2_sout : OUT STD_LOGIC; -- JCPE --TODO - - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - - --------------------------------------------------------------------------- - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF leon3mp IS - ---constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ --- CFG_GRETH+CFG_AHB_JTAG; - CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ - CFG_AHB_UART+ - CFG_GRETH+ - CFG_AHB_JTAG - +3; -- 1 is for the SpaceWire module grspw, which is a master - -- 1 is for the LFR SM - -- 1 is for the LFR WFP - - CONSTANT maxahbm : INTEGER := maxahbmsp; - ---Clk & Rst g�n� - SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL resetnl : STD_ULOGIC; - SIGNAL clk2x : STD_ULOGIC; - SIGNAL lclk2x : STD_ULOGIC; - SIGNAL lclk25MHz : STD_ULOGIC; - SIGNAL lclk50MHz : STD_ULOGIC; - SIGNAL lclk100MHz : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; ---- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); ---UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; ---MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - SIGNAL ramcs : STD_ULOGIC; ---IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); ---Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; ---DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ---------------------------------------------------------------------- ---- AJOUT TEST ------------------------Signaux---------------------- ---------------------------------------------------------------------- - ---------------------------------------------------------------------- - CONSTANT IOAEN : INTEGER := CFG_CAN; - CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz - --- time management signal - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE - signal spw_rxtxclk : std_ulogic; - signal spw_rxclkn : std_ulogic; - SIGNAL spw_clk : std_logic; - SIGNAL swni : grspw_in_type; -- PLE - SIGNAL swno : grspw_out_type; -- PLE - SIGNAL clkmn : STD_ULOGIC; -- PLE - SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 - --- AD Converter RHF1401 - SIGNAL sample : Samples14v(7 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - ----------------------------------------------------------------------------- - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); - cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - - clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) - PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - - PROCESS(lclk100MHz) - BEGIN - IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN - lclk50MHz <= NOT lclk50MHz; - END IF; - END PROCESS; - - PROCESS(lclk50MHz) - BEGIN - IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN - lclk25MHz <= NOT lclk25MHz; - END IF; - END PROCESS; - - lclk2x <= lclk50MHz; - spw_clk <= lclk50MHz; - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - led(2) <= dsuo.active; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => IOAEN, nahbm => maxahbm, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP ( hindex => 4, pindex => 4, paddr => 4) - PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(4)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - led(0) <= NOT ahbuarti.rxd; - led(1) <= NOT ahbuarto.txd; - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - lfrtimemanagement0 : apb_lfr_time_management - GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#, - masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, - pirq => 12) - PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), - coarse_time, fine_time); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - spw_rxtxclk <= spw_clk; - spw_rxclkn <= not spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad generic map (tech => padtech) - port map (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad generic map (tech => padtech) - port map (spw1_sin, stmp(0)); - spw1_txd_pad : outpad generic map (tech => padtech) - port map (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad generic map (tech => padtech) - port map (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad generic map (tech => padtech) - port map (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad generic map (tech => padtech) - port map (spw2_sin, stmp(1)); - spw2_txd_pad : outpad generic map (tech => padtech) - port map (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad generic map (tech => padtech) - port map (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop: for j in 0 to 1 generate - spw_phy0 : grspw_phy - generic map( - tech => fabtech, - rxclkbuftype => 1, - scantest => 0) - port map( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 downto j*5), - dconnect => swni.dconnect(j*2+1 downto j*2)); - end generate spw_inputloop; - - -- SPW core - sw0 : grspwm generic map( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - port map(rstn, clkm, spw_rxclk(0), - spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, - ahbmi, ahbmo(1), apbi, apbo(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (others => '0'); - swni.dcrstval <= (others => '0'); - swni.timerrstval <= (others => '0'); - -------------------------------------------------------------------------------- --- LFR -------------------------------------------------------------------------------- - lpp_lfr_1: lpp_lfr - GENERIC MAP ( - Mem_use => use_RAM, - nb_burst_available_size => 12, - nb_snapshot_param_size => 12, - delta_snapshot_size => 16, - delta_f2_f0_size => 20, - delta_f2_f1_size => 16, - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex_wfp => 2, - hindex_ms => 3) - PORT MAP ( - clk => clkm, - rstn => rstn, - sample_B => sample(2 DOWNTO 0), - sample_E => sample(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi, - apbo => apbo(15), - ahbi_wfp => ahbmi, - ahbo_wfp => ahbmo(2), - ahbi_ms => ahbmi, - ahbo_ms => ahbmo(3), - coarse_time_0 => coarse_time(0), - data_shaping_BW => bias_fail_sw); - - top_ad_conv_RHF1401_1: top_ad_conv_RHF1401 - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk49_152MHz, - cnv_rstn => rstn, - - cnv => ADC_smpclk, - - clk => clkm, - rstn => rstn, - ADC_data => ADC_data, - - ADC_nOE => ADC_OEB_bar_CH, - sample => sample, - sample_val => sample_val); - -END Behavioral;