# HG changeset patch
# User pellion
# Date 2014-10-30 15:28:40
# Node ID cd810ee8afe4715f7c3288f7f4fec50493211013
# Parent  22a9c3950a77fe474ac8c50bf6d8f4bdd54b4f3a

temp_CIC

diff --git a/designs/Validation_CIC/Makefile b/designs/Validation_CIC/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/Validation_CIC/Makefile
@@ -0,0 +1,53 @@
+#GRLIB=../..
+VHDLIB=../..
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=leon3mp
+BOARD=em-LeonLPP-A3PE3kL-v3-core1
+include $(GRLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+XSTOPT=
+SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
+#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
+VHDLSYNFILES=
+VHDLSIMFILES= tb.vhd 
+SIMTOP=testbench
+#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
+#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
+PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
+BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
+CLEAN=soft-clean
+
+TECHLIBS = proasic3e
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann micron usbhc
+
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lpp_cna \
+	./lpp_uart \
+	./lpp_usb \
+	./dsp/lpp_fft_rtax \
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd
+
+include $(GRLIB)/bin/Makefile
+include $(GRLIB)/software/leon3/Makefile
+
+##################  project specific targets ##########################
+
diff --git a/designs/Validation_CIC/from_Paul/cic_with_RAM.ods b/designs/Validation_CIC/from_Paul/cic_with_RAM.ods
new file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..785067941bca2496e04f4eda9b272ccc0f62fb73
GIT binary patch
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zik5p<+1q76@bvRB>9nalO39p4oOC({uwc-Z3O9~aq&7+#HYN~XScLGU^6Lt4{Bs&T
zMR9}+iT-3$`SI9SEEt!vn0}V_@uek!**t?C{E@}eToynv5r4lj<dV4vnGA02UV^?)
zc|r-IK;sb*zx2nroiC{LI-7aq>~Wa=5&S5KNh*aQAFN_NH9eWHzYw*{DG!kg98e%E
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zc46JpC8F+T^hrI{(*Wo4gl5_2w_2s)k<8mfZ?Ucj==&T4gP;QabD7(}zWykB`v>Ze
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O-~R01V0*6bXa5U@=INmT

diff --git a/designs/Validation_CIC/run.do b/designs/Validation_CIC/run.do
new file mode 100644
--- /dev/null
+++ b/designs/Validation_CIC/run.do
@@ -0,0 +1,17 @@
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/chirp/chirp_pkg.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/chirp/chirp.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_pkg.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_integrator.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_downsampler.vhd
+vcom -quiet  -93  -work lpp  ../../lib/lpp/dsp/cic/cic_comb.vhd
+
+vcom -quiet  -93  -work work tb.vhd
+
+vsim work.testbench
+
+log -r *
+
+do wave.do
+
+run -all
diff --git a/designs/Validation_CIC/tb.vhd b/designs/Validation_CIC/tb.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Validation_CIC/tb.vhd
@@ -0,0 +1,78 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lpp;
+USE lpp.cic_pkg.ALL;
+USE lpp.chirp_pkg.ALL;
+
+ENTITY testbench IS
+END;
+
+ARCHITECTURE behav OF testbench IS
+
+  SIGNAL clk            : STD_LOGIC := '0';
+  SIGNAL rstn           : STD_LOGIC;
+  SIGNAL run            : STD_LOGIC;
+  SIGNAL data_in        : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL data_in_valid  : STD_LOGIC;
+  SIGNAL data_out       : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL data_out_valid : STD_LOGIC;
+  
+BEGIN
+
+  clk <= NOT clk AFTER 5 ns;
+
+  PROCESS
+  BEGIN  -- PROCESS
+    WAIT UNTIL clk = '1';
+    rstn <= '0';
+    run  <= '0';
+    data_in_valid <= '0';
+    
+    WAIT UNTIL clk = '1';
+    rstn <= '1';
+    WAIT UNTIL clk = '1';
+    WAIT UNTIL clk = '1';
+    run <= '1';
+    WAIT UNTIL clk = '1';
+    WAIT UNTIL clk = '1';
+    data_in_valid <= '1';
+    WAIT FOR 105 us;
+    REPORT "*** END simulation ***" SEVERITY failure;
+    WAIT;    
+  END PROCESS;
+  -----------------------------------------------------------------------------
+  DUT_cic: cic
+    GENERIC MAP (
+      D_delay_number                   => 2,
+      S_stage_number                   => 3,
+      R_downsampling_decimation_factor => 16,
+      b_data_size                      => 16,
+      b_grow                           => 15)
+    PORT MAP (
+      clk            => clk,
+      rstn           => rstn,
+      run            => run,
+      data_in        => data_in,
+      data_in_valid  => data_in_valid,
+      data_out       => data_out,
+      data_out_valid => data_out_valid);
+  -----------------------------------------------------------------------------
+  chirp_gen: chirp
+    GENERIC MAP (
+      LOW_FREQUENCY_LIMIT  => 0,
+      HIGH_FREQUENCY_LIMIT => 1000,
+      NB_POINT_TO_GEN      => 10000,
+      AMPLITUDE            => 200,
+      NB_BITS              => 16)
+    PORT MAP (
+      clk      => clk,
+      rstn     => rstn,
+      run      => run,
+      data_ack => data_in_valid,
+      data     => data_in);
+  
+END;
diff --git a/designs/Validation_CIC/wave.do b/designs/Validation_CIC/wave.do
new file mode 100644
--- /dev/null
+++ b/designs/Validation_CIC/wave.do
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/dut_cic/d_delay_number
+add wave -noupdate /testbench/dut_cic/s_stage_number
+add wave -noupdate /testbench/dut_cic/r_downsampling_decimation_factor
+add wave -noupdate -format Analog-Step -height 74 -max 1999.9999999999998 /testbench/chirp_gen/freq_chirp
+add wave -noupdate -format Analog-Step -height 74 -max 10000.0 /testbench/chirp_gen/n
+add wave -noupdate -format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal /testbench/dut_cic/data_in
+add wave -noupdate -format Analog-Step -height 74 -max 189.0 -min -172.0 -radix decimal /testbench/dut_cic/data_out
+add wave -noupdate -divider COMB
+add wave -noupdate -radix decimal -expand -subitemconfig {/testbench/dut_cic/c_data(3) {-format Analog-Step -height 74 -max 6208650.0000000009 -min -5630018.0 -radix decimal} /testbench/dut_cic/c_data(2) {-format Analog-Step -height 74 -max 22640530.0 -radix decimal} /testbench/dut_cic/c_data(1) {-format Analog-Step -height 74 -max 1067269590.0 -min -1072646474.0 -radix decimal} /testbench/dut_cic/c_data(0) {-format Analog-Step -height 74 -max 1071549238.9999998 -min -1068913901.0 -radix decimal}} /testbench/dut_cic/c_data
+add wave -noupdate -divider INTEGRATOR
+add wave -noupdate -radix decimal -expand -subitemconfig {/testbench/dut_cic/i_data(3) {-format Analog-Step -height 74 -max 1073731108.9999998 -min -1073537753.0 -radix decimal} /testbench/dut_cic/i_data(2) {-format Analog-Step -height 74 -max 164477947.0 -radix decimal} /testbench/dut_cic/i_data(1) {-format Analog-Step -height 74 -max 22580.0 -radix decimal} /testbench/dut_cic/i_data(0) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal}} /testbench/dut_cic/i_data
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3685000 ps} 0}
+configure wave -namecolwidth 370
+configure wave -valuecolwidth 40
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {110307750 ps}
diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt
--- a/lib/lpp/dirs.txt
+++ b/lib/lpp/dirs.txt
@@ -4,6 +4,8 @@
 ./general_purpose/lpp_balise
 ./general_purpose/lpp_delay
 ./lpp_amba
+./dsp/chirp
+./dsp/cic
 ./dsp/iir_filter
 ./dsp/lpp_downsampling
 ./dsp/lpp_fft_rtax
diff --git a/lib/lpp/dsp/chirp/chirp.vhd b/lib/lpp/dsp/chirp/chirp.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/chirp/chirp.vhd
@@ -0,0 +1,85 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE IEEE.std_logic_arith.ALL;
+USE IEEE.std_logic_signed.ALL;
+USE IEEE.MATH_real.ALL;
+
+ENTITY chirp IS
+  
+  GENERIC (
+    LOW_FREQUENCY_LIMIT  : INTEGER := 0;
+    HIGH_FREQUENCY_LIMIT : INTEGER := 2000;
+    NB_POINT_TO_GEN      : INTEGER := 10000;
+    AMPLITUDE            : INTEGER := 100;
+    NB_BITS              : INTEGER := 16);
+
+  PORT (
+    clk      : IN  STD_LOGIC;
+    rstn     : IN  STD_LOGIC;
+    run      : IN  STD_LOGIC;
+    
+    data_ack : IN  STD_LOGIC;
+    data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
+    );
+
+END chirp;
+
+ARCHITECTURE beh OF chirp IS
+
+  SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
+  SIGNAL n : INTEGER;
+  SIGNAL current_time : REAL := REAL(0);
+  SIGNAL freq_chirp : REAL := REAL(0);
+BEGIN  -- beh
+
+  current_time <= REAL(n) / REAL(NB_POINT_TO_GEN);
+  freq_chirp   <= REAL(LOW_FREQUENCY_LIMIT) + (REAL(HIGH_FREQUENCY_LIMIT) - REAL(LOW_FREQUENCY_LIMIT))*current_time;
+  
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      reg <= (OTHERS => '0');
+      n <= 0;
+    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+      IF run = '0' THEN
+        reg <= (OTHERS => '0');
+        n   <= 0;
+      ELSE
+        IF data_ack = '1' THEN
+          IF n < NB_POINT_TO_GEN THEN
+            n <= n+1;
+            reg <= conv_std_logic_vector(INTEGER(REAL(AMPLITUDE) * SIN(MATH_2_PI*current_time*freq_chirp)),NB_BITS);
+          ELSE
+            reg <= (OTHERS => '0');
+          END IF;
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+  data <= reg;
+
+END beh;
diff --git a/lib/lpp/dsp/chirp/chirp_pkg.vhd b/lib/lpp/dsp/chirp/chirp_pkg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/chirp/chirp_pkg.vhd
@@ -0,0 +1,45 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+PACKAGE chirp_pkg IS
+
+  COMPONENT chirp
+    GENERIC (
+      LOW_FREQUENCY_LIMIT  : INTEGER;
+      HIGH_FREQUENCY_LIMIT : INTEGER;
+      NB_POINT_TO_GEN      : INTEGER;
+      AMPLITUDE            : INTEGER;
+      NB_BITS              : INTEGER);
+    PORT (
+      clk      : IN  STD_LOGIC;
+      rstn     : IN  STD_LOGIC;
+      run      : IN  STD_LOGIC;
+      data_ack : IN  STD_LOGIC;
+      data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0));
+  END COMPONENT;
+  
+
+END chirp_pkg;
diff --git a/lib/lpp/dsp/chirp/vhdlsyn.txt b/lib/lpp/dsp/chirp/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/chirp/vhdlsyn.txt
@@ -0,0 +1,2 @@
+chirp_pkg.vhd
+chirp.vhd
diff --git a/lib/lpp/dsp/cic/cic.vhd b/lib/lpp/dsp/cic/cic.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic.vhd
@@ -0,0 +1,122 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+LIBRARY lpp;
+USE lpp.cic_pkg.ALL;
+
+ENTITY cic IS
+  
+  GENERIC (
+    D_delay_number                   : INTEGER := 2;
+    S_stage_number                   : INTEGER := 3;
+    R_downsampling_decimation_factor : INTEGER := 16;
+    
+    b_data_size                      : INTEGER := 16;
+    b_grow                           : INTEGER := 5 --
+    );
+
+  PORT (
+    clk            : IN  STD_LOGIC;
+    rstn           : IN  STD_LOGIC;
+    run            : IN  STD_LOGIC;
+    
+    data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_in_valid  : IN  STD_LOGIC;
+
+    data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_out_valid : OUT STD_LOGIC
+    );
+
+END cic;
+
+ARCHITECTURE beh OF cic IS
+
+  TYPE data_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b_data_size + b_grow - 1 DOWNTO 0);
+
+  SIGNAL I_data  : data_vector(S_stage_number DOWNTO 0);
+  SIGNAL I_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
+
+  SIGNAL C_data  : data_vector(S_stage_number DOWNTO 0);
+  SIGNAL C_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
+  
+BEGIN  -- beh
+  -----------------------------------------------------------------------------
+  I_valid(0)                        <= data_in_valid;
+  I_data(0)(b_data_size-1 DOWNTO 0) <= data_in;
+  all_bit_grow: FOR I IN 0 TO b_grow-1 GENERATE
+    I_data(0)(I+b_data_size) <= data_in(b_data_size-1);
+  END GENERATE all_bit_grow;
+  -----------------------------------------------------------------------------
+  all_I: FOR S_i IN 1 TO S_stage_number GENERATE
+    I_1: cic_integrator
+      GENERIC MAP (
+        b_data_size => b_data_size + b_grow)
+      PORT MAP (
+        clk            => clk,
+        rstn           => rstn,
+        run            => run,
+        
+        data_in        => I_data(S_i-1),
+        data_in_valid  => I_valid(S_i-1),
+        data_out       => I_data(S_i),
+        data_out_valid => I_valid(S_i)
+        );   
+  END GENERATE all_I;
+  -----------------------------------------------------------------------------  
+  cic_downsampler_1: cic_downsampler
+    GENERIC MAP (
+      R_downsampling_decimation_factor => R_downsampling_decimation_factor,
+      b_data_size                      => b_data_size + b_grow)
+    PORT MAP (
+      clk            => clk,
+      rstn           => rstn,
+      run            => run,
+      data_in        => I_data(S_stage_number),
+      data_in_valid  => I_valid(S_stage_number),
+      data_out       => C_data(0),
+      data_out_valid => C_valid(0));
+  -----------------------------------------------------------------------------
+  all_C: FOR S_i IN 1 TO S_stage_number GENERATE
+    cic_comb_1: cic_comb
+      GENERIC MAP (
+        b_data_size    => b_data_size + b_grow,
+        D_delay_number => D_delay_number)
+      PORT MAP (
+        clk            => clk,
+        rstn           => rstn,
+        run            => run,
+        
+        data_in        => C_data(S_i-1),
+        data_in_valid  => C_valid(S_i-1),
+        data_out       => C_data(S_i),
+        data_out_valid => C_valid(S_i));
+  END GENERATE all_C;
+  -----------------------------------------------------------------------------
+  data_out       <= C_data(S_stage_number)(b_data_size + b_grow - 1 DOWNTO b_grow);
+  data_out_valid <= C_valid(S_stage_number);
+  -----------------------------------------------------------------------------
+END beh;
+
diff --git a/lib/lpp/dsp/cic/cic_comb.vhd b/lib/lpp/dsp/cic/cic_comb.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic_comb.vhd
@@ -0,0 +1,94 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY cic_comb IS
+  
+  GENERIC (
+    b_data_size                      : INTEGER := 16;
+    D_delay_number                   : INTEGER := 2   
+    );
+
+  PORT (
+    clk            : IN  STD_LOGIC;
+    rstn           : IN  STD_LOGIC;
+    run            : IN  STD_LOGIC;
+    
+    data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_in_valid  : IN  STD_LOGIC;
+
+    data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_out_valid : OUT STD_LOGIC
+    );
+
+END cic_comb;
+
+ARCHITECTURE beh OF cic_comb IS
+
+  TYPE data_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b_data_size - 1 DOWNTO 0);
+
+  SIGNAL data_reg : data_vector(D_delay_number DOWNTO 0);
+  
+BEGIN  -- beh
+
+  data_reg(0) <= data_in;
+  
+  all_D: FOR I IN D_delay_number DOWNTO 1 GENERATE
+    PROCESS (clk, rstn)
+    BEGIN
+      IF rstn = '0' THEN
+         data_reg(I) <= (OTHERS => '0');
+      ELSIF clk'event AND clk = '1' THEN 
+        IF run = '0' THEN
+          data_reg(I) <= (OTHERS => '0');
+        ELSIF data_in_valid = '1' THEN
+          data_reg(I) <= data_reg(I-1);
+        END IF;
+      END IF;
+    END PROCESS;
+  END GENERATE all_D;
+
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      data_out <= (OTHERS => '0');
+      data_out_valid <= '0';
+    ELSIF clk'event AND clk = '1' THEN
+      IF run = '0' THEN
+        data_out <= (OTHERS => '0');
+        data_out_valid <= '0';
+      ELSE
+        data_out_valid <= data_in_valid;
+        IF data_in_valid = '1' THEN
+          data_out <= STD_LOGIC_VECTOR(resize(SIGNED(data_reg(0))-SIGNED(data_reg(D_delay_number)),b_data_size));
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+
+END beh;
+
diff --git a/lib/lpp/dsp/cic/cic_downsampler.vhd b/lib/lpp/dsp/cic/cic_downsampler.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic_downsampler.vhd
@@ -0,0 +1,87 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY cic_downsampler IS
+  
+  GENERIC (
+    R_downsampling_decimation_factor : INTEGER := 16;
+    b_data_size                      : INTEGER := 16
+    );
+
+  PORT (
+    clk            : IN  STD_LOGIC;
+    rstn           : IN  STD_LOGIC;
+    run            : IN  STD_LOGIC;
+    
+    data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_in_valid  : IN  STD_LOGIC;
+
+    data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_out_valid : OUT STD_LOGIC
+    );
+
+END cic_downsampler;
+
+ARCHITECTURE beh OF cic_downsampler IS
+
+  SUBTYPE INTEGER_downsampler IS INTEGER RANGE 0 TO R_downsampling_decimation_factor-1;
+  
+  SIGNAL counter_downsampler : INTEGER_downsampler;
+  
+BEGIN  -- beh
+
+  PROCESS (clk, rstn)
+    BEGIN  -- PROCESS
+      IF rstn = '0' THEN                -- asynchronous reset (active low)
+        data_out            <= (OTHERS => '0');
+        data_out_valid      <= '0';
+        counter_downsampler <= 0;     
+      ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+        IF run = '0' THEN
+          data_out       <= (OTHERS => '0');
+          data_out_valid <= '0';
+          counter_downsampler <= 0;
+        ELSE
+          data_out_valid <= '0';
+          IF data_in_valid = '1' THEN
+            IF counter_downsampler = R_downsampling_decimation_factor-1  THEN
+              counter_downsampler <= 0;
+            ELSE
+              counter_downsampler <= counter_downsampler + 1;
+            END IF;
+
+            IF counter_downsampler = 0 THEN
+              data_out_valid <= '1';
+              data_out       <= data_in;
+            END IF;
+            
+          END IF;
+        END IF;
+      END IF;
+    END PROCESS;  
+
+END beh;
+
diff --git a/lib/lpp/dsp/cic/cic_integrator.vhd b/lib/lpp/dsp/cic/cic_integrator.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic_integrator.vhd
@@ -0,0 +1,78 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY cic_integrator IS
+  
+  GENERIC (
+    b_data_size                      : INTEGER := 16
+    );
+
+  PORT (
+    clk            : IN  STD_LOGIC;
+    rstn           : IN  STD_LOGIC;
+    run            : IN  STD_LOGIC;
+    
+    data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_in_valid  : IN  STD_LOGIC;
+
+    data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+    data_out_valid : OUT STD_LOGIC
+    );
+
+END cic_integrator;
+
+ARCHITECTURE beh OF cic_integrator IS
+
+  SIGNAL data_reg : STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+  SIGNAL data_add : STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+  
+BEGIN  -- beh
+
+  data_out <= data_reg;
+
+  data_add <= STD_LOGIC_VECTOR(resize(SIGNED(data_in)+SIGNED(data_reg),b_data_size));
+  
+  PROCESS (clk, rstn)
+    BEGIN  -- PROCESS
+      IF rstn = '0' THEN                -- asynchronous reset (active low)
+        data_reg <= (OTHERS => '0');
+        data_out_valid <= '0';
+      ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+        IF run = '0' THEN
+          data_reg <= (OTHERS => '0');
+          data_out_valid <= '0';
+        ELSE
+          data_out_valid <= data_in_valid;
+          IF data_in_valid = '1' THEN
+            data_reg <= data_add;
+          END IF;
+        END IF;
+      END IF;
+    END PROCESS;  
+
+END beh;
+
diff --git a/lib/lpp/dsp/cic/cic_lfr.vhd b/lib/lpp/dsp/cic/cic_lfr.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic_lfr.vhd
@@ -0,0 +1,55 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+LIBRARY lpp;
+USE lpp.cic_pkg.ALL;
+USE lpp.data_type_pkg.ALL;
+
+ENTITY cic_lfr IS
+    
+  PORT (
+    clk            : IN  STD_LOGIC;
+    rstn           : IN  STD_LOGIC;
+    run            : IN  STD_LOGIC;
+    
+    data_in        : IN  sample_vector(5 DOWNTO 0,15 DOWNTO 0);
+    data_in_valid  : IN  STD_LOGIC;
+
+    data_out_16    : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
+    data_out_256   : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
+    data_out_valid : OUT STD_LOGIC
+    );
+
+END cic_lfr;
+
+ARCHITECTURE beh OF cic_lfr IS
+  
+BEGIN
+
+  
+  
+END beh;
+
diff --git a/lib/lpp/dsp/cic/cic_pkg.vhd b/lib/lpp/dsp/cic/cic_pkg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/cic_pkg.vhd
@@ -0,0 +1,89 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+----------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+PACKAGE cic_pkg IS
+
+  -----------------------------------------------------------------------------
+  COMPONENT cic
+    GENERIC (
+      D_delay_number                   : INTEGER;
+      S_stage_number                   : INTEGER;
+      R_downsampling_decimation_factor : INTEGER;
+      b_data_size                      : INTEGER;
+      b_grow                           : INTEGER);
+    PORT (
+      clk            : IN  STD_LOGIC;
+      rstn           : IN  STD_LOGIC;
+      run            : IN  STD_LOGIC;
+      data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_in_valid  : IN  STD_LOGIC;
+      data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_out_valid : OUT STD_LOGIC);
+  END COMPONENT;
+  -----------------------------------------------------------------------------
+  COMPONENT cic_integrator
+    GENERIC (
+      b_data_size : INTEGER);
+    PORT (
+      clk            : IN  STD_LOGIC;
+      rstn           : IN  STD_LOGIC;
+      run            : IN  STD_LOGIC;
+      data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_in_valid  : IN  STD_LOGIC;
+      data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_out_valid : OUT STD_LOGIC);
+  END COMPONENT;
+
+  COMPONENT cic_downsampler
+    GENERIC (
+      R_downsampling_decimation_factor : INTEGER;
+      b_data_size                      : INTEGER);
+    PORT (
+      clk            : IN  STD_LOGIC;
+      rstn           : IN  STD_LOGIC;
+      run            : IN  STD_LOGIC;
+      data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_in_valid  : IN  STD_LOGIC;
+      data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_out_valid : OUT STD_LOGIC);
+  END COMPONENT;
+
+  COMPONENT cic_comb
+    GENERIC (
+      b_data_size    : INTEGER;
+      D_delay_number : INTEGER);
+    PORT (
+      clk            : IN  STD_LOGIC;
+      rstn           : IN  STD_LOGIC;
+      run            : IN  STD_LOGIC;
+      data_in        : IN  STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_in_valid  : IN  STD_LOGIC;
+      data_out       : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
+      data_out_valid : OUT STD_LOGIC);
+  END COMPONENT;
+  -----------------------------------------------------------------------------
+
+END cic_pkg;
diff --git a/lib/lpp/dsp/cic/vhdlsyn.txt b/lib/lpp/dsp/cic/vhdlsyn.txt
new file mode 100644
--- /dev/null
+++ b/lib/lpp/dsp/cic/vhdlsyn.txt
@@ -0,0 +1,6 @@
+cic_pkg.vhd
+cic.vhd
+cic_integrator.vhd
+cic_downsampler.vhd
+cic_comb.vhd
+cic_lfr.vhd
diff --git a/lib/lpp/general_purpose/data_type_pkg.vhd b/lib/lpp/general_purpose/data_type_pkg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/general_purpose/data_type_pkg.vhd
@@ -0,0 +1,31 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
+--                             jean-christophe.pellion@easii-ic.com
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+PACKAGE data_type_pkg IS
+
+  TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
+  
+END data_type_pkg;
diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt
--- a/lib/lpp/general_purpose/vhdlsyn.txt
+++ b/lib/lpp/general_purpose/vhdlsyn.txt
@@ -1,3 +1,4 @@
+data_type_pkg.vhd
 general_purpose.vhd
 ADDRcntr.vhd
 ALU.vhd