# HG changeset patch # User martin # Date 2010-11-19 11:55:10 # Node ID c673e3c002b4726871f8c6380a907887d63e430a # Parent a7349b2a8f39a6bd8b12c80e0423bbab386c8d82 apb_uart added, APB CNA added diff --git a/lib/lpp/lpp_CNA_amba/APB_CNA.vhd b/lib/lpp/lpp_CNA_amba/APB_CNA.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/APB_CNA.vhd @@ -0,0 +1,126 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- APB_CNA.vhd + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_CNA_amba.all; + + +entity APB_CNA is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + SYNC : out std_logic; + SCLK : out std_logic; + DATA : out std_logic + ); +end APB_CNA; + + +architecture ar_APB_CNA of APB_CNA is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +signal flag_nw : std_logic; +signal bp : std_logic; +signal Rz : std_logic; +signal flag_sd : std_logic; +signal Rdata : std_logic_vector(31 downto 0); + +type CNA_ctrlr_Reg is record + CNA_Cfg : std_logic_vector(3 downto 0); + CNA_Data : std_logic_vector(15 downto 0); +end record; + +signal Rec : CNA_ctrlr_Reg; +--signal ConfigREG : std_logic_vector(3 downto 0); +--signal DataREG : std_logic_vector(15 downto 0); + +begin + +bp <= Rec.CNA_Cfg(0); +flag_nw <= Rec.CNA_Cfg(1); +Rec.CNA_Cfg(2) <= flag_sd; +Rec.CNA_Cfg(3) <= Rz; + + + + CONVERTER : entity Work.CNA_TabloC + port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); + + + + process(rst,clk) + begin + if(rst='0')then + Rec.CNA_Data <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); + when "000001" => + Rec.CNA_Data <= apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + --APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(31 downto 4) <= X"ABCDEF5"; + Rdata(3 downto 0) <= Rec.CNA_Cfg; + when "000001" => + Rdata(31 downto 16) <= X"FD18"; + Rdata(15 downto 0) <= Rec.CNA_Data; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +end ar_APB_CNA; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd b/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd @@ -0,0 +1,71 @@ +-- CNA_TabloC.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.Convertisseur_config.all; + +entity CNA_TabloC is + port( + clock : in std_logic; + rst : in std_logic; + flag_nw : in std_logic; + bp : in std_logic; + Data_C : in std_logic_vector(15 downto 0); + SYNC : out std_logic; + SCLK : out std_logic; + Rz : out std_logic; + flag_sd : out std_logic; + Data : out std_logic + ); +end CNA_TabloC; + + +architecture ar_CNA_TabloC of CNA_TabloC is + +component CLKINT +port( A : in std_logic := 'U'; + Y : out std_logic); +end component; + +signal clk : std_logic; +--signal reset : std_logic; + +signal raz : std_logic; +signal sys_clk : std_logic; +signal Data_int : std_logic_vector(15 downto 0); +signal OKAI_send : std_logic; + +begin + + +CLKINT_0 : CLKINT + port map(A => clock, Y => clk); + +CLKINT_1 : CLKINT + port map(A => rst, Y => raz); + + +SystemCLK : entity work.Clock_Serie + generic map (nb_serial) + port map (clk,raz,sys_clk); + + +Signal_sync : entity work.GeneSYNC_flag + port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); + + +Serial : entity work.serialize + port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); + + +--raz <= not reset; +Rz <= raz; +SCLK <= not sys_clk; +--Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); +--Data_TOT <= "0001" & Data_Cvec; + +with bp select + Data_int <= X"9555" when '1', + Data_C when others; + +end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd b/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd @@ -0,0 +1,24 @@ +-- Convertisseur_config.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +Package Convertisseur_config is + + +--===========================================================| +--================= Valeurs Sinus 1Khz ======================| +--===========================================================| +type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); +constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); + +--constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); + + +--===========================================================| +--============= Fr�quence de s�rialisation ==================| +--===========================================================| +constant Freq_serial : integer := 1_000_000; +constant nb_serial : integer := 40_000_000 / Freq_serial; + +end; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd b/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd @@ -0,0 +1,94 @@ +-- GeneSYNC_flag.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity GeneSYNC_flag is + +port( + clk,raz : in std_logic; + flag_nw : in std_logic; + Sysclk : in std_logic; + OKAI_send : out std_logic; + SYNC : out std_logic +); + +end GeneSYNC_flag; + + +architecture ar_GeneSYNC_flag of GeneSYNC_flag is + +signal Sysclk_reg : std_logic; +signal flag_nw_reg : std_logic; +signal count : integer; + +type etat is (e0,e1,e2,eX); +signal ect : etat; + +begin + process (clk,raz) + begin + if(raz='0')then + SYNC <= '0'; + Sysclk_reg <= '0'; + flag_nw_reg <= '0'; + count <= 14; + OKAI_send <= '0'; + ect <= e0; + + elsif(clk' event and clk='1')then + Sysclk_reg <= Sysclk; + flag_nw_reg <= flag_nw; + + case ect is + when e0 => + if(flag_nw_reg='0' and flag_nw='1')then + ect <= e1; + else + count <= 14; + ect <= e0; + end if; + + + when e1 => + if(Sysclk_reg='1' and Sysclk='0')then + if(count=15)then + SYNC <= '1'; + count <= count+1; + ect <= e2; + elsif(count=16)then + count <= 0; + OKAI_send <= '1'; + ect <= eX; + else + count <= count+1; + OKAI_send <= '0'; + ect <= e1; + end if; + end if; + + + when e2 => + if(Sysclk_reg='0' and Sysclk='1')then + if(count=16)then + SYNC <= '0'; + ect <= e1; + end if; + end if; + + when eX => + if(Sysclk_reg='0' and Sysclk='1')then + if(count=15)then + OKAI_send <= '0'; + ect <= e0; + else + count <= count+1; + ect <= eX; + end if; + end if; + + end case; + end if; + + end process; +end ar_GeneSYNC_flag; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/Serialize.vhd b/lib/lpp/lpp_CNA_amba/Serialize.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/Serialize.vhd @@ -0,0 +1,86 @@ +-- Serialize.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Serialize is + +port( + clk,raz : in std_logic; + sclk : in std_logic; + vectin : in std_logic_vector(15 downto 0); + send : in std_logic; + sended : out std_logic; + Data : out std_logic); + +end Serialize; + + +architecture ar_Serialize of Serialize is + +type etat is (attente,serialize); +signal ect : etat; + +signal vector_int : std_logic_vector(16 downto 0); +signal vectin_reg : std_logic_vector(15 downto 0); +signal load : std_logic; +signal N : integer range 0 to 16; +signal CPT_ended : std_logic:='0'; + +begin + process(clk,raz) + begin + if(raz='0')then + ect <= attente; + vectin_reg <= (others=> '0'); + load <= '0'; + sended <= '1'; + + elsif(clk'event and clk='1')then + vectin_reg <= vectin; + + case ect is + when attente => + if (send='1') then + sended <= '0'; + load <= '1'; + ect <= serialize; + else + ect <= attente; + end if; + + when serialize => + load <= '0'; + if(CPT_ended='1')then + ect <= attente; + sended <= '1'; + end if; + + end case; + end if; + end process; + + process(sclk,load,raz) + begin + if (raz='0')then + vector_int <= (others=> '0'); + N <= 16; + elsif(load='1')then + vector_int <= vectin & '0'; + N <= 0; + elsif(sclk'event and sclk='0')then + if (CPT_ended='0') then + vector_int <= vector_int(15 downto 0) & '0'; + N <= N+1; + end if; + end if; + end process; + +CPT_ended <= '1' when N = 16 else '0'; + +with ect select + Data <= vector_int(16) when serialize, + '0' when others; + +end ar_Serialize; + diff --git a/lib/lpp/lpp_CNA_amba/clock.vhd b/lib/lpp/lpp_CNA_amba/clock.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/clock.vhd @@ -0,0 +1,41 @@ +-- clock.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + + +entity Clock_Serie is + +generic(N :integer := 695); + +port( + clk, raz : in std_logic ; + clock : out std_logic); + +end Clock_Serie; + + +architecture ar_Clock_Serie of Clock_Serie is + +signal clockint : std_logic; +signal countint : integer range 0 to N/2-1; + +begin + process (clk,raz) + begin + if(raz = '0') then + countint <= 0; + clockint <= '0'; + elsif (clk' event and clk='1') then + if (countint = N/2-1) then + countint <= 0; + clockint <= not clockint; + else + countint <= countint+1; + end if; + end if; + end process; + +clock <= clockint; + +end ar_Clock_Serie; \ No newline at end of file diff --git a/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd b/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +-- pragma translate_off +use std.textio.all; +-- pragma translate_on +library lpp; +use lpp.lpp_amba.all; + + +package lpp_CNA_amba is + + +component APB_CNA is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + SYNC : out std_logic; + SCLK : out std_logic; + DATA : out std_logic + ); +end component; + +end; diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd --- a/lib/lpp/lpp_amba/lpp_amba.vhd +++ b/lib/lpp/lpp_amba/lpp_amba.vhd @@ -38,6 +38,8 @@ constant otherCore : am constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#; constant LPP_MULTI_DIODE : amba_device_type := 16#004#; constant LPP_LCD_CTRLR : amba_device_type := 16#005#; +constant LPP_UART : amba_device_type := 16#006#; +constant LPP_CNA : amba_device_type := 16#007#; component APB_SIMPLE_DIODE is diff --git a/lib/lpp/lpp_uart/APB_UART.vhd b/lib/lpp/lpp_uart/APB_UART.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_uart/APB_UART.vhd @@ -0,0 +1,128 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- APB_UART.vhd + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.lpp_uart.all; + +entity APB_UART is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Data_sz : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + TXD : out std_logic; + RXD : in std_logic + ); +end APB_UART; + + +architecture ar_APB_UART of APB_UART is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +signal NwData : std_logic; +signal ACK : std_logic; +signal Capture : std_logic; +signal Send : std_logic; +signal Sended : std_logic; + +type UART_ctrlr_Reg is record + UART_Cfg : std_logic_vector(4 downto 0); + UART_Wdata : std_logic_vector(7 downto 0); + UART_Rdata : std_logic_vector(7 downto 0); + UART_BTrig : std_logic_vector(11 downto 0); +end record; + +signal Rec : UART_ctrlr_Reg; + +begin + +Capture <= Rec.UART_Cfg(0); +ACK <= Rec.UART_Cfg(1); +Send <= Rec.UART_Cfg(2); +Rec.UART_Cfg(3) <= Sended; +Rec.UART_Cfg(4) <= NwData; + + + COM0 : entity work.UART + generic map (Data_sz) + port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); + + + process(rst,clk) + begin + if(rst='0')then + Rec.UART_Wdata <= (others => '0'); + apbo.prdata <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0); + when "000001" => + Rec.UART_Wdata <= apbi.pwdata(7 downto 0); + when others => + null; + end case; + end if; + + --APB READ OP + if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + apbo.prdata(31 downto 27) <= Rec.UART_Cfg; + apbo.prdata(26 downto 12) <= (others => '0'); + apbo.prdata(11 downto 0) <= Rec.UART_BTrig; + when "000001" => + apbo.prdata(7 downto 0) <= Rec.UART_Wdata; + when "000010" => + apbo.prdata(7 downto 0) <= Rec.UART_Rdata; + when others => + apbo.prdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +end ar_APB_UART; \ No newline at end of file diff --git a/lib/lpp/lpp_uart/BaudGen.vhd b/lib/lpp/lpp_uart/BaudGen.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_uart/BaudGen.vhd @@ -0,0 +1,82 @@ +-- BaudGen.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--! Generateur de Bauds + +entity BaudGen is + +port( + clk : in std_logic; + reset : in std_logic; + Capture : in std_logic; + Bclk : out std_logic; + RXD : in std_logic; + BTrigger : out std_logic_vector(11 downto 0) +); +end BaudGen; + + +architecture ar_BaudGen of BaudGen is +signal cpt : std_logic_vector(11 downto 0) := (others => '0'); +signal errorFlag : std_logic; +signal triger : std_logic_vector(11 downto 0) := (others => '0'); +signal RX_reg : std_logic:='1'; + +begin + + +BTrigger <= triger; + + +BaudGeneration: +process(clk,reset) +begin + if reset = '0' then + cpt <= (others => '0'); + triger <= (others => '1'); + errorFlag <= '0'; + elsif clk'event and clk = '1'then + RX_reg <= RXD; + if capture = '1' then + cpt <= (others => '0'); + triger <= (others => '1'); + errorFlag <= '0'; + else + if RX_reg /= RXD then + cpt <= (others => '0'); + if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then + errorFlag <= '1'; + elsif errorFlag = '1' then + triger <= cpt; + errorFlag <= '0'; + else + errorFlag <= '1'; + end if; + else + if cpt = triger then + cpt <= (others => '0'); + errorFlag <= '0'; + else + cpt <= std_logic_vector(unsigned(cpt) + 1); + end if; + end if; + end if; + end if; +end process; + + +process(clk) +begin + if clk'event and clk = '1' then + if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then + Bclk <= '0'; + elsif cpt = '0' & triger(11 downto 1) then + Bclk <= '1'; + end if; + end if; +end process; + + +end ar_BaudGen; \ No newline at end of file diff --git a/lib/lpp/lpp_uart/Shift_REG.vhd b/lib/lpp/lpp_uart/Shift_REG.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_uart/Shift_REG.vhd @@ -0,0 +1,94 @@ +-- Shift_REG.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--! Gestion Reception/Transmission + +entity Shift_REG is +generic(Data_sz : integer := 10); +port( + clk : in std_logic; + Sclk : in std_logic; + reset : in std_logic; + SIN : in std_logic; + SOUT : out std_logic; + Serialize : in std_logic; + Serialized : out std_logic; + D : in std_logic_vector(Data_sz-1 downto 0); + Q : out std_logic_vector(Data_sz-1 downto 0) + +); +end entity; + + +architecture ar_Shift_REG of Shift_REG is + +signal REG : std_logic_vector(Data_sz-1 downto 0); +signal Serialized_int : std_logic; +signal Serialize_reg : std_logic; +signal CptBits : std_logic_vector(Data_sz-1 downto 0); +constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); +signal CptBits_flag : std_logic; +signal CptBits_flag_reg : std_logic; + +begin + +Serialized <= Serialized_int; +CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; + +process(reset,clk) +begin + if reset = '0' then + Serialized_int <= '1'; + CptBits_flag_reg <= '0'; + Q <= (others => '0'); + elsif clk'event and clk = '1' then + CptBits_flag_reg <= CptBits_flag; + + if CptBits_flag = '1' and CptBits_flag_reg = '0' then + Serialized_int <= '1'; + Q <= REG; + elsif Serialize = '1' then + Serialized_int <= '0'; + end if; + end if; +end process; + + +process(reset,Sclk) +begin + if reset = '0' then + CptBits <= (others => '0'); + REG <= (others => '0'); + SOUT <= '1'; + Serialize_reg <= '0'; + elsif Sclk'event and Sclk = '1' then + Serialize_reg <= Serialized_int; + if (Serialized_int = '0' and Serialize_reg ='1') then + REG <= SIN & D(Data_sz-1 downto 1); + SOUT <= D(0); + elsif CptBits_flag ='1' then + REG <= SIN & D(Data_sz-1 downto 1); + SOUT <= D(0); + elsif Serialized_int = '0' then + REG <= SIN & REG(Data_sz-1 downto 1); + SOUT <= REG(0); + else + SOUT <= '1'; + end if; + if Serialized_int = '0' then + if CptBits_flag = '1' then + CptBits <= (others => '0'); + else + CptBits <= '1' & CptBits(Data_sz-1 downto 1); + end if; + + else + CptBits <= (others => '0'); + end if; + + end if; +end process; + +end ar_Shift_REG; \ No newline at end of file diff --git a/lib/lpp/lpp_uart/UART.vhd b/lib/lpp/lpp_uart/UART.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_uart/UART.vhd @@ -0,0 +1,81 @@ +-- UART.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +library lpp; +use lpp.lpp_uart.all; + +--! Programme qui va gerer toute la communication entre le PC et le FPGA + +entity UART is +generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee +port( + clk : in std_logic; --! Horloge a 25Mhz du systeme + reset : in std_logic; --! Reset du systeme + TXD : out std_logic; --! Transmission, cote PC + RXD : in std_logic; --! Reception, cote PC + Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global + NwDat : out std_logic; --! Flag, Nouvelle donnee presente + ACK : in std_logic; --! Flag, Reponse au flag precedent + Send : in std_logic; --! Flag, Demande d'envoi sur le bus + Sended : out std_logic; --! Flag, Envoi termine + BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission + RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur + WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur +); +end entity; + + +--! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation +--! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds) +architecture ar_UART of UART is +signal Bclk : std_logic; + +signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); +signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); + +signal TXD_Dummy : std_logic; +signal NwDat_int : std_logic; +signal NwDat_int_reg : std_logic; +signal receive : std_logic; + +begin + + +RDATA <= RDATA_int(8 downto 1); +WDATA_int <= '1' & WDATA & '0'; + +BaudGenerator : BaudGen + port map(clk,reset,Capture,Bclk,RXD,BTrigger); + + +RX_REG : Shift_REG + generic map(Data_sz+2) + port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,(others => '0'),RDATA_int); + +TX_REG : Shift_REG + generic map(Data_sz+2) + port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); + + + +process(clk,reset) +begin + if reset = '0' then + NwDat <= '0'; + elsif clk'event and clk = '1' then + NwDat_int_reg <= NwDat_int; + if RXD = '1' and NwDat_int = '1' then + receive <= '0'; + elsif RXD = '0' then + receive <= '1'; + end if; + if NwDat_int_reg = '0' and NwDat_int = '1' then + NwDat <= '1'; + elsif ack = '1' then + NwDat <= '0'; + end if; + end if; +end process; + +end ar_UART; \ No newline at end of file diff --git a/lib/lpp/lpp_uart/lpp_uart.vhd b/lib/lpp/lpp_uart/lpp_uart.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_uart/lpp_uart.vhd @@ -0,0 +1,79 @@ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +-- pragma translate_off +use std.textio.all; +-- pragma translate_on +library lpp; +use lpp.lpp_amba.all; + +package lpp_uart is + +component UART is +generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee +port( + clk : in std_logic; --! Horloge a 25Mhz du systeme + reset : in std_logic; --! Reset du systeme + TXD : out std_logic; --! Transmission, cote PC + RXD : in std_logic; --! Reception, cote PC + Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global + NwDat : out std_logic; --! Flag, Nouvelle donnee presente + ACK : in std_logic; --! Flag, Reponse au flag precedent + Send : in std_logic; --! Flag, Demande d'envoi sur le bus + Sended : out std_logic; --! Flag, Envoi termine + BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission + RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur + WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur +); +end component; + + +component Shift_REG is +generic(Data_sz : integer := 10); +port( + clk : in std_logic; + Sclk : in std_logic; + reset : in std_logic; + SIN : in std_logic; + SOUT : out std_logic; + Serialize : in std_logic; + Serialized : out std_logic; + D : in std_logic_vector(Data_sz-1 downto 0); + Q : out std_logic_vector(Data_sz-1 downto 0) + +); +end component; + + +component BaudGen is +port( + clk : in std_logic; + reset : in std_logic; + Capture : in std_logic; + Bclk : out std_logic; + RXD : in std_logic; + BTrigger : out std_logic_vector(11 downto 0) +); +end component; + +component APB_UART is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + Data_sz : integer := 8); + port ( + clk : in std_logic; + rst : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + TXD : out std_logic; + RXD : in std_logic + ); +end component; + + +end lpp_uart; \ No newline at end of file