# HG changeset patch # User pellion # Date 2013-07-22 08:35:42 # Node ID afe160da72479e40a308d17a323257cd3a28ccc1 # Parent b4f5e14be4912ab1ee1c0a9ba9f7f3c6a45b06ff EM Design : GRSPW 2 ports, WFP, FILTER, BW/SP/R OK (Redmine : 2013-07-22-leon3mp-grspw-wfrm.pdb) diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc b/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/Makefile.inc @@ -0,0 +1,19 @@ +PACKAGE=\"\" +SPEED=Std +SYNFREQ=50 + +TECHNOLOGY=ProASIC3E +LIBERO_DIE=IT14X14M4 +PART=A3PE3000 + +DESIGNER_VOLTAGE=COM +DESIGNER_TEMP=COM +DESIGNER_PACKAGE=FBGA +DESIGNER_PINS=324 + +MANUFACTURER=Actel +MGCTECHNOLOGY=Proasic3 +MGCPART=$(PART) +MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} +LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/data/em-LeonLPP-A3PE3kL.pdc.ce b/boards/em-LeonLPP-A3PE3kL-v3-core1/data/em-LeonLPP-A3PE3kL.pdc.ce new file mode 100644 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..85dbcbf26f6540f534dc69937df1526dcfa0dc5a GIT binary patch literal 803 zc$^FHW@Zs#U|`^2a1i$3)Xm)H8^XlE;3UMrzzh@(aB-eGBRc<eVzP>5arny)D%N;+F*r$E7_@2O}<;K>(-@b90C-VF7MKAmO zb%*~}WPP2-pDFd%XU&HEulr=LZ1I|7zOBlbdQrB*}KOTMg0smFChw{1R4N z`M3?{`-IQ^k9p9U)i-5LKC}5NgQa%-g&{5#y7#q?ySqxsT;Fwitx{r4p5&#YDof-%7T&$I9k}v^d>9t0rxN z9h;nr+ukUztd5)$Sdihi(Ah_okNe(Q<71V}KQ<|wU1gkjjnQ$D$C)5m@xVm~{hU>k zURl}wI=$qZ;nYln6I&Ly)jF%O@oq?XwrIme=S7G0PJG#@{B>@vSJEDz>8CE33n+!3 zYTeh!TWfu9)6PGJ|3m-GnEyiQ{DX`vZ}AZKJ!-vg_@}<~m~^V-X`YenEk(Itp@aGK_ueP?BW zBsgv$j`9qM4|5F)_Vo8NzG4hagx-w6B#Aqbf&e1}3;>fXvIcAxAT*RRp;#B-&B_K6 OW&*-2AibCg!~*~nY(WnI diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/default.sdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/default.sdc new file mode 100644 --- /dev/null +++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/default.sdc @@ -0,0 +1,59 @@ +# Synplicity, Inc. constraint file +# /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc +# Written on Wed Aug 1 19:29:24 2007 +# by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor + +# +# Collections +# + +# +# Clocks +# +define_clock {clk} -name {clk} -freq 60 -clockgroup default_clkgroup -route 5 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# +define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} +define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r} + + +# +# Registers +# + +# +# Multicycle Path +# + +# +# False Path +# + +# +# Path Delay +# + +# +# Attributes +# +define_global_attribute syn_useioff {1} +define_global_attribute -disable syn_netlist_hierarchy {0} +define_attribute {etx_clk} syn_noclockbuf {1} + +# +# I/O standards +# + +# +# Compile Points +# + +# +# Other Constraints +# diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc new file mode 100644 --- /dev/null +++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL.pdc @@ -0,0 +1,117 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname N18 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout + +set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout +set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout +set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout +set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout +set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout + +set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout +set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout +set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout + +set_io ahbtxd -pinname J12 -fixed yes -DIRECTION Inout +#set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout +set_io ahbrxd -pinname L16 -fixed yes -DIRECTION Inout +#set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout +set_io urxd1 -pinname M16 -fixed yes -DIRECTION Inout +set_io utxd1 -pinname L13 -fixed yes -DIRECTION Inout +set_io errorn -pinname P6 -fixed yes -DIRECTION Inout +#set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout diff --git a/designs/em-2013-07-22-vhdlib202/.config b/designs/em-2013-07-22-vhdlib202/.config new file mode 100644 --- /dev/null +++ b/designs/em-2013-07-22-vhdlib202/.config @@ -0,0 +1,288 @@ +# +# Automatically generated make config: don't edit +# + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +CONFIG_SYN_PROASIC3=y +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_SPARTAN2 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_VIRTEX is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_UMC is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +CONFIG_CLK_PRO3PLL=y +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_CLKDLL is not set +# CONFIG_CLK_DCM is not set +CONFIG_CLK_MUL=2 +CONFIG_CLK_DIV=8 +CONFIG_OCLK_DIV=2 +# CONFIG_PCI_SYSCLK is not set +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 + +# +# Processor +# + +# +# Integer unit +# +CONFIG_IU_NWINDOWS=8 +# CONFIG_IU_V8MULDIV is not set +# CONFIG_IU_SVT is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=0 +# CONFIG_PWD is not set +CONFIG_IU_RSTADDR=00000 + +# +# Floating-point unit +# +# CONFIG_FPU_ENABLE is not set + +# +# Cache system +# +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO1=y +# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO3 is not set +# CONFIG_ICACHE_ASSO4 is not set +# CONFIG_ICACHE_SZ1 is not set +# CONFIG_ICACHE_SZ2 is not set +CONFIG_ICACHE_SZ4=y +# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ16 is not set +# CONFIG_ICACHE_SZ32 is not set +# CONFIG_ICACHE_SZ64 is not set +# CONFIG_ICACHE_SZ128 is not set +# CONFIG_ICACHE_SZ256 is not set +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO1=y +# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO3 is not set +# CONFIG_DCACHE_ASSO4 is not set +# CONFIG_DCACHE_SZ1 is not set +# CONFIG_DCACHE_SZ2 is not set +CONFIG_DCACHE_SZ4=y +# CONFIG_DCACHE_SZ8 is not set +# CONFIG_DCACHE_SZ16 is not set +# CONFIG_DCACHE_SZ32 is not set +# CONFIG_DCACHE_SZ64 is not set +# CONFIG_DCACHE_SZ128 is not set +# CONFIG_DCACHE_SZ256 is not set +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_SNOOP is not set +CONFIG_CACHE_FIXED=0 + +# +# MMU +# +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +# CONFIG_MMU_REPARRAY is not set +CONFIG_MMU_REPINCREMENT=y +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set + +# +# Debug Support Unit +# +# CONFIG_DSU_ENABLE is not set + +# +# Fault-tolerance +# + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +# CONFIG_DSU_JTAG is not set + +# +# Peripherals +# + +# +# Memory controllers +# + +# +# 8/32-bit PROM/SRAM controller +# +CONFIG_SRCTRL=y +# CONFIG_SRCTRL_8BIT is not set +CONFIG_SRCTRL_PROMWS=3 +CONFIG_SRCTRL_RAMWS=0 +CONFIG_SRCTRL_IOWS=0 +# CONFIG_SRCTRL_RMW is not set +CONFIG_SRCTRL_SRBANKS1=y +# CONFIG_SRCTRL_SRBANKS2 is not set +# CONFIG_SRCTRL_SRBANKS3 is not set +# CONFIG_SRCTRL_SRBANKS4 is not set +# CONFIG_SRCTRL_SRBANKS5 is not set +# CONFIG_SRCTRL_BANKSZ0 is not set +# CONFIG_SRCTRL_BANKSZ1 is not set +# CONFIG_SRCTRL_BANKSZ2 is not set +# CONFIG_SRCTRL_BANKSZ3 is not set +# CONFIG_SRCTRL_BANKSZ4 is not set +# CONFIG_SRCTRL_BANKSZ5 is not set +# CONFIG_SRCTRL_BANKSZ6 is not set +# CONFIG_SRCTRL_BANKSZ7 is not set +# CONFIG_SRCTRL_BANKSZ8 is not set +# CONFIG_SRCTRL_BANKSZ9 is not set +# CONFIG_SRCTRL_BANKSZ10 is not set +# CONFIG_SRCTRL_BANKSZ11 is not set +# CONFIG_SRCTRL_BANKSZ12 is not set +# CONFIG_SRCTRL_BANKSZ13 is not set +CONFIG_SRCTRL_ROMASEL=19 + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +# CONFIG_MCTRL_8BIT is not set +# CONFIG_MCTRL_16BIT is not set +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# PC133 SDRAM controller +# +# CONFIG_SDCTRL is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +# CONFIG_AHBRAM_ENABLE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# CAN +# +# CONFIG_CAN_ENABLE is not set + +# +# PCI +# +# CONFIG_PCI_SIMPLE_TARGET is not set +# CONFIG_PCI_MASTER_TARGET is not set +# CONFIG_PCI_ARBITER is not set +# CONFIG_PCI_TRACE is not set + +# +# Spacewire +# +# CONFIG_SPW_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +CONFIG_UA1_FIFO4=y +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +# CONFIG_UA1_FIFO32 is not set +# CONFIG_UART2_ENABLE is not set +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=8 +CONFIG_GRGPIO_IMASK=0000 + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/em-2013-07-22-vhdlib202/Makefile b/designs/em-2013-07-22-vhdlib202/Makefile new file mode 100644 --- /dev/null +++ b/designs/em-2013-07-22-vhdlib202/Makefile @@ -0,0 +1,49 @@ +GRLIB=../.. +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES=config.vhd leon3mp.vhd +#VHDLSIMFILES=testbench.vhd +#SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./dsp/lpp_fft \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_demux \ + ./lpp_matrix \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_Header \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/em-2013-07-22-vhdlib202/config.vhd b/designs/em-2013-07-22-vhdlib202/config.vhd new file mode 100644 --- /dev/null +++ b/designs/em-2013-07-22-vhdlib202/config.vhd @@ -0,0 +1,182 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + + +-- Technology and synthesis options + constant CFG_FABTECH : integer := apa3e; + constant CFG_MEMTECH : integer := apa3e; + constant CFG_PADTECH : integer := inferred; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; + +-- Clock generator + constant CFG_CLKTECH : integer := inferred; + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + --constant CFG_NWIN : integer := (7); -- PLE + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist + --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DFIXED : integer := 16#00F3#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; + +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- DSU UART + constant CFG_AHB_UART : integer := 1; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#00007A#; + constant CFG_ETH_ENL : integer := 16#CC0001#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- SSRAM controller + constant CFG_SSCTRL : integer := 0; + constant CFG_SSCTRLP16 : integer := 0; + +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := 0; + constant CFG_AHBRSZ : integer := 1; + constant CFG_AHBRADDR : integer := 16#A00#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; + constant CFG_CANIO : integer := 16#0#; + constant CFG_CANIRQ : integer := 0; + constant CFG_CANLOOP : integer := 0; + constant CFG_CAN_SYNCRST : integer := 0; + constant CFG_CANFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (3); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + + +end; diff --git a/designs/em-2013-07-22-vhdlib202/leon3mp.vhd b/designs/em-2013-07-22-vhdlib202/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/designs/em-2013-07-22-vhdlib202/leon3mp.vhd @@ -0,0 +1,542 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +--use lpp.lpp_amba.all; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +--use lpp.lpp_uart.all; +--use lpp.lpp_matrix.all; +--use lpp.lpp_delay.all; +--use lpp.lpp_fft.all; +--use lpp.fft_components.all; +use lpp.iir_filter.all; +USE lpp.general_purpose.ALL; +--use lpp.Filtercfg.all; +USE lpp.lpp_lfr_time_management.ALL; -- PLE +--use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE + +ENTITY leon3mp IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + spw2_din : IN STD_LOGIC; -- JCPE --TODO + spw2_sin : IN STD_LOGIC; -- JCPE --TODO + spw2_dout : OUT STD_LOGIC; -- JCPE --TODO + spw2_sout : OUT STD_LOGIC; -- JCPE --TODO + + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + + --------------------------------------------------------------------------- + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF leon3mp IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART+ + CFG_GRETH+ + CFG_AHB_JTAG + +2; -- 1 is for the SpaceWire module grspw2, which is a master + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst g�n� + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL resetnl : STD_ULOGIC; + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- time management signal + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + signal spw_rxtxclk : std_ulogic; + signal spw_rxclkn : std_ulogic; + SIGNAL spw_clk : std_logic; + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + spw_clk <= lclk50MHz; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + led(2) <= dsuo.active; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) + PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + led(0) <= NOT ahbuarti.rxd; + led(1) <= NOT ahbuarto.txd; + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + lfrtimemanagement0 : apb_lfr_time_management + GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#, + masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536, + pirq => 12) + PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6), + coarse_time, fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + spw_rxtxclk <= spw_clk; + spw_rxclkn <= not spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad generic map (tech => padtech) + port map (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad generic map (tech => padtech) + port map (spw1_sin, stmp(0)); + spw1_txd_pad : outpad generic map (tech => padtech) + port map (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad generic map (tech => padtech) + port map (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad generic map (tech => padtech) + port map (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad generic map (tech => padtech) + port map (spw2_sin, stmp(1)); + spw2_txd_pad : outpad generic map (tech => padtech) + port map (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad generic map (tech => padtech) + port map (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop: for j in 0 to 1 generate + spw_phy0 : grspw_phy + generic map( + tech => fabtech, + rxclkbuftype => 1, + scantest => 0) + port map( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 downto j*5), + dconnect => swni.dconnect(j*2+1 downto j*2)); + end generate spw_inputloop; + + -- SPW core + sw0 : grspwm generic map( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + port map(rstn, clkm, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbmi, ahbmo(1), apbi, apbo(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (others => '0'); + swni.dcrstval <= (others => '0'); + swni.timerrstval <= (others => '0'); + +------------------------------------------------------------------------------- +-- WAVEFORM PICKER +------------------------------------------------------------------------------- + waveform_picker0 : top_wf_picker + GENERIC MAP( + hindex => 2, + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq => 14, + tech => CFG_FABTECH, + nb_burst_available_size => 12, -- size of the register holding the nb of burst + nb_snapshot_param_size => 12, -- size of the register holding the snapshots size + delta_snapshot_size => 16, -- snapshots period + delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts + delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot + ENABLE_FILTER => '1' + ) + PORT MAP( + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + -- + cnv_clk => clkm, + cnv_rstn => rstn, + -- AMBA AHB system signals + HCLK => clkm, + HRESETn => rstn, + -- AMBA APB Slave Interface + apbi => apbi, + apbo => apbo(15), + -- AMBA AHB Master Interface + AHB_Master_In => ahbmi, + AHB_Master_Out => ahbmo(2), + -- + coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time + -- + data_shaping_BW => bias_fail_sw + ); + + top_ad_conv_RHF1401_1: top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + + cnv => ADC_smpclk, + + clk => clkm, + rstn => rstn, + ADC_data => ADC_data, + --ADC_smpclk => , + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + + -- ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1 + -- ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2 + -- ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3 + + -- ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1 + -- ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2 + -- ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3 + -- ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4 + -- ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5 + +END Behavioral; \ No newline at end of file