# HG changeset patch
# User martin
# Date 2013-04-23 10:42:44
# Node ID afd41c98ea9b548a6702902eee1fa5b532af5b31
# Parent  2d172732dabf249965a4307e7049ef95595558f2

Modif demux + Partage pour recherche de bug

diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd b/lib/lpp/dsp/lpp_fft/FFT.vhd
--- a/lib/lpp/dsp/lpp_fft/FFT.vhd
+++ b/lib/lpp/dsp/lpp_fft/FFT.vhd
@@ -22,9 +22,10 @@
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
-library lpp;
+use work.fft_components.all;
 use lpp.lpp_fft.all;
-use work.fft_components.all;
+
+-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
 
 entity FFT is
     generic(
@@ -36,6 +37,7 @@ entity FFT is
         FifoIN_Empty    : in std_logic_vector(4 downto 0);
         FifoIN_Data     : in std_logic_vector(79 downto 0);
         FifoOUT_Full    : in std_logic_vector(4 downto 0);
+        Load            : out std_logic;
         Read            : out std_logic_vector(4 downto 0);
         Write           : out std_logic_vector(4 downto 0);
         ReUse           : out std_logic_vector(4 downto 0);
@@ -62,6 +64,7 @@ signal Link_Read        : std_logic;
 begin
 
 Start <= '0';
+Load <= FFT_Load;
 
     DRIVE : Driver_FFT
         generic map(Data_sz,NbData)
diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
--- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
+++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd
@@ -84,6 +84,7 @@ component FFT is
         FifoIN_Empty    : in std_logic_vector(4 downto 0);
         FifoIN_Data     : in std_logic_vector(79 downto 0);
         FifoOUT_Full    : in std_logic_vector(4 downto 0);
+        Load            : out std_logic;
         Read            : out std_logic_vector(4 downto 0);
         Write           : out std_logic_vector(4 downto 0);
         ReUse           : out std_logic_vector(4 downto 0);
diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd
--- a/lib/lpp/leon3mp.vhd
+++ b/lib/lpp/leon3mp.vhd
@@ -98,14 +98,14 @@ entity leon3mp is
     UART_RXD : in std_logic;
     UART_TXD : out std_logic;
 -- ACQ
-    Clk_49Mhz   : IN  STD_LOGIC;
     CNV_CH1     : OUT STD_LOGIC;
     SCK_CH1     : OUT STD_LOGIC;
     SDO_CH1     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    Bias_Fails  : out std_logic;
 -- ADC
 --    ADC_in  : in AD7688_in(4 downto 0);
 --    ADC_out : out AD7688_out;
---    Bias_Fails : out std_logic;
+
 -- CNA
 --    DAC_SYNC : out std_logic;
 --    DAC_SCLK : out std_logic;
@@ -177,25 +177,17 @@ signal dsuo     : dsu_out_type;
 ---  AJOUT TEST ------------------------Signaux----------------------
 ---------------------------------------------------------------------
 -- FIFOs
-signal FifoF0a_Full      : std_logic_vector(4 downto 0);
-signal FifoF0a_Empty     : std_logic_vector(4 downto 0);
-signal FifoF0a_Data      : std_logic_vector(79 downto 0);
-signal FifoF0b_Full      : std_logic_vector(4 downto 0);
-signal FifoF0b_Empty     : std_logic_vector(4 downto 0);
-signal FifoF0b_Data      : std_logic_vector(79 downto 0);
-signal FifoF1_Full      : std_logic_vector(4 downto 0);
+signal FifoF0_Empty     : std_logic_vector(4 downto 0);
+signal FifoF0_Data      : std_logic_vector(79 downto 0);
 signal FifoF1_Empty     : std_logic_vector(4 downto 0);
 signal FifoF1_Data      : std_logic_vector(79 downto 0);
-signal FifoF3_Full      : std_logic_vector(4 downto 0);
 signal FifoF3_Empty     : std_logic_vector(4 downto 0);
 signal FifoF3_Data      : std_logic_vector(79 downto 0);
 
 signal FifoINT_Full     : std_logic_vector(4 downto 0);
 signal FifoINT_Data     : std_logic_vector(79 downto 0);
 
---signal FifoOUT_FullV    : std_logic;
 signal FifoOUT_Full     : std_logic_vector(1 downto 0);
---signal Matrix_WriteV    : std_logic_vector(0 downto 0);
 
 -- MATRICE SPECTRALE
 signal SM_FlagError : std_logic;
@@ -207,19 +199,23 @@ signal SM_Data      : std_logic_vector(6
 signal Dma_acq      : std_logic;
 
 -- FFT
+signal FFT_Load        : std_logic;
 signal FFT_Read        : std_logic_vector(4 downto 0);
 signal FFT_Write       : std_logic_vector(4 downto 0);
 signal FFT_ReUse       : std_logic_vector(4 downto 0);
 signal FFT_Data        : std_logic_vector(79 downto 0);
 
 -- DEMUX
-signal DEMU_Read    : std_logic_vector(19 downto 0);
+signal DEMU_Read    : std_logic_vector(14 downto 0);
 signal DEMU_Empty   : std_logic_vector(4 downto 0);
 signal DEMU_Data    : std_logic_vector(79 downto 0);
 
 -- ACQ
-signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
-signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+signal sample_val : STD_LOGIC;
+signal sample : Samples(8-1 DOWNTO 0);
+
+signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
@@ -311,7 +307,7 @@ led(1 downto 0) <= gpio(1 downto 0);
 --        port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
 --
 --enableADC <= gpio(0);
---Bias_Fails <= '0';
+
 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
 --
 --
@@ -319,32 +315,68 @@ led(1 downto 0) <= gpio(1 downto 0);
 --        generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
 --        port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
     
-    TopACQ : lpp_top_acq
-        port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
+  DIGITAL_acquisition : ADS7886_drvr
+    GENERIC MAP (
+      ChanelCount     => 8,
+      ncycle_cnv_high => 79,
+      ncycle_cnv      => 500)
+    PORT MAP (
+      cnv_clk    => clk50MHz,                      -- 
+      cnv_rstn   => rstn,                     -- 
+      cnv_run    => '1',                      --
+      cnv        => CNV_CH1,                          -- 
+      clk        => clkm,                          -- 
+      rstn       => rstn,                         -- 
+      sck        => SCK_CH1,                          -- 
+      sdo        => SDO_CH1,  -- 
+      sample     => sample,
+      sample_val => sample_val);
+--
+TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
+TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0);
+--
+TEST(0) <= TopACQ_WenF0(1);
+TEST(1) <= SDO_CH1(1);
+--
+--
+--
+--process(clkm,rstn)
+--begin
+--      if(rstn='0')then
+--        TopACQ_WenF0a <= (others => '1');
+--            
+--        elsif(clkm'event and clkm='1')then
+--            TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
+--
+--    end if;
+--end process;
 
+--    TopACQ : lpp_top_acq
+--        port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
+
+Bias_Fails <= '0';    
 --- FIFO IN -------------------------------------------------------------
 
-    Memf0a : lppFIFOxN
-        generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
+    MemOut : APB_FIFO
+        generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
+        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
+--    Memf0 : lppFIFOxN
+--        generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
+--        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
     
-    Memf0b : lppFIFOxN
-        generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
-
     Memf1 : lppFIFOxN
-        generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
+        generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
+        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
     
     Memf3 : lppFIFOxN
-        generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
-        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
+        generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
+        port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
 
 --- DEMUX -------------------------------------------------------------
 
-    DEMUX0 : Demultiplex
+    DEMU0 : DEMUX
         generic map(Data_sz => 16)
-        port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
+        port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
 
 --- FFT -------------------------------------------------------------
     
@@ -354,18 +386,18 @@ led(1 downto 0) <= gpio(1 downto 0);
 
     FFT0 : FFT
         generic map(Data_sz => 16,NbData => 256)
-        port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
+        port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
 
 ----- LINK MEMORY -------------------------------------------------------
 
 --    MemOut : APB_FIFO
 --        generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
---        port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
+--        port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
 
     MemInt : lppFIFOxN
         generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
         port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
-
+--
 --    MemIn : APB_FIFO
 --        generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
 --        port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
@@ -378,9 +410,9 @@ led(1 downto 0) <= gpio(1 downto 0);
 
 Dma_acq <= '1';
 
-    MemOut : APB_FIFO
-        generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
-        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
+--    MemOut : APB_FIFO
+--        generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
+--        port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
 
 ----- FIFO -------------------------------------------------------------
 
diff --git a/lib/lpp/lpp_demux/DEMUX.vhd b/lib/lpp/lpp_demux/DEMUX.vhd
--- a/lib/lpp/lpp_demux/DEMUX.vhd
+++ b/lib/lpp/lpp_demux/DEMUX.vhd
@@ -31,19 +31,17 @@ port(
     rstn   :   in std_logic;
 
     Read : in std_logic_vector(4 downto 0);
-    DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
+    Load : in std_logic;
 
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
+    EmptyF0    :   in std_logic_vector(4 downto 0);
     EmptyF1     :   in std_logic_vector(4 downto 0);
     EmptyF2     :   in std_logic_vector(4 downto 0);
 
-    DataF0a     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF0b     :   in std_logic_vector((5*Data_sz)-1 downto 0);
+    DataF0     :   in std_logic_vector((5*Data_sz)-1 downto 0);
     DataF1      :   in std_logic_vector((5*Data_sz)-1 downto 0);
     DataF2      :   in std_logic_vector((5*Data_sz)-1 downto 0);
 
-    Read_DEMUX : out std_logic_vector(19 downto 0);
+    Read_DEMUX : out std_logic_vector(14 downto 0);
     Empty   :   out std_logic_vector(4 downto 0);
     Data    :   out std_logic_vector((5*Data_sz)-1 downto 0)
 );
@@ -55,9 +53,8 @@ architecture ar_DEMUX of DEMUX is
 type etat is (eX,e0,e1,e2,e3);
 signal ect : etat;
 
-signal pong : std_logic;
 
-signal DataCpt_reg : std_logic_vector(3 downto 0);
+signal load_reg : std_logic;
 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
 
 signal Countf0 : integer;
@@ -68,61 +65,40 @@ begin
     begin
         if(rstn='0')then
             ect <= e0;
-            pong <= '0';
-            Countf0 <= 1;
+            load_reg <= '0';
+            Countf0 <= 5;
             Countf1 <= 0;
 
         elsif(clk'event and clk='1')then
-            DataCpt_reg <= DataCpt;
+            load_reg <= Load;
 
             case ect is
 
                 when e0 =>
-                    if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then
-                        pong <= not pong;
-                        if(Countf0 = 5)then
+                    if(load_reg = '1' and Load = '0')then
+                        if(Countf0 = 24)then
                             Countf0 <= 0;
-                            ect <= e2;
+                            ect <= e1;
                         else
                             Countf0 <= Countf0 + 1;
-                            ect <= e1;
+                            ect <= e0;
                         end if;
                     end if;                        
 
                 when e1 =>
-                    if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then
-                        pong <= not pong;
-                        if(Countf0 = 5)then
-                            Countf0 <= 0;
+                    if(load_reg = '1' and Load = '0')then
+                        if(Countf1 = 74)then
+                            Countf1 <= 0;
                             ect <= e2;
                         else
-                            Countf0 <= Countf0 + 1;
+                            Countf1 <= Countf1 + 1;
                             ect <= e0;
                         end if;
                     end if;  
 
                 when e2 =>
-                    if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then
-                        if(Countf1 = 15)then
-                            Countf1 <= 0;
-                            ect <= e3;
-                        else
-                            Countf1 <= Countf1 + 1;
-                            if(pong = '0')then
-                                ect <= e0;
-                            else
-                                ect <= e1;
-                            end if;
-                        end if;
-                    end if;  
-
-                when e3 =>
-                    if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then
-                        if(pong = '0')then
-                            ect <= e0;
-                        else
-                            ect <= e1;
-                        end if;
+                    if(load_reg = '1' and Load = '0')then
+                        ect <= e0;
                     end if;                
                 
                 when others =>
@@ -133,29 +109,23 @@ begin
     end process;
 
 with ect select
-    Empty      <=   EmptyF0a when e0,
-                    EmptyF0b when e1,
-                    EmptyF1 when e2,
-                    EmptyF2 when e3,
+    Empty      <=   EmptyF0 when e0,
+                    EmptyF1 when e1,
+                    EmptyF2 when e2,
                     (others => '1') when others;
 
 with ect select
-    Data      <=    DataF0a when e0,
-                    DataF0b when e1,
-                    DataF1 when e2,
-                    DataF2 when e3,
+    Data      <=    DataF0 when e0,
+                    DataF1 when e1,
+                    DataF2 when e2,
                     (others => '0') when others;
 
 with ect select
-    Read_DEMUX  <=  Dummy_Read & Dummy_Read & Dummy_Read & Read when e0,
-                    Dummy_Read & Dummy_Read & Read & Dummy_Read when e1,
-                    Dummy_Read & Read & Dummy_Read & Dummy_Read when e2,
-                    Read & Dummy_Read & Dummy_Read & Dummy_Read when e3,
+    Read_DEMUX  <=  Dummy_Read & Dummy_Read & Read when e0,
+                    Dummy_Read & Read & Dummy_Read when e1,
+                    Read & Dummy_Read & Dummy_Read when e2,
                     (others => '1') when others;
 
-
-
-
 end architecture;
 
 
diff --git a/lib/lpp/lpp_demux/Demultiplex.vhd b/lib/lpp/lpp_demux/Demultiplex.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_demux/Demultiplex.vhd
+++ /dev/null
@@ -1,87 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library lpp;
-use lpp.lpp_demux.all;
-
-entity Demultiplex is
-generic(
-    Data_sz        :   integer range 1 to 32 := 16);
-port(
-    clk    :   in std_logic;
-    rstn   :   in std_logic;
-
-    Read : in std_logic_vector(4 downto 0);
-
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
-    EmptyF1     :   in std_logic_vector(4 downto 0);
-    EmptyF2     :   in std_logic_vector(4 downto 0);
-
-    DataF0a     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF0b     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF1      :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF2      :   in std_logic_vector((5*Data_sz)-1 downto 0);
-
-    Read_DEMUX : out std_logic_vector(19 downto 0);
-    Empty   :   out std_logic_vector(4 downto 0);
-    Data    :   out std_logic_vector((5*Data_sz)-1 downto 0)
-);
-end entity;
-
-
-architecture ar_Demultiplex of Demultiplex is
-
-signal DataCpt      : std_logic_vector(3 downto 0);
-
-begin
-
-    FLG0 : WatchFlag
-        port map(clk,rstn,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataCpt);
-
-    DEM : DEMUX
-        generic map(Data_sz)
-        port map(clk,rstn,Read,DataCpt,EmptyF0a,EmptyF0b,EmptyF1,EmptyF2,DataF0a,DataF0b,DataF1,DataF2,Read_DEMUX,Empty,Data);
-
-end architecture;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/lpp/lpp_demux/WatchFlag.vhd b/lib/lpp/lpp_demux/WatchFlag.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_demux/WatchFlag.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity WatchFlag is
-port(
-    clk    :   in std_logic;
-    rstn   :   in std_logic;
-
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
-    EmptyF1     :   in std_logic_vector(4 downto 0);
-    EmptyF2     :   in std_logic_vector(4 downto 0);
-
-    DataCpt     :   out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
-);
-end entity;
-
-
-architecture ar_WatchFlag of WatchFlag is
-
-constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
-constant OneToSet : std_logic_vector(4 downto 0) := "01111";
-
-begin
-    process(clk,rstn)
-    begin
-        if(rstn='0')then
-            DataCpt <= (others => '0');
-
-        elsif(clk'event and clk='1')then
-           
-            if(EmptyF0a = OneToSet)then
-                DataCpt(0) <= '1';
-            elsif(EmptyF0a = FlagSet)then
-                DataCpt(0) <= '0';
-            end if;
-
-            if(EmptyF0b = OneToSet)then
-                DataCpt(1) <= '1';
-            elsif(EmptyF0b = FlagSet)then
-                DataCpt(1) <= '0';
-            end if;
-
-            if(EmptyF1 = OneToSet)then
-                DataCpt(2) <= '1';
-            elsif(EmptyF1 = FlagSet)then
-                DataCpt(2) <= '0';
-            end if;
-
-            if(EmptyF2 = OneToSet)then
-                DataCpt(3) <= '1';
-            elsif(EmptyF2 = FlagSet)then
-                DataCpt(3) <= '0';
-            end if;
-
-        end if;
-    end process;
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_demux/lpp_demux.vhd b/lib/lpp/lpp_demux/lpp_demux.vhd
--- a/lib/lpp/lpp_demux/lpp_demux.vhd
+++ b/lib/lpp/lpp_demux/lpp_demux.vhd
@@ -29,34 +29,7 @@ use lpp.lpp_amba.all;
 
 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on 
 
-package lpp_demux is
-
-
-component Demultiplex is
-generic(
-    Data_sz        :   integer range 1 to 32 := 16);
-port(
-    clk    :   in std_logic;
-    rstn   :   in std_logic;
-
-    Read : in std_logic_vector(4 downto 0);
-
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
-    EmptyF1     :   in std_logic_vector(4 downto 0);
-    EmptyF2     :   in std_logic_vector(4 downto 0);
-
-    DataF0a     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF0b     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF1      :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF2      :   in std_logic_vector((5*Data_sz)-1 downto 0);
-
-    Read_DEMUX : out std_logic_vector(19 downto 0);
-    Empty   :   out std_logic_vector(4 downto 0);
-    Data    :   out std_logic_vector((5*Data_sz)-1 downto 0)
-);
-end component;
-
+package lpp_demux is 
 
 component DEMUX is
 generic(
@@ -66,38 +39,20 @@ port(
     rstn   :   in std_logic;
 
     Read : in std_logic_vector(4 downto 0);
-    DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
+    Load : in std_logic;
 
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
+    EmptyF0    :   in std_logic_vector(4 downto 0);
     EmptyF1     :   in std_logic_vector(4 downto 0);
     EmptyF2     :   in std_logic_vector(4 downto 0);
 
-    DataF0a     :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    DataF0b     :   in std_logic_vector((5*Data_sz)-1 downto 0);
+    DataF0     :   in std_logic_vector((5*Data_sz)-1 downto 0);
     DataF1      :   in std_logic_vector((5*Data_sz)-1 downto 0);
     DataF2      :   in std_logic_vector((5*Data_sz)-1 downto 0);
 
-    Read_DEMUX : out std_logic_vector(19 downto 0);
+    Read_DEMUX : out std_logic_vector(14 downto 0);
     Empty   :   out std_logic_vector(4 downto 0);
     Data    :   out std_logic_vector((5*Data_sz)-1 downto 0)
 );
 end component;
 
-
-component WatchFlag is
-port(
-    clk    :   in std_logic;
-    rstn   :   in std_logic;
-
-    EmptyF0a    :   in std_logic_vector(4 downto 0);
-    EmptyF0b    :   in std_logic_vector(4 downto 0);
-    EmptyF1     :   in std_logic_vector(4 downto 0);
-    EmptyF2     :   in std_logic_vector(4 downto 0);
-
-    DataCpt     :   out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
-);
-end component;
-
-
 end;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd
--- a/lib/lpp/lpp_memory/lppFIFOxN.vhd
+++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd
@@ -31,6 +31,7 @@ entity lppFIFOxN is
 generic(
     tech          :   integer := 0;
     Data_sz       :   integer range 1 to 32 := 8;
+    Addr_sz       :   integer range 1 to 32 := 8;
     FifoCnt : integer := 1;
     Enable_ReUse  :   std_logic := '0'
     );
@@ -55,32 +56,9 @@ begin
 
 fifos: for i in 0 to FifoCnt-1 generate
     FIFO0 : lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
+        generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
         port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
 end generate;
 
-
-
---    fifoB1 : entity work.lpp_fifo
---        generic map (tech,Enable_ReUse,Data_sz,8)
---        port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
---
---    fifoB2 : entity work.lpp_fifo
---        generic map (tech,Enable_ReUse,Data_sz,8)
---        port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
---
---    fifoB3 : entity work.lpp_fifo
---        generic map (tech,Enable_ReUse,Data_sz,8)
---        port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
---
---    fifoE1 : entity work.lpp_fifo
---        generic map (tech,Enable_ReUse,Data_sz,8)
---        port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
---
---    fifoE2 : entity work.lpp_fifo
---        generic map (tech,Enable_ReUse,Data_sz,8)
---        port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
-
-
 end architecture;
 
diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd
--- a/lib/lpp/lpp_memory/lpp_memory.vhd
+++ b/lib/lpp/lpp_memory/lpp_memory.vhd
@@ -99,6 +99,7 @@ component lppFIFOxN is
 generic(
     tech          :   integer := 0;
     Data_sz       :   integer range 1 to 32 := 8;
+    Addr_sz       :   integer range 1 to 32 := 8;
     FifoCnt : integer := 1;
     Enable_ReUse  :   std_logic := '0'
     );
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
@@ -26,8 +26,7 @@ ENTITY lpp_top_acq IS
     clk             : IN  STD_LOGIC;    -- 25 MHz
     rstn            : IN  STD_LOGIC;
     --
-    sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
-    sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
     sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
     --
     sample_f1_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -86,11 +85,7 @@ ARCHITECTURE tb OF lpp_top_acq IS
   SIGNAL sample_downsampling_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
   --
   SIGNAL sample_f0_val               : STD_LOGIC;
-  SIGNAL sample_f0                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
-  --  
-  SIGNAL sample_f0_0_val             : STD_LOGIC;
-  SIGNAL sample_f0_1_val             : STD_LOGIC;
-  SIGNAL counter_f0                  : INTEGER;
+  SIGNAL sample_f0                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);  
   -----------------------------------------------------------------------------
   SIGNAL sample_f1_val               : STD_LOGIC;
   SIGNAL sample_f1                   : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -207,35 +202,11 @@ BEGIN
     sample_f0_wdata(16*4+I) <= sample_f0(7, I);
   END GENERATE all_bit_sample_f0;
 
-  PROCESS (clk, rstn)
-  BEGIN  -- PROCESS
-    IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      counter_f0 <= 0;
-    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-      IF sample_f0_val = '1' THEN
-        IF counter_f0 = 511 THEN
-          counter_f0 <= 0;
-        ELSE
-          counter_f0 <= counter_f0 + 1;
-        END IF;
-      END IF;
-    END IF;
-  END PROCESS;
-
-  sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
-  sample_f0_0_wen <= NOT(sample_f0_0_val) &
-                       NOT(sample_f0_0_val) &
-                       NOT(sample_f0_0_val) &
-                       NOT(sample_f0_0_val) &
-                       NOT(sample_f0_0_val);
-  
-  sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
-  sample_f0_1_wen <= NOT(sample_f0_1_val) &
-                       NOT(sample_f0_1_val) &
-                       NOT(sample_f0_1_val) &
-                       NOT(sample_f0_1_val) &
-                       NOT(sample_f0_1_val);
-
+    sample_f0_wen <= NOT(sample_f0_val) &
+                     NOT(sample_f0_val) &
+                     NOT(sample_f0_val) &
+                     NOT(sample_f0_val) &
+                     NOT(sample_f0_val);
 
   -----------------------------------------------------------------------------
   -- F1 -- @4096 Hz
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
@@ -15,26 +15,34 @@ USE techmap.gencomp.ALL;
 PACKAGE lpp_top_lfr_pkg IS
 
   COMPONENT lpp_top_acq
-    GENERIC (
-      tech : integer);
-    PORT (
-      cnv_run         : IN  STD_LOGIC;
-      cnv             : OUT STD_LOGIC;
-      sck             : OUT STD_LOGIC;
-      sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
-      cnv_clk         : IN  STD_LOGIC;
-      cnv_rstn        : IN  STD_LOGIC;
-      clk             : IN  STD_LOGIC;
-      rstn            : IN  STD_LOGIC;
-      sample_f0_0_wen : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sample_f0_1_wen : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-      sample_f1_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-      sample_f2_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-      sample_f3_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
-      sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
+  GENERIC(
+    tech : INTEGER := 0
+    );
+  PORT (
+    -- ADS7886
+    cnv_run         : IN  STD_LOGIC;
+    cnv             : OUT STD_LOGIC;
+    sck             : OUT STD_LOGIC;
+    sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    --
+    cnv_clk         : IN  STD_LOGIC;    -- 49 MHz
+    cnv_rstn        : IN  STD_LOGIC;
+    --
+    clk             : IN  STD_LOGIC;    -- 25 MHz
+    rstn            : IN  STD_LOGIC;
+    --
+    sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+    --
+    sample_f1_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+    --
+    sample_f2_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+    --
+    sample_f3_wen   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
+    );
   END COMPONENT;
 
   COMPONENT lpp_top_apbreg