# HG changeset patch # User martin # Date 2011-03-21 11:39:07 # Node ID add206a96e71386d1a66569c3591538a7db8ff2f # Parent 82690b69adf41e1e32ef69f59eb01d0f5e1ad8f0 fixed bug on UART diff --git a/LPP_drivers/exemples/BenchUART/Makefile b/LPP_drivers/exemples/BenchUART/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/BenchUART/Makefile @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ + +include ../../rules.mk +LIBDIR = ../../lib +INCPATH = ../../includes +SCRIPTDIR=../../scripts/ +LIBS=-lapb_uart_Driver -llpp_apb_functions +INPUTFILE=main.c +EXEC=BenchUART.bin +OUTBINDIR=bin/ + + +.PHONY:bin + +all:bin + @echo $(EXEC)" file created" + +clean: + rm -f *.{o,a} + + + +help:ruleshelp + @echo " all : makes an executable file called "$(EXEC) + @echo " in "$(OUTBINDIR) + @echo " clean : removes temporary files" + diff --git a/LPP_drivers/exemples/BenchUART/Makefile.txt b/LPP_drivers/exemples/BenchUART/Makefile.txt deleted file mode 100644 --- a/LPP_drivers/exemples/BenchUART/Makefile.txt +++ /dev/null @@ -1,44 +0,0 @@ -#------------------------------------------------------------------------------ -#-- This file is a part of the LPP VHDL IP LIBRARY -#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS -#-- -#-- This program is free software; you can redistribute it and/or modify -#-- it under the terms of the GNU General Public License as published by -#-- the Free Software Foundation; either version 3 of the License, or -#-- (at your option) any later version. -#-- -#-- This program is distributed in the hope that it will be useful, -#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -#-- GNU General Public License for more details. -#-- -#-- You should have received a copy of the GNU General Public License -#-- along with this program; if not, write to the Free Software -#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -#------------------------------------------------------------------------------ - -include ../../rules.mk -LIBDIR = ../../lib -INCPATH = ../../includes -SCRIPTDIR=../../scripts/ -LIBS=-lapb_uart_Driver -llpp_apb_functions -INPUTFILE=main.c -EXEC=BenchUART.bin -OUTBINDIR=bin/ - - -.PHONY:bin - -all:bin - @echo $(EXEC)" file created" - -clean: - rm -f *.{o,a} - - - -help:ruleshelp - @echo " all : makes an executable file called "$(EXEC) - @echo " in "$(OUTBINDIR) - @echo " clean : removes temporary files" - diff --git a/LPP_drivers/includes/apb_uart_Driver.h b/LPP_drivers/includes/apb_uart_Driver.h new file mode 100644 --- /dev/null +++ b/LPP_drivers/includes/apb_uart_Driver.h @@ -0,0 +1,56 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#ifndef APB_UART_DRIVER_H +#define APB_UART_DRIVER_H + + +#define BaudGenOnDuty 0 +#define DataSended 0x10 +#define NewData 0x100 + +/*=================================================== + T Y P E S D E F +====================================================*/ + +struct UART_Driver +{ + int ConfigReg; + int DataWReg; + int DataRReg; +}; + +typedef struct UART_Driver UART_Device; + + +/*=================================================== + F U N C T I O N S +====================================================*/ + + +UART_Device* openUART(int count); +void uartputc(UART_Device* dev,char c); +void uartputs(UART_Device* dev,char* s); +char uartgetc(UART_Device* dev); +void uartgets(UART_Device* dev,char* s); + + +#endif diff --git a/LPP_drivers/libsrc/UART/Makefile b/LPP_drivers/libsrc/UART/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/libsrc/UART/Makefile @@ -0,0 +1,25 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ +FILE = apb_uart_Driver +LIB = liblpp_uart_Driver.a + +include ../../rules.mk + +all: $(FILE).a + @echo $(FILE)".a created" diff --git a/LPP_drivers/libsrc/UART/Makefile.txt b/LPP_drivers/libsrc/UART/Makefile.txt deleted file mode 100644 --- a/LPP_drivers/libsrc/UART/Makefile.txt +++ /dev/null @@ -1,25 +0,0 @@ -#------------------------------------------------------------------------------ -#-- This file is a part of the LPP VHDL IP LIBRARY -#-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS -#-- -#-- This program is free software; you can redistribute it and/or modify -#-- it under the terms of the GNU General Public License as published by -#-- the Free Software Foundation; either version 3 of the License, or -#-- (at your option) any later version. -#-- -#-- This program is distributed in the hope that it will be useful, -#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -#-- GNU General Public License for more details. -#-- -#-- You should have received a copy of the GNU General Public License -#-- along with this program; if not, write to the Free Software -#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -#------------------------------------------------------------------------------ -FILE = apb_uart_driver -LIB = liblpp_uart_driver.a - -include ../../rules.mk - -all: $(FILE).a - @echo $(FILE)".a created" diff --git a/LPP_drivers/libsrc/UART/apb_uart_Driver.c b/LPP_drivers/libsrc/UART/apb_uart_Driver.c --- a/LPP_drivers/libsrc/UART/apb_uart_Driver.c +++ b/LPP_drivers/libsrc/UART/apb_uart_Driver.c @@ -27,7 +27,7 @@ UART_Device* openUART(int count) { UART_Device* uart0; - uart0 = (UART_Device*) apbgetdevice(LPP_UART_CTRLR,VENDOR_LPP,count); + uart0 = (UART_Device*) apbgetdevice(LPP_UART,VENDOR_LPP,count); uart0->ConfigReg = BaudGenOnDuty; return uart0; } diff --git a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd @@ -29,6 +29,7 @@ library lpp; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.lpp_fft.all; +use lpp.lpp_memory.all; use work.fft_components.all; --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba @@ -63,20 +64,24 @@ signal DataOut : std_logic_vector(D signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); -signal X,Y,Z : std_logic; ---signal Pong : std_logic; ---signal Valid : std_logic; +signal start : std_logic; +signal load : std_logic; +signal rdy : std_logic; signal DummyIn : std_logic_vector(Data_sz-1 downto 0); ---signal DummyOut : std_logic_vector(Data_sz-1 downto 0); + begin - APB : entity work.ApbDriver + APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int) port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - + - DEVICE : entity work.CoreFFT + Extremum : Flag_Extremum + port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty); + + + DEVICE : CoreFFT generic map( LOGPTS => gLOGPTS, LOGLOGPTS => gLOGLOGPTS, @@ -89,11 +94,11 @@ begin PTS => gPTS, HALFPTS => gHALFPTS, inBuf_RWDLY => gInBuf_RWDLY) - port map(clk,X,rst,WriteEnable,ReadEnable,DummyIn,DataIn,Y,open,open,DataOut,open,Z); + port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy); -X <= not rst; -Y <= not FlagFull; -Z <= not FlagEmpty; -DummyIn <= (others => '0'); +start <= not rst; +--FlagFull <= not load; +--FlagEmpty <= not rdy; +DummyIn <= (others => '0'); end ar_APB_FFT; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd @@ -0,0 +1,124 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.FFT_config.all; + +entity Flag_Extremum is + port( + clk,raz : in std_logic; + load : in std_logic; + y_rdy : in std_logic; + d_valid_WR : in std_logic; + read_y_RE : in std_logic; + full : out std_logic; + empty : out std_logic + ); +end Flag_Extremum; + +architecture ar_Flag_Extremum of Flag_Extremum is + +type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3); +signal ect : etat; + +signal load_reg : std_logic; +signal y_rdy_reg : std_logic; +signal RE_reg : std_logic; +signal WR_reg : std_logic; + +begin + process (clk,raz) + begin + if(raz='0')then + full <= '0'; + empty <= '1'; + ect <= eA; + + elsif(clk' event and clk='1')then + load_reg <= load; + y_rdy_reg <= y_rdy; + RE_reg <= read_y_RE; + WR_reg <= d_valid_WR; + + case ect is + + when eA => + if(WR_reg='0' and d_valid_WR='1')then + empty <= '0'; + ect <= eB; + end if; + + when eB => + if(load_reg='1' and load='0')then + ect <= eC; + end if; + + when eC => + if(load_reg='1' and load='0')then + full <= '1'; + ect <= eD; + end if; + + when eD => + if(RE_reg='0' and read_y_RE='1')then + full <= '0'; + ect <= eX; + end if; + + when eX => + empty <= '1'; + ect <= e0; + + when e0 => + if(WR_reg='0' and d_valid_WR='1')then + empty <= '0'; + ect <= e1; + end if; + + when e1 => + if(load_reg='1' and load='0')then + full <= '1'; + ect <= e2; + end if; + + when e2 => + if(RE_reg='0' and read_y_RE='1')then + full <= '0'; + ect <= e3; + end if; + + when e3 => + if(y_rdy_reg='1' and y_rdy='0')then + empty <= '1'; + ect <= e0; + end if; + + end case; + end if; + end process; + +end ar_Flag_Extremum; + + + + diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -53,6 +53,19 @@ component APB_FFT is end component; +component Flag_Extremum is + port( + clk,raz : in std_logic; + load : in std_logic; + y_rdy : in std_logic; + d_valid_WR : in std_logic; + read_y_RE : in std_logic; + full : out std_logic; + empty : out std_logic + ); +end component; + + component CoreFFT IS GENERIC ( LOGPTS : integer := gLOGPTS; diff --git a/lib/lpp/lpp_cna/APB_CNA.vhd b/lib/lpp/lpp_cna/APB_CNA.vhd --- a/lib/lpp/lpp_cna/APB_CNA.vhd +++ b/lib/lpp/lpp_cna/APB_CNA.vhd @@ -77,7 +77,7 @@ begin enable <= Rec.CNA_Cfg(0); Rec.CNA_Cfg(1) <= flag_sd; - CONVERTER : entity Work.CNA_TabloC + CONVERTER : CNA_TabloC port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd @@ -28,7 +28,7 @@ use grlib.devices.all; library lpp; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; -use lpp.lpp_fifo.all; +use lpp.lpp_memory.all; --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba @@ -64,12 +64,12 @@ signal AddrOut : std_logic_vector(A begin - APB : entity work.ApbDriver + APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - DEVICE : entity work.Top_FIFO + DEVICE : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ b/lib/lpp/lpp_memory/APB_FifoRead.vhd @@ -52,76 +52,29 @@ entity APB_FifoRead is ); end APB_FifoRead; +--! @details Gestion de la FIFO uniquement en �criture architecture ar_APB_FifoRead of APB_FifoRead is -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -type FIFO_ctrlr_Reg is record - FIFO_Cfg : std_logic_vector(1 downto 0); - FIFO_DataW : std_logic_vector(15 downto 0); - FIFO_DataR : std_logic_vector(15 downto 0); - FIFO_AddrR : std_logic_vector(7 downto 0); -end record; - -signal Rec : FIFO_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -signal flag_RE : std_logic; -signal empty : std_logic; +signal ReadEnable : std_logic; +--signal WriteEnable : std_logic; +signal FlagEmpty : std_logic; +--signal FlagFull : std_logic; +signal DataIn : std_logic_vector(Data_sz-1 downto 0); +signal DataOut : std_logic_vector(Data_sz-1 downto 0); +--signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); +signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); begin -Rec.FIFO_Cfg(0) <= flag_RE; -Rec.FIFO_Cfg(2) <= empty; - - - MEMORY_READ : entity Work.Top_FifoRead - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Rec.FIFO_AddrR,full,Waddr,Rec.FIFO_DataR); + APB : ApbDriver + generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) + port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo); - process(rst,clk) - begin - if(rst='0')then - Rec.FIFO_AddrR <= (others => '0'); - - elsif(clk'event and clk='1')then - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when others => - null; - end case; - end if; + MEMORY_READ : Top_FifoRead + generic map(Data_sz,Addr_sz,addr_max_int) + port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut); - --APB Read OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 16) <= X"DDDD"; - Rdata(15 downto 0) <= Rec.FIFO_DataR; - when "000001" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.FIFO_AddrR; - when "000010" => - Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0); - Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1); - Rdata(31 downto 8) <= X"CCCCCC"; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; end ar_APB_FifoReade; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ b/lib/lpp/lpp_memory/APB_FifoWrite.vhd @@ -52,80 +52,29 @@ entity APB_FifoWrite is ); end APB_FifoWrite; +--! @details Gestion de la FIFO uniquement en lecture architecture ar_APB_FifoWrite of APB_FifoWrite is -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -type FIFO_ctrlr_Reg is record - FIFO_Cfg : std_logic_vector(1 downto 0); - FIFO_DataW : std_logic_vector(15 downto 0); - FIFO_DataR : std_logic_vector(15 downto 0); - FIFO_AddrW : std_logic_vector(7 downto 0); -end record; - -signal Rec : FIFO_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -signal flag_WR : std_logic; -signal full : std_logic; +--signal ReadEnable : std_logic; +signal WriteEnable : std_logic; +--signal FlagEmpty : std_logic; +signal FlagFull : std_logic; +signal DataIn : std_logic_vector(Data_sz-1 downto 0); +signal DataOut : std_logic_vector(Data_sz-1 downto 0); +signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); +--signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); begin -Rec.FIFO_Cfg(0) <= flag_WR; -Rec.FIFO_Cfg(1) <= full; - - MEMORY_WRITE : entity Work.Top_FifoWrite - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,Raddr,full,Rec.FIFO_AddrW,Rec.FIFO_DataR); + APB : ApbDriver + generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) + port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - process(rst,clk) - begin - if(rst='0')then - Rec.FIFO_DataW <= (others => '0'); - - elsif(clk'event and clk='1')then - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - flag_WR <= '1'; - Rec.FIFO_DataW <= apbi.pwdata(15 downto 0); - when others => - null; - end case; - else - flag_WR <= '0'; - end if; + MEMORY_WRITE : Top_FifoWrite + generic map(Data_sz,Addr_sz,addr_max_int) + port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut); - --APB Read OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 16) <= X"DDDD"; - Rdata(15 downto 0) <= Rec.FIFO_DataR; - when "000001" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.FIFO_AddrW; - when "000010" => - Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0); - Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1); - Rdata(31 downto 8) <= X"CCCCCC"; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; end ar_APB_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -29,6 +29,7 @@ library lpp; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; +--! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO entity ApbDriver is generic ( @@ -42,21 +43,22 @@ entity ApbDriver is Addr_sz : integer := 8; addr_max_int : integer := 256); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - ReadEnable : out std_logic; - WriteEnable : out std_logic; - FlagEmpty : in std_logic; - FlagFull : in std_logic; - DataIn : out std_logic_vector(Data_sz-1 downto 0); - DataOut : in std_logic_vector(Data_sz-1 downto 0); - AddrIn : in std_logic_vector(Addr_sz-1 downto 0); - AddrOut : in std_logic_vector(Addr_sz-1 downto 0); - apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + ReadEnable : out std_logic; --! Instruction de lecture en m�moire + WriteEnable : out std_logic; --! Instruction d'�criture en m�moire + FlagEmpty : in std_logic; --! Flag, M�moire vide + FlagFull : in std_logic; --! Flag, M�moire pleine + DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e + DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie + AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture) + AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end ApbDriver; +--! @details Utilisable avec n'importe quelle IP VHDL de type FIFO architecture ar_ApbDriver of ApbDriver is diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ b/lib/lpp/lpp_memory/Top_FIFO.vhd @@ -25,6 +25,7 @@ use IEEE.numeric_std.all; library techmap; use techmap.gencomp.all; use work.config.all; +use lpp.lpp_memory.all; --! Programme de la FIFO @@ -75,7 +76,7 @@ signal s_flag_WR : std_logic; begin - WR : entity work.Fifo_Write + WR : Fifo_Write generic map(Addr_sz,addr_max_int) port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); @@ -85,11 +86,11 @@ begin port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); - link : entity work.Link_Reg + link : Link_Reg generic map(Data_sz) port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out); - RE : entity work.Fifo_Read + RE : Fifo_Read generic map(Addr_sz,addr_max_int) port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr); diff --git a/lib/lpp/lpp_memory/Top_FifoRead.vhd b/lib/lpp/lpp_memory/Top_FifoRead.vhd --- a/lib/lpp/lpp_memory/Top_FifoRead.vhd +++ b/lib/lpp/lpp_memory/Top_FifoRead.vhd @@ -39,7 +39,6 @@ entity Top_FifoRead is flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire - full : out std_logic; --! Flag, M�moire pleine empty : out std_logic; --! Flag, M�moire vide Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la m�moire Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -85,20 +85,20 @@ end component; component Top_FIFO is generic( - Addr_sz : integer := 8; Data_sz : integer := 16; - addr_max_int : integer := 256); + Addr_sz : integer := 8; + addr_max_int : integer := 256 + ); port( - clk : in std_logic; - raz : in std_logic; - Send_RE : in std_logic; - Send_WR : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); - Addr_RE : out std_logic_vector(addr_sz-1 downto 0); - Addr_WR : out std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - empty : out std_logic; - Data_out : out std_logic_vector(Data_sz-1 downto 0) + clk,raz : in std_logic; --! Horloge et reset general du composant + flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire + flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire + Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant + Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture + Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture + full : out std_logic; --! Flag, M�moire pleine + empty : out std_logic; --! Flag, M�moire vide + Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant ); end component; diff --git a/lib/lpp/lpp_uart/APB_UART.vhd b/lib/lpp/lpp_uart/APB_UART.vhd --- a/lib/lpp/lpp_uart/APB_UART.vhd +++ b/lib/lpp/lpp_uart/APB_UART.vhd @@ -83,7 +83,7 @@ Rec.UART_Cfg(1) <= Sended; Rec.UART_Cfg(2) <= NwData; - COM0 : entity work.UART + COM0 : UART generic map (Data_sz) port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);