# HG changeset patch # User pellion # Date 2015-04-21 09:25:37 # Node ID 86f47bdf2a6eb9e71225bed5bb7ec7f20331d2f8 # Parent f2c158b74433509c1e0db67e8b24c9a771bde803 force ADC output to constant or ramp. diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -53,7 +53,10 @@ USE lpp.lpp_bootloader_pkg.ALL; ENTITY LFR_EQM IS GENERIC ( Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0 + USE_BOOTLOADER : INTEGER := 0; + USE_ADCDRIVER : INTEGER := 0; + tech : INTEGER := apa3e; + tech_leon : INTEGER := apa3e ); PORT ( @@ -179,7 +182,7 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- CLK_LOCK ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN); + rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); PROCESS (clk50MHz_int, rstn_50) BEGIN -- PROCESS @@ -191,7 +194,7 @@ BEGIN -- beh nSRAM_BUSY_reg <= nSRAM_BUSY; IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN IF clk_busy_counter = "1111" THEN - clk_lock = '1'; + clk_lock <= '1'; ELSE clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); END IF; @@ -228,8 +231,8 @@ BEGIN -- beh -- leon3_soc_1 : leon3_soc GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, + fabtech => tech_leon, + memtech => tech_leon, padtech => inferred, clktech => inferred, disas => 0, @@ -290,7 +293,7 @@ BEGIN -- beh ------------------------------------------------------------------------------- apb_lfr_management_1 : apb_lfr_management GENERIC MAP ( - tech => apa3l, + tech => tech, pindex => 6, paddr => 6, pmask => 16#fff#, @@ -361,7 +364,7 @@ BEGIN -- beh spw_inputloop : FOR j IN 0 TO 1 GENERATE spw_phy0 : grspw_phy GENERIC MAP( - tech => apa3l, + tech => tech_leon, rxclkbuftype => 1, scantest => 0) PORT MAP( @@ -376,7 +379,7 @@ BEGIN -- beh -- SPW core sw0 : grspwm GENERIC MAP( - tech => apa3l, + tech => tech_leon, hindex => 1, pindex => 5, paddr => 5, @@ -393,7 +396,7 @@ BEGIN -- beh netlist => 0, ports => 2, --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3l, + memtech => tech_leon, destkey => 2, spwcore => 1 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 @@ -468,23 +471,66 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- ----------------------------------------------------------------------------- - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 13, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); + USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 13, + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn_25, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH_s, + sample => sample, + sample_val => sample_val); + + END GENERATE USE_ADCDRIVER_true; + + USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE + top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter + GENERIC MAP ( + ChanelCount => 9, + ncycle_cnv_high => 13, + ncycle_cnv => 25, + FILTER_ENABLED => 16#FF#) + PORT MAP ( + cnv_clk => clk_24, + cnv_rstn => rstn_24, + cnv => ADC_smpclk_s, + clk => clk_25, + rstn => rstn_25, + ADC_data => ADC_data, + ADC_nOE => OPEN, + sample => OPEN, + sample_val => sample_val); + + ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); + all_sample: FOR I IN 8 DOWNTO 0 GENERATE + ramp_generator_1: ramp_generator + GENERIC MAP ( + DATA_SIZE => 14, + VALUE_UNSIGNED_INIT => 2**I, + VALUE_UNSIGNED_INCR => 0, + VALUE_UNSIGNED_MASK => 16#3FFF#) + PORT MAP ( + clk => clk_25, + rstn => rstn_25, + new_data => sample_val, + output_data => sample(I) ); + END GENERATE all_sample; + + + END GENERATE USE_ADCDRIVER_false; + + + + ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); ADC_smpclk <= ADC_smpclk_s; diff --git a/designs/LFR-EQM-WFP_MS/Makefile b/designs/LFR-EQM-WFP_MS/Makefile --- a/designs/LFR-EQM-WFP_MS/Makefile +++ b/designs/LFR-EQM-WFP_MS/Makefile @@ -16,7 +16,7 @@ SYNPOPT="set_option -pipe 0; set_option VHDLSYNFILES=LFR-EQM.vhd VHDLSIMFILES=testbench.vhd #SIMTOP=testbench -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_NoADC.pdc SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc diff --git a/designs/LFR-EQM-WFP_MS/TB.vhd b/designs/LFR-EQM-WFP_MS/TB.vhd --- a/designs/LFR-EQM-WFP_MS/TB.vhd +++ b/designs/LFR-EQM-WFP_MS/TB.vhd @@ -24,6 +24,8 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; LIBRARY lpp; USE lpp.lpp_sim_pkg.ALL; @@ -65,7 +67,10 @@ ARCHITECTURE beh OF TB IS COMPONENT LFR_EQM GENERIC ( Mem_use : INTEGER; - USE_BOOTLOADER : INTEGER); + USE_BOOTLOADER : INTEGER; + USE_ADCDRIVER : INTEGER; + tech : INTEGER; + tech_leon : INTEGER); PORT ( clk50MHz : IN STD_ULOGIC; clk49_152MHz : IN STD_ULOGIC; @@ -215,7 +220,10 @@ BEGIN -- beh LFR_EQM_1 : LFR_EQM GENERIC MAP ( Mem_use => use_RAM, - USE_BOOTLOADER => 0) + USE_BOOTLOADER => 0, + USE_ADCDRIVER => 0, + tech => apa3e, + tech_leon => inferred) PORT MAP ( clk50MHz => clk50MHz, --IN --ok clk49_152MHz => clk49_152MHz, --in --ok @@ -316,7 +324,7 @@ BEGIN -- beh reset <= '0'; WAIT FOR 500 ns; reset <= '1'; - WAIT FOR 10000 ns; + WAIT FOR 100 us; message_simu <= "0 - UART init "; UART_INIT(TXD1, txp); @@ -324,7 +332,7 @@ BEGIN -- beh -- LAUNCH leon 3 software --------------------------------------------------------------------------- message_simu <= "2- GO Leon3...."; - + -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- --Force a debug break UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); @@ -523,18 +531,25 @@ BEGIN -- beh message_simu <= "4 - GO GO GO !!"; + data_message <= "---------------"; UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); - UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); + -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); + + data_read_v := (OTHERS => '1'); READ_STATUS : LOOP + data_message <= "---------------"; WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); - data_read <= data_read_v; + data_message <= "READ_STATUS_SM_"; + --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); + --data_message <= "--------------r"; + --data_read <= data_read_v; UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); - UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); - data_read <= data_read_v; + data_message <= "READ_STATUS_WF_"; + --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); + --data_message <= "--------------r"; + --data_read <= data_read_v; UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); END LOOP READ_STATUS; diff --git a/designs/LFR-EQM-WFP_MS/run.do b/designs/LFR-EQM-WFP_MS/run.do --- a/designs/LFR-EQM-WFP_MS/run.do +++ b/designs/LFR-EQM-WFP_MS/run.do @@ -41,6 +41,7 @@ vcom -quiet -93 -work lpp ../../../grl vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd +vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd @@ -187,10 +188,36 @@ vsim work.tb #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 -force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000100000000000100100000000000100001000000000100000100000000100000010000000100000001000000100000 0 -force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 001000000000000100100000000000100010000000000100001000000000100000100000000100000010000000100000 0 -force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 010000000000000101000000000000100100000000000100010000000000100001000000000100000100000000100000 0 -force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 100000000000000110000000000000101000000000000100100000000000100010000000000100001000000000100000 0 +#force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 +#force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 +#force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 +#force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 + +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd + +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd + +mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd + +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9 +#mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9 log -r *; do wave.do ; diff --git a/designs/LFR-EQM-WFP_MS/wave.do b/designs/LFR-EQM-WFP_MS/wave.do --- a/designs/LFR-EQM-WFP_MS/wave.do +++ b/designs/LFR-EQM-WFP_MS/wave.do @@ -15,16 +15,16 @@ add wave -noupdate -expand -group RAM -r add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val -add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val +add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst @@ -59,12 +59,12 @@ add wave -noupdate -group LFR1_s -radix add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp -add wave -noupdate -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 -add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f1 -add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f2 -add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f0 -add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f1 -add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f2 +add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 +add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f1 +add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2 +add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f0 +add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f1 +add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f2 add wave -noupdate /tb/error_wfp add wave -noupdate /tb/error_wfp_addr add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a @@ -94,11 +94,11 @@ add wave -noupdate -group LPP_DMA_FSM -r add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren -add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}} -expand} /tb/sample(2)(5) {-radix decimal} /tb/sample(2)(4) {-radix decimal} /tb/sample(2)(3) {-radix decimal} /tb/sample(2)(2) {-radix decimal} /tb/sample(2)(1) {-radix decimal} /tb/sample(2)(0) {-radix decimal} /tb/sample(1) {-radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} /tb/sample(1)(5) {-radix decimal} /tb/sample(1)(4) {-radix decimal} /tb/sample(1)(3) {-radix decimal} /tb/sample(1)(2) {-radix decimal} /tb/sample(1)(1) {-radix decimal} /tb/sample(1)(0) {-radix decimal} /tb/sample(0) {-radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-radix decimal} /tb/sample(0)(4) {-radix decimal} /tb/sample(0)(3) {-radix decimal} /tb/sample(0)(2) {-radix decimal} /tb/sample(0)(1) {-radix decimal} /tb/sample(0)(0) {-radix decimal}} /tb/sample -add wave -noupdate -expand /tb/sample_counter +add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample +add wave -noupdate /tb/sample_counter TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {279190000 ps} 0} {{Cursor 2} {277950000 ps} 0} {{Cursor 3} {11005133000 ps} 0} -quietly wave cursor active 3 +WaveRestoreCursors {{Cursor 1} {14590425667 ps} 0} {{Cursor 2} {5525050896 ps} 0} {{Cursor 3} {24728625854 ps} 0} +quietly wave cursor active 1 configure wave -namecolwidth 517 configure wave -valuecolwidth 347 configure wave -justifyvalue left @@ -113,4 +113,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {27243436500 ps} +WaveRestoreZoom {0 ps} {40323664500 ps} diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -51,17 +51,17 @@ PACKAGE general_purpose IS COMPONENT Clk_divider IS GENERIC(OSC_freqHz : INTEGER := 50000000; TargetFreq_Hz : INTEGER := 50000); - PORT (clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - clk_divided : OUT STD_LOGIC); + PORT (clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clk_divided : OUT STD_LOGIC); END COMPONENT; COMPONENT Clk_divider2 IS - generic(N : integer := 16); - port( - clk_in : in std_logic; - clk_out : out std_logic); + GENERIC(N : INTEGER := 16); + PORT( + clk_in : IN STD_LOGIC; + clk_out : OUT STD_LOGIC); END COMPONENT; COMPONENT Adder IS @@ -74,7 +74,7 @@ PACKAGE general_purpose IS clk : IN STD_LOGIC; reset : IN STD_LOGIC; clr : IN STD_LOGIC; - load : IN STD_LOGIC; + load : IN STD_LOGIC; add : IN STD_LOGIC; OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); @@ -82,22 +82,22 @@ PACKAGE general_purpose IS ); END COMPONENT; -COMPONENT Adder_V0 is -generic( - Input_SZ_A : integer := 16; - Input_SZ_B : integer := 16 + COMPONENT Adder_V0 IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 -); -port( - clk : in std_logic; - reset : in std_logic; - clr : in std_logic; - add : in std_logic; - OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); - OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); - RES : out std_logic_vector(Input_SZ_A-1 downto 0) -); -end COMPONENT; + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) + ); + END COMPONENT; COMPONENT ADDRcntr IS PORT( @@ -115,77 +115,77 @@ end COMPONENT; Logic_en : INTEGER := 1; Input_SZ_1 : INTEGER := 16; Input_SZ_2 : INTEGER := 9; - COMP_EN : INTEGER := 0 -- 1 => No Comp + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( clk : IN STD_LOGIC; reset : IN STD_LOGIC; - ctrl : IN STD_LOGIC_VECTOR(2 downto 0); - comp : IN STD_LOGIC_VECTOR(1 downto 0); + ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT ALU_V0 IS + GENERIC( + Arith_en : INTEGER := 1; + Logic_en : INTEGER := 1; + Input_SZ_1 : INTEGER := 16; + Input_SZ_2 : INTEGER := 9 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) ); END COMPONENT; -COMPONENT ALU_V0 IS - GENERIC( - Arith_en : INTEGER := 1; - Logic_en : INTEGER := 1; - Input_SZ_1 : INTEGER := 16; - Input_SZ_2 : INTEGER := 9 + COMPONENT MAC_V0 IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8 - ); - PORT( - clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); - RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT MAC_V0 is -generic( - Input_SZ_A : integer := 8; - Input_SZ_B : integer := 8 - -); -port( - clk : in std_logic; - reset : in std_logic; - clr_MAC : in std_logic; - MAC_MUL_ADD : in std_logic_vector(1 downto 0); - OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); - OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); - RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) -); -end COMPONENT; + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; --------------------------------------------------------- -------- // Sélection grace a l'entrée "ctrl" \\ -------- --------------------------------------------------------- -Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; -Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; -Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; -Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; -Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; + CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; + CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001"; + CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010"; + CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011"; + CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100"; -Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; -Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; -Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; -Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; -Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; + CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; + CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; + CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; + CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; + CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; --------------------------------------------------------- COMPONENT MAC IS GENERIC( Input_SZ_A : INTEGER := 8; Input_SZ_B : INTEGER := 8; - COMP_EN : INTEGER := 0 -- 1 => No Comp + COMP_EN : INTEGER := 0 -- 1 => No Comp ); PORT( clk : IN STD_LOGIC; @@ -199,18 +199,18 @@ Constant CLR_MAC_V0 : std_logic_vector(3 ); END COMPONENT; - COMPONENT TwoComplementer is - generic( - Input_SZ : integer := 16); - port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - clr : in std_logic; --! Un reset spécifique au programme - TwoComp : in std_logic; --! Autorise l'utilisation du complément - OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée - RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non - ); - end COMPONENT; + COMPONENT TwoComplementer IS + GENERIC( + Input_SZ : INTEGER := 16); + PORT( + clk : IN STD_LOGIC; --! Horloge du composant + reset : IN STD_LOGIC; --! Reset general du composant + clr : IN STD_LOGIC; --! Un reset spécifique au programme + TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément + OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée + RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non + ); + END COMPONENT; COMPONENT MAC_CONTROLER IS PORT( @@ -275,19 +275,19 @@ Constant CLR_MAC_V0 : std_logic_vector(3 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; - + COMPONENT MUXN GENERIC ( Input_SZ : INTEGER; NbStage : INTEGER); PORT ( sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); - INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); + INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0); --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); END COMPONENT; - + COMPONENT Multiplier IS GENERIC( @@ -365,7 +365,7 @@ Constant CLR_MAC_V0 : std_logic_vector(3 sin : IN STD_LOGIC; sout : OUT STD_LOGIC); END COMPONENT; - + --COMPONENT SYNC_VALID_BIT -- GENERIC ( -- NB_FF_OF_SYNC : INTEGER); @@ -397,11 +397,24 @@ Constant CLR_MAC_V0 : std_logic_vector(3 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; -COMPONENT Clock_Divider is -generic(N :integer := 10); -port( - clk, rst : in std_logic; - sclk : out std_logic); -end COMPONENT; + COMPONENT Clock_Divider IS + GENERIC(N : INTEGER := 10); + PORT( + clk, rst : IN STD_LOGIC; + sclk : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT ramp_generator + GENERIC ( + DATA_SIZE : INTEGER; + VALUE_UNSIGNED_INIT : INTEGER; + VALUE_UNSIGNED_INCR : INTEGER; + VALUE_UNSIGNED_MASK : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + new_data : IN STD_LOGIC; + output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); + END COMPONENT; END; diff --git a/lib/lpp/general_purpose/ramp_generator.vhd b/lib/lpp/general_purpose/ramp_generator.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/ramp_generator.vhd @@ -0,0 +1,63 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +ENTITY ramp_generator IS + + GENERIC ( + DATA_SIZE : INTEGER := 16; + VALUE_UNSIGNED_INIT : INTEGER := 0; + VALUE_UNSIGNED_INCR : INTEGER := 1; + VALUE_UNSIGNED_MASK : INTEGER := 16#FFFF#); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + new_data : IN STD_LOGIC; + output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); + +END ramp_generator; + +ARCHITECTURE beh OF ramp_generator IS + + SIGNAL data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); + +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INIT,DATA_SIZE)) + AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK,DATA_SIZE)); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF new_data = '1' THEN + data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INCR + to_integer(UNSIGNED(data)),DATA_SIZE)) + AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK ,DATA_SIZE)); + END IF; + END IF; + END PROCESS; + + output_data <= data; + +END beh; diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -24,3 +24,4 @@ lpp_front_positive_detection.vhd SYNC_VALID_BIT.vhd RR_Arbiter_4.vhd general_counter.vhd +ramp_generator.vhd