# HG changeset patch
# User Alexis Jeandet
# Date 2016-11-25 16:32:26
# Node ID 86e42f03c37d809c72542c8d42fdb252ed77e4f1
# Parent  0343834a1e0edd86803b311b1e1dbda7d3861df2

Removed unmaintained modules.

diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
+++ /dev/null
@@ -1,71 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-
-entity FRAME_CLK_GEN is
-	generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           FRAME_CLK : out  STD_LOGIC);
-end FRAME_CLK_GEN;
-
-architecture Behavioral of FRAME_CLK_GEN is
-
-Constant	Goal_FRAME_CLK_FREQ	:	integer := 25;
-
-Constant FRAME_CLK_TRIG	:	integer	:= OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1;
-
-signal	CPT	:	integer := 0;
-signal	FRAME_CLK_reg : std_logic :='0';
-
-begin
-
-FRAME_CLK	<=	FRAME_CLK_reg;
-
-process(reset,clk)
-begin
-	if reset = '0' then
-		CPT <=	0;
-		FRAME_CLK_reg <= '0';
-	elsif clk'event and clk = '1' then
-		if CPT = FRAME_CLK_TRIG then
-			CPT <= 0;
-			FRAME_CLK_reg	<= not FRAME_CLK_reg;
-		else
-			CPT	<=	CPT + 1;
-		end if;
-	end if;
-end process;
-end Behavioral;
-
-
-
-
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-
-
-
-package LCD_16x2_CFG is
-  
-  	
-constant ClearDSPLY		:	std_logic_vector(7 downto 0):= X"01";	
-constant	FunctionSet		:	std_logic_vector(7 downto 0):= X"38";	
-constant RetHome			:	std_logic_vector(7 downto 0):= X"02";	
-constant SetEntryMode	:	std_logic_vector(7 downto 0):= X"06";	
-constant DSPL_CTRL		:	std_logic_vector(7 downto 0):= X"0E";	
-	
-constant CursorON			:	std_logic_vector(7 downto 0):= X"0E";	
-constant CursorOFF		:	std_logic_vector(7 downto 0):= X"0C";	
-
---===========================================================|
---======L C D    D R I V E R     T I M I N G     C O D E=====|
---===========================================================|	
-	
-constant    Duration_4us    		:   std_logic_vector(1 downto 0) := "00";
-constant    Duration_100us   		:   std_logic_vector(1 downto 0) := "01";
-constant    Duration_4ms    		:   std_logic_vector(1 downto 0) := "10";	
-constant    Duration_20ms    		:   std_logic_vector(1 downto 0) := "11";	
-	
-	
-
-end LCD_16x2_CFG;
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-
----TDODO => Clean Enable pulse FSM
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.all;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-use lpp.lcd_16x2_cfg.all;
-
-entity LCD_16x2_DRIVER is
-	generic(
-		OSC_Freq_KHz	 :	integer:=50000
-	);
-    Port( 
-	   reset      : in  STD_LOGIC;
-	   clk        : in  STD_LOGIC;
-      LCD_CTRL	  : out LCD_DRVR_CTRL_BUSS;
-	   SYNCH	     : out LCD_DRVR_SYNCH_BUSS;
-	   DRIVER_CMD : in  LCD_DRVR_CMD_BUSS
-			  );
-end LCD_16x2_DRIVER;
-
-architecture Behavioral of LCD_16x2_DRIVER is
-
-type stateT is (idle,Enable0,Enable1,Enable2,tempo);
-signal	state	:	stateT;
-
-
-constant	trigger_4us		:	integer := 5;
-constant	trigger_100us	:	integer := 100;
-constant	trigger_4ms		:	integer := 4200;
-constant	trigger_20ms	:	integer := 20000;
-
-
-signal	i 				:	integer :=0;
-signal	reset_i		:	std_logic := '0';
-signal	tempoTRIG	:	integer :=0;
-
-signal	clk_1us		:	std_logic;
-signal	clk_1us_reg	:	std_logic;
-
-begin
-
-
-CLK0: LCD_CLK_GENERATOR
-	 generic map(OSC_Freq_KHz)
-    Port map( clk,reset,clk_1us);
-
-
-
-process(clk_1us,reset_i)
-begin
-	if reset_i = '0' then
-		i	<=	0;
-	elsif clk_1us'event and clk_1us ='1' then
-			i	<=	i+1;
-	end if;
-end process;
-
-LCD_CTRL.LCD_RW	<=	'0';
-
-process(clk,reset)
-begin
-	if reset = '0' then
-		state	<=	idle;
-		LCD_CTRL.LCD_E				<=	'0';
-		SYNCH.DRVR_READY			<=	'0';
-		SYNCH.LCD_INITIALISED	<=	'0';
-		reset_i						<=	'0';
-	elsif clk'event and clk = '1' then
-		case state is
-			when idle =>
-				SYNCH.LCD_INITIALISED	<=	'1';
-				LCD_CTRL.LCD_E				<=	'0';
-				if DRIVER_CMD.Exec = '1' then
-					state	<=	Enable0;
-					reset_i	<=	'1';
-					SYNCH.DRVR_READY			<=	'0';
-					LCD_CTRL.LCD_DATA	<=	DRIVER_CMD.Word;
-					LCD_CTRL.LCD_RS	<=	DRIVER_CMD.CMD_Data;
-					case DRIVER_CMD.Duration is
-						when Duration_4us =>
-							tempoTRIG	<=	trigger_4us;
-						when Duration_100us =>
-							tempoTRIG	<=	trigger_100us;
-						when Duration_4ms =>
-							tempoTRIG	<=	trigger_4ms;
-						when Duration_20ms =>
-							tempoTRIG	<=	trigger_20ms;
-						when others =>
-							tempoTRIG	<=	trigger_20ms;
-					end case;
-				else
-					SYNCH.DRVR_READY			<=	'1';
-					reset_i						<=	'0';
-				end if;
-			when Enable0 =>
-				if i = 1 then
-					reset_i	<=	'0';
-					LCD_CTRL.LCD_E				<=	'1';
-					state	<=	Enable1;
-				else
-					reset_i	<=	'1';
-					LCD_CTRL.LCD_E				<=	'0';
-				end if;
-			when Enable1 =>
-				if i = 2 then
-					reset_i	<=	'0';
-					LCD_CTRL.LCD_E				<=	'0';
-					state	<=	Enable2;
-				else
-					reset_i	<=	'1';
-					LCD_CTRL.LCD_E				<=	'1';
-				end if;
-			when Enable2 =>
-				if i = 1 then
-					reset_i	<=	'0';
-					LCD_CTRL.LCD_E				<=	'0';
-					state	<=	tempo;
-				else
-					reset_i	<=	'1';
-					LCD_CTRL.LCD_E				<=	'0';
-				end if;
-			when tempo =>
-				if i = tempoTRIG then
-					reset_i	<=	'0';
-					state	<=	idle;
-				else
-					reset_i	<=	'1';
-				end if;
-		end case;
-	end if;
-end process;
-
-end Behavioral;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
+++ /dev/null
@@ -1,213 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-use lpp.LCD_16x2_CFG.all;
-
-
-entity LCD_16x2_ENGINE is
-	generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk 	:	in  STD_LOGIC;
-           reset 	:	in  STD_LOGIC;
-			  DATA	:	in FRM_Buff_Space;
-			  CMD		:	in std_logic_vector(10 downto 0);
-			  Exec	:	in	std_logic;
-			  Ready	:	out std_logic;
-			  LCD_CTRL	:	out LCD_DRVR_CTRL_BUSS
-			  );
-end LCD_16x2_ENGINE;
-
-architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
-
-constant ConfigTbl	: LCD_CFG_Tbl	:=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
-
-
-
-signal	SYNCH		:	 LCD_DRVR_SYNCH_BUSS;
-signal   DRIVER_CMD	   :	 LCD_DRVR_CMD_BUSS;
-signal	FRAME_CLK	:	std_logic;
-
-signal	FRAME_CLK_reg	:	std_logic;
-signal	RefreshFlag		:	std_logic;
-signal	CMD_Flag			:	std_logic;
-signal	Exec_Reg			:	std_logic;
-
-type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
-signal	state	:	state_t;
-signal	i		:	integer range 0 to lcd_space_size := 0;
-
-
-
-begin
-
-Driver0 :  LCD_16x2_DRIVER
-	generic map(OSC_freqKHz)
-    Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
-
-FRAME_CLK_GEN0 : FRAME_CLK_GEN
-	generic map(OSC_freqKHz)
-    Port map( clk,reset,FRAME_CLK);
-
-
-
-process(reset,clk)
-begin
-	if reset = '0' then
-		state <=	INIT0;
-		Ready	<=	'0';
-		RefreshFlag	<=	'0';
-		i	<=	0;
-	elsif clk'event and clk ='1' then
-		FRAME_CLK_reg	<=	FRAME_CLK;
-		Exec_Reg			<=	Exec;
-		
-		if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
-			RefreshFlag	<=	'1';
-		elsif state = Refresh or state = Refresh0 or state = Refresh1 then
-			RefreshFlag	<=	'0';
-		end if;
-		
-		if Exec_Reg = '0' and Exec = '1' then
-			CMD_Flag	<=	'1';
-		elsif state = ExecCMD0 or state = ExecCMD1 then
-			CMD_Flag	<=	'0';
-		end if;
-		
-		case state is
-			when	INIT0 =>
-				if SYNCH.DRVR_READY = '1' then 
-					DRIVER_CMD.Exec		<=	'1';
-					DRIVER_CMD.Duration	<=	Duration_20ms;
-					DRIVER_CMD.CMD_Data	<=	'0';
-					DRIVER_CMD.Word			<=	ConfigTbl(i);
-					i	<=	i + 1;
-					state	<=	INIT1;
-				else
-					DRIVER_CMD.Exec		<=	'0';
-				end if;
-			when	INIT1 =>
-				state	<=	INIT2;
-				DRIVER_CMD.Exec		<=	'0';
-			when	INIT2 =>
-				if SYNCH.DRVR_READY = '1' then 
-					if i = 5 then
-						state	<=	Idle;
-					else
-						state	<=	INIT0;
-					end if;
-				end if;
-			when Idle=>
-				DRIVER_CMD.Exec		<=	'0';
-				if RefreshFlag	=	'1' then
-					Ready	<=	'0';
-					state	<=	Refresh;
-				elsif CMD_Flag = '1' then
-					Ready	<=	'0';
-					state	<=	ExecCMD0;
-				else
-					Ready	<=	'1';
-				end if;
-				i	<=	0;
-			when Refresh=>
-				if SYNCH.DRVR_READY = '1' then 
-					DRIVER_CMD.Exec		<=	'1';
-					DRIVER_CMD.Duration	<=	Duration_100us;
-					DRIVER_CMD.CMD_Data	<=	'1';
-					DRIVER_CMD.Word			<=	DATA(i);
-					state	<=	Refresh0;
-				else
-					DRIVER_CMD.Exec		<=	'0';
-				end if;
-			when Refresh0=>
-				i	<=	i + 1;
-				state	<=	Refresh1;
-				DRIVER_CMD.Exec		<=	'0';
-			when Refresh1=>
-				if SYNCH.DRVR_READY = '1' then 
-					if i = lcd_space_size then
---						state	<=	ReturnHome;
-						state	<=	Idle;
---					elsif i = 16 then
---						state	<=	GoLine2;
-					else
-						state	<=	Refresh;
-					end if;
-				end if;
-				
-			when ExecCMD0=>
-				if SYNCH.DRVR_READY = '1' then 
-					DRIVER_CMD.Exec		<=	'1';
-					DRIVER_CMD.Duration	<=	CMD(9 downto 8);
-					DRIVER_CMD.CMD_Data	<=	'0';
-					DRIVER_CMD.Word		<= CMD(7 downto 0);
-					state	<=	ExecCMD1;
-				else
-					DRIVER_CMD.Exec		<=	'0';
-				end if;
-			
-			when ExecCMD1=>
-				state	<=	Idle;
-				DRIVER_CMD.Exec		<=	'0';
-				
-			when	GoLine2=>
-				if SYNCH.DRVR_READY = '1' then 
-					DRIVER_CMD.Exec		<=	'1';
-					DRIVER_CMD.Duration	<=	Duration_4ms;
-					DRIVER_CMD.CMD_Data	<=	'0';
-					DRIVER_CMD.Word			<= X"C0";
-					state	<=	GoLine2_0;
-				else
-					DRIVER_CMD.Exec		<=	'0';
-				end if;
-			when	GoLine2_0=>
-				state	<=	Refresh;
-				DRIVER_CMD.Exec		<=	'0';
-			when ReturnHome=>
-				if SYNCH.DRVR_READY = '1' then 
-					DRIVER_CMD.Exec		<=	'1';
-					DRIVER_CMD.Duration	<=	Duration_4ms;
-					DRIVER_CMD.CMD_Data	<=	'0';
-					DRIVER_CMD.Word			<= RetHome;
-					state	<=	Idle;
-				else
-					DRIVER_CMD.Exec		<=	'0';
-				end if;
-		end case;
-	end if;
-end process;
-
-
-end ar_LCD_16x2_ENGINE;
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.all;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-
-entity LCD_2x16_DRIVER is
-	generic(
-		OSC_Freq_MHz	 :	integer:=60;
-		Refresh_RateHz :	integer:=5
-	);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           FramBUFF : in  STD_LOGIC_VECTOR(16*2*8-1 downto 0);
-           LCD_data : out  STD_LOGIC_VECTOR (7 downto 0);
-           LCD_RS : out  STD_LOGIC;
-           LCD_RW : out  STD_LOGIC;
-			  LCD_E  : out  STD_LOGIC;
-           LCD_RET : out  STD_LOGIC;
-           LCD_CS1 : out  STD_LOGIC;
-           LCD_CS2 : out  STD_LOGIC;
-			  STATEOUT:	out	std_logic_vector(3 downto 0);
-			  refreshPulse	:	out	std_logic
-			  );
-end LCD_2x16_DRIVER;
-
-architecture Behavioral of LCD_2x16_DRIVER is
-
-type	stateT is(Rst,Configure,IDLE,RefreshScreen);
-signal	state	:	stateT;
-
-signal	ShortTimePulse		:	 std_logic;
-signal	MidleTimePulse		:	 std_logic;
-signal   Refresh_RatePulse	:	 std_logic;
-signal   Start 				:   STD_LOGIC;
-
-signal	CFGM_LCD_RS			:	std_logic;
-signal	CFGM_LCD_RW			:	std_logic;
-signal	CFGM_LCD_E			:	std_logic;
-signal	CFGM_LCD_DATA		:	std_logic_vector(7 downto 0);
-signal	CFGM_Enable			:	std_logic;
-signal	CFGM_completed		:	std_logic;
-
-
-signal	FRMW_LCD_RS			:	std_logic;
-signal	FRMW_LCD_RW			:	std_logic;
-signal	FRMW_LCD_E			:	std_logic;
-signal	FRMW_LCD_DATA		:	std_logic_vector(7 downto 0);
-signal	FRMW_Enable			:	std_logic;
-signal	FRMW_completed		:	std_logic;
-
-begin
-
-
-Counter : LCD_Counter
-generic map(OSC_Freq_MHz,Refresh_RateHz)
-port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start);
-
-ConfigModule	:	Config_Module
-port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse);
-
-
-FrameWriter	:	FRAME_WRITER 
-port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse);
-
-
-STATEOUT(0)	<=	'1' when state = 	Rst else '0';
-STATEOUT(1)	<=	'1' when state = 	Configure else '0';
-STATEOUT(2)	<=	'1' when state = 	IDLE else '0';
-STATEOUT(3)	<=	'1' when state = 	RefreshScreen else '0';
-
-
-
-refreshPulse	<=	Refresh_RatePulse;
-
-Start			<=	'1';
-
-process(reset,clk)
-begin
-	if reset = '0' then
-		LCD_data	<=	(others=>'0');
-		LCD_RS	<=	'0';
-		LCD_RW	<=	'0';
-		LCD_RET	<=	'0';
-		LCD_CS1	<=	'0';
-		LCD_CS2	<=	'0';
-		LCD_E		<=	'0';
-		state		<=	Rst;
-		CFGM_Enable	<=	'0';
-		FRMW_Enable	<=	'0';
-	elsif clk'event and clk ='1' then
-		case state is
-			when	Rst =>
-				LCD_data		<=	(others=>'0');
-				LCD_RS		<=	'0';
-				LCD_RW		<=	'0';
-				LCD_E			<=	'0';
-				CFGM_Enable	<=	'1';
-				FRMW_Enable	<=	'0';
-				if	Refresh_RatePulse = '1' then
-					state <=	Configure;
-				end if; 
-			when	Configure =>
-				LCD_data		<=	CFGM_LCD_data;
-				LCD_RS		<=	CFGM_LCD_RS;
-				LCD_RW		<=	CFGM_LCD_RW;
-				LCD_E			<=	CFGM_LCD_E;
-				CFGM_Enable	<=	'0';
-				if CFGM_completed	=	'1' then
-					state	<=	IDLE;
-				end if;
-			when	IDLE =>
-				if	Refresh_RatePulse = '1' then
-					state <=	RefreshScreen;
-					FRMW_Enable	<=	'1';
-				end if;
-				LCD_RS		<=	'0';
-				LCD_RW		<=	'0';
-				LCD_E			<=	'0';
-				LCD_data		<=	(others=>'0');
-			when	RefreshScreen =>
-				LCD_data		<=	FRMW_LCD_data;
-				LCD_RS		<=	FRMW_LCD_RS;
-				LCD_RW		<=	FRMW_LCD_RW;
-				LCD_E			<=	FRMW_LCD_E;
-				FRMW_Enable	<=	'0';
-				if FRMW_completed	=	'1' then
-					state	<=	IDLE;
-				end if;
-		end case;
-	end if;
-end process;
-end Behavioral;
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
+++ /dev/null
@@ -1,75 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-
-entity LCD_CLK_GENERATOR is
-	 generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           clk_1us : out  STD_LOGIC);
-end LCD_CLK_GENERATOR;
-
-architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is
-
-Constant clk_1usTRIGER	:	integer	:=	(OSC_freqKHz/2000)+1;
-
-
-signal	cpt1				:	integer;
-
-signal	clk_1us_int		:	std_logic := '0';
-
-
-begin
-
-clk_1us		<=	clk_1us_int;
-
-
-process(reset,clk)
-begin
-	if reset = '0' then
-		cpt1			<=	0;
-		clk_1us_int		<=	'0';
-	elsif clk'event and clk = '1' then
-		if cpt1 = clk_1usTRIGER then
-			clk_1us_int	<=	not clk_1us_int;
-			cpt1			<=	0;
-		else
-			cpt1			<=	cpt1 + 1;
-		end if;
-	end if;
-end process;
-
-
-end ar_LCD_CLK_GENERATOR;
-
-
-
-
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 2 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-use lpp.LCD_16x2_CFG.all;
-
-
-entity AMBA_LCD_16x2_DRIVER is
-    Port ( reset 		: in  STD_LOGIC;
-           clk 		: in  STD_LOGIC;
-           Bp0 		: in  STD_LOGIC;
-           Bp1 		: in  STD_LOGIC;
-           Bp2 		: in  STD_LOGIC;
-			  LCD_data 	: out  STD_LOGIC_VECTOR (7 downto 0);
-           LCD_RS 	: out  STD_LOGIC;
-           LCD_RW 	: out  STD_LOGIC;
-			  LCD_E  	: out  STD_LOGIC;
-           LCD_RET 	: out  STD_LOGIC;
-           LCD_CS1 	: out  STD_LOGIC;
-           LCD_CS2 	: out  STD_LOGIC;
-			  SF_CE0		: out	std_logic
-			  );
-end AMBA_LCD_16x2_DRIVER;
-
-architecture Behavioral of AMBA_LCD_16x2_DRIVER is
-
-signal	FramBUFF :  STD_LOGIC_VECTOR(16*2*8-1 downto 0);
-signal	CMD		:	std_logic_vector(10 downto 0);
-signal	Exec	:		std_logic;
-signal	Ready	:	 std_logic;
-signal	rst	:	std_logic;
-signal	LCD_CTRL	:	 LCD_DRVR_CTRL_BUSS;
-
-begin
-
-LCD_data 	<=	LCD_CTRL.LCD_DATA;
-LCD_RS 	<=	LCD_CTRL.LCD_RS;
-LCD_RW 	<=	LCD_CTRL.LCD_RW;
-LCD_E  	<=	LCD_CTRL.LCD_E;
-
-
-LCD_RET	<=	'0';
-LCD_CS1	<=	'0';
-LCD_CS2	<=	'0';
-
-SF_CE0	<=	'1';
-
-
-
-
-Driver0 : LCD_16x2_ENGINE
-	generic map(50000)
-    Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
-
-FramBUFF(0*8+7 downto 0*8)	<=	X"41" when	Bp0 = '1' else
-								X"42" when	Bp1 = '1' else
-								X"43" when	Bp2 = '1' else
-								X"44";
-								
-FramBUFF(1*8+7 downto 1*8)<=	X"46" when	Bp0 = '1' else
-								X"47" when	Bp1 = '1' else
-								X"48" when	Bp2 = '1' else
-								X"49";
-
-
-CMD(9 downto 0)	<=	Duration_100us & CursorON when	Bp0 = '1' else
-							Duration_100us & CursorOFF;
-							
-
-Exec	<=	Bp1;
-
-FramBUFF(2*8+7 downto 2*8) <= X"23";
-FramBUFF(3*8+7 downto 3*8) <= X"66";
-FramBUFF(4*8+7 downto 4*8) <= X"67";
-FramBUFF(5*8+7 downto 5*8) <= X"68";
-FramBUFF(17*8+7 downto 17*8) <= X"69";
---FramBUFF(16*2*8-1 downto 16) <= (others => '0');
-
-end Behavioral;
-
-
-
-
-
-
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf
+++ /dev/null
@@ -1,37 +0,0 @@
-
-NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_E"	LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RS"	LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RW"	LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-
-NET "LCD_RET"	LOC = "E3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS1"	LOC = "P3" | IOSTANDARD = SSTL2_I;
-NET "LCD_CS2"	LOC = "P4" | IOSTANDARD = SSTL2_I;
-
-NET "LCD_data<0>"	LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<1>"	LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<2>"	LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<3>"	LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<4>"	LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<5>"	LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<6>"	LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
-NET "LCD_data<7>"	LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
- 
-NET "reset"			LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp0"			LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp1"			LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
-NET "Bp2"			LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN;
-
-net "clk"			LOC = "C9"	| IOSTANDARD = LVCMOS33;
-net "clk"	PERIOD = 20.0ns HIGH 40%;
-#net "clkOUT"		LOC = "N14"	| IOSTANDARD = LVCMOS33;
-
-#net "STATEOUT<0>"		LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<1>"		LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<2>"		LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-#net "STATEOUT<3>"		LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ;
-
-#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
\ No newline at end of file
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
+++ /dev/null
@@ -1,173 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-
-
-package amba_lcd_16x2_ctrlr is
-
-constant lcd_space_size : integer := 80;
-
-type FRM_Buff_Space	is array(lcd_space_size-1 downto 0) of std_logic_vector(7 downto 0);
-
-
-type LCD_DRVR_CTRL_BUSS is
-    record
-        LCD_RW	        : std_logic;
-        LCD_RS         : std_logic;
-		  LCD_E          : std_logic;
-		  LCD_DATA		  : std_logic_vector(7 downto 0);
-    end record;
-
-	 type LCD_DRVR_SYNCH_BUSS is
-    record
-        DRVR_READY     	: std_logic;
-        LCD_INITIALISED	: std_logic;
-    end record;
-	
-	
-	 type LCD_DRVR_CMD_BUSS is
-    record
-		  Word				: std_logic_vector(7 downto 0);
-        CMD_Data			: std_logic;  --CMD = '0' and data = '1'
-		  Exec				: std_logic;
-        Duration			: std_logic_vector(1 downto 0);
-    end record;
-	type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0);
-	
-
-
-component LCD_16x2_DRIVER is
-	generic(
-		OSC_Freq_MHz	 :	integer:=60
-	);
-    Port ( reset : in  STD_LOGIC;
-	   clk : in  STD_LOGIC;
-           LCD_CTRL	:	out LCD_DRVR_CTRL_BUSS;
-	   SYNCH	:	out LCD_DRVR_SYNCH_BUSS;
-	   DRIVER_CMD	:	in  LCD_DRVR_CMD_BUSS
-			  );
-end component;
-
-
-
-component  amba_lcd_16x2_driver is
-    Port ( reset 		: in  STD_LOGIC;
-           clk 		: in  STD_LOGIC;
-           Bp0 		: in  STD_LOGIC;
-           Bp1 		: in  STD_LOGIC;
-           Bp2 		: in  STD_LOGIC;
-			  LCD_data 	: out  STD_LOGIC_VECTOR (7 downto 0);
-           LCD_RS 	: out  STD_LOGIC;
-           LCD_RW 	: out  STD_LOGIC;
-			  LCD_E  	: out  STD_LOGIC;
-           LCD_RET 	: out  STD_LOGIC;
-           LCD_CS1 	: out  STD_LOGIC;
-           LCD_CS2 	: out  STD_LOGIC;
-			  SF_CE0		: out	std_logic
-			  );
-end component; 
-
-
-
-component FRAME_CLK_GEN is
-	generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           FRAME_CLK : out  STD_LOGIC);
-end component;
-
-
-
-component LCD_2x16_DRIVER is
-	generic(
-		OSC_Freq_MHz	 :	integer:=60;
-		Refresh_RateHz :	integer:=5
-	);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           FramBUFF : in  STD_LOGIC_VECTOR(16*2*8-1 downto 0);
-           LCD_data : out  STD_LOGIC_VECTOR (7 downto 0);
-           LCD_RS : out  STD_LOGIC;
-           LCD_RW : out  STD_LOGIC;
-	   LCD_E  : out  STD_LOGIC;
-           LCD_RET : out  STD_LOGIC;
-           LCD_CS1 : out  STD_LOGIC;
-           LCD_CS2 : out  STD_LOGIC;
-	   STATEOUT:	out	std_logic_vector(3 downto 0);
-	   refreshPulse	:	out	std_logic
-			  );
-end component;
-
-
-component LCD_CLK_GENERATOR is
-	 generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk : in  STD_LOGIC;
-           reset : in  STD_LOGIC;
-           clk_1us : out  STD_LOGIC);
-end component;
-
-component LCD_16x2_ENGINE is
-	generic(OSC_freqKHz	:	integer := 50000);
-    Port ( clk 	:	in  STD_LOGIC;
-           reset 	:	in  STD_LOGIC;
-	  DATA	:	in FRM_Buff_Space;
-	  CMD		:	in std_logic_vector(10 downto 0);
-	  Exec	:	in	std_logic;
-	  Ready	:	out std_logic;
-	  LCD_CTRL	:	out LCD_DRVR_CTRL_BUSS
-			  );
-end component;
-
-
-
-component apb_lcd_ctrlr is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-	rst    : in  std_ulogic;
-	clk    : in  std_ulogic;
-	apbi   : in  apb_slv_in_type;
-	apbo   : out apb_slv_out_type;
-	LCD_data 	: out  STD_LOGIC_VECTOR (7 downto 0);
-	LCD_RS 	: out  STD_LOGIC;
-	LCD_RW 	: out  STD_LOGIC;
-	LCD_E  	: out  STD_LOGIC;
-	LCD_RET 	: out  STD_LOGIC;
-	LCD_CS1 	: out  STD_LOGIC;
-	LCD_CS2 	: out  STD_LOGIC;
-	SF_CE0		: out	std_logic
-    );
-end component;
-
-
-
-
-end;
diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
deleted file mode 100644
--- a/lib/lpp/amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
+++ /dev/null
@@ -1,167 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.amba_lcd_16x2_ctrlr.all;
-use lpp.LCD_16x2_CFG.all;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-
-entity apb_lcd_ctrlr is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-	rst    : in  std_ulogic;
-	clk    : in  std_ulogic;
-	apbi   : in  apb_slv_in_type;
-	apbo   : out apb_slv_out_type;
-	LCD_data 	: out  STD_LOGIC_VECTOR (7 downto 0);
-	LCD_RS 	: out  STD_LOGIC;
-	LCD_RW 	: out  STD_LOGIC;
-	LCD_E  	: out  STD_LOGIC;
-	LCD_RET 	: out  STD_LOGIC;
-	LCD_CS1 	: out  STD_LOGIC;
-	LCD_CS2 	: out  STD_LOGIC;
-	SF_CE0		: out	std_logic
-    );
-end apb_lcd_ctrlr;
-
-architecture Behavioral of apb_lcd_ctrlr is
-
-signal	FramBUFF :  FRM_Buff_Space;
-signal	CMD		:	std_logic_vector(10 downto 0);
-signal	Exec		:	std_logic;
-signal	Ready		:	std_logic;
-signal	LCD_CTRL	:	LCD_DRVR_CTRL_BUSS;
-
-
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_LCD_CTRLR, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-
---type FRM_Buff_El	is std_logic_vector(31 downto 0);
-type FRM_Buff_Reg	is array(lcd_space_size-1 downto 0) of std_logic_vector(31 downto 0);
-
-
-type LCD_ctrlr_Reg is record
-  CTRL_Reg 		:   std_logic_vector(31 downto 0);
-  FRAME_BUFF   :   FRM_Buff_Reg;
-end record;
-
-signal r : LCD_ctrlr_Reg;
-
-signal Rdata	:	std_logic_vector(31 downto 0);
-
-begin
-
-LCD_data 	<=	LCD_CTRL.LCD_DATA;
-LCD_RS 		<=	LCD_CTRL.LCD_RS;
-LCD_RW 		<=	LCD_CTRL.LCD_RW;
-LCD_E  		<=	LCD_CTRL.LCD_E;
-
-
-LCD_RET	<=	'0';
-LCD_CS1	<=	'0';
-LCD_CS2	<=	'0';
-
-SF_CE0	<=	'1';
-
-CMD(7 downto 0)	<=	r.CTRL_Reg(7 downto 0); --CMD value
-CMD(9 downto 8)	<=	r.CTRL_Reg(9 downto 8); --CMD tempo value
-
-r.CTRL_Reg(10)		<=	Ready;
-
-Driver0 : LCD_16x2_ENGINE
-	generic map(50000)
-    Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
-
-FRM_BF : for i in 0 to lcd_space_size-1 generate
-	FramBUFF(i)	<=	r.FRAME_BUFF(i)(7 downto 0);
-end generate;
-
-
-process(rst,clk)
-begin
-    if rst = '0' then
-        r.CTRL_Reg(9 downto 0) <= (others => '0');
-		  Exec	<=	'0';
-    elsif clk'event and clk = '1' then
-
---APB Write OP
-        if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-            case apbi.paddr(7 downto 2) is
-                when "000000" =>
-                    r.CTRL_Reg(9 downto 0) <= apbi.pwdata(9 downto 0);
-						  Exec	<=	'1';
-                when others =>
-                 writeC:   for i in 1 to lcd_space_size loop
-								if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
-									r.FRAME_BUFF(i-1)	<=	apbi.pwdata;
-								end if;
-						Exec	<=	'0';
-					end loop;
-            end case;
-			else
-				Exec	<=	'0';
-        end if;
-
---APB READ OP
-        if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-            case apbi.paddr(7 downto 2) is
-                when "000000" =>
-                    Rdata <= r.CTRL_Reg;
-                when others =>
-                    readC:   for i in 1 to lcd_space_size loop
-								if TO_INTEGER(unsigned(apbi.paddr(abits-1 downto 2))) =i then
-									Rdata(7 downto 0) <= r.FRAME_BUFF(i-1)(7 downto 0);
-								end if;
-					end loop;
-            end case;
-        end if;
-    
-    end if;
-    apbo.pconfig <= pconfig;
-end process;
-
-apbo.prdata <=	Rdata when apbi.penable = '1' ;
-
-end Behavioral;
-
-
-
-
-
-
diff --git a/lib/lpp/general_purpose/lpp_AMR/APB_AMR.vhd b/lib/lpp/general_purpose/lpp_AMR/APB_AMR.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/APB_AMR.vhd
+++ /dev/null
@@ -1,110 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-use lpp.lpp_AMR.all;
-
---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
-
-entity APB_AMR is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    clkH    : in  std_logic;
-    clk_MOD     : out std_logic;                        --! Horloge de sortie, Modulation
-    clk_DMOD    : out std_logic;                       --! Horloge de sortie, Demodulation
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
-);
-end APB_AMR;
-
-
-architecture ar_APB_AMR of APB_AMR is
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_BALISE, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-type AMR_ctrlr_Reg is record
-     AMR_CTRL : std_logic_vector(31 downto 0);
-     AMR_FREQ : std_logic_vector(31 downto 0);
-     AMR_PHI : std_logic_vector(31 downto 0);
-
-end record;
-
-signal Rec : AMR_ctrlr_Reg := ((others => '0'),std_logic_vector(to_unsigned(149,32)),std_logic_vector(to_unsigned(4,32)));
-signal Rdata : std_logic_vector(31 downto 0);
-signal Div : integer range 250 to 1024*1024;
-signal Phi : integer range 4 to 1024*8;
-signal Stop_count : std_logic;
-
-
-begin
-
-    DEF0 : entity work.Dephaseur
-        port map(clk,rst,Div,Phi,Stop_count,clk_MOD,clk_DMOD);
- 
-
-Div <= to_integer(unsigned(Rec.AMR_FREQ(19 downto 0)));
-Phi <= to_integer(unsigned(Rec.AMR_PHI(12 downto 0)));
-Stop_count <= Rec.AMR_CTRL(0);
-
-
-    process(rst,clk)
-    begin
-        if(rst='0')then
-            Rec.AMR_CTRL <= (others => '0');     
-            Rec.AMR_FREQ <= std_logic_vector(to_unsigned(149,32));
-            Rec.AMR_PHI <= std_logic_vector(to_unsigned(4,32));
-
-        elsif(clk'event and clk='1')then 
-
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>                         
-                         Rec.AMR_CTRL <= apbi.pwdata;
-                    when "000001" =>
-                         Rec.AMR_FREQ <= apbi.pwdata;
-                    when "000010" =>
-                         Rec.AMR_PHI <= apbi.pwdata;
-                    when others =>
-                        null;
-                end case;
-            end if;
-
-    --APB READ OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                         Rdata <= Rec.AMR_CTRL;
-                     when "000001" =>
-                         Rdata <= Rec.AMR_FREQ;
-                    when "000010" =>
-                         Rdata <= Rec.AMR_PHI;
-                    when others =>
-                        Rdata <= (others => '0');
-                end case;
-            end if;
-
-        end if;
-        apbo.pconfig <= pconfig;
-    end process;
-
-apbo.prdata     <=   Rdata when apbi.penable = '1';
-
-end ar_APB_AMR;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_AMR/Clock_multi.vhd b/lib/lpp/general_purpose/lpp_AMR/Clock_multi.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/Clock_multi.vhd
+++ /dev/null
@@ -1,42 +0,0 @@
--- Clock_multi.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---! Compteur utilise en diviseur de frequence
-
-entity Clock_multi is
-
-port( 
-    clk,raz     : in std_logic;                     --! Horloge 25Mhz et reset du systeme
-    pulse       : in std_logic;                     --! Reset local
-    N           : in integer range 4 to 25_000;     --! La valeur MAX du compteur
-    clk_var     : out std_logic);                   --! Horloge obtenu en sortie
-
-end Clock_multi;
-
---!@details Il permet a partir de l'horloge en entree, d'obtenir un horloge en sortie de frequence plus faible
-architecture ar_Clock_multi of Clock_multi is
-
-signal clockint : std_logic;
-signal countint : integer range 0 to 15_000;
-
-begin 
-    process (clk,raz)
-    begin
-        if(raz='0' or pulse='1')then
-            clockint <= '0';
-            countint <= 0;
-        elsif(clk' event and clk='1')then
-            if(countint = N/2-1)then 
-                countint <= 0;
-                clockint <= not clockint;
-            else 
-                countint <= countint+1;
-            end if;
-        end if;
-    end process;
-
-clk_var <= clockint;
-
-end ar_Clock_multi;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_AMR/Dephaseur.vhd b/lib/lpp/general_purpose/lpp_AMR/Dephaseur.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/Dephaseur.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
--- Dephaseur.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---! Programme qui va gerer la creation des deux signaux de sortie
-
-entity Dephaseur is
-
-port( 
-    clk,raz     : in std_logic;                         --! Horloge 25Mhz et reset du systeme 
-    div         : in integer range 250 to 25_000;       --! Valeur MAX pour le compteur (Frequence)
-    phi         : in integer range 4 to 12500;          --! Valeur MAX pour le compteur (Dephasage)
-    Stop_count  : in std_logic;                         --! Flag, interuption des compteur / synchronise phi et div
-    clk_MOD     : out std_logic;                        --! Horloge de sortie, Modulation
-    clk_DMOD    : out std_logic);                       --! Horloge de sortie, Demodulation
-
-end Dephaseur;
-
-
-architecture ar_Dephaseur of Dephaseur is
-
-signal clk_var      : std_logic;
-signal s_clk_MOD    : std_logic;
-signal s_clk_DMOD   : std_logic;
-signal pulse        : std_logic;
-signal ou           : std_logic;
-
-begin
-
-    MODUL : entity work.Clock_multi
-        port map(clk,raz,Stop_count,div,s_clk_MOD);
-
-    Rz : entity work.Gene_Rz
-        port map(clk,raz,s_clk_MOD,pulse);
-
-
-    CLKVAR : entity work.Clock_multi
-        port map(clk,raz,ou,phi,clk_var);
-                    
-                    
-    RETARD : entity work.bclk_reg
-        port map(clk_var,raz,s_clk_MOD,clk_DMOD);
-
-clk_MOD <= s_clk_MOD;
-ou <= pulse or Stop_count;
-
-end ar_Dephaseur;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_AMR/Gene_Rz.vhd b/lib/lpp/general_purpose/lpp_AMR/Gene_Rz.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/Gene_Rz.vhd
+++ /dev/null
@@ -1,42 +0,0 @@
--- Gene_Rz.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
---! Programme qui genere un reset local utilise pour synchroniser les compteur
-
-entity Gene_Rz is
-
-port( 
-    clk,raz     : in std_logic;     --! Horloge 25Mhz et reset du systeme
-    clk_20K     : in std_logic;     --! Horloge de modulation
-    pulse       : out std_logic);   --! Reset local
-
-end Gene_Rz;
-
-
-architecture ar_Gene_Rz of Gene_Rz is
-
-signal s_clk : std_logic;
-
-begin 
-    process (clk,raz)
-    begin
-        if(raz='0')then
-            pulse <= '0';
-            s_clk <= '0';           
-            
-        elsif(clk' event and clk='1')then            
-            s_clk <= clk_20K;
-            
-            if(s_clk='0' and clk_20K='1')then
-                pulse <= '1';
-            elsif(s_clk='1' and clk_20K='0')then
-                pulse <= '1';
-            else
-                pulse <= '0';  
-            end if;
-
-        end if;
-    end process;
-end ar_Gene_Rz;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_AMR/bclk_reg.vhd b/lib/lpp/general_purpose/lpp_AMR/bclk_reg.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/bclk_reg.vhd
+++ /dev/null
@@ -1,34 +0,0 @@
--- bclk_reg.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
---! Simple bascule D utilise pour retarder d'un top d'horloge le signal d'entre
-
-entity bclk_reg is 
-
-port(
-    clk,raz     : in std_logic;     --! Horloge 25Mhz et reset du systeme 
-    D           : in std_logic;     --! Signal d'entre
-    Q           : out std_logic);   --! Signal de sortie
-
-end bclk_reg;
-
-
-architecture ar_bclk_reg of bclk_reg is
-
-begin
-    process(clk,raz)
-        begin
-
-        if(raz='0')then
-            Q <= '0';
-
-        elsif(clk'event and clk='1')then
-           Q <= D;            
-
-        end if;
-
-    end process;
-
-end ar_bclk_reg;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_AMR/lpp_AMR.vhd b/lib/lpp/general_purpose/lpp_AMR/lpp_AMR.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_AMR/lpp_AMR.vhd
+++ /dev/null
@@ -1,72 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-
---! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on 
-
-package lpp_AMR is
-
-component APB_AMR is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
- port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    clkH    : in  std_logic; 
-    clk_MOD     : out std_logic;                        --! Horloge de sortie, Modulation
-    clk_DMOD    : out std_logic;                       --! Horloge de sortie, Demodulation
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
-);
-end component;
-
-component bclk_reg is
-
-port(
-    clk,raz     : in std_logic;     --! Horloge 25Mhz et reset du systeme 
-    D           : in std_logic;     --! Signal d'entre
-    Q           : out std_logic);   --! Signal de sortie
-
-end component;
-
- component Clock_multi is
-
-port( 
-    clk,raz     : in std_logic;                     --! Horloge 25Mhz et reset du systeme
-    pulse       : in std_logic;                     --! Reset local
-    N           : in integer range 4 to 25_000;     --! La valeur MAX du compteur
-    clk_var     : out std_logic);                   --! Horloge obtenu en sortie
-
-end component;
-
-
-component Dephaseur is
-
-port( 
-    clk,raz     : in std_logic;                         --! Horloge 25Mhz et reset du systeme 
-    div         : in integer range 250 to 25_000;       --! Valeur MAX pour le compteur (Frequence)
-    phi         : in integer range 4 to 12500;          --! Valeur MAX pour le compteur (Dephasage)
-    Stop_count  : in std_logic;                         --! Flag, interuption des compteur / synchronise phi et div
-    clk_MOD     : out std_logic;                        --! Horloge de sortie, Modulation
-    clk_DMOD    : out std_logic);                       --! Horloge de sortie, Demodulation
-
-end component;
-
-
-component Gene_Rz is
-
-port( 
-    clk,raz     : in std_logic;     --! Horloge 25Mhz et reset du systeme
-    clk_20K     : in std_logic;     --! Horloge de modulation
-    pulse       : out std_logic);   --! Reset local
-
-end component;
-end;
diff --git a/lib/lpp/general_purpose/lpp_balise/APB_Balise.vhd b/lib/lpp/general_purpose/lpp_balise/APB_Balise.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_balise/APB_Balise.vhd
+++ /dev/null
@@ -1,120 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                        Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-use lpp.lpp_balise.all;
-
---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
-
-entity APB_Balise is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    Flag    : out std_logic_vector(3 downto 0);
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
-);
-end APB_Balise;
-
-
-architecture ar_APB_Balise of APB_Balise is
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_BALISE, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-type BALISE_ctrlr_Reg is record
-     BALISE_Flag0 : std_logic;
-     BALISE_Flag1 : std_logic;
-     BALISE_Flag2 : std_logic;
-     BALISE_Flag3 : std_logic;
-end record;
-
-signal Rec : BALISE_ctrlr_Reg;
-signal Rdata : std_logic_vector(31 downto 0);
-
-begin
-
-Flag(0) <= Rec.BALISE_Flag0;
-Flag(1) <= Rec.BALISE_Flag1;
-Flag(2) <= Rec.BALISE_Flag2;
-Flag(3) <= Rec.BALISE_Flag3;
-
-    process(rst,clk)
-    begin
-        if(rst='0')then
-            Rec.BALISE_Flag0 <= '0';
-            Rec.BALISE_Flag1 <= '0';
-            Rec.BALISE_Flag2 <= '0';
-            Rec.BALISE_Flag3 <= '0';
-            
-        elsif(clk'event and clk='1')then 
-
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>                         
-                         Rec.BALISE_Flag0 <= apbi.pwdata(0);
-                         Rec.BALISE_Flag1 <= apbi.pwdata(4);
-                         Rec.BALISE_Flag2 <= apbi.pwdata(8);
-                         Rec.BALISE_Flag3 <= apbi.pwdata(12);
-                    when others =>
-                        null;
-                end case;
-            end if;
-
-    --APB READ OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                         Rdata(31 downto 16) <= (others => '0');
-                         Rdata(15 downto 12) <= "000" & Rec.BALISE_Flag3;
-                         Rdata(11 downto 8) <= "000" & Rec.BALISE_Flag2;
-                         Rdata(7 downto 4) <= "000" & Rec.BALISE_Flag1;
-                         Rdata(3 downto 0) <= "000" & Rec.BALISE_Flag0;
-                    when others =>
-                        Rdata <= (others => '0');
-                end case;
-            end if;
-
-        end if;
-        apbo.pconfig <= pconfig;
-    end process;
-
-apbo.prdata     <=   Rdata when apbi.penable = '1';
-
-end ar_APB_Balise;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_balise/lpp_balise.vhd b/lib/lpp/general_purpose/lpp_balise/lpp_balise.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_balise/lpp_balise.vhd
+++ /dev/null
@@ -1,51 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-
---! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on 
-
-package lpp_balise is
-
-component APB_Balise is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-    clk     : in  std_logic;
-    rst     : in  std_logic;
-    Flag    : out std_logic_vector(3 downto 0);
-    apbi    : in  apb_slv_in_type;
-    apbo    : out apb_slv_out_type
-);
-end component;
-
-
-end;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_delay/APB_Delay.vhd b/lib/lpp/general_purpose/lpp_delay/APB_Delay.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_delay/APB_Delay.vhd
+++ /dev/null
@@ -1,137 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                        Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-use lpp.lpp_delay.all;
-
---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
-
-entity APB_Delay is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
-);
-end APB_Delay;
-
-
-architecture ar_APB_Delay of APB_Delay is
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_DELAY, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-type DELAY_ctrlr_Reg is record
-    Delay_CFG : std_logic_vector(3 downto 0);
-    Delay_FreqBoard : std_logic_vector(25 downto 0);
-    Delay_Timer : std_logic_vector(25 downto 0);
-end record;
-
-signal Rec : DELAY_ctrlr_Reg;
-signal Rdata : std_logic_vector(31 downto 0);
-
-signal Flag_st : std_logic;
-signal Flag_end : std_logic;
-signal Flag_OKend : std_logic;
-signal Rz : std_logic;
-signal Raz : std_logic;
-
-begin
-
-Flag_st <= Rec.Delay_CFG(1);
-Rec.Delay_CFG(3) <= Flag_end;
-Rz <= Rec.Delay_CFG(0);
-Flag_OKend <= Rec.Delay_CFG(2);
-
-Raz <= rst and Rz;
-
-Delay0 : TimerDelay
-    port map(clk,Raz,Flag_st,Flag_OKend,Flag_end,Rec.Delay_Timer);
-
-    process(rst,clk)
-    begin
-        if(rst='0')then
-            Rec.Delay_FreqBoard <= (others => '0');
-            Rec.Delay_Timer <= (others => '0');
-            Rec.Delay_CFG(2 downto 0) <= (others => '0');
-            
-        elsif(clk'event and clk='1')then 
-
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                        Rec.Delay_CFG(0) <= apbi.pwdata(0); 
-                        Rec.Delay_CFG(1) <= apbi.pwdata(4);
-                        Rec.Delay_CFG(2) <= apbi.pwdata(8);
-                    when "000001" =>                             
-                        Rec.Delay_FreqBoard <= apbi.pwdata(25 downto 0);
-                    when "000010" =>                             
-                        Rec.Delay_Timer <= apbi.pwdata(25 downto 0);                      
-                    when others =>
-                        null;
-                end case;
-            end if;
-
-    --APB Read OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-                case apbi.paddr(abits-1 downto 2) is
-                    when "000000" =>
-                        Rdata(31 downto 16) <= (others => '0');
-                        Rdata(15 downto 12) <= "000" & Rec.Delay_CFG(3);
-                        Rdata(11 downto 8) <= "000" & Rec.Delay_CFG(2);
-                        Rdata(7 downto 4) <= "000" & Rec.Delay_CFG(1);
-                        Rdata(3 downto 0) <= "000" & Rec.Delay_CFG(0);
-                    when "000001" =>
-                         Rdata(31 downto 26) <= X"0" & "00";
-                         Rdata(25 downto 0) <= Rec.Delay_FreqBoard;
-                    when "000010" =>
-                         Rdata(31 downto 26) <= X"0" & "00";
-                         Rdata(25 downto 0) <= Rec.Delay_Timer;
-                    when others =>
-                        Rdata <= (others => '0');
-                end case;
-            end if;
-
-        end if;
-        apbo.pconfig <= pconfig;
-    end process;
-
-apbo.prdata     <=   Rdata when apbi.penable = '1';
-
-end ar_APB_Delay;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_delay/TimerDelay.vhd b/lib/lpp/general_purpose/lpp_delay/TimerDelay.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_delay/TimerDelay.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--- TimerDelay.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity TimerDelay is
-port(
-    clk     : in  std_logic;
-    raz     : in  std_logic;
-    Start : in std_logic;
-    OKfin : in std_logic;
-    Fin : out std_logic;
-    Cpt : in std_logic_vector(25 downto 0)
-);
-end TimerDelay;
-
-
-architecture ar_TimerDelay of TimerDelay is
-
-type state is (stX,st1,st2);
-signal ect : state;
-
-constant MAX : integer := 67_108_863;
-
-signal delay : integer range 0 to MAX;
-signal compt : integer range 0 to MAX;
---signal Start_reg : std_logic;
-
-
-begin
-
-delay  <= to_integer(unsigned(Cpt));
-
-    process(clk,raz)
-    begin
-    
-        if(raz='0')then
-            Fin <= '1';
-            --Start_reg <= '0';
-            ect <= stX;
-        
-        elsif(clk'event and clk='1')then 
-            --Start_reg <= Start;
-              
-            case ect is
-
-                when stX =>
-                    if(Start = '1')then
-                        --OKst <= '1';
-                        ect <= st1;
-                    end if;
-
-                when st1 =>
-                    if(compt = delay)then
-                        compt <= 0;
-                        --OKst <= '0';
-                        Fin <= '1';
-                        ect <= st2;
-                    else
-                        compt <= compt + 1;
-                        ect <= st1;
-                    end if;
-             
-                when st2 =>
-                     if(OKfin = '1')then
-                         Fin <= '0';
-                         ect <= stX;
-                     end if;
-
-            end case;
-        end if;
-    end process;
-
-end ar_TimerDelay;
\ No newline at end of file
diff --git a/lib/lpp/general_purpose/lpp_delay/lpp_delay.vhd b/lib/lpp/general_purpose/lpp_delay/lpp_delay.vhd
deleted file mode 100644
--- a/lib/lpp/general_purpose/lpp_delay/lpp_delay.vhd
+++ /dev/null
@@ -1,60 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-
---! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on 
-
-package lpp_delay is
-
-component APB_Delay is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8);
-  port (
-    clk     : in  std_logic;           --! Horloge du composant
-    rst     : in  std_logic;           --! Reset general du composant
-    apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-    apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
-);
-end component;
-
-component TimerDelay is
-port(
-    clk     : in  std_logic;
-    raz     : in  std_logic;
-    Start   : in std_logic;
-    OKfin   : in std_logic;
-    Fin     : out std_logic;
-    Cpt     : in std_logic_vector(25 downto 0)
-);
-end component;
-
-end;
\ No newline at end of file