# HG changeset patch # User pellion # Date 2013-05-02 11:53:26 # Node ID 7b269012117520ae6cd9c7483f09e62774b91ad6 # Parent e393b84667faf570e763c8d7623dee816ffc8eb5 # Parent 74b59a804717449910eed9466e8b8a859fb2cb1d WF picker IP + Reg -> the IP is in the reg lib/lpp/lpp_top_lfr_wf_picker.vhd diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/TB_Data_Acquisition.vhd @@ -37,56 +37,60 @@ ARCHITECTURE tb OF TB_Data_Acquisition I sdo : OUT STD_LOGIC); END COMPONENT; - COMPONENT Top_Data_Acquisition - GENERIC ( - hindex : INTEGER; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10; - tech : integer); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - coarse_time_0 : IN STD_LOGIC; - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - enable_f0 : IN STD_LOGIC; - enable_f1 : IN STD_LOGIC; - enable_f2 : IN STD_LOGIC; - enable_f3 : IN STD_LOGIC; - burst_f0 : IN STD_LOGIC; - burst_f1 : IN STD_LOGIC; - burst_f2 : IN STD_LOGIC; - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); - END COMPONENT; + --COMPONENT Top_Data_Acquisition + -- GENERIC ( + -- hindex : INTEGER; + -- nb_burst_available_size : INTEGER := 11; + -- nb_snapshot_param_size : INTEGER := 11; + -- delta_snapshot_size : INTEGER := 16; + -- delta_f2_f0_size : INTEGER := 10; + -- delta_f2_f1_size : INTEGER := 10; + -- tech : integer); + -- PORT ( + -- cnv_run : IN STD_LOGIC; + -- cnv : OUT STD_LOGIC; + -- sck : OUT STD_LOGIC; + -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- cnv_clk : IN STD_LOGIC; + -- cnv_rstn : IN STD_LOGIC; + -- clk : IN STD_LOGIC; + -- rstn : IN STD_LOGIC; + -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0); + -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- AHB_Master_In : IN AHB_Mst_In_Type; + -- AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- coarse_time_0 : IN STD_LOGIC; + -- data_shaping_SP0 : IN STD_LOGIC; + -- data_shaping_SP1 : IN STD_LOGIC; + -- data_shaping_R0 : IN STD_LOGIC; + -- data_shaping_R1 : IN STD_LOGIC; + -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + -- enable_f0 : IN STD_LOGIC; + -- enable_f1 : IN STD_LOGIC; + -- enable_f2 : IN STD_LOGIC; + -- enable_f3 : IN STD_LOGIC; + -- burst_f0 : IN STD_LOGIC; + -- burst_f1 : IN STD_LOGIC; + -- burst_f2 : IN STD_LOGIC; + -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + --END COMPONENT; -- component ports SIGNAL cnv_rstn : STD_LOGIC; @@ -153,7 +157,12 @@ ARCHITECTURE tb OF TB_Data_Acquisition I SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; BEGIN -- tb MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE @@ -211,11 +220,14 @@ BEGIN -- tb ----------------------------------------------------------------------------- - Top_Data_Acquisition_2: Top_Data_Acquisition + Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip GENERIC MAP ( hindex => 2, nb_burst_available_size => nb_burst_available_size, nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size =>16, + delta_f2_f0_size =>10, + delta_f2_f1_size =>10, tech => 0) PORT MAP ( cnv_run => run_cnv, @@ -236,7 +248,11 @@ BEGIN -- tb sample_f3_wdata => sample_f3_wdata, AHB_Master_In => AHB_Master_In, AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, + coarse_time_0 => coarse_time_0, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, delta_snapshot => delta_snapshot, delta_f2_f1 => delta_f2_f1, delta_f2_f0 => delta_f2_f0, @@ -277,6 +293,10 @@ BEGIN -- tb burst_f1 <= '0'; --TODO test burst_f2 <= '0'; + data_shaping_SP0 <= '0'; + data_shaping_SP1 <= '0'; + data_shaping_R0 <= '1'; + data_shaping_R1 <= '1'; delta_snapshot <= "0000000000000001"; --nb_snapshot_param <= "00000001110"; -- 14+1 = 15 diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/Top_Data_Acquisition.vhd @@ -1,5 +1,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; LIBRARY lpp; USE lpp.lpp_ad_conv.ALL; @@ -59,6 +60,11 @@ ENTITY Top_Data_Acquisition IS coarse_time_0 : IN STD_LOGIC; --config + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); @@ -124,13 +130,25 @@ ARCHITECTURE tb OF Top_Data_Acquisition -- SIGNAL sample_filter_v2_out_val : STD_LOGIC; SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); -- SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); -- SIGNAL sample_f2_val : STD_LOGIC; SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); @@ -196,7 +214,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_RAM, + Mem_use => use_CEL, -- use_RAM Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, @@ -213,12 +231,63 @@ BEGIN sample_out_val => sample_filter_v2_out_val, sample_out => sample_filter_v2_out); - --sample_filter_v2_out_val <= sample_val_delay; + ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_data_shaping_out_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; + END IF; + END PROCESS; - ChanelLoopOut : FOR i IN 0 TO 5 GENERATE + SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0,j) <= '0'; + sample_data_shaping_out(1,j) <= '0'; + sample_data_shaping_out(2,j) <= '0'; + sample_data_shaping_out(3,j) <= '0'; + sample_data_shaping_out(4,j) <= '0'; + sample_data_shaping_out(5,j) <= '0'; + sample_data_shaping_out(6,j) <= '0'; + sample_data_shaping_out(7,j) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); + END IF; + sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); + sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); + sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); + sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE SampleLoopOut : FOR j IN 0 TO 15 GENERATE - sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j); - --sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); + sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); END GENERATE; END GENERATE; ----------------------------------------------------------------------------- @@ -226,39 +295,39 @@ BEGIN ----------------------------------------------------------------------------- Downsampling_f0 : Downsampling GENERIC MAP ( - ChanelCount => 6, + ChanelCount => 8, SampleSize => 16, DivideParam => 4) PORT MAP ( clk => clk, rstn => rstn, - sample_in_val => sample_filter_v2_out_val, + sample_in_val => sample_filter_v2_out_val_s, sample_in => sample_filter_v2_out_s, sample_out_val => sample_f0_val, sample_out => sample_f0); - + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata_s(I) <= sample_f0(0, I); - sample_f0_wdata_s(16*1+I) <= sample_f0(1, I); - sample_f0_wdata_s(16*2+I) <= sample_f0(2, I); - sample_f0_wdata_s(16*3+I) <= sample_f0(3, I); - sample_f0_wdata_s(16*4+I) <= sample_f0(4, I); - sample_f0_wdata_s(16*5+I) <= sample_f0(5, I); + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 END GENERATE all_bit_sample_f0; sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); ----------------------------------------------------------------------------- -- F1 -- @4096 Hz ----------------------------------------------------------------------------- Downsampling_f1 : Downsampling GENERIC MAP ( - ChanelCount => 6, + ChanelCount => 8, SampleSize => 16, DivideParam => 6) PORT MAP ( @@ -268,26 +337,35 @@ BEGIN sample_in => sample_f0, sample_out_val => sample_f1_val, sample_out => sample_f1); - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1; - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata_s(I) <= sample_f1(0, I); - sample_f1_wdata_s(16*1+I) <= sample_f1(1, I); - sample_f1_wdata_s(16*2+I) <= sample_f1(2, I); - sample_f1_wdata_s(16*3+I) <= sample_f1(3, I); - sample_f1_wdata_s(16*4+I) <= sample_f1(4, I); - sample_f1_wdata_s(16*5+I) <= sample_f1(5, I); - END GENERATE all_bit_sample_f1; + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); ----------------------------------------------------------------------------- -- F2 -- @256 Hz ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + Downsampling_f2 : Downsampling GENERIC MAP ( ChanelCount => 6, @@ -297,16 +375,16 @@ BEGIN clk => clk, rstn => rstn, sample_in_val => sample_f0_val , - sample_in => sample_f0, + sample_in => sample_f0_s, sample_out_val => sample_f2_val, sample_out => sample_f2); sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE sample_f2_wdata_s(I) <= sample_f2(0, I); @@ -320,6 +398,15 @@ BEGIN ----------------------------------------------------------------------------- -- F3 -- @16 Hz ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + Downsampling_f3 : Downsampling GENERIC MAP ( ChanelCount => 6, @@ -329,16 +416,16 @@ BEGIN clk => clk, rstn => rstn, sample_in_val => sample_f1_val , - sample_in => sample_f1, + sample_in => sample_f1_s, sample_out_val => sample_f3_val, sample_out => sample_f3); sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE sample_f3_wdata_s(I) <= sample_f3(0, I); diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_waveform_picker.do @@ -42,7 +42,10 @@ vcom -quiet -93 -work lpp ../../lib/lpp/ vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +#vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd vcom -quiet -93 -work lpp ../../lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd diff --git a/lib/lpp/general_purpose/Adder.vhd b/lib/lpp/general_purpose/Adder.vhd --- a/lib/lpp/general_purpose/Adder.vhd +++ b/lib/lpp/general_purpose/Adder.vhd @@ -22,10 +22,6 @@ LIBRARY IEEE; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.general_purpose.ALL; - - ENTITY Adder IS GENERIC( diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd --- a/lib/lpp/general_purpose/MAC_CONTROLER.vhd +++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - --IDLE =00 MAC =01 MULT =10 ADD =11 diff --git a/lib/lpp/general_purpose/MAC_MUX.vhd b/lib/lpp/general_purpose/MAC_MUX.vhd --- a/lib/lpp/general_purpose/MAC_MUX.vhd +++ b/lib/lpp/general_purpose/MAC_MUX.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_MUX is generic( diff --git a/lib/lpp/general_purpose/MAC_MUX2.vhd b/lib/lpp/general_purpose/MAC_MUX2.vhd --- a/lib/lpp/general_purpose/MAC_MUX2.vhd +++ b/lib/lpp/general_purpose/MAC_MUX2.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - entity MAC_MUX2 is diff --git a/lib/lpp/general_purpose/MAC_REG.vhd b/lib/lpp/general_purpose/MAC_REG.vhd --- a/lib/lpp/general_purpose/MAC_REG.vhd +++ b/lib/lpp/general_purpose/MAC_REG.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_REG is generic(size : integer := 16); diff --git a/lib/lpp/general_purpose/Multiplier.vhd b/lib/lpp/general_purpose/Multiplier.vhd --- a/lib/lpp/general_purpose/Multiplier.vhd +++ b/lib/lpp/general_purpose/Multiplier.vhd @@ -23,11 +23,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - - entity Multiplier is generic( Input_SZ_A : integer := 16; diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -22,7 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; use lpp.general_purpose.all; --! Driver de l'ALU diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -22,8 +22,8 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_matrix.all; +--library lpp; +--use lpp.lpp_matrix.all; entity MatriceSpectrale is generic( @@ -34,14 +34,17 @@ entity MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end entity; @@ -59,18 +62,23 @@ signal TopSM_Data2 : std_logic_vect begin - TopSM : TopSpecMatrix + CTRL0 : entity work.ReUse_CTRLR + port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); + + + TopSM : entity work.TopSpecMatrix generic map (Input_SZ) port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); - SM : SpectralMatrix + SM : entity work.SpectralMatrix generic map (Input_SZ,Result_SZ) port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); - DISP : Dispatch + DISP : entity work.Dispatch generic map(Result_SZ) port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); +Statu <= TopSM_Statu; end architecture; diff --git a/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + + ReUse : out std_logic_vector(4 downto 0) + ); +end entity; + + +architecture ar_ReUse_CTRLR of ReUse_CTRLR is + +signal ResetReUse : std_logic_vector(4 downto 0); +signal MatrixParam : integer; +signal MatrixParam_Reg : integer; + +begin + + + + process (clk,reset) +-- variable MatrixParam : integer; + begin +-- MatrixParam := to_integer(unsigned(Statu)); + + if(reset='0')then + ResetReUse <= (others => '1'); + MatrixParam_Reg <= 0; + + + elsif(clk' event and clk='1')then + MatrixParam_Reg <= MatrixParam; + + if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11 + ResetReUse(0) <= '0'; + elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12 + ResetReUse(1) <= '0'; + elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13 + ResetReUse(2) <= '0'; + elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14 + ResetReUse(3) <= '0'; + elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15 + ResetReUse(4) <= '0'; + end if; + + end if; + end process; + + MatrixParam <= to_integer(unsigned(Statu)); + ReUse <= SetReUse and ResetReUse; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -65,14 +65,17 @@ component MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end component; @@ -250,4 +253,14 @@ component ALU_Driver is ); end component; +component ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + ReUse : out std_logic_vector(4 downto 0) + ); +end component; + end; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -143,7 +143,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_CEL, + Mem_use => use_RAM, Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, -- TODO diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -36,6 +36,12 @@ USE techmap.gencomp.ALL; ENTITY lpp_top_apbreg IS GENERIC ( + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + pindex : INTEGER := 4; paddr : INTEGER := 4; pmask : INTEGER := 16#fff#; @@ -49,6 +55,8 @@ ENTITY lpp_top_apbreg IS apbi : IN apb_slv_in_type; apbo : OUT apb_slv_out_type; + --------------------------------------------------------------------------- + -- Spectral Matrix Reg -- IN ready_matrix_f0_0 : IN STD_LOGIC; ready_matrix_f0_1 : IN STD_LOGIC; @@ -71,7 +79,43 @@ ENTITY lpp_top_apbreg IS addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- WaveForm picker Reg + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- OUT + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + --------------------------------------------------------------------------- ); END lpp_top_apbreg; @@ -84,7 +128,7 @@ ARCHITECTURE beh OF lpp_top_apbreg IS 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); - TYPE lpp_dma_regs IS RECORD + TYPE lpp_SpectralMatrix_regs IS RECORD config_active_interruption_onNewMatrix : STD_LOGIC; config_active_interruption_onError : STD_LOGIC; status_ready_matrix_f0_0 : STD_LOGIC; @@ -98,56 +142,144 @@ ARCHITECTURE beh OF lpp_top_apbreg IS addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); END RECORD; + SIGNAL reg_sp : lpp_SpectralMatrix_regs; - SIGNAL reg : lpp_dma_regs; + TYPE lpp_WaveformPicker_regs IS RECORD + status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : STD_LOGIC; + data_shaping_SP0 : STD_LOGIC; + data_shaping_SP1 : STD_LOGIC; + data_shaping_R0 : STD_LOGIC; + data_shaping_R1 : STD_LOGIC; + delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : STD_LOGIC; + enable_f1 : STD_LOGIC; + enable_f2 : STD_LOGIC; + enable_f3 : STD_LOGIC; + burst_f0 : STD_LOGIC; + burst_f1 : STD_LOGIC; + burst_f2 : STD_LOGIC; + addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + SIGNAL reg_wp : lpp_WaveformPicker_regs; SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN -- beh - status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; - status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; - status_ready_matrix_f1 <= reg.status_ready_matrix_f1; - status_ready_matrix_f2 <= reg.status_ready_matrix_f2; - status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; - status_error_bad_component_error <= reg.status_error_bad_component_error; + status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; + status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; + status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; + status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; + status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; + status_error_bad_component_error <= reg_sp.status_error_bad_component_error; + + config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; + config_active_interruption_onError <= reg_sp.config_active_interruption_onError; + addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; + addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; + addr_matrix_f1 <= reg_sp.addr_matrix_f1; + addr_matrix_f2 <= reg_sp.addr_matrix_f2; + - config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; - config_active_interruption_onError <= reg.config_active_interruption_onError; - addr_matrix_f0_0 <= reg.addr_matrix_f0_0; - addr_matrix_f0_1 <= reg.addr_matrix_f0_1; - addr_matrix_f1 <= reg.addr_matrix_f1; - addr_matrix_f2 <= reg.addr_matrix_f2; + + + data_shaping_BW <= reg_wp.data_shaping_BW; + data_shaping_SP0 <= reg_wp.data_shaping_SP0; + data_shaping_SP1 <= reg_wp.data_shaping_SP1; + data_shaping_R0 <= reg_wp.data_shaping_R0; + data_shaping_R1 <= reg_wp.data_shaping_R1; + + delta_snapshot <= reg_wp.delta_snapshot; + delta_f2_f1 <= reg_wp.delta_f2_f1; + delta_f2_f0 <= reg_wp.delta_f2_f0; + nb_burst_available <= reg_wp.nb_burst_available; + nb_snapshot_param <= reg_wp.nb_snapshot_param; + + enable_f0 <= reg_wp.enable_f0; + enable_f1 <= reg_wp.enable_f1; + enable_f2 <= reg_wp.enable_f2; + enable_f3 <= reg_wp.enable_f3; + + burst_f0 <= reg_wp.burst_f0; + burst_f1 <= reg_wp.burst_f1; + burst_f2 <= reg_wp.burst_f2; + + addr_data_f0 <= reg_wp.addr_data_f0; + addr_data_f1 <= reg_wp.addr_data_f1; + addr_data_f2 <= reg_wp.addr_data_f2; + addr_data_f3 <= reg_wp.addr_data_f3; lpp_top_apbreg : PROCESS (HCLK, HRESETn) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); BEGIN -- PROCESS lpp_dma_top - IF HRESETn = '0' THEN -- asynchronous reset (active low) - reg.config_active_interruption_onNewMatrix <= '0'; - reg.config_active_interruption_onError <= '0'; - reg.status_ready_matrix_f0_0 <= '0'; - reg.status_ready_matrix_f0_1 <= '0'; - reg.status_ready_matrix_f1 <= '0'; - reg.status_ready_matrix_f2 <= '0'; - reg.status_error_anticipating_empty_fifo <= '0'; - reg.status_error_bad_component_error <= '0'; - reg.addr_matrix_f0_0 <= (OTHERS => '0'); - reg.addr_matrix_f0_1 <= (OTHERS => '0'); - reg.addr_matrix_f1 <= (OTHERS => '0'); - reg.addr_matrix_f2 <= (OTHERS => '0'); - prdata <= (OTHERS => '0'); + IF HRESETn = '0' THEN -- asynchronous reset (active low) + reg_sp.config_active_interruption_onNewMatrix <= '0'; + reg_sp.config_active_interruption_onError <= '0'; + reg_sp.status_ready_matrix_f0_0 <= '0'; + reg_sp.status_ready_matrix_f0_1 <= '0'; + reg_sp.status_ready_matrix_f1 <= '0'; + reg_sp.status_ready_matrix_f2 <= '0'; + reg_sp.status_error_anticipating_empty_fifo <= '0'; + reg_sp.status_error_bad_component_error <= '0'; + reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); + reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f2 <= (OTHERS => '0'); + prdata <= (OTHERS => '0'); - apbo.pirq <= (OTHERS => '0'); + apbo.pirq <= (OTHERS => '0'); + + status_full_ack <= (OTHERS => '0'); + + reg_wp.data_shaping_BW <= '0'; + reg_wp.data_shaping_SP0 <= '0'; + reg_wp.data_shaping_SP1 <= '0'; + reg_wp.data_shaping_R0 <= '0'; + reg_wp.data_shaping_R1 <= '0'; + reg_wp.enable_f0 <= '0'; + reg_wp.enable_f1 <= '0'; + reg_wp.enable_f2 <= '0'; + reg_wp.enable_f3 <= '0'; + reg_wp.burst_f0 <= '0'; + reg_wp.burst_f1 <= '0'; + reg_wp.burst_f2 <= '0'; + reg_wp.addr_data_f0 <= (OTHERS => '0'); + reg_wp.addr_data_f1 <= (OTHERS => '0'); + reg_wp.addr_data_f2 <= (OTHERS => '0'); + reg_wp.addr_data_f3 <= (OTHERS => '0'); + reg_wp.status_full <= (OTHERS => '0'); + reg_wp.status_full_err <= (OTHERS => '0'); + reg_wp.status_new_err <= (OTHERS => '0'); + reg_wp.delta_snapshot <= (OTHERS => '0'); + reg_wp.delta_f2_f1 <= (OTHERS => '0'); + reg_wp.delta_f2_f0 <= (OTHERS => '0'); + reg_wp.nb_burst_available <= (OTHERS => '0'); + reg_wp.nb_snapshot_param <= (OTHERS => '0'); ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + status_full_ack <= (OTHERS => '0'); - reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; - reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; - reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; - reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; + reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; + reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; + reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; + reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; - reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; - reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; + reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; + reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; + + reg_wp.status_full <= reg_wp.status_full OR status_full; + reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; + reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; paddr := "000000"; paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); @@ -155,55 +287,119 @@ BEGIN -- beh IF apbi.psel(pindex) = '1' THEN -- APB DMA READ -- CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; - prdata(1) <= reg.config_active_interruption_onError; - WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; - prdata(1) <= reg.status_ready_matrix_f0_1; - prdata(2) <= reg.status_ready_matrix_f1; - prdata(3) <= reg.status_ready_matrix_f2; - prdata(4) <= reg.status_error_anticipating_empty_fifo; - prdata(5) <= reg.status_error_bad_component_error; - WHEN "000010" => prdata <= reg.addr_matrix_f0_0; - WHEN "000011" => prdata <= reg.addr_matrix_f0_1; - WHEN "000100" => prdata <= reg.addr_matrix_f1; - WHEN "000101" => prdata <= reg.addr_matrix_f2; - WHEN "000110" => prdata <= debug_reg; + -- + WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; + prdata(1) <= reg_sp.config_active_interruption_onError; + WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; + prdata(1) <= reg_sp.status_ready_matrix_f0_1; + prdata(2) <= reg_sp.status_ready_matrix_f1; + prdata(3) <= reg_sp.status_ready_matrix_f2; + prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; + prdata(5) <= reg_sp.status_error_bad_component_error; + WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; + WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; + WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; + WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; + WHEN "000110" => prdata <= debug_reg; + -- + WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; + prdata(1) <= reg_wp.data_shaping_SP0; + prdata(2) <= reg_wp.data_shaping_SP1; + prdata(3) <= reg_wp.data_shaping_R0; + prdata(4) <= reg_wp.data_shaping_R1; + WHEN "001001" => prdata(0) <= reg_wp.enable_f0; + prdata(1) <= reg_wp.enable_f1; + prdata(2) <= reg_wp.enable_f2; + prdata(3) <= reg_wp.enable_f3; + prdata(4) <= reg_wp.burst_f0; + prdata(5) <= reg_wp.burst_f1; + prdata(6) <= reg_wp.burst_f2; + WHEN "001010" => prdata <= reg_wp.addr_data_f0; + WHEN "001011" => prdata <= reg_wp.addr_data_f1; + WHEN "001100" => prdata <= reg_wp.addr_data_f2; + WHEN "001101" => prdata <= reg_wp.addr_data_f3; + WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; + prdata(7 DOWNTO 4) <= reg_wp.status_full_err; + prdata(11 DOWNTO 8) <= reg_wp.status_new_err; + WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; + WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; + WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; + WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + -- WHEN OTHERS => NULL; END CASE; IF (apbi.pwrite AND apbi.penable) = '1' THEN -- APB DMA WRITE -- CASE paddr(7 DOWNTO 2) IS - WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); - reg.config_active_interruption_onError <= apbi.pwdata(1); - WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); - reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); - reg.status_ready_matrix_f1 <= apbi.pwdata(2); - reg.status_ready_matrix_f2 <= apbi.pwdata(3); - reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); - reg.status_error_bad_component_error <= apbi.pwdata(5); - WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; - WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; - WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; - WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); + reg_sp.config_active_interruption_onError <= apbi.pwdata(1); + WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); + reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); + reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg_sp.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); + reg_wp.data_shaping_SP0 <= apbi.pwdata(1); + reg_wp.data_shaping_SP1 <= apbi.pwdata(2); + reg_wp.data_shaping_R0 <= apbi.pwdata(3); + reg_wp.data_shaping_R1 <= apbi.pwdata(4); + WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); + reg_wp.enable_f1 <= apbi.pwdata(1); + reg_wp.enable_f2 <= apbi.pwdata(2); + reg_wp.enable_f3 <= apbi.pwdata(3); + reg_wp.burst_f0 <= apbi.pwdata(4); + reg_wp.burst_f1 <= apbi.pwdata(5); + reg_wp.burst_f2 <= apbi.pwdata(6); + WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; + WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; + WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; + WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); + reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); + reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); + status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); + status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); + status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); + status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); + WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); + WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); + WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); + WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); + WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + -- WHEN OTHERS => NULL; END CASE; END IF; END IF; - apbo.pirq(pirq) <= ( reg.config_active_interruption_onNewMatrix AND ( ready_matrix_f0_0 OR - ready_matrix_f0_1 OR - ready_matrix_f1 OR - ready_matrix_f2) - ) + apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR + ready_matrix_f1 OR + ready_matrix_f2) + ) OR - ( reg.config_active_interruption_onError AND ( error_anticipating_empty_fifo OR - error_bad_component_error) - ); + (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR + error_bad_component_error) + ) + OR + (status_full(0) OR status_full_err(0) OR status_new_err(0) OR + status_full(1) OR status_full_err(1) OR status_new_err(1) OR + status_full(2) OR status_full_err(2) OR status_new_err(2) OR + status_full(3) OR status_full_err(3) OR status_new_err(3) + ); END IF; END PROCESS lpp_top_apbreg; - + apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.prdata <= prdata; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -47,10 +47,15 @@ PACKAGE lpp_top_lfr_pkg IS COMPONENT lpp_top_apbreg GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER); PORT ( HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; @@ -74,7 +79,120 @@ PACKAGE lpp_top_lfr_pkg IS addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_top_lfr_wf_picker + GENERIC ( + hindex : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER; + tech : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + data_shaping_BW : OUT STD_LOGIC); END COMPONENT; -END lpp_top_lfr_pkg; \ No newline at end of file + + COMPONENT lpp_top_lfr_wf_picker_ip + GENERIC ( + hindex : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + tech : INTEGER); + PORT ( + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + + +END lpp_top_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak deleted file mode 100644 --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak +++ /dev/null @@ -1,71 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY grlib; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE lpp_top_lfr_pkg IS - - COMPONENT lpp_top_acq - GENERIC ( - tech : integer); - PORT ( - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); - END COMPONENT; - - COMPONENT lpp_top_apbreg - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ready_matrix_f0_0 : IN STD_LOGIC; - ready_matrix_f0_1 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_anticipating_empty_fifo : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; - debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - status_ready_matrix_f0_0 : OUT STD_LOGIC; - status_ready_matrix_f0_1 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - status_error_anticipating_empty_fifo : OUT STD_LOGIC; - status_error_bad_component_error : OUT STD_LOGIC; - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; - addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - END COMPONENT; - -END lpp_top_lfr_pkg; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd @@ -0,0 +1,243 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker IS + GENERIC ( + hindex : INTEGER := 2; + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq : INTEGER := 0; + tech : INTEGER := 0; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- + coarse_time_0 : IN STD_LOGIC; + + -- + data_shaping_BW : OUT STD_LOGIC + ); +END lpp_top_lfr_wf_picker; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS + + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + +BEGIN + + lpp_top_apbreg_1: lpp_top_apbreg + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq => pirq) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => data_shaping_BW, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip + GENERIC MAP ( + hindex => hindex, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + tech => tech) + PORT MAP ( + cnv_run => cnv_run, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + + clk => HCLK, + rstn => HRESETn, + + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + coarse_time_0 => coarse_time_0, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd @@ -0,0 +1,498 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker_ip IS + GENERIC( + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + tech : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + coarse_time_0 : IN STD_LOGIC; + + --config + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END lpp_top_lfr_wf_picker_ip; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, -- use_RAM + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_data_shaping_out_val <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; + END IF; + END PROCESS; + + SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0,j) <= '0'; + sample_data_shaping_out(1,j) <= '0'; + sample_data_shaping_out(2,j) <= '0'; + sample_data_shaping_out(3,j) <= '0'; + sample_data_shaping_out(4,j) <= '0'; + sample_data_shaping_out(5,j) <= '0'; + sample_data_shaping_out(6,j) <= '0'; + sample_data_shaping_out(7,j) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j); + END IF; + sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j); + sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j); + sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j); + sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j); + END GENERATE; + END GENERATE; + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val_s, + sample_in => sample_filter_v2_out_s, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1; + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + ----------------------------------------------------------------------------- + -- F2 -- @256 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0_s, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1_s, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); + END GENERATE all_bit_sample_f3; + + lpp_waveform_1 : lpp_waveform + GENERIC MAP ( + hindex => hindex, + tech => tech, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + coarse_time_0 => coarse_time_0, -- IN + delta_snapshot => delta_snapshot, -- IN + delta_f2_f1 => delta_f2_f1, -- IN + delta_f2_f0 => delta_f2_f0, -- IN + enable_f0 => enable_f0, -- IN + enable_f1 => enable_f1, -- IN + enable_f2 => enable_f2, -- IN + enable_f3 => enable_f3, -- IN + burst_f0 => burst_f0, -- IN + burst_f1 => burst_f1, -- IN + burst_f2 => burst_f2, -- IN + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, -- IN + status_full_err => status_full_err, + status_new_err => status_new_err, + + addr_data_f0 => addr_data_f0, -- IN + addr_data_f1 => addr_data_f1, -- IN + addr_data_f2 => addr_data_f2, -- IN + addr_data_f3 => addr_data_f3, -- IN + + data_f0_in => data_f0_in_valid, + data_f1_in => data_f1_in_valid, + data_f2_in => data_f2_in_valid, + data_f3_in => data_f3_in_valid, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s; + data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s; + data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s; + data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s; + + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; + +END tb; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd @@ -34,19 +34,19 @@ ENTITY lpp_waveform_dma_selectaddress IS nb_burst_available_size : INTEGER := 11 ); PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - - addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - status_full : OUT STD_LOGIC; - status_full_ack : IN STD_LOGIC; - status_full_err : OUT STD_LOGIC + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + status_full : OUT STD_LOGIC; + status_full_ack : IN STD_LOGIC; + status_full_err : OUT STD_LOGIC ); END; @@ -59,12 +59,13 @@ ARCHITECTURE Behavioral OF lpp_waveform_ SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); SIGNAL update_s : STD_LOGIC; + SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN update_s <= update(0) OR update(1); - + addr_data <= address; - nb_send_next <= std_logic_vector(unsigned(nb_send) + 1); + nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1); FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) BEGIN @@ -74,7 +75,9 @@ BEGIN nb_send <= (OTHERS => '0'); status_full <= '0'; status_full_err <= '0'; + update_r <= "00"; ELSIF HCLK'EVENT AND HCLK = '1' THEN + update_r <= update; CASE state IS WHEN IDLE => IF update_s = '1' THEN @@ -83,12 +86,12 @@ BEGIN WHEN ADD => IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN - state <= IDLE; - IF update = "10" THEN - address <= std_logic_vector(unsigned(address) + 16); + state <= IDLE; + IF update_r = "10" THEN + address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64); nb_send <= nb_send_next; - ELSIF update = "01" THEN - address <= std_logic_vector(unsigned(address) + 1); + ELSIF update_r = "01" THEN + address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4); END IF; ELSE state <= FULL;