# HG changeset patch
# User pellion
# Date 2015-03-25 13:54:50
# Node ID 5d1455cd50ac0ffbd32a4ad2e91acceac7c2f7c9
# Parent  69ac13e4d1370835935455ab8178206a4aec928a

EQM debug

diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc
new file mode 100644
--- /dev/null
+++ b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc
@@ -0,0 +1,30 @@
+# Top Level Design Parameters
+
+# Clocks
+
+create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
+#create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
+#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25_int:Q
+#create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
+create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
+
+
+# False Paths Between Clocks
+
+
+# False Path Constraints
+
+
+# Maximum Delay Constraints
+
+
+# Multicycle Constraints
+
+
+# Virtual Clocks
+# Output Load Constraints
+# Driving Cell Constraints
+# Wire Loads
+# set_wire_load_mode top
+
+# Other Constraints