# HG changeset patch # User pellion # Date 2015-01-20 14:44:42 # Node ID 50f24bdc968c98ce662923b39e39f3e121f6e912 # Parent ac8423f903164a24f68376f549cee83a03a87fbd Correction du CIC (probleme d'ecriture des datas des COMB 256) diff --git a/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc new file mode 100644 --- /dev/null +++ b/boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc @@ -0,0 +1,122 @@ +set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout +set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout +set_io reset -pinname N18 -fixed yes -DIRECTION Inout + +set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout +set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout +set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout +set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout +set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout +set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout +set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout +set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout +set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout +set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout +set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout +set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout +set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout +set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout +set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout +set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout +set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout +set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout +set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout +set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout + +set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout +set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout +set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout +set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout +set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout +set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout +set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout +set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout +set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout +set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout +set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout +set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout +set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout +set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout +set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout +set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout +set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout +set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout +set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout +set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout +set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout +set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout +set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout +set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout +set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout +set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout +set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout +set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout +set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout +set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout +set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout +set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout + +set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout +set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout +set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout +set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout +set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout +set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout + +set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout +set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout +set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout +set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout + +set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout +set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout +set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout +set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout + +set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout +set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout +set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout + +set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout +set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout +set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout +set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout +#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout +#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout +#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout +set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout +#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout + +set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout + +set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout +set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout + +set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout + +set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout +set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout +set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout +set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout + +set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout +set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout +set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout +set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout +set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout +set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout +set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout +set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout +set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout +set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout +set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout +set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout +set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout +set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout diff --git a/designs/Validation_CIC_LFR/Makefile b/designs/Validation_CIC_LFR/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/Makefile @@ -0,0 +1,53 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_CIC_LFR/run.do b/designs/Validation_CIC_LFR/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/run.do @@ -0,0 +1,23 @@ +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_integrator.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_downsampler.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_comb.vhd + + +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_control.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_address_gen.vhd + +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave_inout.do + +run -all + diff --git a/designs/Validation_CIC_LFR/run_add_sub.do b/designs/Validation_CIC_LFR/run_add_sub.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/run_add_sub.do @@ -0,0 +1,12 @@ +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd + +vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd + +vsim work.testbench + +log -r * + +do wave_add_sub.do + +run -all diff --git a/designs/Validation_CIC_LFR/run_calc.do b/designs/Validation_CIC_LFR/run_calc.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/run_calc.do @@ -0,0 +1,10 @@ +vcom -quiet -93 -work work tb_calc.vhd + +vsim work.testbench + +log -r * + +do wave_calc.do + +run -all + diff --git a/designs/Validation_CIC_LFR/run_calc.vhd b/designs/Validation_CIC_LFR/run_calc.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/run_calc.vhd @@ -0,0 +1,10 @@ +vcom -quiet -93 -work work tb_calc.vhd + +vsim work.testbench + +log -r * + +do wave_calc.do + +run -all + diff --git a/designs/Validation_CIC_LFR/tb.vhd b/designs/Validation_CIC_LFR/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/tb.vhd @@ -0,0 +1,238 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_24k : STD_LOGIC := '0'; + SIGNAL clk_24k_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + SIGNAL run : STD_LOGIC; + SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_gen : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0); + SIGNAL data_in_valid : STD_LOGIC; + + CONSTANT DATA_VALUE_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"7FFF"; + CONSTANT DATA_VALUE_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"FFFF"; + CONSTANT DATA_VALUE_2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8000"; + CONSTANT DATA_VALUE_3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0010"; + CONSTANT DATA_VALUE_4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0020"; + CONSTANT DATA_VALUE_5 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040"; + + SIGNAL data_in_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_in_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_3 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_4 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_5 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_in_0_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_1_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_2_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_3_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_4_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_5_temp : STD_LOGIC_VECTOR(15 DOWNTO 0); + +BEGIN + + + + clk <= NOT clk AFTER 5 ns; + clk_24k <= NOT clk_24k AFTER 20345 ns; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_in_valid <= '0'; + clk_24k_r <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + clk_24k_r <= clk_24k; + IF clk_24k = '1' AND clk_24k_r = '0' THEN + data_in_valid <= '1'; + ELSE + data_in_valid <= '0'; + END IF; + END IF; + END PROCESS; + + + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + run <= '0'; + + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + + + WAIT FOR 30 ms; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + cic_lfr_1: cic_lfr + GENERIC MAP ( + tech => 0, + use_RAM_nCEL => 0) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + data_in => data_in_v, + data_in_valid => data_in_valid, + data_out_16 => OPEN, + data_out_16_valid => OPEN, + data_out_256 => OPEN, + data_out_256_valid => OPEN); + ----------------------------------------------------------------------------- + all_bit: FOR J IN 15 DOWNTO 0 GENERATE + data_in_v(0,J) <= data_in_0(J); + data_in_v(1,J) <= data_in_1(J); + data_in_v(2,J) <= data_in_2(J); + data_in_v(3,J) <= data_in_3(J); + data_in_v(4,J) <= data_in_4(J); + data_in_v(5,J) <= data_in_5(J); + END GENERATE all_bit; + ----------------------------------------------------------------------------- + --chirp_gen: chirp + -- GENERIC MAP ( + -- LOW_FREQUENCY_LIMIT => 0, + -- HIGH_FREQUENCY_LIMIT => 1000, + -- NB_POINT_TO_GEN => 10000, + -- AMPLITUDE => 200, + -- NB_BITS => 16) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- data_ack => data_in_valid, + -- data => data_in); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_in_0_temp <= (OTHERS => '0'); + data_in_1_temp <= (OTHERS => '0'); + data_in_2_temp <= (OTHERS => '0'); + data_in_3_temp <= (OTHERS => '0'); + data_in_4_temp <= (OTHERS => '0'); + data_in_5_temp <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF data_in_valid = '1' THEN + data_in_0_temp <= DATA_VALUE_0; + data_in_1_temp <= DATA_VALUE_1; + data_in_2_temp <= DATA_VALUE_2; + data_in_3_temp <= DATA_VALUE_3; + data_in_4_temp <= DATA_VALUE_4; + data_in_5_temp <= DATA_VALUE_5; + END IF; + END IF; + END PROCESS; + --data_in_0 <= data_in_0_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_0; + data_in_1 <= data_in_1_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_1; + data_in_2 <= data_in_2_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_2; + data_in_3 <= data_in_3_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_3; + data_in_4 <= data_in_4_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_4; + data_in_5 <= data_in_5_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_5; + + ----------------------------------------------------------------------------- + chirp_gen: chirp + GENERIC MAP ( + LOW_FREQUENCY_LIMIT => 0, + HIGH_FREQUENCY_LIMIT => 1000, + NB_POINT_TO_GEN => 10000, + AMPLITUDE => 200, + NB_BITS => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + data_ack => data_in_valid, + data => data_in_0_s); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_in_0 <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF data_in_valid = '1' THEN + data_in_0 <= data_in_0_s; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + cic_1: cic + GENERIC MAP ( + D_delay_number => 2, + S_stage_number => 3, + R_downsampling_decimation_factor => 16, + b_data_size => 16, + b_grow => 15) --16 #### log2(RD)*S + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + data_in => data_in_0_s, + data_in_valid => data_in_valid, + data_out => OPEN, + data_out_valid => OPEN); + + --cic_16: cic + -- GENERIC MAP ( + -- D_delay_number => 2, + -- S_stage_number => 3, + -- R_downsampling_decimation_factor => 16, + -- b_data_size => 16, + -- b_grow => 15) --16 #### log2(RD)*S + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + -- data_in => data_in_0_s, + -- data_in_valid => data_in_valid, + -- data_out => OPEN, + -- data_out_valid => OPEN); + + cic_256: cic + GENERIC MAP ( + D_delay_number => 2, + S_stage_number => 3, + R_downsampling_decimation_factor => 256, + b_data_size => 16, + b_grow => 27) --32 #### log2(RD)*S = log2(256*2)*3 + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + data_in => data_in_0_s, + data_in_valid => data_in_valid, + data_out => OPEN, + data_out_valid => OPEN); + + + + + +END; diff --git a/designs/Validation_CIC_LFR/tb_calc.vhd b/designs/Validation_CIC_LFR/tb_calc.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/tb_calc.vhd @@ -0,0 +1,124 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + CONSTANT VECTOR_SIZE : INTEGER := 4*2; + SIGNAL VECTOR_1 : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL VECTOR_MIN : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL VECTOR_MAX : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL all_done : STD_LOGIC; + SIGNAL all_ok : STD_LOGIC; + SIGNAL all_ok_E : STD_LOGIC; + + SIGNAL A : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + SIGNAL B : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL C : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL D_0 : STD_LOGIC_VECTOR(VECTOR_SIZE/2 DOWNTO 0); + SIGNAL D_1 : STD_LOGIC_VECTOR(VECTOR_SIZE/2-1 DOWNTO 0); + SIGNAL D : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + SIGNAL E : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0); + + +BEGIN + VECTOR_1(0) <= '1'; + VECTOR_1(VECTOR_SIZE-1 DOWNTO 1) <= (OTHERS => '0') ; + + VECTOR_MIN(VECTOR_SIZE-1) <= '1'; + VECTOR_MIN(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '0') ; + VECTOR_MAX(VECTOR_SIZE-1) <= '0'; + VECTOR_MAX(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '1') ; + + clk <= NOT clk AFTER 5 ns; + + PROCESSD_0(VECTOR_SIZE/2) + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + + + WAIT FOR 2 ms; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + A <= VECTOR_MIN; + B <= VECTOR_MIN; + all_done <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + all_done <= '0'; + IF A = VECTOR_MAX THEN + A <= VECTOR_MIN; + IF B = VECTOR_MAX THEN + B <= VECTOR_MIN; + all_done <= '1'; + ELSE + B <= STD_LOGIC_VECTOR(signed(B) + signed(VECTOR_1)); + END IF; + ELSE + A <= STD_LOGIC_VECTOR(signed(A) + signed(VECTOR_1)); + END IF; + END IF; + END PROCESS; + + + C <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B)); + + E <= STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B)); + + + + + D_0 <= STD_LOGIC_VECTOR(SIGNED('0'&A(VECTOR_SIZE/2-1 DOWNTO 0)) - SIGNED('0' & B(VECTOR_SIZE/2-1 DOWNTO 0))); + + D_1 <= STD_LOGIC_VECTOR( SIGNED(A(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) + - SIGNED(B(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2)) + - SIGNED(VECTOR_1(VECTOR_SIZE/2-1 DOWNTO 1) & D_0(VECTOR_SIZE/2) )); + + D <= D_1(VECTOR_SIZE/2-1 DOWNTO 0) & D_0(VECTOR_SIZE/2-1 DOWNTO 0); + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + all_ok <= '1'; + all_ok_E <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF D = C THEN + all_ok <= '1'; + ELSE + all_ok <= '0'; + END IF; + + IF E = C THEN + all_ok_E <= '1'; + ELSE + all_ok_E <= '0'; + END IF; + END IF; + END PROCESS; + +END; + diff --git a/designs/Validation_CIC_LFR/tb_cic_lfr_add_sub.vhd b/designs/Validation_CIC_LFR/tb_cic_lfr_add_sub.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/tb_cic_lfr_add_sub.vhd @@ -0,0 +1,173 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; +USE lpp.chirp_pkg.ALL; + +ENTITY testbench IS + +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL clk_24k : STD_LOGIC := '0'; + SIGNAL clk_24k_r : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + SIGNAL run : STD_LOGIC; + SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0); + SIGNAL data_in_valid : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT CARRY : STD_LOGIC := '1'; + CONSTANT CARRY_NO : STD_LOGIC := '0'; + CONSTANT ADD : STD_LOGIC := '0'; + CONSTANT SUB : STD_LOGIC := '1'; + SIGNAL OP : STD_LOGIC; + SIGNAL OP_0 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL OP_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL data_out_verif : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_verif_s : STD_LOGIC_VECTOR(32 DOWNTO 0); + SIGNAL data_in_A_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_B_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_A : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_B : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_diff : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_Carry : STD_LOGIC; + + SIGNAL COUNTER_A : INTEGER; + SIGNAL COUNTER_B : INTEGER; + CONSTANT COUNTER_MIN : INTEGER := INTEGER'LOW; + CONSTANT COUNTER_MAX : INTEGER := INTEGER'HIGH; + CONSTANT COUNTER_STEP : INTEGER := INTEGER'HIGH/100; + + SIGNAL ALL_is_OK : STD_LOGIC; +BEGIN + + clk <= NOT clk AFTER 5 ns; + + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + run <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + OP <= ADD; + WAIT FOR 500 us; + OP <= SUB; + WAIT FOR 500 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + COUNTER_A <= COUNTER_MIN; + COUNTER_B <= COUNTER_MIN; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF COUNTER_A < COUNTER_MAX - COUNTER_STEP THEN + COUNTER_A <= COUNTER_A + COUNTER_STEP; + ELSE + COUNTER_A <= COUNTER_MIN; + IF COUNTER_B < COUNTER_MAX - COUNTER_STEP THEN + COUNTER_B <= COUNTER_B + COUNTER_STEP; + ELSE + COUNTER_B <= COUNTER_MIN; + END IF; + END IF; + END IF; + END PROCESS; + + data_in_A <= STD_LOGIC_VECTOR(to_signed(COUNTER_A,32)); + data_in_B <= STD_LOGIC_VECTOR(to_signed(COUNTER_B,32)); + + ----------------------------------------------------------------------------- + OP_0 <= CARRY_NO & OP; + OP_1 <= CARRY & OP; + cic_lfr_add_sub_1: cic_lfr_add_sub + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + OP => OP_0, + data_in_A => data_in_A(15 DOWNTO 0), + data_in_B => data_in_B(15 DOWNTO 0), + data_in_Carry => '0', + data_out => data_out_s, + data_out_Carry => data_out_Carry); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_in_A_reg <= (OTHERS => '0'); + data_in_B_reg <= (OTHERS => '0'); + data_out(15 DOWNTO 0) <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_in_A_reg <= data_in_A; + data_in_B_reg <= data_in_B; + data_out(15 DOWNTO 0) <= data_out_s; + END IF; + END PROCESS; + + cic_lfr_add_sub_2: cic_lfr_add_sub + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + OP => OP_1, + data_in_A => data_in_A_reg(31 DOWNTO 16), + data_in_B => data_in_B_reg(31 DOWNTO 16), + data_in_Carry => data_out_Carry, + data_out => data_out(31 DOWNTO 16), + data_out_Carry => OPEN); + ----------------------------------------------------------------------------- + data_out_verif_s <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) + to_integer(SIGNED(data_in_B_reg)),33)) WHEN OP = ADD ELSE + STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) - to_integer(SIGNED(data_in_B_reg)),33)); + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_verif <= (OTHERS => '0'); + ALL_is_OK <= '0'; + data_out_pre <= (OTHERS => '0'); + data_out_diff <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_out_verif <= data_out_verif_s(31 DOWNTO 0); + IF data_out_verif = data_out THEN + ALL_is_OK <= '1'; + ELSE + ALL_is_OK <= '0'; + END IF; + ------------------------------------------------------------------------- + data_out_pre <= data_out; + IF OP = ADD THEN + data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); + ELSE + data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32)); + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + + + + + + +END; diff --git a/designs/Validation_CIC_LFR/wave.do b/designs/Validation_CIC_LFR/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/wave.do @@ -0,0 +1,130 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix hexadecimal /testbench/cic_1/data_out_valid +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix decimal /testbench/cic_1/data_out +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix decimal /testbench/cic_1/data_in +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix hexadecimal /testbench/cic_1/data_in_valid +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal /testbench/cic_1/I_valid +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in_valid +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal -childformat {{/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) {-radix decimal}} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out_valid +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-radix hexadecimal} /testbench/cic_1/C_data(2) {-radix hexadecimal} /testbench/cic_1/C_data(1) {-radix hexadecimal} /testbench/cic_1/C_data(0) {-radix hexadecimal}} /testbench/cic_1/C_data +add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal /testbench/cic_1/C_valid +add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) +add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) +add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) +add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) +add wave -noupdate -expand -group C16_REG -group C0 -radix hexadecimal /testbench/cic_1/C_data(0) +add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) +add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) +add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) +add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) +add wave -noupdate -expand -group C16_REG -group C1 -radix hexadecimal /testbench/cic_1/C_data(1) +add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) +add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) +add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) +add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) +add wave -noupdate -expand -group C16_REG -group C2 -radix hexadecimal /testbench/cic_1/C_data(2) +add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix decimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s +add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(31) -radix hexadecimal} {/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_1/C_data(3)(31) {-radix hexadecimal} /testbench/cic_1/C_data(3)(30) {-radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-radix hexadecimal}} /testbench/cic_1/C_data(3) +add wave -noupdate -group Literal -radix hexadecimal /testbench/cic_1/C_data(0) +add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(1) +add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) +add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) +add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) +add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(2) +add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) +add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) +add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) +add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(3) +add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) +add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) +add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) +add wave -noupdate -group OLD -divider DEBUG +add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_channel +add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR +add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/OPERATION +add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd +add wave -noupdate -group OLD -group INPUT -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in +add wave -noupdate -group OLD -group INPUT -radix hexadecimal /testbench/cic_lfr_1/data_in_valid +add wave -noupdate -group OLD -group SEL_INPUT -radix unsigned -childformat {{/testbench/cic_lfr_1/sel_sample(2) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(1) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(0) -radix unsigned}} -expand -subitemconfig {/testbench/cic_lfr_1/sel_sample(2) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(1) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(0) {-height 15 -radix unsigned}} /testbench/cic_lfr_1/sel_sample +add wave -noupdate -group OLD -group SEL_INPUT -radix hexadecimal /testbench/cic_lfr_1/sample +add wave -noupdate -group OLD -group ALU -radix unsigned -radixenum symbolic /testbench/cic_lfr_1/ALU/OP +add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A +add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B +add wave -noupdate -group OLD -group ALU -expand -group INPUT /testbench/cic_lfr_1/ALU/data_in_Carry +add wave -noupdate -group OLD -group ALU -expand -group OUTPUT /testbench/cic_lfr_1/ALU/data_out_Carry +add wave -noupdate -group OLD -group ALU -expand -group OUTPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out +add wave -noupdate -group OLD -group RAM -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray +add wave -noupdate -group OLD -group RAM -expand -group WRITE /testbench/cic_lfr_1/memCEL/RAMblk/WEN +add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD +add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/WADDR +add wave -noupdate -group OLD -group RAM -expand -group READ /testbench/cic_lfr_1/memCEL/RAMblk/REN +add wave -noupdate -group OLD -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD +add wave -noupdate -group OLD -group RAM -expand -group READ -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/RADDR +add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base +add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init +add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1 +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr +add wave -noupdate -group OLD -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16 +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256 +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16_valid +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16 +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256 +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256_valid +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256_s +add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg16_s +add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR +add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_channel +add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd +add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE /testbench/cic_lfr_1/sel_sample +add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE -radix hexadecimal /testbench/cic_lfr_1/sample +add wave -noupdate -expand -group CIC_LFR -group SEL_A /testbench/cic_lfr_1/sel_A +add wave -noupdate -expand -group CIC_LFR -group SEL_A -radix hexadecimal /testbench/cic_lfr_1/data_A +add wave -noupdate -expand -group CIC_LFR -group ALU -radix hexadecimal /testbench/cic_lfr_1/ALU/OP +add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A +add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B +add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry +add wave -noupdate -expand -group CIC_LFR -group ALU /testbench/cic_lfr_1/CARRY_POP +add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out +add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry +add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/CARRY_PUSH +add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/carry_reg +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/REN +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix decimal /testbench/cic_lfr_1/memCEL/RAMblk/RADDR +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WEN +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD +add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WADDR +add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry +add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_PUSH +add wave -noupdate -group CARRY /testbench/cic_lfr_1/carry_reg +add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry +add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_POP +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in_valid +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256 +add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6254226873 ps} 0} {{Cursor 2} {10074245984 ps} 0} {{Cursor 3} {36151600 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 377 +configure wave -valuecolwidth 188 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {15750047250 ps} diff --git a/designs/Validation_CIC_LFR/wave_add_sub.do b/designs/Validation_CIC_LFR/wave_add_sub.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/wave_add_sub.do @@ -0,0 +1,27 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_a +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_b +add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_out +add wave -noupdate /testbench/data_out_carry +add wave -noupdate /testbench/all_is_ok +add wave -noupdate -radix hexadecimal /testbench/data_out +add wave -noupdate -radix hexadecimal /testbench/data_out_pre +add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/data_out_diff(31) {-radix hexadecimal} /testbench/data_out_diff(30) {-radix hexadecimal} /testbench/data_out_diff(29) {-radix hexadecimal} /testbench/data_out_diff(28) {-radix hexadecimal} /testbench/data_out_diff(27) {-radix hexadecimal} /testbench/data_out_diff(26) {-radix hexadecimal} /testbench/data_out_diff(25) {-radix hexadecimal} /testbench/data_out_diff(24) {-radix hexadecimal} /testbench/data_out_diff(23) {-radix hexadecimal} /testbench/data_out_diff(22) {-radix hexadecimal} /testbench/data_out_diff(21) {-radix hexadecimal} /testbench/data_out_diff(20) {-radix hexadecimal} /testbench/data_out_diff(19) {-radix hexadecimal} /testbench/data_out_diff(18) {-radix hexadecimal} /testbench/data_out_diff(17) {-radix hexadecimal} /testbench/data_out_diff(16) {-radix hexadecimal} /testbench/data_out_diff(15) {-radix hexadecimal} /testbench/data_out_diff(14) {-radix hexadecimal} /testbench/data_out_diff(13) {-radix hexadecimal} /testbench/data_out_diff(12) {-radix hexadecimal} /testbench/data_out_diff(11) {-radix hexadecimal} /testbench/data_out_diff(10) {-radix hexadecimal} /testbench/data_out_diff(9) {-radix hexadecimal} /testbench/data_out_diff(8) {-radix hexadecimal} /testbench/data_out_diff(7) {-radix hexadecimal} /testbench/data_out_diff(6) {-radix hexadecimal} /testbench/data_out_diff(5) {-radix hexadecimal} /testbench/data_out_diff(4) {-radix hexadecimal} /testbench/data_out_diff(3) {-radix hexadecimal} /testbench/data_out_diff(2) {-radix hexadecimal} /testbench/data_out_diff(1) {-radix hexadecimal} /testbench/data_out_diff(0) {-radix hexadecimal}} /testbench/data_out_diff +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {55000 ps} 0} +configure wave -namecolwidth 182 +configure wave -valuecolwidth 97 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {424577 ps} diff --git a/designs/Validation_CIC_LFR/wave_calc.do b/designs/Validation_CIC_LFR/wave_calc.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/wave_calc.do @@ -0,0 +1,23 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/a +add wave -noupdate /testbench/b +add wave -noupdate /testbench/c +add wave -noupdate /testbench/all_done +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {631245000 ps} 1} {{Cursor 2} {590125000 ps} 0} +configure wave -namecolwidth 424 +configure wave -valuecolwidth 119 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {2100026250 ps} diff --git a/designs/Validation_CIC_LFR/wave_inout.do b/designs/Validation_CIC_LFR/wave_inout.do new file mode 100644 --- /dev/null +++ b/designs/Validation_CIC_LFR/wave_inout.do @@ -0,0 +1,50 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data +add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid +add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data +add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid +add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16 +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256 +add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid +add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0) +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s +add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s +add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0) +add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} 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{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {21545643925 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {8443215000 ps} 0} +quietly wave cursor active 3 +configure wave -namecolwidth 299 +configure wave -valuecolwidth 188 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {300136435256 ps} diff --git a/lib/lpp/dsp/cic/cic_lfr.vhd b/lib/lpp/dsp/cic/cic_lfr.vhd --- a/lib/lpp/dsp/cic/cic_lfr.vhd +++ b/lib/lpp/dsp/cic/cic_lfr.vhd @@ -227,7 +227,8 @@ BEGIN STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE - STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)); + STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE + STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,8)); PROCESS (clk, rstn) BEGIN -- PROCESS @@ -375,8 +376,8 @@ BEGIN all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE all_bits: FOR J IN 15 DOWNTO 0 GENERATE - data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-1); - data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -1); + data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27); + data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15); END GENERATE all_bits; END GENERATE all_channel_out_v; diff --git a/lib/lpp/dsp/cic/cic_lfr_control.vhd b/lib/lpp/dsp/cic/cic_lfr_control.vhd --- a/lib/lpp/dsp/cic/cic_lfr_control.vhd +++ b/lib/lpp/dsp/cic/cic_lfr_control.vhd @@ -90,17 +90,17 @@ ARCHITECTURE beh OF cic_lfr_control IS "1010" & "10010" & "11101", --16 --PROG_C256 "1001" & "00100" & "10010", --17 - "1001" & "10010" & "10101", --18 - "1001" & "10010" & "10101", --19 - "1010" & "10010" & "10101", --20 + "1001" & "10110" & "10101", --18 + "1001" & "10110" & "10101", --19 + "1010" & "10110" & "10101", --20 "1001" & "01000" & "10010", --21 - "1001" & "10010" & "11101", --22 - "1001" & "10010" & "11101", --23 - "1010" & "10010" & "11101", --24 + "1001" & "10110" & "11101", --22 + "1001" & "10110" & "11101", --23 + "1010" & "10110" & "11101", --24 "1001" & "01100" & "10010", --25 - "1001" & "10010" & "11101", --26 - "1001" & "10010" & "11101", --27 - "1010" & "10010" & "11101" --28 + "1001" & "10110" & "11101", --26 + "1001" & "10110" & "11101", --27 + "1010" & "10110" & "11101" --28 ); @@ -119,9 +119,16 @@ BEGIN OPERATION(7) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4); --CARRY_PUSH OPERATION(8) <= PROG(current_cmd)(5); --@_init OPERATION(9) <= PROG(current_cmd)(6); --@_add_1 - OPERATION(11 DOWNTO 10) <= PROG(current_cmd)(8 DOWNTO 7); --@_sel(1..0) - OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE - PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; --@_sel(2) + + OPERATION(10) <= PROG(current_cmd)(7) AND PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE + PROG(current_cmd)(7); --@_sel(1..0) + OPERATION(11) <= PROG(current_cmd)(8); + OPERATION(12) <= PROG(current_cmd)(9) AND sample_16_odd WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE + --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE + PROG(current_cmd)(9) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE + '0'; --@_sel(2) + + OPERATION(13) <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10); --WE OPERATION(14) <= PROG(current_cmd)(12); -- SEL_DATA_A = data_b_reg OPERATION(15) <= PROG(current_cmd)(13); -- WRITE_ADDR_sel diff --git a/lib/lpp/lpp_ad_Conv/lpp_lfr_hk.vhd b/lib/lpp/lpp_ad_Conv/lpp_lfr_hk.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_ad_Conv/lpp_lfr_hk.vhd @@ -0,0 +1,140 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY lpp; +USE lpp.apb_devices_list.ALL; + +ENTITY lpp_lfr_hk IS + + GENERIC ( + pindex : INTEGER := 0; + paddr : INTEGER := 0; + pmask : INTEGER := 16#fff#); --! MASK field of the APB BAR); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + + sample_val : IN STD_LOGIC; + sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); + +END lpp_lfr_hk; + + +ARCHITECTURE Behavioral OF lpp_lfr_hk IS + + ----------------------------------------------------------------------------- + -- APB REG + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_HK_DEVICE, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask) + ); + + TYPE lpp_lfr_HK_reg IS RECORD + temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + END RECORD; + + SIGNAL reg_hk : lpp_lfr_HK_reg; + + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL HK_SEL_s :STD_LOGIC_VECTOR(1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- APB REG + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + Rdata <= (OTHERS => '0'); + + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + --APB READ OP + IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => Rdata(15 DOWNTO 0) <= reg_hk.temp_0; + WHEN "000001" => Rdata(15 DOWNTO 0) <= reg_hk.temp_1; + WHEN "000010" => Rdata(15 DOWNTO 0) <= reg_hk.temp_2; + WHEN OTHERS => Rdata(31 DOWNTO 0) <= (others => '0'); + END CASE; + END IF; + + END IF; + END PROCESS; + + apbo.pirq <= (OTHERS => '0'); + apbo.prdata <= Rdata; + apbo.pconfig <= pconfig; + apbo.pindex <= pindex; + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + reg_hk.temp_0 <= (OTHERS => '0'); + reg_hk.temp_1 <= (OTHERS => '0'); + reg_hk.temp_2 <= (OTHERS => '0'); + + HK_SEL_s <= "00"; + + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + + IF sample_val = '1' THEN + CASE HK_SEL_s IS + WHEN "00" => reg_hk.temp_0 <= sample; HK_SEL_s <= "01"; + WHEN "01" => reg_hk.temp_1 <= sample; HK_SEL_s <= "10"; + WHEN "10" => reg_hk.temp_2 <= sample; HK_SEL_s <= "00"; + WHEN OTHERS => NULL; + END CASE; + + END IF; + + END IF; + END PROCESS; + + HK_SEL <= HK_SEL_s; + +END Behavioral; + + +