# HG changeset patch # User pellion # Date 2013-04-09 12:54:52 # Node ID 4b259071bd4181134c5b8b04babf4e7fb0d7c750 # Parent 7dce9fffce58475a29509b10a9aabd49eac879ed # Parent f1bafb11f790d59b35955585d3a10551ae7d4789 FUSION AVEC MARTIN diff --git a/LPP_drivers/exemples/BenchFFT+Matrix/Makefile b/LPP_drivers/exemples/BenchFFT+Matrix/Makefile --- a/LPP_drivers/exemples/BenchFFT+Matrix/Makefile +++ b/LPP_drivers/exemples/BenchFFT+Matrix/Makefile @@ -21,7 +21,7 @@ include ../../rules.mk LIBDIR = ../../lib INCPATH = ../../includes SCRIPTDIR=../../scripts/ -LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_delay_Driver -lapb_fifo_Driver -lapb_uart_Driver -lapb_gpio_Driver +LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions INPUTFILE=main.c EXEC=BenchFFT+Matrix.bin OUTBINDIR=bin/ diff --git a/LPP_drivers/exemples/BenchFFT+Matrix/main.c b/LPP_drivers/exemples/BenchFFT+Matrix/main.c --- a/LPP_drivers/exemples/BenchFFT+Matrix/main.c +++ b/LPP_drivers/exemples/BenchFFT+Matrix/main.c @@ -2,79 +2,72 @@ #include "lpp_apb_functions.h" #include "apb_fifo_Driver.h" #include "apb_uart_Driver.h" -#include "apb_delay_Driver.h" -#include "apb_fft_Driver.h" - int main() { - int i; - int data1,data2; + int i=0; + int data; char temp[256]; - int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; - int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; - int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ; -/* int TblSin5K[256] = {0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872}; - int TblSin8K[256] = {0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA}; - int TblSin11K[256] = {0x0000,0x11A3,0x22F0,0x3392,0x4339,0x5197,0x5E67,0x696A,0x7269,0x793B,0x7DBC,0x7FD7,0x7F81,0x7CBD,0x7798,0x702B,0x669A,0x5B14,0x4DD1,0x3F12,0x2F1F,0x1E46,0x0CD9,0xFB2D,0xE999,0xD872,0xC80D,0xB8B8,0xAAC0,0x9E68,0x93ED,0x8B82,0x854F,0x8174,0x8003,0x8102,0x846E,0x8A36,0x923D,0x9C5B,0xA861,0xB612,0xC52C,0xD566,0xE670,0xF7F6,0x09A4,0x1B23,0x2C1D,0x3C40,0x4B3D,0x58CA,0x64A5,0x6E95,0x7669,0x7BFB,0x7F2F,0x7FF6,0x7E4C,0x7A39,0x73D1,0x6B34,0x608B,0x540B,0x45F0,0x3680,0x2605,0x14D1,0x0337,0xF18E,0xE02B,0xCF63,0xBF89,0xB0EA,0xA3CD,0x9872,0x8F11,0x87D8,0x82E9,0x805D,0x8041,0x8294,0x874C,0x8E52,0x9782,0xA2B1,0xAFA8,0xBE27,0xCDE7,0xDE9D,0xEFF5,0x019C,0x133B,0x247C,0x350A,0x4496,0x52D3,0x5F7B,0x6A51,0x7320,0x79BC,0x7E06,0x7FE9,0x7F5B,0x7C5E,0x7703,0x6F62,0x65A1,0x59F0,0x4C88,0x3DAA,0x2D9F,0x1CB5,0x0B3F,0xF992,0xE804,0xD6EB,0xC69B,0xB764,0xA98F,0x9D60,0x9313,0x8AD9,0x84DC,0x8139,0x8000,0x8139,0x84DC,0x8AD9,0x9313,0x9D60,0xA98F,0xB764,0xC69B,0xD6EB,0xE804,0xF992,0x0B3F,0x1CB5,0x2D9F,0x3DAA,0x4C88,0x59F0,0x65A1,0x6F62,0x7703,0x7C5E,0x7F5B,0x7FE9,0x7E06,0x79BC,0x7320,0x6A51,0x5F7B,0x52D3,0x4496,0x350A,0x247C,0x133B,0x019C,0xEFF5,0xDE9D,0xCDE7,0xBE27,0xAFA8,0xA2B1,0x9782,0x8E52,0x874C,0x8294,0x8041,0x805D,0x82E9,0x87D8,0x8F11,0x9872,0xA3CD,0xB0EA,0xBF89,0xCF63,0xE02B,0xF18E,0x0337,0x14D1,0x2605,0x3680,0x45F0,0x540B,0x608B,0x6B34,0x73D1,0x7A39,0x7E4C,0x7FF6,0x7F2F,0x7BFB,0x7669,0x6E95,0x64A5,0x58CA,0x4B3D,0x3C40,0x2C1D,0x1B23,0x09A4,0xF7F6,0xE670,0xD566,0xC52C,0xB612,0xA861,0x9C5B,0x923D,0x8A36,0x846E,0x8102,0x8003,0x8174,0x854F,0x8B82,0x93ED,0x9E68,0xAAC0,0xB8B8,0xC80D,0xD872,0xE999,0xFB2D,0x0CD9,0x1E46,0x2F1F,0x3F12,0x4DD1,0x5B14,0x669A,0x702B,0x7798,0x7CBD,0x7F81,0x7FD7,0x7DBC,0x793B,0x7269,0x696A,0x5E67,0x5197,0x4339,0x3392,0x22F0,0x11A3,0x0000,0xEE5D,0xDD10,0xCC6E,0xBCC7,0xAE69}; -*/ int TblSin15K[256] = {0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872}; - int TblSin19K[256] = {0x0000,0x1E46,0x3AD4,0x540B,0x687E,0x7703,0x7EC7,0x7F5B,0x78B4,0x6B34,0x579F,0x3F12,0x22F0,0x04D3,0xE670,0xC980,0xAFA8,0x9A5F,0x8AD9,0x81FA,0x8041,0x85C7,0x923D,0xA4EC,0xBCC7,0xD872,0xF65C,0x14D1,0x3219,0x4C88,0x62A0,0x7320,0x7D17,0x7FF6,0x7B92,0x702B,0x5E67,0x4748,0x2C1D,0x0E72,0xEFF5,0xD261,0xB764,0xA085,0x8F11,0x8405,0x8003,0x8343,0x8D97,0x9E68,0xB4C3,0xCF63,0xECC5,0x0B3F,0x2915,0x4496,0x5C33,0x6E95,0x7AB1,0x7FD7,0x7DBC,0x747E,0x64A5,0x4F16,0x350A,0x17FC,0xF992,0xDB84,0xBF89,0xA736,0x93ED,0x86C5,0x807F,0x8174,0x8997,0x9872,0xAD2D,0xC69B,0xE34B,0x019C,0x1FD5,0x3C40,0x5540,0x696A,0x7798,0x7EFE,0x7F2F,0x7828,0x6A51,0x5671,0x3DAA,0x2163,0x0337,0xE4DD,0xC80D,0xAE69,0x9966,0x8A36,0x81B4,0x805D,0x8644,0x9313,0xA610,0xBE27,0xD9FB,0xF7F6,0x1667,0x3392,0x4DD1,0x63A5,0x73D1,0x7D6C,0x7FE9,0x7B24,0x6F62,0x5D4F,0x45F0,0x2A9A,0x0CD9,0xEE5D,0xD0E1,0xB612,0x9F75,0x8E52,0x83A2,0x8000,0x83A2,0x8E52,0x9F75,0xB612,0xD0E1,0xEE5D,0x0CD9,0x2A9A,0x45F0,0x5D4F,0x6F62,0x7B24,0x7FE9,0x7D6C,0x73D1,0x63A5,0x4DD1,0x3392,0x1667,0xF7F6,0xD9FB,0xBE27,0xA610,0x9313,0x8644,0x805D,0x81B4,0x8A36,0x9966,0xAE69,0xC80D,0xE4DD,0x0337,0x2163,0x3DAA,0x5671,0x6A51,0x7828,0x7F2F,0x7EFE,0x7798,0x696A,0x5540,0x3C40,0x1FD5,0x019C,0xE34B,0xC69B,0xAD2D,0x9872,0x8997,0x8174,0x807F,0x86C5,0x93ED,0xA736,0xBF89,0xDB84,0xF992,0x17FC,0x350A,0x4F16,0x64A5,0x747E,0x7DBC,0x7FD7,0x7AB1,0x6E95,0x5C33,0x4496,0x2915,0x0B3F,0xECC5,0xCF63,0xB4C3,0x9E68,0x8D97,0x8343,0x8003,0x8405,0x8F11,0xA085,0xB764,0xD261,0xEFF5,0x0E72,0x2C1D,0x4748,0x5E67,0x702B,0x7B92,0x7FF6,0x7D17,0x7320,0x62A0,0x4C88,0x3219,0x14D1,0xF65C,0xD872,0xBCC7,0xA4EC,0x923D,0x85C7,0x8041,0x81FA,0x8AD9,0x9A5F,0xAFA8,0xC980,0xE670,0x04D3,0x22F0,0x3F12,0x579F,0x6B34,0x78B4,0x7F5B,0x7EC7,0x7703,0x687E,0x540B,0x3AD4,0x1E46,0x0000,0xE1BA,0xC52C,0xABF5,0x9782,0x88FD}; - int Table[256]; + int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; + int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; + int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; + int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; + int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; - FFT_Device* fft0 = openFFT(0); - DELAY_Device* delay = openDELAY(0); - UART_Device* uart0 = openUART(0); - FIFO_Device* fifoIn = openFIFO(0); - FIFO_Device* fifoOut = openFIFO(1); + UART_Device* uart0 = openUART(0); + FIFO_Device* fifotry = openFIFO(0); + FIFO_Device* fifoIn = openFIFO(1); + FIFO_Device* fifoOut = openFIFO(2); printf("\nDebut Main\n\n"); - Setup(delay,30000000); - - FftInput(TblSinA,fft0,delay); - FftOutput(Table,fft0); - /*for (i = 0 ; i < 256 ; i=i+2) - { - sprintf(temp,"%x\t%x\n\r",Table[i],Table[i+1]); - uartputs(uart0,temp); - }*/ - FillFifo(fifoIn,0,Table); + FillFifo(fifoIn,0,TblSinA,256); fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); - FftInput(TblSinAB,fft0,delay); - FftOutput(Table,fft0); - FillFifo(fifoIn,1,Table); + FillFifo(fifoIn,1,TblSinAB,256); fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); - FftInput(TblSinB,fft0,delay); - FftOutput(Table,fft0); - FillFifo(fifoIn,2,Table); + FillFifo(fifoIn,2,TblSinB,256); fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); - FftInput(TblSin15K,fft0,delay); - FftOutput(Table,fft0); - FillFifo(fifoIn,3,Table); + FillFifo(fifoIn,3,TblSinBC,256); fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); - FftInput(TblSin19K,fft0,delay); - FftOutput(Table,fft0); - FillFifo(fifoIn,4,Table); + FillFifo(fifoIn,4,TblSinC,256); fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); -printf("ok"); -while(1){ + + + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN + printf("\nFull 1\n"); + while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN + printf("\nFull 2\n"); + + while(1){ + + sprintf(temp,"PONG A\n\r"); + uartputs(uart0,temp); - while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN + while(i<257){ + data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); + i++; + sprintf(temp,"%d\n\r",data); + uartputs(uart0,temp); + } - data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; - data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; + i=0; + sprintf(temp,"PONG B\n\r"); + uartputs(uart0,temp); - sprintf(temp,"%d\t%d\n\r",data1,data2); + while(i<257){ + data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); + i++; + sprintf(temp,"%d\n\r",data); uartputs(uart0,temp); + } + + i=0; } printf("\nFin Main\n\n"); return 0; } - - - diff --git a/LPP_drivers/exemples/BenchFFT/Makefile b/LPP_drivers/exemples/BenchFFT/Makefile --- a/LPP_drivers/exemples/BenchFFT/Makefile +++ b/LPP_drivers/exemples/BenchFFT/Makefile @@ -21,7 +21,7 @@ include ../../rules.mk LIBDIR = ../../lib INCPATH = ../../includes SCRIPTDIR=../../scripts/ -LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_uart_Driver -lapb_delay_Driver +LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions INPUTFILE=main.c EXEC=BenchFFT.bin OUTBINDIR=bin/ diff --git a/LPP_drivers/exemples/BenchFFT/main.c b/LPP_drivers/exemples/BenchFFT/main.c --- a/LPP_drivers/exemples/BenchFFT/main.c +++ b/LPP_drivers/exemples/BenchFFT/main.c @@ -1,45 +1,51 @@ #include #include "lpp_apb_functions.h" +#include "apb_fifo_Driver.h" #include "apb_uart_Driver.h" -#include "apb_fft_Driver.h" -#include "apb_delay_Driver.h" +//#include "TableTest.h" int main() { + int i=0,j=0; + int data1,data2; char temp[256]; - int i; - int Table[256]; -//Somme de 2 sinus// - //int Tablo[256] = {0x00000000,0x0DA20000,0x1B080000,0x27F70000,0x34380000,0x3F960000,0x49E10000,0x52F10000,0x5AA10000,0x60D60000,0x657D0000,0x688C0000,0x69FE0000,0x69DB0000,0x68310000,0x65170000,0x60A90000,0x5B0D0000,0x546D0000,0x4CF90000,0x44E30000,0x3C610000,0x33AA0000,0x2AF40000,0x22750000,0x1A610000,0x12E70000,0x0C310000,0x06660000,0x01A30000,0xFE010000,0xFB8E0000,0xFA520000,0xFA4D0000,0xFB770000,0xFDBE0000,0x010A0000,0x053E0000,0x0A330000,0x0FBF0000,0x15B30000,0x1BDE0000,0x220C0000,0x28080000,0x2D9D0000,0x329B0000,0x36D20000,0x3A170000,0x3C440000,0x3D390000,0x3CDE0000,0x3B210000,0x37F90000,0x33650000,0x2D6D0000,0x26210000,0x1D990000,0x13F30000,0x09570000,0xFDF10000,0xF1F20000,0xE58F0000,0xD9030000,0xCC870000,0xC0560000,0xB4AA0000,0xA9BC0000,0x9FBF0000,0x96E40000,0x8F570000,0x893A0000,0x84AB0000,0x81BF0000,0x80830000,0x80FB0000,0x83220000,0x86EC0000,0x8C430000,0x93090000,0x9B1B0000,0xA44D0000,0xAE700000,0xB9500000,0xC4B40000,0xD0630000,0xDC240000,0xE7BD0000,0xF2F60000,0xFD9A0000,0x077A0000,0x106B0000,0x18480000,0x1EF30000,0x24570000,0x28650000,0x2B160000,0x2C6F0000,0x2C790000,0x2B470000,0x28F30000,0x259E0000,0x216E0000,0x1C8F0000,0x17310000,0x11860000,0x0BC10000,0x06170000,0x00BA0000,0xFBDD0000,0xF7AC0000,0xF44F0000,0xF1EA0000,0xF09C0000,0xF0790000,0xF1900000,0xF3E80000,0xF77E0000,0xFC4A0000,0x02370000,0x092E0000,0x110E0000,0x19AF0000,0x22E40000,0x2C7C0000,0x36420000,0x3FFF0000,0x497C0000,0x52810000,0x5AD70000,0x624B0000,0x68AD0000,0x6DD40000,0x71990000,0x73E10000,0x74950000,0x73A60000,0x71100000,0x6CD60000,0x67040000,0x5FAD0000,0x56EE0000,0x4CEA0000,0x41CD0000,0x35C50000,0x29070000,0x1BCC0000,0x0E4E0000,0x00CA0000,0xF37C0000,0xE69C0000,0xDA620000,0xCF040000,0xC4AE0000,0xBB8B0000,0xB3BC0000,0xAD5C0000,0xA87D0000,0xA5290000,0xA3630000,0xA3220000,0xA4590000,0xA6EF0000,0xAAC80000,0xAFBD0000,0xB5A40000,0xBC4F0000,0xC38B0000,0xCB220000,0xD2E00000,0xDA8E0000,0xE1F70000,0xE8EC0000,0xEF3C0000,0xF4C10000,0xF9560000,0xFCDF0000,0xFF470000,0x007F0000,0x00850000,0xFF5C0000,0xFD0B0000,0xF9A80000,0xF54B0000,0xF0170000,0xEA320000,0xE3C90000,0xDD0B0000,0xD62B0000,0xCF5F0000,0xC8DA0000,0xC2D30000,0xBD7A0000,0xB8FF0000,0xB58D0000,0xB3490000,0xB2510000,0xB2BE0000,0xB49F0000,0xB7FC0000,0xBCD60000,0xC3220000,0xCAD10000,0xD3C70000,0xDDE50000,0xE9030000,0xF4F20000,0x01800000,0x0E770000,0x1B9D0000,0x28B70000,0x35880000,0x41D70000,0x4D6C0000,0x58100000,0x61950000,0x69D00000,0x709C0000,0x75DE0000,0x79800000,0x7B750000,0x7BBB0000,0x7A570000,0x77550000,0x72CB0000,0x6CD70000,0x659E0000,0x5D490000,0x54090000,0x4A110000,0x3F980000,0x34D80000,0x2A090000,0x1F630000,0x151D0000,0x0B690000,0x02760000,0xFA6F0000,0xF3730000,0xEDA10000,0xE90B0000,0xE5BF0000,0xE3C00000,0xE30A0000,0xE38F0000,0xE53D0000,0xE7F80000,0xEB9D0000,0xF0050000,0xF5030000,0xFA680000,0x00000000,0x05980000,0x0AFD0000,0x0FFB0000,0x14630000,0x18080000}; -//1 Sinus// - int Tablo[256] = {0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000}; - printf("Debut Main\n\n"); - UART_Device* uart0 = openUART(0); - FFT_Device* fft0 = openFFT(0); - DELAY_Device* delay = openDELAY(0); + + int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE}; + int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD}; + int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF}; + int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C}; + int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E}; + + UART_Device* uart0 = openUART(0); + FIFO_Device* fifotry = openFIFO(0); + FIFO_Device* fifoIn = openFIFO(1); + FIFO_Device* fifoOut = openFIFO(2); + + printf("\nDebut Main\n\n"); - printf("addr_fft: %x\n",(unsigned int)fft0); - printf("addr_uart: %x\n\n",(unsigned int)uart0); - printf("cfg_fft: %x\n",fft0->ConfigReg); - printf("cfg_uart: %x\n\n",uart0->ConfigReg); + FillFifo(fifoIn,0,TblSinA,256); + FillFifo(fifoIn,1,TblSinAB,256); + FillFifo(fifoIn,2,TblSinB,256); + FillFifo(fifoIn,3,TblSinBC,256); + FillFifo(fifoIn,4,TblSinC,256); + + while(j<5){ + while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN - while(1) - { - FftInput(Tablo,fft0,delay); - /* for (i = 0 ; i < 256 ; i++) - { - sprintf(temp,"%x/in",Tablo[i]); - uartputs(uart0,temp); - }*/ - - FftOutput(Table,fft0); - for (i = 0 ; i < 128 ; i++) - { - sprintf(temp,"%x/out",Table[i]); + sprintf(temp,"FIFO %d\n\r",j); + uartputs(uart0,temp); + //while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS + while(i < 128){ + data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; + data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex; + i++; + sprintf(temp,"%d\t%d\n\r",data1,data2); uartputs(uart0,temp); } + i=0; + j++; } + printf("\nFin Main\n\n"); return 0; } - diff --git a/LPP_drivers/exemples/BenchMatrix/main.c b/LPP_drivers/exemples/BenchMatrix/main.c --- a/LPP_drivers/exemples/BenchMatrix/main.c +++ b/LPP_drivers/exemples/BenchMatrix/main.c @@ -32,8 +32,8 @@ int main() /////////////////////////////////////////////////////////////////////////// mspec->Statu = 2; - FillFifo(fifoIn,0,TblB1); - FillFifo(fifoIn,1,TblB2); + FillFifo(fifoIn,0,TblB1,256); + FillFifo(fifoIn,1,TblB2,256); gpio0->Dout = 0x1; while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS @@ -56,7 +56,7 @@ int main() /////////////////////////////////////////////////////////////////////////// mspec->Statu = 1; - FillFifo(fifoIn,0,TblB1); + FillFifo(fifoIn,0,TblB1,256); gpio0->Dout = 0x1; while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS { @@ -78,8 +78,8 @@ int main() /////////////////////////////////////////////////////////////////////////// mspec->Statu = 4; - FillFifo(fifoIn,0,TblB1); - FillFifo(fifoIn,1,TblB3); + FillFifo(fifoIn,0,TblB1,256); + FillFifo(fifoIn,1,TblB3,256); gpio0->Dout = 0x1; while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS @@ -123,19 +123,19 @@ int main2() printf("\nDebut Main\n\n"); - FillFifo(fifoIn,0,TblB1); + FillFifo(fifoIn,0,TblB1,256); fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); - FillFifo(fifoIn,1,TblB2); + FillFifo(fifoIn,1,TblB2,256); fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); - FillFifo(fifoIn,2,TblB3); + FillFifo(fifoIn,2,TblB3,256); fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); - FillFifo(fifoIn,3,TblE1); + FillFifo(fifoIn,3,TblE1,256); fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); - FillFifo(fifoIn,4,TblE2); + FillFifo(fifoIn,4,TblE2,256); fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); diff --git a/LPP_drivers/exemples/BenchMatrix/main2.c b/LPP_drivers/exemples/BenchMatrix/main2.c new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/BenchMatrix/main2.c @@ -0,0 +1,74 @@ +#include +#include "lpp_apb_functions.h" +#include "apb_fifo_Driver.h" +#include "apb_uart_Driver.h" + + +int main() +{ + int i=0; + int data; + char temp[256]; + + int TblSinA[256] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255} ; + int TblSinAB[256] = {255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129,128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} ; + int TblSinB[256] = {100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100} ; + int TblSinBC[256] = {128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129} ; + int TblSinC[256] = {128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127} ; + + UART_Device* uart0 = openUART(0); + FIFO_Device* fifotry = openFIFO(0); + FIFO_Device* fifoIn = openFIFO(1); + FIFO_Device* fifoOut = openFIFO(2); + + printf("\nDebut Main\n\n"); + + FillFifo(fifoIn,0,TblSinA,256); + fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,1,TblSinAB,256); + fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,2,TblSinB,256); + fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,3,TblSinBC,256); + fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse); + + FillFifo(fifoIn,4,TblSinC,256); + fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse); + + + while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN + printf("\nFull 1\n"); + while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN + printf("\nFull 2\n"); + + while(1){ + + sprintf(temp,"PONG A\n\r"); + uartputs(uart0,temp); + + while(i<257){ + data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]); + i++; + sprintf(temp,"%d\n\r",data); + uartputs(uart0,temp); + } + + i=0; + sprintf(temp,"PONG B\n\r"); + uartputs(uart0,temp); + + while(i<257){ + data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]); + i++; + sprintf(temp,"%d\n\r",data); + uartputs(uart0,temp); + } + + i=0; + } + printf("\nFin Main\n\n"); + return 0; +} diff --git a/LPP_drivers/includes/apb_fifo_Driver.h b/LPP_drivers/includes/apb_fifo_Driver.h --- a/LPP_drivers/includes/apb_fifo_Driver.h +++ b/LPP_drivers/includes/apb_fifo_Driver.h @@ -51,8 +51,8 @@ */ struct APB_FIFO_REG { - int IDreg; - int FIFOreg[2*8]; + volatile int IDreg; + volatile int FIFOreg[2*8]; }; typedef volatile struct APB_FIFO_REG FIFO_Device; @@ -71,6 +71,6 @@ typedef volatile struct APB_FIFO_REG FIF \return The pointer to the device. */ FIFO_Device* openFIFO(int count); -int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); +int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); #endif diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c @@ -32,13 +32,22 @@ FIFO_Device* openFIFO(int count) } -int FillFifo(FIFO_Device* dev,int ID,int Tbl[]) +int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count) { int i=0; - while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS + //int poub; + //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]); + while(iFIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS { + //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); + //printf("%d\n",i); dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i]; i++; } + //poub = dev->FIFOreg[(2*ID)+FIFO_RWdata]; + //dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[0]; + //printf("END:%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); + //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN return 0; } diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.h @@ -51,8 +51,8 @@ */ struct APB_FIFO_REG { - int IDreg; - int FIFOreg[2*8]; + volatile int IDreg; + volatile int FIFOreg[2*8]; }; typedef volatile struct APB_FIFO_REG FIFO_Device; @@ -71,6 +71,6 @@ typedef volatile struct APB_FIFO_REG FIF \return The pointer to the device. */ FIFO_Device* openFIFO(int count); -int FillFifo(FIFO_Device* dev,int ID,int Tbl[]); +int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count); #endif diff --git a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/Driver_FFT.vhd @@ -25,14 +25,14 @@ use IEEE.numeric_std.all; entity Driver_FFT is generic( - Data_sz : integer range 1 to 32 := 16 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; rstn : in std_logic; Load : in std_logic; Empty : in std_logic_vector(4 downto 0); - Full : in std_logic_vector(4 downto 0); DATA : in std_logic_vector((5*Data_sz)-1 downto 0); Valid : out std_logic; Read : out std_logic_vector(4 downto 0); @@ -47,111 +47,75 @@ architecture ar_Driver of Driver_FFT is type etat is (eX,e0,e1,e2); signal ect : etat; -signal FifoCpt : integer; ---signal DataTmp : std_logic_vector(Data_sz-1 downto 0); +signal DataCount : integer range 0 to 255 := 0; +signal FifoCpt : integer range 0 to 4 := 0; -signal sEmpty : std_logic; -signal sFull : std_logic; -signal sData : std_logic_vector(Data_sz-1 downto 0); +signal sLoad : std_logic; begin process(clk,rstn) begin if(rstn='0')then - ect <= eX; + ect <= e0; Read <= (others => '1'); Valid <= '0'; - FifoCpt <= 1; Data_re <= (others => '0'); Data_im <= (others => '0'); + DataCount <= 0; + FifoCpt <= 0; + sLoad <= '0'; elsif(clk'event and clk='1')then + sLoad <= Load; + if(sLoad='1' and Load='0')then + if(FifoCpt=4)then + FifoCpt <= 0; + else + FifoCpt <= FifoCpt + 1; + end if; + end if; + case ect is - when eX => - if(sFull='1')then - ect <= e0; - end if; - when e0 => - Valid <= '0'; - if(Load='1' and sEmpty='0')then - Read(FifoCpt-1) <= '0'; - ect <= e2; --- ect <= e1; - elsif(sEmpty='1')then - if(FifoCpt=6)then - FifoCpt <= 1; - else - FifoCpt <= FifoCpt+1; - end if; - ect <= eX; + if(Load='1' and Empty(FifoCpt)='0')then + Read(FifoCpt) <= '0'; + ect <= e1; end if; when e1 => - null; --- DataTmp <= sData; --- ect <= e2; - + Valid <= '0'; + Read(FifoCpt) <= '1'; + ect <= e2; + when e2 => - Read(FifoCpt-1) <= '1'; - Data_re <= sData; + Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)); Data_im <= (others => '0'); --- Data_re <= DataTmp; --- Data_im <= sData; Valid <= '1'; + if(DataCount=NbData-1)then + DataCount <= 0; + ect <= eX; + else + DataCount <= DataCount + 1; + if(Load='1' and Empty(FifoCpt)='0')then + Read(FifoCpt) <= '0'; + ect <= e1; + else + ect <= eX; + end if; + end if; + + when eX => + Valid <= '0'; ect <= e0; - + + when others => + null; end case; end if; end process; -with FifoCpt select - sFull <= Full(0) when 1, - Full(1) when 2, - Full(2) when 3, - Full(3) when 4, - Full(4) when 5, - '1' when others; - -with FifoCpt select - sEmpty <= Empty(0) when 1, - Empty(1) when 2, - Empty(2) when 3, - Empty(3) when 4, - Empty(4) when 5, - '1' when others; - -with FifoCpt select - sData <= DATA(Data_sz-1 downto 0) when 1, - DATA((2*Data_sz)-1 downto Data_sz) when 2, - DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3, - DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4, - DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5, - (others => '0') when others; - -end architecture; - - - - - - - - - - - - - - - - - - - - - +end architecture; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/FFTamont.vhd b/lib/lpp/dsp/lpp_fft/FFTamont.vhd --- a/lib/lpp/dsp/lpp_fft/FFTamont.vhd +++ b/lib/lpp/dsp/lpp_fft/FFTamont.vhd @@ -5,14 +5,14 @@ use IEEE.numeric_std.all; entity FFTamont is generic( - Data_sz : integer range 1 to 32 := 16 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; rstn : in std_logic; Load : in std_logic; Empty : in std_logic; - Full : in std_logic; DATA : in std_logic_vector(Data_sz-1 downto 0); Valid : out std_logic; Read : out std_logic; @@ -27,69 +27,95 @@ architecture ar_FFTamont of FFTamont is type etat is (eX,e0,e1,e2); signal ect : etat; +signal DataCount : integer; begin process(clk,rstn) begin if(rstn='0')then - ect <= eX; + ect <= e0; Read <= '1'; Valid <= '0'; Data_re <= (others => '0'); Data_im <= (others => '0'); + DataCount <= 0; elsif(clk'event and clk='1')then - case ect is - when eX => - if(Full='1')then - ect <= e0; - end if; - when e0 => - Valid <= '0'; if(Load='1' and Empty='0')then Read <= '0'; - ect <= e1; - elsif(Empty='1')then - ect <= eX; + ect <= e1; end if; when e1 => + Valid <= '0'; Read <= '1'; + ect <= e2; + + when e2 => Data_re <= DATA; Data_im <= (others => '0'); Valid <= '1'; - ect <= e0; - - when e2 => - null; + if(DataCount=NbData-1)then + DataCount <= 0; + ect <= eX; + else + DataCount <= DataCount + 1; + if(Load='1' and Empty='0')then + Read <= '0'; + ect <= e1; + else + ect <= eX; + end if; + end if; + + when eX => + Valid <= '0'; + ect <= e0; + + when others => + null; end case; + +--*********************************************************** +-- Chargement Rapide (toutes a la suite) +--*********************************************************** +-- case ect is +-- +-- when e0 => +-- if(Load='1' and Empty='0')then +-- Read <= '0'; +-- ect <= eX; +-- end if; +-- +-- when eX => +-- ect <= e1; +-- +-- when e1 => +-- Data_re <= DATA; +-- Data_im <= (others => '0'); +-- Valid <= '1'; +-- if(DataCount=NbData-2)then +-- Read <= '1'; +-- DataCount <= DataCount + 1; +-- elsif(DataCount=NbData)then +-- Valid <= '0'; +-- DataCount <= 0; +-- ect <= e0; +-- else +-- DataCount <= DataCount + 1; +-- end if; +-- +-- when others => +-- null; +-- +-- end case; +--*********************************************************** end if; end process; end architecture; - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/lpp_fft/FFTaval.vhd b/lib/lpp/dsp/lpp_fft/FFTaval.vhd --- a/lib/lpp/dsp/lpp_fft/FFTaval.vhd +++ b/lib/lpp/dsp/lpp_fft/FFTaval.vhd @@ -5,7 +5,8 @@ use IEEE.numeric_std.all; entity FFTaval is generic( - Data_sz : integer range 1 to 32 := 8 + Data_sz : integer range 1 to 32 := 8; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; @@ -30,7 +31,8 @@ signal ect : etat; signal DataTmp : std_logic_vector(Data_sz-1 downto 0); -signal sReady : std_logic; +signal sRead : std_logic; +signal DataCount : integer; begin @@ -38,53 +40,51 @@ begin begin if(rstn='0')then ect <= e0; - Read <= '0'; + sRead <= '0'; Write <= '1'; Reuse <= '0'; + DataCount <= 0; elsif(clk'event and clk='1')then - sReady <= Ready; + + if(Ready='1')then + sRead <= not sRead; + else + sRead <= '0'; + end if; + if(DataCount=NbData or Ready='0')then + DataCount <= 0; + elsif(Valid='1')then + DataCount <= DataCount+1; + end if; + + case ect is when e0 => Write <= '1'; - if(sReady='0' and Ready='1' and full='0')then - Read <= '1'; - ect <= e1; - end if; - - when e1 => - Read <= '0'; if(Valid='1' and full='0')then DataTmp <= Data_im; DATA <= Data_re; Write <= '0'; - ect <= e2; + ect <= e1; elsif(full='1')then - ReUse <= '1'; - ect <= e0; + ReUse <= '1'; end if; - when e2 => + when e1 => DATA <= DataTmp; - ect <= e3; - - when e3 => - Write <= '1'; - if(Ready='1' and full='0')then - Read <= '1'; - ect <= e1; - end if; + ect <= e0; - when eX => - null; + when others => + null; end case; end if; end process; - +Read <= sRead; end architecture; diff --git a/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/Linker_FFT.vhd @@ -25,7 +25,8 @@ use IEEE.numeric_std.all; entity Linker_FFT is generic( - Data_sz : integer range 1 to 32 := 8 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; @@ -45,15 +46,15 @@ end entity; architecture ar_Linker of Linker_FFT is -type etat is (eX,e0,e1,e2,e3); +type etat is (eX,e0,e1,e2); signal ect : etat; -signal FifoCpt : integer; signal DataTmp : std_logic_vector(Data_sz-1 downto 0); -signal sFull : std_logic; -signal sData : std_logic_vector(Data_sz-1 downto 0); -signal sReady : std_logic; +signal sRead : std_logic; +signal sReady : std_logic; + +signal FifoCpt : integer range 0 to 4 := 0; begin @@ -61,69 +62,51 @@ begin begin if(rstn='0')then ect <= e0; - Read <= '0'; + sRead <= '0'; + sReady <= '0'; Write <= (others => '1'); Reuse <= (others => '0'); - FifoCpt <= 1; - sDATA <= (others => '0'); + FifoCpt <= 0; elsif(clk'event and clk='1')then sReady <= Ready; + if(sReady='1' and Ready='0')then + if(FifoCpt=4)then + FifoCpt <= 0; + else + FifoCpt <= FifoCpt + 1; + end if; + elsif(Ready='1')then + sRead <= not sRead; + else + sRead <= '0'; + end if; + case ect is when e0 => - Write(FifoCpt-1) <= '1'; - if(sReady='0' and Ready='1' and sfull='0')then - Read <= '1'; + Write(FifoCpt) <= '1'; + if(Valid='1' and Full(FifoCpt)='0')then + DataTmp <= Data_im; + DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re; + Write(FifoCpt) <= '0'; ect <= e1; - end if; - - when e1 => - Read <= '0'; - if(Valid='1' and sfull='0')then - DataTmp <= Data_im; - sDATA <= Data_re; - Write(FifoCpt-1) <= '0'; - ect <= e2; - elsif(sfull='1')then - ReUse(FifoCpt-1) <= '1'; - ect <= eX; + elsif(Full(FifoCpt)='1')then + ReUse(FifoCpt) <= '1'; end if; - when e2 => - sDATA <= DataTmp; - ect <= e3; - - when e3 => - Write(FifoCpt-1) <= '1'; - if(Ready='1' and sfull='0')then - Read <= '1'; - ect <= e1; - end if; + when e1 => + DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp; + ect <= e0; - when eX => - if(FifoCpt=5)then - FifoCpt <= 1; - else - FifoCpt <= FifoCpt+1; - end if; - ect <= e0; + when others => + null; end case; end if; end process; -DATA <= sData & sData & sData & sData & sData; +Read <= sRead; -with FifoCpt select - sFull <= Full(0) when 1, - Full(1) when 2, - Full(2) when 3, - Full(3) when 4, - Full(4) when 5, - '1' when others; - - -end architecture; - +end architecture; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -89,7 +89,8 @@ end component; component Linker_FFT is generic( - Data_sz : integer range 1 to 32 := 16 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; @@ -109,14 +110,14 @@ end component; component Driver_FFT is generic( - Data_sz : integer range 1 to 32 := 16 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; rstn : in std_logic; Load : in std_logic; Empty : in std_logic_vector(4 downto 0); - Full : in std_logic_vector(4 downto 0); DATA : in std_logic_vector((5*Data_sz)-1 downto 0); Valid : out std_logic; Read : out std_logic_vector(4 downto 0); @@ -127,14 +128,14 @@ end component; component FFTamont is generic( - Data_sz : integer range 1 to 32 := 16 + Data_sz : integer range 1 to 32 := 16; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; rstn : in std_logic; Load : in std_logic; Empty : in std_logic; - Full : in std_logic; DATA : in std_logic_vector(Data_sz-1 downto 0); Valid : out std_logic; Read : out std_logic; @@ -145,7 +146,8 @@ end component; component FFTaval is generic( - Data_sz : integer range 1 to 32 := 8 + Data_sz : integer range 1 to 32 := 8; + NbData : integer range 1 to 512 := 256 ); port( clk : in std_logic; diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/leon3mp.vhd @@ -0,0 +1,612 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +library techmap; +use techmap.gencomp.all; +library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; +use gaisler.uart.all; +use gaisler.misc.all; +library esa; +use esa.memoryctrl.all; +use work.config.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.lpp_memory.all; +use lpp.lpp_uart.all; +use lpp.lpp_matrix.all; +use lpp.lpp_delay.all; +use lpp.lpp_fft.all; +use lpp.fft_components.all; +use lpp.lpp_ad_conv.all; +use lpp.iir_filter.all; +use lpp.general_purpose.all; +use lpp.Filtercfg.all; + +entity leon3mp is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW + ); + port ( + clk50MHz : in std_ulogic; + reset : in std_ulogic; + ramclk : out std_logic; + + ahbrxd : in std_ulogic; -- DSU rx data + ahbtxd : out std_ulogic; -- DSU tx data + dsubre : in std_ulogic; + dsuact : out std_ulogic; + urxd1 : in std_ulogic; -- UART1 rx data + utxd1 : out std_ulogic; -- UART1 tx data + errorn : out std_ulogic; + + address : out std_logic_vector(18 downto 0); + data : inout std_logic_vector(31 downto 0); + gpio : inout std_logic_vector(6 downto 0); -- I/O port + + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + SSRAM_CLK : out std_logic; + ZZ : out std_logic; +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------In/Out----------------------- +--------------------------------------------------------------------- +-- UART + UART_RXD : in std_logic; + UART_TXD : out std_logic; +-- ADC +-- ADC_in : in AD7688_in(4 downto 0); +-- ADC_out : out AD7688_out; +-- Bias_Fails : out std_logic; +-- CNA +-- DAC_SYNC : out std_logic; +-- DAC_SCLK : out std_logic; +-- DAC_DATA : out std_logic; +-- Diver + SPW1_EN : out std_logic; + SPW2_EN : out std_logic; + TEST : out std_logic_vector(3 downto 0); + + BP : in std_logic; +--------------------------------------------------------------------- + led : out std_logic_vector(1 downto 0) + ); +end; + +architecture Behavioral of leon3mp is + +constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ + CFG_GRETH+CFG_AHB_JTAG; +constant maxahbm : integer := maxahbmsp; + +--Clk & Rst g�n� +signal vcc : std_logic_vector(4 downto 0); +signal gnd : std_logic_vector(4 downto 0); +signal resetnl : std_ulogic; +signal clk2x : std_ulogic; +signal lclk : std_ulogic; +signal lclk2x : std_ulogic; +signal clkm : std_ulogic; +signal rstn : std_ulogic; +signal rstraw : std_ulogic; +signal pciclk : std_ulogic; +signal sdclkl : std_ulogic; +signal cgi : clkgen_in_type; +signal cgo : clkgen_out_type; +--- AHB / APB +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); +--UART +signal ahbuarti : uart_in_type; +signal ahbuarto : uart_out_type; +signal apbuarti : uart_in_type; +signal apbuarto : uart_out_type; +--MEM CTRLR +signal memi : memory_in_type; +signal memo : memory_out_type; +signal wpo : wprot_out_type; +signal sdo : sdram_out_type; +--IRQ +signal irqi : irq_in_vector(0 to CFG_NCPU-1); +signal irqo : irq_out_vector(0 to CFG_NCPU-1); +--Timer +signal gpti : gptimer_in_type; +signal gpto : gptimer_out_type; +--GPIO +signal gpioi : gpio_in_type; +signal gpioo : gpio_out_type; +--DSU +signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); +signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); +signal dsui : dsu_in_type; +signal dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- +-- FIFOs +signal FifoIN_Full : std_logic_vector(4 downto 0); +signal FifoIN_Empty : std_logic_vector(4 downto 0); +signal FifoIN_Data : std_logic_vector(79 downto 0); + +signal FifoINT_Full : std_logic_vector(4 downto 0); +signal FifoINT_Data : std_logic_vector(79 downto 0); + +signal FifoOUT_FullV : std_logic; +signal FifoOUT_Full : std_logic_vector(1 downto 0); +signal Matrix_WriteV : std_logic_vector(0 downto 0); + +-- MATRICE SPECTRALE +signal Matrix_Write : std_logic; +signal Matrix_Read : std_logic_vector(1 downto 0); +signal Matrix_Result : std_logic_vector(31 downto 0); + +signal TopSM_Start : std_logic; +signal TopSM_Statu : std_logic_vector(3 downto 0); +signal TopSM_Read : std_logic_vector(4 downto 0); +signal TopSM_Data1 : std_logic_vector(15 downto 0); +signal TopSM_Data2 : std_logic_vector(15 downto 0); + +signal Disp_FlagError : std_logic; +signal Disp_Pong : std_logic; +signal Disp_Write : std_logic_vector(1 downto 0);-- +signal Disp_Data : std_logic_vector(63 downto 0);-- +signal Dma_acq : std_logic; + +-- FFT +signal Drive_Write : std_logic; +signal Drive_Read : std_logic_vector(4 downto 0); +signal Drive_DataRE : std_logic_vector(15 downto 0); +signal Drive_DataIM : std_logic_vector(15 downto 0); + +signal Start : std_logic; +signal RstnFFT : std_logic; +signal FFT_Load : std_logic; +signal FFT_Ready : std_logic; +signal FFT_Valid : std_logic; +signal FFT_DataRE : std_logic_vector(15 downto 0); +signal FFT_DataIM : std_logic_vector(15 downto 0); + +signal Link_Read : std_logic; +signal Link_Write : std_logic_vector(4 downto 0); +signal Link_ReUse : std_logic_vector(4 downto 0); +signal Link_Data : std_logic_vector(79 downto 0); + +-- ADC +signal SmplClk : std_logic; +signal ADC_DataReady : std_logic; +signal ADC_SmplOut : Samples_out(4 downto 0); +signal enableADC : std_logic; + +signal WG_Write : std_logic_vector(4 downto 0); +signal WG_ReUse : std_logic_vector(4 downto 0); +signal WG_DATA : std_logic_vector(79 downto 0); +signal s_out : std_logic_vector(79 downto 0); + +signal fuller : std_logic_vector(4 downto 0); +signal reader : std_logic_vector(4 downto 0); +signal try : std_logic_vector(1 downto 0); +signal TXDint : std_logic; + +-- IIR Filter +signal sample_clk_out : std_logic; + +signal Rd : std_logic_vector(0 downto 0); +signal Ept : std_logic_vector(4 downto 0); + +signal Bwr : std_logic_vector(0 downto 0); +signal Bre : std_logic_vector(0 downto 0); +signal DataTMP : std_logic_vector(15 downto 0); +signal FullUp : std_logic_vector(0 downto 0); +signal EmptyUp : std_logic_vector(0 downto 0); +signal FullDown : std_logic_vector(0 downto 0); +signal EmptyDown : std_logic_vector(0 downto 0); +--------------------------------------------------------------------- +constant IOAEN : integer := CFG_CAN; +constant boardfreq : integer := 50000; + +begin + +--------------------------------------------------------------------- +--- AJOUT TEST -------------------------------------IPs------------- +--------------------------------------------------------------------- +led(1 downto 0) <= gpio(1 downto 0); + +--- COM USB --------------------------------------------------------- +-- MemIn0 : APB_FifoWrite +-- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) +-- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5)); +-- +-- BUF0 : APB_USB +-- generic map (6,6,DataMax => 1024) +-- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6)); +-- +-- MemOut0 : APB_FifoRead +-- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256) +-- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7)); +-- +--slrd <= usb_Read; +--slwr <= usb_Write; + +--- CNA ------------------------------------------------------------- + +-- CONV : APB_CNA +-- generic map (5,5) +-- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA); + +--TEST(0) <= SmplClk; +--TEST(1) <= WG_Write(0); +--TEST(2) <= Fuller(0); +--TEST(3) <= s_out(s_out'length-1); + + +--SPW1_EN <= '1'; +--SPW2_EN <= '0'; + +--- CAN ------------------------------------------------------------- + +-- Divider : Clk_divider +-- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576) +-- Port map(clkm,rstn,SmplClk); +-- +-- ADC : AD7688_drvr +-- generic map (ChanelCount => 5, clkkHz => 24_576) +-- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out); +-- +-- WG : WriteGen_ADC +-- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write); +-- +--enableADC <= gpio(0); +--Bias_Fails <= '0'; +--WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0); +-- +-- +-- MemIn1 : APB_FIFO +-- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); + +--- FFT ------------------------------------------------------------- + + MemIn : APB_FIFO + generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) + port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); + + DRIVE : Driver_FFT + generic map(Data_sz => 16) + port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM); + +Start <= '0'; + + FFT : CoreFFT + generic map( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); + + LINK : Linker_FFT + generic map(Data_sz => 16) + port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data); + +----- LINK MEMORY ------------------------------------------------------- + +-- MemOut : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9)); + + MemInt : lppFIFOxN + generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') + port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open); + +-- MemIn : APB_FIFO +-- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); + +----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- + + TopSM : TopSpecMatrix + generic map (Input_SZ => 16) + port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); + + SM : SpectralMatrix + generic map (Input_SZ => 16, Result_SZ => 32) + port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); + +Dma_acq <= '1'; + + DISP : Dispatch + generic map(Data_SZ => 32) + port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError); + + MemOut : APB_FIFO + generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9)); + +----- FIFO ------------------------------------------------------------- + + Memtest : APB_FIFO + generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); + +--***************************************TEST DEMI-FIFO******************************************************************************** +-- MemIn : APB_FIFO +-- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8)); +-- +-- Pont : Bridge +-- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0)); +-- +-- MemOut : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9)); +--************************************************************************************************************************************* + +--- UART ------------------------------------------------------------- + + COM0 : APB_UART + generic map (pindex => 4, paddr => 4) + port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD); + +--- DELAY ------------------------------------------------------------ + +-- Delay0 : APB_Delay +-- generic map (pindex => 4, paddr => 4) +-- port map (clkm,rstn,apbi,apbo(4)); + +--- IIR Filter ------------------------------------------------------- +--Test(0) <= sample_clk_out; +-- +-- +-- IIR1: APB_IIR_Filter +-- generic map( +-- tech => CFG_MEMTECH, +-- pindex => 8, +-- paddr => 8, +-- Sample_SZ => Sample_SZ, +-- ChanelsCount => ChanelsCount, +-- Coef_SZ => Coef_SZ, +-- CoefCntPerCel => CoefCntPerCel, +-- Cels_count => Cels_count, +-- virgPos => virgPos +-- ) +-- port map( +-- rst => rstn, +-- clk => clkm, +-- apbi => apbi, +-- apbo => apbo(8), +-- sample_clk_out => sample_clk_out, +-- GOtest => Test(1), +-- CoefsInitVal => (others => '1') +-- ); +---------------------------------------------------------------------- + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (others => '1'); gnd <= (others => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); + + clkgen0 : clkgen -- clock generator + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); + + ramclk <= clkm; +process(lclk2x) +begin + if lclk2x'event and lclk2x = '1' then + lclk <= not lclk; + end if; +end process; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : if CFG_LEON3 = 1 generate + cpu : for i in 0 to CFG_NCPU-1 generate + u0 : leon3s -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + end generate; + errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); + + dsugen : if CFG_DSU = 1 generate + dsu0 : dsu3 -- LEON3 Debug Support Unit + generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); +-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); + dsui.enable <= '1'; + dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); + dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); + end generate; + end generate; + + nodsu : if CFG_DSU = 0 generate + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + end generate; + + irqctrl : if CFG_IRQ3_ENABLE /= 0 generate + irqctrl0 : irqmp -- interrupt controller + generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + end generate; + irq3 : if CFG_IRQ3_ENABLE = 0 generate + x : for i in 0 to CFG_NCPU-1 generate + irqi(i).irl <= "0000"; + end generate; + apbo(2) <= apb_none; + end generate; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + + memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) + port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); + + memi.brdyn <= '1'; memi.bexcn <= '1'; + memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; + + bdr : for i in 0 to 3 generate + data_pad : iopadv generic map (tech => padtech, width => 8) + port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), + memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); + end generate; + + + addr_pad : outpadv generic map (width => 19, tech => padtech) + port map (address, memo.address(20 downto 2)); + + + SSRAM_0:entity ssram_plugin + generic map (tech => padtech) + port map + (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); +-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; + end generate; + nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 1, haddr => CFG_APBADDR) + port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + + gpt : if CFG_GPT_ENABLE /= 0 generate + timer0 : gptimer -- timer unit + generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + port map (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; +-- led(4) <= gpto.wdog; + end generate; + notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + ua1 : if CFG_UART1_ENABLE /= 0 generate + uart1 : apbuart -- UART 1 + generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); + apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; +-- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; + end generate; + noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- GPIO ----------------------------------------------------------- +---------------------------------------------------------------------- + + gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit + grgpio0: grgpio + generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) + port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); + + pio_pads : for i in 0 to 6 generate + pio_pad : iopad generic map (tech => padtech) + port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); + end generate; + end generate; + + +end Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_demux/DEMUX.vhd b/lib/lpp/lpp_demux/DEMUX.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_demux/DEMUX.vhd @@ -0,0 +1,179 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity DEMUX is +generic( + Data_sz : integer range 1 to 32 := 16); +port( + clk : in std_logic; + rstn : in std_logic; + + Read : in std_logic_vector(4 downto 0); + DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + + Read_DEMUX : out std_logic_vector(19 downto 0); + Empty : out std_logic_vector(4 downto 0); + Data : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end entity; + + +architecture ar_DEMUX of DEMUX is + +type etat is (eX,e0,e1,e2,e3); +signal ect : etat; + +signal pong : std_logic; + +signal DataCpt_reg : std_logic_vector(3 downto 0); +constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); + +signal Countf0 : integer; +signal Countf1 : integer; + +begin + process(clk,rstn) + begin + if(rstn='0')then + ect <= e0; + pong <= '0'; + Countf0 <= 1; + Countf1 <= 0; + + elsif(clk'event and clk='1')then + DataCpt_reg <= DataCpt; + + case ect is + + when e0 => + if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then + pong <= not pong; + if(Countf0 = 5)then + Countf0 <= 0; + ect <= e2; + else + Countf0 <= Countf0 + 1; + ect <= e1; + end if; + end if; + + when e1 => + if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then + pong <= not pong; + if(Countf0 = 5)then + Countf0 <= 0; + ect <= e2; + else + Countf0 <= Countf0 + 1; + ect <= e0; + end if; + end if; + + when e2 => + if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then + if(Countf1 = 15)then + Countf1 <= 0; + ect <= e3; + else + Countf1 <= Countf1 + 1; + if(pong = '0')then + ect <= e0; + else + ect <= e1; + end if; + end if; + end if; + + when e3 => + if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then + if(pong = '0')then + ect <= e0; + else + ect <= e1; + end if; + end if; + + when others => + null; + + end case; + end if; + end process; + +with ect select + Empty <= EmptyF0a when e0, + EmptyF0b when e1, + EmptyF1 when e2, + EmptyF2 when e3, + (others => '1') when others; + +with ect select + Data <= DataF0a when e0, + DataF0b when e1, + DataF1 when e2, + DataF2 when e3, + (others => '0') when others; + +with ect select + Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0, + Dummy_Read & Dummy_Read & Read & Dummy_Read when e1, + Dummy_Read & Read & Dummy_Read & Dummy_Read when e2, + Read & Dummy_Read & Dummy_Read & Dummy_Read when e3, + (others => '1') when others; + + + + +end architecture; + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_demux/WatchFlag.vhd b/lib/lpp/lpp_demux/WatchFlag.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_demux/WatchFlag.vhd @@ -0,0 +1,65 @@ +-- WatchFlag.vhd +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity WatchFlag is +port( + clk : in std_logic; + rstn : in std_logic; + + FullF0a : in std_logic_vector(4 downto 0); + FullF0b : in std_logic_vector(4 downto 0); + FullF1 : in std_logic_vector(4 downto 0); + FullF2 : in std_logic_vector(4 downto 0); + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a +); +end entity; + + +architecture ar_WatchFlag of WatchFlag is + +constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1'); + +begin + process(clk,rstn) + begin + if(rstn='0')then + DataCpt <= (others => '0'); + + elsif(clk'event and clk='1')then + + if(FullF0a = FlagSet)then + DataCpt(0) <= '1'; + elsif(EmptyF0a = FlagSet)then + DataCpt(0) <= '0'; + end if; + + if(FullF0b = FlagSet)then + DataCpt(1) <= '1'; + elsif(EmptyF0b = FlagSet)then + DataCpt(1) <= '0'; + end if; + + if(FullF1 = FlagSet)then + DataCpt(2) <= '1'; + elsif(EmptyF1 = FlagSet)then + DataCpt(2) <= '0'; + end if; + + if(FullF2 = FlagSet)then + DataCpt(3) <= '1'; + elsif(EmptyF2 = FlagSet)then + DataCpt(3) <= '0'; + end if; + + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_demux/lpp_demux.vhd b/lib/lpp/lpp_demux/lpp_demux.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_demux/lpp_demux.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; + +--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on + +package lpp_demux is + +component DEMUX is +generic( + Data_sz : integer range 1 to 32 := 16); +port( + clk : in std_logic; + rstn : in std_logic; + + Read : in std_logic_vector(4 downto 0); + DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); + DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + + Read_DEMUX : out std_logic_vector(19 downto 0); + Empty : out std_logic_vector(4 downto 0); + Data : out std_logic_vector((5*Data_sz)-1 downto 0) +); +end component; + + +component WatchFlag is +port( + clk : in std_logic; + rstn : in std_logic; + + FullF0a : in std_logic_vector(4 downto 0); + FullF0b : in std_logic_vector(4 downto 0); + FullF1 : in std_logic_vector(4 downto 0); + FullF2 : in std_logic_vector(4 downto 0); + + EmptyF0a : in std_logic_vector(4 downto 0); + EmptyF0b : in std_logic_vector(4 downto 0); + EmptyF1 : in std_logic_vector(4 downto 0); + EmptyF2 : in std_logic_vector(4 downto 0); + + DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a +); +end component; + + +end; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/Dispatch.vhd b/lib/lpp/lpp_matrix/Dispatch.vhd --- a/lib/lpp/lpp_matrix/Dispatch.vhd +++ b/lib/lpp/lpp_matrix/Dispatch.vhd @@ -22,7 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -use lpp.lpp_matrix.all; entity Dispatch is generic( @@ -34,65 +33,52 @@ port( Data : in std_logic_vector(Data_SZ-1 downto 0); Write : in std_logic; Full : in std_logic_vector(1 downto 0); --- Empty : in std_logic_vector(1 downto 0); FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); FifoWrite : out std_logic_vector(1 downto 0); --- FifoFull : out std_logic; Pong : out std_logic; Error : out std_logic - ); end entity; architecture ar_Dispatch of Dispatch is -type etat is (e0,e1,e2,e3); +type etat is (eX,e0,e1,e2); signal ect : etat; +signal Pong_int : std_logic; +signal FifoCpt : integer range 0 to 1 := 0; + begin process (clk,reset) begin if(reset='0')then - Pong <= '0'; - Error <= '0'; + Pong_int <= '0'; + Error <= '0'; + ect <= e0; elsif(clk' event and clk='1')then case ect is when e0 => - if(Full(0) = '1')then - pong <= '1'; + if(Full(FifoCpt) = '1')then + Pong_int <= not Pong_int; ect <= e1; end if; when e1 => - if(Acq <= '1')then - Error <= '0'; - pong <= '0'; - ect <= e2; - else + if(Acq = '0')then Error <= '1'; ect <= e1; - end if; - - when e2 => - if(Full(1) = '1')then - pong <= '1'; - ect <= e3; - end if; - - when e3 => - if(Acq <= '1')then + else Error <= '0'; - pong <= '0'; ect <= e0; - else - Error <= '1'; - ect <= e3; - end if; + end if; + + when others => + null; end case; @@ -100,10 +86,10 @@ begin end process; FifoData <= Data & Data; +Pong <= Pong_int; -with ect select - FifoWrite <= '1' & not Write when e0, - not Write & '1' when e2, - "11" when others; +FifoCpt <= 0 when Pong_int='0' else 1; + +FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/TopSpecMatrix.vhd b/lib/lpp/lpp_matrix/TopSpecMatrix.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/TopSpecMatrix.vhd @@ -0,0 +1,198 @@ + ------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity TopSpecMatrix is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + rstn : in std_logic; + Write : in std_logic; + ReadIn : in std_logic_vector(1 downto 0); + Full : in std_logic_vector(4 downto 0); + Data : in std_logic_vector((5*Input_SZ)-1 downto 0); + Start : out std_logic; + ReadOut : out std_logic_vector(4 downto 0); + Statu : out std_logic_vector(3 downto 0); + DATA1 : out std_logic_vector(Input_SZ-1 downto 0); + DATA2 : out std_logic_vector(Input_SZ-1 downto 0) +); +end entity; + +architecture ar_TopSpecMatrix of TopSpecMatrix is + +type etat is (eX,e0,e1,e2); +signal ect : etat; + +signal DataCount : integer range 0 to 256 := 0; +signal StatuINT : integer range 1 to 15 := 1; + +signal Write_reg : std_logic; +signal Full_int : std_logic_vector(1 downto 0); + +begin + process(clk,rstn) + begin + + if(rstn='0')then + DataCount <= 0; + StatuINT <= 1; + Write_reg <= '0'; + Start <= '0'; + ect <= e0; + + elsif(clk'event and clk='1')then + Write_reg <= Write; + + if(Write_reg='1' and Write='0')then + if(DataCount=256)then + DataCount <= 0; + else + DataCount <= DataCount + 1; + end if; + end if; + + + case ect is + + when e0 => + if(Full_int = "11")then + Start <= '1'; + if(StatuINT=1 or StatuINT=3 or StatuINT=6 or StatuINT=10 or StatuINT=15)then + ect <= e1; + else + ect <= e2; + end if; + end if; + + when e1 => + if(DataCount=128)then + if(StatuINT=15)then + StatuINT <= 1; + else + StatuINT <= StatuINT + 1; + end if; + DataCount <= 0; + Start <= '0'; + ect <= e0; + end if; + + when e2 => + if(DataCount=256)then + DataCount <= 0; + StatuINT <= StatuINT + 1; + Start <= '0'; + ect <= e0; + end if; + + when others => + null; + + end case; + end if; + end process; + +Statu <= std_logic_vector(to_unsigned(StatuINT,4)); + +with StatuINT select + DATA1 <= Data(15 downto 0) when 1, + Data(15 downto 0) when 2, + Data(31 downto 16) when 3, + Data(15 downto 0) when 4, + Data(31 downto 16) when 5, + Data(47 downto 32) when 6, + Data(15 downto 0) when 7, + Data(31 downto 16) when 8, + Data(47 downto 32) when 9, + Data(63 downto 48) when 10, + Data(15 downto 0) when 11, + Data(31 downto 16) when 12, + Data(47 downto 32) when 13, + Data(63 downto 48) when 14, + Data(79 downto 64) when 15, + X"0000" when others; + + +with StatuINT select + DATA2 <= (others => '0') when 1, + Data(31 downto 16) when 2, + (others => '0') when 3, + Data(47 downto 32) when 4, + Data(47 downto 32) when 5, + (others => '0') when 6, + Data(63 downto 48) when 7, + Data(63 downto 48) when 8, + Data(63 downto 48) when 9, + (others => '0') when 10, + Data(79 downto 64) when 11, + Data(79 downto 64) when 12, + Data(79 downto 64) when 13, + Data(79 downto 64) when 14, + (others => '0') when 15, + X"0000" when others; + +with StatuINT select + ReadOut <= "1111" & not READin(0) when 1, + "111" & not READin(1) & not READin(0) when 2, + "111" & not READin(0) & '1' when 3, + "11" & not READin(1) & '1' & not READin(0) when 4, + "11" & not READin(1) & not READin(0) & '1' when 5, + "11" & not READin(0) & "11" when 6, + "1" & not READin(1) & "11" & not READin(0) when 7, + '1' & not READin(1) & '1' & not READin(0) & '1' when 8, + '1' & not READin(1) & not READin(0) & "11" when 9, + '1' & not READin(0) & "111" when 10, + not READin(1) & "111" & not READin(0) when 11, + not READin(1) & "11" & not READin(0) & '1' when 12, + not READin(1) & '1' & not READin(0) & "11" when 13, + not READin(1) & not READin(0) & "111" when 14, + not READin(0) & "1111" when 15, + "11111" when others; + +with StatuINT select + Full_int <= Full(0) & Full(0) when 1, + Full(1) & Full(0) when 2, + Full(1) & Full(1) when 3, + Full(2) & Full(0) when 4, + Full(2) & Full(1) when 5, + Full(2) & Full(2) when 6, + Full(3) & Full(0) when 7, + Full(3) & Full(1) when 8, + Full(3) & Full(2) when 9, + Full(3) & Full(3) when 10, + Full(4) & Full(0) when 11, + Full(4) & Full(1) when 12, + Full(4) & Full(2) when 13, + Full(4) & Full(3) when 14, + Full(4) & Full(4) when 15, + "00" when others; + +end architecture; + + + + + + diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -56,6 +56,25 @@ component APB_Matrix is ); end component; +component TopSpecMatrix is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + rstn : in std_logic; + Write : in std_logic; + ReadIn : in std_logic_vector(1 downto 0); + Full : in std_logic_vector(4 downto 0); + Data : in std_logic_vector((5*Input_SZ)-1 downto 0); + Start : out std_logic; + ReadOut : out std_logic_vector(4 downto 0); + Statu : out std_logic_vector(3 downto 0); + DATA1 : out std_logic_vector(Input_SZ-1 downto 0); + DATA2 : out std_logic_vector(Input_SZ-1 downto 0) +); +end component; + + component Top_MatrixSpec is generic( Input_SZ : integer := 16; diff --git a/lib/lpp/lpp_memory/Bridge.vhd b/lib/lpp/lpp_memory/Bridge.vhd --- a/lib/lpp/lpp_memory/Bridge.vhd +++ b/lib/lpp/lpp_memory/Bridge.vhd @@ -4,75 +4,50 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Bridge is -generic( - Data_sz : integer range 1 to 32 := 16 - ); -port( - clk : in std_logic; - raz : in std_logic; - Start : in std_logic; - FullUp : in std_logic; - EmptyUp : in std_logic; - FullDown : in std_logic; - EmptyDown : in std_logic; - Write : out std_logic; - Read : out std_logic -); + port( + clk : in std_logic; + raz : in std_logic; + EmptyUp : in std_logic; + FullDwn : in std_logic; + WriteDwn : out std_logic; + ReadUp : out std_logic + ); end entity; architecture ar_Bridge of Bridge is -type etat is (eX,e1,e2,e3); +type etat is (e0,e1); signal ect : etat; -signal i : integer; - begin process(clk,raz) begin if(raz='0')then - Write <= '1'; - Read <= '1'; - i <= 0; - ect <= eX; - + WriteDwn <= '1'; + ReadUp <= '1'; + ect <= e0; + elsif(clk'event and clk='1')then - + case ect is - - when eX => - if(FullUp='1' and EmptyDown='1' and start='0')then - ect <= e1; - end if; + + when e0 => + WriteDwn <= '1'; + if(EmptyUp='0' and FullDwn='0')then + ReadUp <= '0'; + ect <= e1; + end if; when e1 => - Write <= '1'; - if(EmptyUp='0')then - Read <= '0'; - ect <= e2; - else - Read <= '1'; - ect <= e3; - end if; - - when e2 => - Read <= '1'; - if(FullDown='0')then - Write <= '0'; - ect <= e1; - else - Write <= '1'; - ect <= e3; - end if; - - when e3 => - null; - - end case; + ReadUp <= '1'; + WriteDwn <= '0'; + ect <= e0; + + end case; + end if; end process; - end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -138,20 +138,14 @@ port( end component; component Bridge is -generic( - Data_sz : integer range 1 to 32 := 16 - ); -port( - clk : in std_logic; - raz : in std_logic; - Start : in std_logic; - FullUp : in std_logic; - EmptyUp : in std_logic; - FullDown : in std_logic; - EmptyDown : in std_logic; - Write : out std_logic; - Read : out std_logic -); + port( + clk : in std_logic; + raz : in std_logic; + EmptyUp : in std_logic; + FullDwn : in std_logic; + WriteDwn : out std_logic; + ReadUp : out std_logic + ); end component; component ssram_plugin is