# HG changeset patch # User martin # Date 2013-11-18 13:17:05 # Node ID 30d38bdb470054f518d5962d872291f72a7497be # Parent 95bafd2668d9ed6463fd6b5e98de97689c863089 ReName some files diff --git a/lib/lpp/lpp_cna/APB_CNA.vhd b/lib/lpp/lpp_cna/APB_CNA.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/APB_CNA.vhd +++ /dev/null @@ -1,125 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_cna.all; - ---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba - -entity APB_CNA is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus - apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus - Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL - SYNC : out std_logic; --! Signal de synchronisation du convertisseur - SCLK : out std_logic; --! Horloge systeme du convertisseur - DATA : out std_logic --! Donn�e num�rique s�rialis� - ); -end APB_CNA; - ---! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus ---! et les sorties seront cabl�es vers le convertisseur. - -architecture ar_APB_CNA of APB_CNA is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -signal enable : std_logic; -signal flag_sd : std_logic; - -type CNA_ctrlr_Reg is record - CNA_Cfg : std_logic_vector(1 downto 0); - CNA_Data : std_logic_vector(15 downto 0); -end record; - -signal Rec : CNA_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -begin - -enable <= Rec.CNA_Cfg(0); -Rec.CNA_Cfg(1) <= flag_sd; - - CONVERTER : CNA_TabloC - port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); - - - process(rst,clk) - begin - if(rst='0')then - Rec.CNA_Data <= (others => '0'); - - elsif(clk'event and clk='1')then - - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rec.CNA_Cfg(0) <= apbi.pwdata(0); - when "000001" => - Rec.CNA_Data <= apbi.pwdata(15 downto 0); - when others => - null; - end case; - end if; - - --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 2) <= X"ABCDEF5" & "00"; - Rdata(1 downto 0) <= Rec.CNA_Cfg; - when "000001" => - Rdata(31 downto 16) <= X"FD18"; - Rdata(15 downto 0) <= Rec.CNA_Data; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -Cal_EN <= enable; -end ar_APB_CNA; diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/APB_DAC.vhd @@ -0,0 +1,125 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.lpp_cna.all; + +--! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba + +entity APB_DAC is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus + Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL + SYNC : out std_logic; --! Signal de synchronisation du convertisseur + SCLK : out std_logic; --! Horloge systeme du convertisseur + DATA : out std_logic --! Donn�e num�rique s�rialis� + ); +end entity; + +--! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus +--! et les sorties seront cabl�es vers le convertisseur. + +architecture ar_APB_DAC of APB_DAC is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +signal enable : std_logic; +signal flag_sd : std_logic; + +type DAC_ctrlr_Reg is record + DAC_Cfg : std_logic_vector(1 downto 0); + DAC_Data : std_logic_vector(15 downto 0); +end record; + +signal Rec : DAC_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); + +begin + +enable <= Rec.DAC_Cfg(0); +Rec.DAC_Cfg(1) <= flag_sd; + + CONV0 : DacDriver + port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); + + + process(rst,clk) + begin + if(rst='0')then + Rec.DAC_Data <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.DAC_Cfg(0) <= apbi.pwdata(0); + when "000001" => + Rec.DAC_Data <= apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(31 downto 2) <= X"ABCDEF5" & "00"; + Rdata(1 downto 0) <= Rec.DAC_Cfg; + when "000001" => + Rdata(31 downto 16) <= X"FD18"; + Rdata(15 downto 0) <= Rec.DAC_Data; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +Cal_EN <= enable; +end architecture; diff --git a/lib/lpp/lpp_cna/CNA_TabloC.vhd b/lib/lpp/lpp_cna/CNA_TabloC.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/CNA_TabloC.vhd +++ /dev/null @@ -1,67 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.Convertisseur_config.all; - ---! Programme du Convertisseur Num�rique/Analogique - -entity CNA_TabloC is - port( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - enable : in std_logic; --! Autorise ou non l'utilisation du composant - Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits - SYNC : out std_logic; --! Signal de synchronisation du convertisseur - SCLK : out std_logic; --! Horloge systeme du convertisseur - flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e - Data : out std_logic --! Donn�e num�rique s�rialis� - ); -end CNA_TabloC; - ---! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits, ---! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur. - -architecture ar_CNA_TabloC of CNA_TabloC is - -signal s_SCLK : std_logic; -signal OKAI_send : std_logic; - -begin - -SystemCLK : entity work.Systeme_Clock - generic map (nb_serial) - port map (clk,rst,s_SCLK); - - -Signal_sync : entity work.Gene_SYNC - port map (s_SCLK,rst,enable,OKAI_send,SYNC); - - -Serial : entity work.serialize - port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); - - -SCLK <= s_SCLK; - -end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/DacDriver.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.Convertisseur_config.all; +use lpp.lpp_cna.all; + +--! Programme du Convertisseur Num�rique/Analogique + +entity DacDriver is + port( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + enable : in std_logic; --! Autorise ou non l'utilisation du composant + Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits + SYNC : out std_logic; --! Signal de synchronisation du convertisseur + SCLK : out std_logic; --! Horloge systeme du convertisseur + flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e + Data : out std_logic --! Donn�e num�rique s�rialis� + ); +end entity; + +--! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits, +--! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur. + +architecture ar_DacDriver of DacDriver is + +signal s_SCLK : std_logic; +signal OKAI_send : std_logic; + +begin + +SystemCLK : Systeme_Clock + generic map (nb_serial) + port map (clk,rst,s_SCLK); + + +Signal_sync : Gene_SYNC + port map (s_SCLK,rst,enable,OKAI_send,SYNC); + + +Serial : serialize + port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); + + +SCLK <= s_SCLK; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -31,7 +31,7 @@ use lpp.lpp_amba.all; package lpp_cna is -component APB_CNA is +component APB_DAC is generic ( pindex : integer := 0; paddr : integer := 0; @@ -51,7 +51,7 @@ component APB_CNA is end component; -component CNA_TabloC is +component DacDriver is port( clk : in std_logic; rst : in std_logic;