# HG changeset patch # User Jeandet Alexis # Date 2013-12-13 19:43:59 # Node ID 252bd09e4210666c40386cb212c08371704ad0cc # Parent c293782dc1e12987578f9bc318642b1a76e94e99 Working bbone GPMC_interface interface diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd --- a/designs/BeagleSynth/BeagleSynth.vhd +++ b/designs/BeagleSynth/BeagleSynth.vhd @@ -154,7 +154,7 @@ DAC0 : entity work.beagleSigGen CAL_IN_SCK => CAL_IN_SCK, DAC_nCS => DAC_nCS, DAC_SDI => DAC_SDI, - address => GPMC_SLAVE_ADDRESS(3 downto 1), + address => GPMC_SLAVE_ADDRESS(19 downto 1), DATA => GPMC_SLAVE_DATA, WEN => GPMC_SLAVE_WEN, REN_debug => open, @@ -164,8 +164,8 @@ DAC0 : entity work.beagleSigGen ---LED(0) <= GPMC_SLAVE_ADDRESS(1); ---LED(1) <= GPMC_SLAVE_ADDRESS(2); +LED(0) <= GPMC_SLAVE_STATUS(0); +LED(1) <= GPMC_SLAVE_STATUS(8); LED(2) <= GPMC_SLAVE_WEN; gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); @@ -178,8 +178,8 @@ GPMCS0: entity work.GPMC_SLAVE DATA => GPMC_SLAVE_DATA, ADDRESS => GPMC_SLAVE_ADDRESS, WEN => GPMC_SLAVE_WEN, - SMP_CKL => LED(0), - SMP_WEN => LED(1), + SMP_CKL => open, + SMP_WEN => open, GPMC_AD => GPMC_AD, GPMC_A => GPMC_A, GPMC_CLK => gpmc_clk, diff --git a/designs/BeagleSynth/beagleSigGen.vhd b/designs/BeagleSynth/beagleSigGen.vhd --- a/designs/BeagleSynth/beagleSigGen.vhd +++ b/designs/BeagleSynth/beagleSigGen.vhd @@ -40,7 +40,7 @@ entity beagleSigGen is CAL_IN_SCK : out std_ulogic; DAC_nCS : out std_ulogic; DAC_SDI : out std_logic_vector(7 downto 0); - address : in std_logic_vector(2 downto 0); + address : in std_logic_vector(18 downto 0); DATA : in std_logic_vector(15 downto 0); REN_debug : out std_logic; WEN : in std_logic; @@ -51,23 +51,28 @@ end beagleSigGen; architecture Behavioral of beagleSigGen is +subtype TAB16 is std_logic_vector(15 downto 0); +type FIFOout_t is array(7 downto 0) of TAB16; signal FIFO_FULL_net : std_logic_vector(7 downto 0); signal FIFO_EMPTY_net : std_logic_vector(7 downto 0); -signal FIFO_WEN : std_logic_vector(7 downto 0); -signal FIFO_REN : std_logic; - -subtype TAB16 is std_logic_vector(15 downto 0); -type FIFOout_t is array(7 downto 0) of TAB16; +signal FIFO_WEN : std_logic_vector(7 downto 0); +signal FIFO_REN : std_logic; signal FIFO_out : FIFOout_t; + signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); signal smpclk : std_logic; signal smpclk_reg : std_logic; signal DAC_SDO : std_logic; signal DATA_reg : std_logic_vector(15 downto 0); +Constant clk_TRIGER_MAX : integer := (150000000/(2*4096))+1; +signal clk_TRIGER : integer range 0 to clk_TRIGER_MAX := clk_TRIGER_MAX; +signal cpt1 : integer; +signal clk_TRIGER_load : std_logic; + begin @@ -75,174 +80,55 @@ begin FIFO_FULL <= FIFO_FULL_net; FIFO_EMPTY <= FIFO_EMPTY_net; -fron_fifo1: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(0), - empty => FIFO_EMPTY_net(0), - raddr => open, - wclk => clk, - wen => FIFO_WEN(0), - wdata => DATA_reg, - full => FIFO_FULL_net(0), - waddr => open - ); -fron_fifo2: lpp_fifo +FIFOlp : FOR I IN 0 to 7 GENERATE +front_fifoN: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(1), - empty => FIFO_EMPTY_net(1), - raddr => open, - wclk => clk, - wen => FIFO_WEN(1), - wdata => DATA_reg, - full => FIFO_FULL_net(1), - waddr => open - ); -fron_fifo3: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(2), - empty => FIFO_EMPTY_net(2), - raddr => open, - wclk => clk, - wen => FIFO_WEN(2), - wdata => DATA_reg, - full => FIFO_FULL_net(2), - waddr => open - ); -fron_fifo4: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 + AddrSz => 12 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, - rdata => FIFO_out(3), - empty => FIFO_EMPTY_net(3), - raddr => open, - wclk => clk, - wen => FIFO_WEN(3), - wdata => DATA_reg, - full => FIFO_FULL_net(3), - waddr => open - ); -fron_fifo5: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(4), - empty => FIFO_EMPTY_net(4), - raddr => open, - wclk => clk, - wen => FIFO_WEN(4), - wdata => DATA_reg, - full => FIFO_FULL_net(4), - waddr => open - ); -fron_fifo6: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(5), - empty => FIFO_EMPTY_net(5), + rdata => FIFO_out(I), + empty => FIFO_EMPTY_net(I), raddr => open, wclk => clk, - wen => FIFO_WEN(5), + wen => FIFO_WEN(I), wdata => DATA_reg, - full => FIFO_FULL_net(5), + full => FIFO_FULL_net(I), waddr => open ); -fron_fifo7: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(6), - empty => FIFO_EMPTY_net(6), - raddr => open, - wclk => clk, - wen => FIFO_WEN(6), - wdata => DATA_reg, - full => FIFO_FULL_net(6), - waddr => open - ); -fron_fifo8: lpp_fifo - generic map( - tech => memtech, - Mem_use => 1, --use RAM not CELS - DataSz => 16, - AddrSz => 8 - ) - port map( - rstn => rstn, - ReUse => '0', - rclk => clk, - ren => FIFO_REN, - rdata => FIFO_out(7), - empty => FIFO_EMPTY_net(7), - raddr => open, - wclk => clk, - wen => FIFO_WEN(7), - wdata => DATA_reg, - full => FIFO_FULL_net(7), - waddr => open - ); +END GENERATE; + +--FIFOlp : FOR I IN 0 to 7 GENERATE +--front_fifoN: FIFO_pipeline +--generic map( +-- tech => memtech, +-- fifoCount => 8, +-- Mem_use => 1, --use RAM not CELS +-- DataSz => 16, +-- abits => 10 +-- ) +--port map( +-- rstn => rstn, +-- ReUse => '0', +-- rclk => clk, +-- ren => FIFO_REN, +-- rdata => FIFO_out(I), +-- empty => FIFO_EMPTY_net(I), +-- raddr => open, +-- wclk => clk, +-- wen => FIFO_WEN(I), +-- wdata => DATA_reg, +-- full => FIFO_FULL_net(I), +-- waddr => open +--); +--END GENERATE; + REN_debug <= FIFO_REN; @@ -250,30 +136,42 @@ process(clk,rstn) begin if rstn = '0' then DATA_reg <= (others => '0'); - FIFO_WEN <= (others => '0'); + FIFO_WEN <= (others => '1'); + clk_TRIGER <= clk_TRIGER_MAX; + clk_TRIGER_load <= '0'; elsif clk'event and clk = '1' then if WEN = '0' then DATA_reg <= DATA; - case address is - when "000"=> + case address(3 downto 0) is + when "0000"=> FIFO_WEN <= "11111110"; - when "001"=> + when "0001"=> FIFO_WEN <= "11111101"; - when "010"=> + when "0010"=> FIFO_WEN <= "11111011"; - when "011"=> + when "0011"=> FIFO_WEN <= "11110111"; - when "100"=> + when "0100"=> FIFO_WEN <= "11101111"; - when "101"=> + when "0101"=> FIFO_WEN <= "11011111"; - when "110"=> + when "0110"=> FIFO_WEN <= "10111111"; - when "111"=> + when "0111"=> FIFO_WEN <= "01111111"; when others => FIFO_WEN <= "11111111"; end case; + else + FIFO_WEN <= "11111111"; + end if; + if WEN = '0' then + if address(3 downto 0) = "1000" then + clk_TRIGER <= to_integer(unsigned(DATA)); + clk_TRIGER_load <= '1'; + end if; + else + clk_TRIGER_load <= '0'; end if; end if; end process; @@ -292,9 +190,9 @@ begin FIFO_REN <= '1'; smpclk_reg <= '0'; elsif clk'event and clk = '1' then - smpclk_reg <= smpclk; - if smpclk = '1' and smpclk_reg = '0' then - FIFO_REN <= '0'; + smpclk_reg <= smpclk; + if smpclk = '1' and smpclk_reg = '0' and FIFO_EMPTY_net = X"00" then + FIFO_REN <= '0' ; else FIFO_REN <= '1'; end if; @@ -316,14 +214,29 @@ DAC0 : DAC8581 -smpclk0: Clk_divider - GENERIC map(OSC_freqHz => 150000000, - TargetFreq_Hz => 256000) - PORT map( - clk => clk, - reset => rstn, - clk_divided => smpclk - ); +--smpclk0: Clk_divider +-- GENERIC map(OSC_freqHz => 150000000, +-- TargetFreq_Hz => 256000) +-- PORT map( +-- clk => clk, +-- reset => rstn, +-- clk_divided => smpclk +-- ); + +process(rstn,clk) +begin + if rstn = '0' then + cpt1 <= 0; + smpclk <= '0'; + elsif clk'event and clk = '1' then + if cpt1 = clk_TRIGER or clk_TRIGER_load = '1' then + smpclk <= not smpclk; + cpt1 <= 0; + else + cpt1 <= cpt1 + 1; + end if; + end if; +end process; end Behavioral; diff --git a/lib/lpp/lpp_memory/FIFO_pipeline.vhd b/lib/lpp/lpp_memory/FIFO_pipeline.vhd --- a/lib/lpp/lpp_memory/FIFO_pipeline.vhd +++ b/lib/lpp/lpp_memory/FIFO_pipeline.vhd @@ -71,7 +71,7 @@ fifos : for i in 0 to fifoCount-1 genera Mem_use => Mem_use, Enable_ReUse => '0', DataSz => DataSz, - abits => abits + AddrSz => abits ) port map( rstn => rstn,