# HG changeset patch # User pellion # Date 2013-04-03 11:34:46 # Node ID 0b9053df38a5b397e1416430e36154eb1b05ad6c # Parent 222ef5b6b7cb6d89848e0a9bb4cc806ebf50c3db add MAC + MAC_CONTROLLER diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd --- a/lib/lpp/general_purpose/MAC.vhd +++ b/lib/lpp/general_purpose/MAC.vhd @@ -19,76 +19,68 @@ -- Author : Alexis Jeandet -- Mail : alexis.jeandet@lpp.polytechnique.fr ---------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.general_purpose.ALL; --TODO --terminer le testbensh puis changer le resize dans les instanciations --par un resize sur un vecteur en combi - - - -entity MAC is -generic( - Input_SZ_A : integer := 8; - Input_SZ_B : integer := 8 +ENTITY MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8 -); -port( - clk : in std_logic; - reset : in std_logic; - clr_MAC : in std_logic; - MAC_MUL_ADD : in std_logic_vector(1 downto 0); - OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); - OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); - RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) -); -end MAC; - - - - -architecture ar_MAC of MAC is - + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); +END MAC; -signal add,mult : std_logic; -signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +ARCHITECTURE ar_MAC OF MAC IS -signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal MACMUXsel : std_logic; -signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); -signal MACMUX2sel : std_logic; + SIGNAL MACMUX2sel : STD_LOGIC; -signal add_D : std_logic; -signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0); -signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0); -signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); -signal MACMUXsel_D : std_logic; -signal MACMUX2sel_D : std_logic; -signal MACMUX2sel_D_D : std_logic; -signal clr_MAC_D : std_logic; -signal clr_MAC_D_D : std_logic; + SIGNAL add_D : STD_LOGIC; + SIGNAL OP1_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; - - + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; - -begin +BEGIN @@ -96,15 +88,16 @@ begin --============================================================== --=============M A C C O N T R O L E R========================= --============================================================== -MAC_CONTROLER1 : MAC_CONTROLER -port map( - ctrl => MAC_MUL_ADD, - MULT => mult, - ADD => add, - MACMUX_sel => MACMUXsel, - MACMUX2_sel => MACMUX2sel + MAC_CONTROLER1 : MAC_CONTROLER + PORT MAP( + ctrl => MAC_MUL_ADD, + MULT => mult, + ADD => add, + LOAD_ADDER => load_mult_result, + MACMUX_sel => MACMUXsel, + MACMUX2_sel => MACMUX2sel -); + ); --============================================================== @@ -113,166 +106,157 @@ port map( --============================================================== --=============M U L T I P L I E R============================== --============================================================== -Multiplieri_nst : Multiplier -generic map( - Input_SZ_A => Input_SZ_A, - Input_SZ_B => Input_SZ_B -) -port map( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1, - OP2 => OP2, - RES => MULTout -); - + Multiplieri_nst : Multiplier + GENERIC MAP( + Input_SZ_A => Input_SZ_A, + Input_SZ_B => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1, + OP2 => OP2, + RES => MULTout + ); --============================================================== - - - + PROCESS (clk, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + load_mult_result_D <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + load_mult_result_D <= load_mult_result; + END IF; + END PROCESS; + --============================================================== --======================A D D E R ============================== --============================================================== -adder_inst : Adder -generic map( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B -) -port map( - clk => clk, - reset => reset, - clr => clr_MAC_D, - add => add_D, - OP1 => ADDERinA, - OP2 => ADDERinB, - RES => ADDERout -); - + adder_inst : Adder + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC_D, + load => load_mult_result_D, + add => add_D, + OP1 => ADDERinA, + OP2 => ADDERinB, + RES => ADDERout + ); --============================================================== -clr_MACREG1 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => clr_MAC, - Q(0) => clr_MAC_D -); + clr_MACREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_D + ); -clr_MACREG2 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => clr_MAC_D, - Q(0) => clr_MAC_D_D -); + addREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add, + Q(0) => add_D + ); -addREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => add, - Q(0) => add_D -); + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1, + Q => OP1_D + ); -OP1REG : MAC_REG -generic map(size => Input_SZ_A) -port map( - reset => reset, - clk => clk, - D => OP1, - Q => OP1_D -); - + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2, + Q => OP2_D + ); -OP2REG : MAC_REG -generic map(size => Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => OP2, - Q => OP2_D -); - + MULToutREG : MAC_REG + GENERIC MAP(size => Input_SZ_A+Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => MULTout, + Q => MULTout_D + ); -MULToutREG : MAC_REG -generic map(size => Input_SZ_A+Input_SZ_B) -port map( - reset => reset, - clk => clk, - D => MULTout, - Q => MULTout_D -); - + MACMUXselREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel, + Q(0) => MACMUXsel_D + ); -MACMUXselREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUXsel, - Q(0) => MACMUXsel_D -); + MACMUX2selREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel, + Q(0) => MACMUX2sel_D + ); -MACMUX2selREG : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUX2sel, - Q(0) => MACMUX2sel_D -); - -MACMUX2selREG2 : MAC_REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => MACMUX2sel_D, - Q(0) => MACMUX2sel_D_D -); + MACMUX2selREG2 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D, + Q(0) => MACMUX2sel_D_D + ); --============================================================== --======================M A C M U X =========================== --============================================================== -MACMUX_inst : MAC_MUX -generic map( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B + MACMUX_inst : MAC_MUX + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B -) -port map( - sel => MACMUXsel_D, - INA1 => ADDERout, - INA2 => OP2_D_Resz, - INB1 => MULTout, - INB2 => OP1_D_Resz, - OUTA => ADDERinA, - OUTB => ADDERinB -); -OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B)); -OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B)); + ) + PORT MAP( + sel => MACMUXsel_D, + INA1 => ADDERout, + INA2 => OP2_D_Resz, + INB1 => MULTout, + INB2 => OP1_D_Resz, + OUTA => ADDERinA, + OUTB => ADDERinB + ); + OP1_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_D), Input_SZ_A+Input_SZ_B)); + OP2_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_D), Input_SZ_A+Input_SZ_B)); --============================================================== --============================================================== --======================M A C M U X2 ========================== --============================================================== -MAC_MUX2_inst : MAC_MUX2 -generic map(Input_SZ => Input_SZ_A+Input_SZ_B) -port map( - sel => MACMUX2sel_D_D, - RES2 => MULTout_D, - RES1 => ADDERout, - RES => RES -); - - + MAC_MUX2_inst : MAC_MUX2 + GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) + PORT MAP( + sel => MACMUX2sel_D_D, + RES2 => MULTout_D, + RES1 => ADDERout, + RES => RES + ); --============================================================== -end ar_MAC; +END ar_MAC; diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd --- a/lib/lpp/general_purpose/MAC_CONTROLER.vhd +++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd @@ -34,6 +34,7 @@ port( ctrl : in std_logic_vector(1 downto 0); MULT : out std_logic; ADD : out std_logic; + LOAD_ADDER : out std_logic; MACMUX_sel : out std_logic; MACMUX2_sel : out std_logic @@ -52,8 +53,12 @@ begin MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; -MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; -MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01"or ctrl = "11") else '1'; +LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result + -- to permit to compute a + -- MULT follow by a MAC +--MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; +MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1'; +MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1'; end ar_MAC_CONTROLER;