diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd --- a/lib/lpp/leon3mp.vhd +++ b/lib/lpp/leon3mp.vhd @@ -194,6 +194,8 @@ signal SM_FlagError : std_logic; signal SM_Pong : std_logic; signal SM_Read : std_logic_vector(4 downto 0); signal SM_Write : std_logic_vector(1 downto 0); +signal SM_ReUse : std_logic_vector(4 downto 0); +signal SM_Param : std_logic_vector(3 downto 0); signal SM_Data : std_logic_vector(63 downto 0); signal Dma_acq : std_logic; @@ -211,7 +213,6 @@ signal DEMU_Empty : std_logic_vector(4 signal DEMU_Data : std_logic_vector(79 downto 0); -- ACQ - signal sample_val : STD_LOGIC; signal sample : Samples(8-1 DOWNTO 0); @@ -315,30 +316,29 @@ led(1 downto 0) <= gpio(1 downto 0); -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6)); - DIGITAL_acquisition : ADS7886_drvr - GENERIC MAP ( - ChanelCount => 8, - ncycle_cnv_high => 79, - ncycle_cnv => 500) - PORT MAP ( - cnv_clk => clk50MHz, -- - cnv_rstn => rstn, -- - cnv_run => '1', -- - cnv => CNV_CH1, -- - clk => clkm, -- - rstn => rstn, -- - sck => SCK_CH1, -- - sdo => SDO_CH1, -- - sample => sample, - sample_val => sample_val); +-- DIGITAL_acquisition : ADS7886_drvr +-- GENERIC MAP ( +-- ChanelCount => 8, +-- ncycle_cnv_high => 79, +-- ncycle_cnv => 500) +-- PORT MAP ( +-- cnv_clk => clk50MHz, -- +-- cnv_rstn => rstn, -- +-- cnv_run => '1', -- +-- cnv => CNV_CH1, -- +-- clk => clkm, -- +-- rstn => rstn, -- +-- sck => SCK_CH1, -- +-- sdo => SDO_CH1, -- +-- sample => sample, +-- sample_val => sample_val); -- -TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val; -TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0); +--TopACQ_WenF0 <= not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val & not sample_filter_v2_out_val; +--TopACQ_DataF0 <= E & D & C & B & A; + -- -TEST(0) <= TopACQ_WenF0(1); -TEST(1) <= SDO_CH1(1); --- --- +--TEST(0) <= TopACQ_WenF0(1); +--TEST(1) <= SDO_CH1(1); -- --process(clkm,rstn) --begin @@ -351,18 +351,18 @@ TEST(1) <= SDO_CH1(1); -- end if; --end process; --- TopACQ : lpp_top_acq --- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); + TopACQ : lpp_top_acq + port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); Bias_Fails <= '0'; --- FIFO IN ------------------------------------------------------------- - MemOut : APB_FIFO - generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); --- Memf0 : lppFIFOxN --- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') --- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); +-- MemOut : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); + Memf0 : lppFIFOxN + generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); Memf1 : lppFIFOxN generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') @@ -396,7 +396,7 @@ Bias_Fails <= '0'; MemInt : lppFIFOxN generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') - port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); + port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); -- -- MemIn : APB_FIFO -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) @@ -406,13 +406,13 @@ Bias_Fails <= '0'; SM0 : MatriceSpectrale generic map(Input_SZ => 16,Result_SZ => 32) - port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data); + port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); Dma_acq <= '1'; --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); + MemOut : APB_FIFO + generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); ----- FIFO ------------------------------------------------------------- diff --git a/lib/lpp/lpp_Header/HeaderBuilder.vhd b/lib/lpp/lpp_Header/HeaderBuilder.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_Header/HeaderBuilder.vhd @@ -0,0 +1,110 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity HeaderBuilder is + generic( + Data_sz : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + pong : in std_logic; + Statu : in std_logic_vector(3 downto 0); + Matrix_Type : in std_logic_vector(1 downto 0); + Matrix_Write : in std_logic; + Valid : out std_logic; + + dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); + emptyIN : in std_logic_vector(1 downto 0); + RenOUT : out std_logic_vector(1 downto 0); + + dataOUT : out std_logic_vector(Data_sz-1 downto 0); + emptyOUT : out std_logic; + RenIN : in std_logic; + + header : out std_logic_vector(Data_sz-1 DOWNTO 0); + header_val : out std_logic; + header_ack : in std_logic + ); +end entity; + + +architecture ar_HeaderBuilder of HeaderBuilder is + +signal Matrix_Param : std_logic_vector(3 downto 0); +signal Write_reg : std_logic; +signal Data_cpt : integer; +signal MAX : integer; + + +begin + + process (clkm,rstn) + begin + if(rstn='0')then + Valid <= '0'; + Write_reg <= '0'; + Data_cpt <= 0; + MAX <= 0; + + + elsif(clkm' event and clkm='1')then + Write_reg <= Matrix_Write; + + if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then + MAX <= 128; + else + MAX <= 256; + end if; + + if(Write_reg = '0' and Matrix_Write = '1')then + if(Data_cpt = MAX)then + Data_cpt <= 0; + Valid <= '1'; + header_val <= '1'; + else + Data_cpt <= Data_cpt + 1; + Valid <= '0'; + end if; + end if; + + if(header_ack = '1')then + header_val <= '0'; + end if; + + end if; + end process; + +Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); + +header(1 downto 0) <= Matrix_Type; +header(5 downto 2) <= Matrix_Param; + +dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz); +emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1); + +RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1'; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_Header/lpp_Header.vhd b/lib/lpp/lpp_Header/lpp_Header.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_Header/lpp_Header.vhd @@ -0,0 +1,61 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_Header is + +component HeaderBuilder is + generic( + Data_sz : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + pong : in std_logic; + Statu : in std_logic_vector(3 downto 0); + Matrix_Type : in std_logic_vector(1 downto 0); + Matrix_Write : in std_logic; + Valid : out std_logic; + + dataIN : in std_logic_vector((2*Data_sz)-1 downto 0); + emptyIN : in std_logic_vector(1 downto 0); + RenOUT : out std_logic_vector(1 downto 0); + + dataOUT : out std_logic_vector(Data_sz-1 downto 0); + emptyOUT : out std_logic; + RenIN : in std_logic; + + header : out std_logic_vector(Data_sz-1 DOWNTO 0); + header_val : out std_logic; + header_ack : in std_logic + ); +end component; + +end; \ No newline at end of file diff --git a/lib/lpp/lpp_demux/DEMUX.vhd b/lib/lpp/lpp_demux/DEMUX.vhd --- a/lib/lpp/lpp_demux/DEMUX.vhd +++ b/lib/lpp/lpp_demux/DEMUX.vhd @@ -41,6 +41,7 @@ port( DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + WorkFreq : out std_logic_vector(1 downto 0); Read_DEMUX : out std_logic_vector(14 downto 0); Empty : out std_logic_vector(4 downto 0); Data : out std_logic_vector((5*Data_sz)-1 downto 0) @@ -59,6 +60,7 @@ constant Dummy_Read : std_logic_vector(4 signal Countf0 : integer; signal Countf1 : integer; +signal i : integer; begin process(clk,rstn) @@ -66,8 +68,9 @@ begin if(rstn='0')then ect <= e0; load_reg <= '0'; - Countf0 <= 5; + Countf0 <= 0; Countf1 <= 0; + i <= 0; elsif(clk'event and clk='1')then load_reg <= Load; @@ -92,13 +95,25 @@ begin ect <= e2; else Countf1 <= Countf1 + 1; - ect <= e0; + if(i=4)then + i <= 0; + ect <= e0; + else + i <= i+1; + ect <= e1; + end if; end if; end if; when e2 => if(load_reg = '1' and Load = '0')then - ect <= e0; + if(i=4)then + i <= 0; + ect <= e0; + else + i <= i+1; + ect <= e2; + end if; end if; when others => @@ -126,6 +141,12 @@ with ect select Read & Dummy_Read & Dummy_Read when e2, (others => '1') when others; +with ect select + WorkFreq <= "01" when e0, + "10" when e1, + "11" when e2, + "00" when others; + end architecture; diff --git a/lib/lpp/lpp_demux/lpp_demux.vhd b/lib/lpp/lpp_demux/lpp_demux.vhd --- a/lib/lpp/lpp_demux/lpp_demux.vhd +++ b/lib/lpp/lpp_demux/lpp_demux.vhd @@ -29,7 +29,7 @@ use lpp.lpp_amba.all; --! Package contenant tous les programmes qui forment le composant intégré dans le léon -package lpp_demux is +package lpp_demux is component DEMUX is generic( @@ -49,6 +49,7 @@ port( DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); + WorkFreq : out std_logic_vector(1 downto 0); Read_DEMUX : out std_logic_vector(14 downto 0); Empty : out std_logic_vector(4 downto 0); Data : out std_logic_vector((5*Data_sz)-1 downto 0)