diff --git a/designs/Validation_IIR_f0_LFR/Makefile b/designs/Validation_IIR_f0_LFR/Makefile --- a/designs/Validation_IIR_f0_LFR/Makefile +++ b/designs/Validation_IIR_f0_LFR/Makefile @@ -1,61 +1,61 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=testbench -BOARD=LFR-EQM -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd -VHDLSIMFILES= tb.vhd sig_reader.vhd -SIMTOP=testbench -#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc -BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc opencores - -DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ - ./dsp/lpp_fft_rtax \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./lfr_management \ - ./lpp_sim \ - ./lpp_sim/CY7C1061DV33 \ - ./lpp_cna \ - ./lpp_uart \ - ./lpp_usb \ - ./dsp/lpp_fft \ - ./lpp_leon3_soc \ - ./lpp_debug_lfr - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd \ - lpp_lfr_ms_FFT.vhd \ - lpp_lfr_apbreg.vhd \ - CoreFFT.vhd \ - lpp_lfr_ms.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-EQM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc +SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = axcelerator + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc opencores + +DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \ + ./dsp/lpp_fft_rtax \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lfr_management \ + ./lpp_sim/CY7C1061DV33 \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft \ + ./lpp_leon3_soc \ + ./lpp_debug_lfr + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_ms_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd \ + lpp_lfr_ms.vhd \ + lpp_lfr_sim_pkg.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_IIR_f0_LFR/generator.vhd b/designs/Validation_IIR_f0_LFR/generator.vhd deleted file mode 100644 --- a/designs/Validation_IIR_f0_LFR/generator.vhd +++ /dev/null @@ -1,74 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -use ieee.numeric_std.all; -USE IEEE.std_logic_signed.ALL; -USE IEEE.MATH_real.ALL; - -ENTITY generator IS - - GENERIC ( - AMPLITUDE : INTEGER := 100; - NB_BITS : INTEGER := 16 - ); - - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - run : IN STD_LOGIC; - - data_ack : IN STD_LOGIC; - offset : IN STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); - data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) - ); - -END generator; - -ARCHITECTURE beh OF generator IS - - SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0); -BEGIN -- beh - - PROCESS (clk, rstn) - variable seed1, seed2: positive; -- seed values for random generator - variable rand: real; -- random real-number value in range 0 to 1.0 - BEGIN -- PROCESS - uniform(seed1, seed2, rand);--more entropy by skipping values - IF rstn = '0' THEN -- asynchronous reset (active low) - reg <= (OTHERS => '0'); - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF run = '0' THEN - reg <= (OTHERS => '0'); - ELSE - IF data_ack = '1' THEN - reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS)); - END IF; - END IF; - END IF; - END PROCESS; - - data <= reg; - -END beh; diff --git a/designs/Validation_IIR_f0_LFR/sig_reader.vhd b/designs/Validation_IIR_f0_LFR/sig_reader.vhd deleted file mode 100644 --- a/designs/Validation_IIR_f0_LFR/sig_reader.vhd +++ /dev/null @@ -1,53 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY std; -USE std.textio.ALL; - -LIBRARY lpp; -USE lpp.data_type_pkg.ALL; - -ENTITY sig_reader IS -GENERIC( - FNAME : STRING := "input.txt"; - WIDTH : INTEGER := 1; - RESOLUTION : INTEGER := 8; - GAIN : REAL := 1.0 -); -PORT( - clk : IN std_logic; - end_of_simu : out std_logic; - out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) -); -END sig_reader; - -ARCHITECTURE beh OF sig_reader IS - FILE input_file : TEXT OPEN read_mode IS FNAME; - SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0')); - SIGNAL end_of_simu_reg : std_logic:='0'; -BEGIN - out_signal <= out_signal_reg; - end_of_simu <= end_of_simu_reg; - PROCESS - VARIABLE line_var : LINE; - VARIABLE value : INTEGER; - VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0); - BEGIN - WAIT UNTIL clk = '1'; - IF endfile(input_file) THEN - end_of_simu_reg <= '1'; - ELSE - end_of_simu_reg <= '0'; - readline(input_file,line_var); - FOR COL IN 0 TO WIDTH-1 LOOP - read(line_var, value); - cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION)); - FOR bit_idx IN RESOLUTION-1 downto 0 LOOP - out_signal_reg(COL,bit_idx) <= cell(bit_idx); - END LOOP; - END LOOP; - END IF; - END PROCESS; - -END beh; diff --git a/designs/Validation_IIR_f0_LFR/tb.vhd b/designs/Validation_IIR_f0_LFR/tb.vhd --- a/designs/Validation_IIR_f0_LFR/tb.vhd +++ b/designs/Validation_IIR_f0_LFR/tb.vhd @@ -20,6 +20,7 @@ USE lpp.general_purpose.ALL; USE lpp.data_type_pkg.ALL; USE lpp.lpp_lfr_pkg.ALL; USE lpp.general_purpose.ALL; +USE lpp.lpp_sim_pkg.ALL; ENTITY testbench IS GENERIC( @@ -74,20 +75,20 @@ ARCHITECTURE behav OF testbench IS data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0) ); END COMPONENT; - - COMPONENT sig_reader IS - GENERIC( - FNAME : STRING := "input.txt"; - WIDTH : INTEGER := 1; - RESOLUTION : INTEGER := 8; - GAIN : REAL := 1.0 - ); - PORT( - clk : IN std_logic; - end_of_simu : out std_logic; - out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) - ); - END COMPONENT; + + -- COMPONENT sig_reader IS + -- GENERIC( + -- FNAME : STRING := "input.txt"; + -- WIDTH : INTEGER := 1; + -- RESOLUTION : INTEGER := 8; + -- GAIN : REAL := 1.0 + -- ); + -- PORT( + -- clk : IN std_logic; + -- end_of_simu : out std_logic; + -- out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) + -- ); + -- END COMPONENT; FILE input : TEXT OPEN read_mode IS "input.txt"; @@ -110,7 +111,7 @@ BEGIN WAIT UNTIL clk = '1'; rstn <= '1'; WAIT UNTIL end_of_simu = '1'; - WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; REPORT "*** END simulation ***" SEVERITY failure; WAIT; END PROCESS; @@ -188,8 +189,8 @@ BEGIN sample(i,17) <= signal_gen(i,17); END GENERATE; - - + + ----------------------------------------------------------------------------- -- READ INPUT SIGNALS ----------------------------------------------------------------------------- @@ -206,8 +207,8 @@ BEGIN end_of_simu => end_of_simu, out_signal => signal_gen ); - - + + ----------------------------------------------------------------------------- -- RECORD OUTPUT SIGNALS ----------------------------------------------------------------------------- diff --git a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd --- a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd +++ b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd @@ -32,6 +32,9 @@ USE gaisler.jtagtst.ALL; LIBRARY techmap; USE techmap.gencomp.ALL; +LIBRARY lpp; +USE lpp.data_type_pkg.ALL; + PACKAGE lpp_sim_pkg IS PROCEDURE UART_INIT ( @@ -58,7 +61,19 @@ PACKAGE lpp_sim_pkg IS DATA : OUT STD_LOGIC_VECTOR ); - + COMPONENT sig_reader IS + GENERIC( + FNAME : STRING := "input.txt"; + WIDTH : INTEGER := 1; + RESOLUTION : INTEGER := 8; + GAIN : REAL := 1.0 + ); + PORT( + clk : IN std_logic; + end_of_simu : out std_logic; + out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) + ); + END COMPONENT; END lpp_sim_pkg; PACKAGE BODY lpp_sim_pkg IS diff --git a/lib/lpp/lpp_sim/sig_reader.vhd b/lib/lpp/lpp_sim/sig_reader.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/sig_reader.vhd @@ -0,0 +1,53 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY lpp; +USE lpp.data_type_pkg.ALL; + +ENTITY sig_reader IS +GENERIC( + FNAME : STRING := "input.txt"; + WIDTH : INTEGER := 1; + RESOLUTION : INTEGER := 8; + GAIN : REAL := 1.0 +); +PORT( + clk : IN std_logic; + end_of_simu : out std_logic; + out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0) +); +END sig_reader; + +ARCHITECTURE beh OF sig_reader IS + FILE input_file : TEXT OPEN read_mode IS FNAME; + SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0')); + SIGNAL end_of_simu_reg : std_logic:='0'; +BEGIN + out_signal <= out_signal_reg; + end_of_simu <= end_of_simu_reg; + PROCESS + VARIABLE line_var : LINE; + VARIABLE value : INTEGER; + VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0); + BEGIN + WAIT UNTIL clk = '1'; + IF endfile(input_file) THEN + end_of_simu_reg <= '1'; + ELSE + end_of_simu_reg <= '0'; + readline(input_file,line_var); + FOR COL IN 0 TO WIDTH-1 LOOP + read(line_var, value); + cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION)); + FOR bit_idx IN RESOLUTION-1 downto 0 LOOP + out_signal_reg(COL,bit_idx) <= cell(bit_idx); + END LOOP; + END LOOP; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt --- a/lib/lpp/lpp_sim/vhdlsim.txt +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -1,3 +1,3 @@ +sig_reader.vhd lpp_sim_pkg.vhd lpp_lfr_sim_pkg.vhd -