diff --git a/boards/MiniSpartan6p/Makefile.inc b/boards/MiniSpartan6p/Makefile.inc
--- a/boards/MiniSpartan6p/Makefile.inc
+++ b/boards/MiniSpartan6p/Makefile.inc
@@ -9,3 +9,9 @@ MANUFACTURER=Xilinx
 MGCPART=XC6SLX25$(PACKAGE)
 MGCTECHNOLOGY=SPARTAN-6
 MGCPACKAGE=$(PACKAGE)
+
+config_USB_as_FIFO:
+	ftdi_eeprom --flash-eeprom $(VHDLIB)/boards/$(BOARD)/ft2232h_JTAG_FIFO.conf
+
+config_USB_as_UART:
+	ftdi_eeprom --flash-eeprom $(VHDLIB)/boards/$(BOARD)/ft2232h_JTAG_UART.conf
diff --git a/boards/MiniSpartan6p/bscan_spi_s6lx25_ftg256.bit b/boards/MiniSpartan6p/bscan_spi_s6lx25_ftg256.bit
new file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9eaf918fb99905c1129f7aafb3068c01dc8ea4d4
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diff --git a/boards/MiniSpartan6p/default.ucf b/boards/MiniSpartan6p/default.ucf
--- a/boards/MiniSpartan6p/default.ucf
+++ b/boards/MiniSpartan6p/default.ucf
@@ -1,64 +1,133 @@
 # Clocks
-NET "CLK50" PERIOD = 20 ns | LOC = "K3";
+NET "CLK50" PERIOD = 20 ns |LOC = "K3";
 #NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
-
 # LEDs
-NET "LEDS<0>" LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<1>" LOC="N9"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<2>" LOC="M9"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<3>" LOC="P9"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<4>" LOC="T8"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<5>" LOC="N8"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<6>" LOC="P8"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
-NET "LEDS<7>" LOC="P7"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;
+NET "LEDS<0>" LOC="P11" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<1>" LOC="N9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<2>" LOC="M9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<3>" LOC="P9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<4>" LOC="T8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<5>" LOC="N8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<6>" LOC="P8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<7>" LOC="P7"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
 
 # DIP Switches
-NET "SW<1>"   LOC="L1" | IOSTANDARD=LVTTL | PULLUP;
-NET "SW<2>"   LOC="L3" | IOSTANDARD=LVTTL | PULLUP;
-NET "SW<3>"   LOC="L4" | IOSTANDARD=LVTTL | PULLUP;
-NET "SW<4>"   LOC="L5" | IOSTANDARD=LVTTL | PULLUP;
+NET "SW<1>"   LOC="L1" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<2>"   LOC="L3" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<3>"   LOC="L4" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<4>"   LOC="L5" |IOSTANDARD=LVTTL |PULLUP;
 
-NET "uart_rxd"  LOC="M7" | IOSTANDARD=LVTTL;
-NET "uart_txd"  LOC="N6" | IOSTANDARD=LVTTL;
+NET "uart_rxd"  LOC="M7" |IOSTANDARD=LVTTL;
+NET "uart_txd"  LOC="N6" |IOSTANDARD=LVTTL;
 
 # SDRAM
-NET "dram_udqm"    LOC="F15"   | IOSTANDARD=LVTTL;
-NET "dram_clk" LOC="G16" | IOSTANDARD=LVTTL;
-NET "dram_cke"     LOC="H16"   | IOSTANDARD=LVTTL;
-NET "dram_ba_1"     LOC="T14"   | IOSTANDARD=LVTTL;
-NET "dram_ba_0"     LOC="R14"   | IOSTANDARD=LVTTL;
-NET "dram_cs_n" LOC="R1"  | IOSTANDARD=LVTTL;
-NET "dram_ras_n"    LOC="R2"    | IOSTANDARD=LVTTL;
-NET "dram_cas_n"    LOC="T4"    | IOSTANDARD=LVTTL;
-NET "dram_we_n"     LOC="R5"    | IOSTANDARD=LVTTL;
-NET "dram_ldqm"    LOC="T5"    | IOSTANDARD=LVTTL;
-NET "dram_addr<0>"    LOC="T15"   | IOSTANDARD=LVTTL;
-NET "dram_addr<1>"    LOC="R16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<2>"    LOC="P15"   | IOSTANDARD=LVTTL;
-NET "dram_addr<3>"    LOC="P16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<4>"    LOC="N16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<5>"    LOC="M15"   | IOSTANDARD=LVTTL;
-NET "dram_addr<6>"    LOC="M16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<7>"    LOC="L16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<8>"    LOC="K15"   | IOSTANDARD=LVTTL;
-NET "dram_addr<9>"    LOC="K16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<10>"   LOC="R15"   | IOSTANDARD=LVTTL;
-NET "dram_addr<11>"   LOC="J16"   | IOSTANDARD=LVTTL;
-NET "dram_addr<12>"   LOC="H15"   | IOSTANDARD=LVTTL;
-NET "dram_dq<0>"    LOC="T13"   | IOSTANDARD=LVTTL;
-NET "dram_dq<1>"    LOC="T12"   | IOSTANDARD=LVTTL;
-NET "dram_dq<2>"    LOC="R12"   | IOSTANDARD=LVTTL;
-NET "dram_dq<3>"    LOC="T9"    | IOSTANDARD=LVTTL;
-NET "dram_dq<4>"    LOC="R9"    | IOSTANDARD=LVTTL;
-NET "dram_dq<5>"    LOC="T7"    | IOSTANDARD=LVTTL;
-NET "dram_dq<6>"    LOC="R7"    | IOSTANDARD=LVTTL;
-NET "dram_dq<7>"    LOC="T6"    | IOSTANDARD=LVTTL;
-NET "dram_dq<8>"    LOC="F16"   | IOSTANDARD=LVTTL;
-NET "dram_dq<9>"    LOC="E15"   | IOSTANDARD=LVTTL;
-NET "dram_dq<10>"   LOC="E16"   | IOSTANDARD=LVTTL;
-NET "dram_dq<11>"   LOC="D16"   | IOSTANDARD=LVTTL;
-NET "dram_dq<12>"   LOC="B16"   | IOSTANDARD=LVTTL;
-NET "dram_dq<13>"   LOC="B15"   | IOSTANDARD=LVTTL;
-NET "dram_dq<14>"   LOC="C16"   | IOSTANDARD=LVTTL;
-NET "dram_dq<15>"   LOC="C15"   | IOSTANDARD=LVTTL;
-
+NET "dram_udqm"    LOC="F15"   |IOSTANDARD=LVTTL;
+NET "dram_clk" LOC="G16" |IOSTANDARD=LVTTL;
+NET "dram_cke"     LOC="H16"   |IOSTANDARD=LVTTL;
+NET "dram_ba_1"     LOC="T14"   |IOSTANDARD=LVTTL;
+NET "dram_ba_0"     LOC="R14"   |IOSTANDARD=LVTTL;
+NET "dram_cs_n" LOC="R1"  |IOSTANDARD=LVTTL;
+NET "dram_ras_n"    LOC="R2"    |IOSTANDARD=LVTTL;
+NET "dram_cas_n"    LOC="T4"    |IOSTANDARD=LVTTL;
+NET "dram_we_n"     LOC="R5"    |IOSTANDARD=LVTTL;
+NET "dram_ldqm"    LOC="T5"    |IOSTANDARD=LVTTL;
+NET "dram_addr<0>"    LOC="T15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<1>"    LOC="R16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<2>"    LOC="P15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<3>"    LOC="P16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<4>"    LOC="N16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<5>"    LOC="M15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<6>"    LOC="M16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<7>"    LOC="L16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<8>"    LOC="K15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<9>"    LOC="K16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<10>"   LOC="R15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<11>"   LOC="J16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<12>"   LOC="H15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<0>"    LOC="T13"   |IOSTANDARD=LVTTL;
+NET "dram_dq<1>"    LOC="T12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<2>"    LOC="R12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<3>"    LOC="T9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<4>"    LOC="R9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<5>"    LOC="T7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<6>"    LOC="R7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<7>"    LOC="T6"    |IOSTANDARD=LVTTL;
+NET "dram_dq<8>"    LOC="F16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<9>"    LOC="E15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<10>"   LOC="E16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<11>"   LOC="D16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<12>"   LOC="B16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<13>"   LOC="B15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<14>"   LOC="C16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<15>"   LOC="C15"   |IOSTANDARD=LVTTL;
+#Created by Constraints Editor (xc6slx25-ftg256-3) - 2016/12/08
+INST "dram_addr(0)" TNM = dram_addr;
+INST "dram_addr(1)" TNM = dram_addr;
+INST "dram_addr(2)" TNM = dram_addr;
+INST "dram_addr(3)" TNM = dram_addr;
+INST "dram_addr(4)" TNM = dram_addr;
+INST "dram_addr(5)" TNM = dram_addr;
+INST "dram_addr(6)" TNM = dram_addr;
+INST "dram_addr(7)" TNM = dram_addr;
+INST "dram_addr(8)" TNM = dram_addr;
+INST "dram_addr(9)" TNM = dram_addr;
+INST "dram_addr(10)" TNM = dram_addr;
+INST "dram_addr(11)" TNM = dram_addr;
+INST "dram_addr(12)" TNM = dram_addr;
+INST "dram_addr(0)" TNM = dram_out;
+INST "dram_addr(1)" TNM = dram_out;
+INST "dram_addr(2)" TNM = dram_out;
+INST "dram_addr(3)" TNM = dram_out;
+INST "dram_addr(4)" TNM = dram_out;
+INST "dram_addr(5)" TNM = dram_out;
+INST "dram_addr(6)" TNM = dram_out;
+INST "dram_addr(7)" TNM = dram_out;
+INST "dram_addr(8)" TNM = dram_out;
+INST "dram_addr(9)" TNM = dram_out;
+INST "dram_addr(10)" TNM = dram_out;
+INST "dram_addr(11)" TNM = dram_out;
+INST "dram_addr(12)" TNM = dram_out;
+INST "dram_ba_0" TNM = dram_out;
+INST "dram_ba_1" TNM = dram_out;
+INST "dram_cas_n" TNM = dram_out;
+INST "dram_cke" TNM = dram_out;
+#INST "dram_clk" TNM = dram_out;
+INST "dram_cs_n" TNM = dram_out;
+INST "dram_dq(0)" TNM = dram_out;
+INST "dram_dq(1)" TNM = dram_out;
+INST "dram_dq(2)" TNM = dram_out;
+INST "dram_dq(3)" TNM = dram_out;
+INST "dram_dq(4)" TNM = dram_out;
+INST "dram_dq(5)" TNM = dram_out;
+INST "dram_dq(6)" TNM = dram_out;
+INST "dram_dq(7)" TNM = dram_out;
+INST "dram_dq(8)" TNM = dram_out;
+INST "dram_dq(9)" TNM = dram_out;
+INST "dram_dq(10)" TNM = dram_out;
+INST "dram_dq(11)" TNM = dram_out;
+INST "dram_dq(12)" TNM = dram_out;
+INST "dram_dq(13)" TNM = dram_out;
+INST "dram_dq(14)" TNM = dram_out;
+INST "dram_dq(15)" TNM = dram_out;
+INST "dram_ldqm" TNM = dram_out;
+INST "dram_ras_n" TNM = dram_out;
+INST "dram_udqm" TNM = dram_out;
+INST "dram_we_n" TNM = dram_out;
+TIMEGRP "dram_out" OFFSET = OUT 12 ns AFTER "CLK50";
+INST "dram_dq(0)" TNM = dram_in;
+INST "dram_dq(1)" TNM = dram_in;
+INST "dram_dq(2)" TNM = dram_in;
+INST "dram_dq(3)" TNM = dram_in;
+INST "dram_dq(4)" TNM = dram_in;
+INST "dram_dq(5)" TNM = dram_in;
+INST "dram_dq(6)" TNM = dram_in;
+INST "dram_dq(7)" TNM = dram_in;
+INST "dram_dq(8)" TNM = dram_in;
+INST "dram_dq(9)" TNM = dram_in;
+INST "dram_dq(10)" TNM = dram_in;
+INST "dram_dq(11)" TNM = dram_in;
+INST "dram_dq(12)" TNM = dram_in;
+INST "dram_dq(13)" TNM = dram_in;
+INST "dram_dq(14)" TNM = dram_in;
+INST "dram_dq(15)" TNM = dram_in;
+TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE "CLK50" RISING;
diff --git a/boards/MiniSpartan6p/ft2232h_JTAG_FIFO.conf b/boards/MiniSpartan6p/ft2232h_JTAG_FIFO.conf
new file mode 100644
--- /dev/null
+++ b/boards/MiniSpartan6p/ft2232h_JTAG_FIFO.conf
@@ -0,0 +1,15 @@
+vendor_id=0x0403        # Vendor ID
+product_id=0x6010       # Product ID
+self_powered=false
+remote_wakeup=false
+max_power=0
+in_is_isochronous=false
+out_is_isochronous=false
+suspend_pull_downs=false
+use_serial=false
+change_usb_version=false
+usb_version=0
+manufacturer="LPP"
+product="LPP USB SPW Brick"
+serial=""
+chb_type=FIFO
diff --git a/boards/MiniSpartan6p/ft2232h_JTAG_UART.conf b/boards/MiniSpartan6p/ft2232h_JTAG_UART.conf
new file mode 100644
--- /dev/null
+++ b/boards/MiniSpartan6p/ft2232h_JTAG_UART.conf
@@ -0,0 +1,15 @@
+vendor_id=0x0403        # Vendor ID
+product_id=0x6010       # Product ID
+self_powered=false
+remote_wakeup=false
+max_power=0
+in_is_isochronous=false
+out_is_isochronous=false
+suspend_pull_downs=false
+use_serial=false
+change_usb_version=false
+usb_version=0
+manufacturer="LPP"
+product="LPP USB SPW Brick"
+serial=""
+chb_type=UART
diff --git a/boards/MiniSpartan6p/with-fifo.ucf b/boards/MiniSpartan6p/with-fifo.ucf
new file mode 100644
--- /dev/null
+++ b/boards/MiniSpartan6p/with-fifo.ucf
@@ -0,0 +1,145 @@
+# Clocks
+NET "CLK50" PERIOD = 20 ns |LOC = "K3";
+#NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
+# LEDs
+NET "LEDS<0>" LOC="P11" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<1>" LOC="N9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<2>" LOC="M9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<3>" LOC="P9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<4>" LOC="T8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<5>" LOC="N8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<6>" LOC="P8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<7>" LOC="P7"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+
+# DIP Switches
+NET "SW<1>"   LOC="L1" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<2>"   LOC="L3" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<3>"   LOC="L4" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<4>"   LOC="L5" |IOSTANDARD=LVTTL |PULLUP;
+
+# SDRAM
+NET "dram_udqm"    LOC="F15"   |IOSTANDARD=LVTTL;
+NET "dram_clk" LOC="G16" |IOSTANDARD=LVTTL;
+NET "dram_cke"     LOC="H16"   |IOSTANDARD=LVTTL;
+NET "dram_ba_1"     LOC="T14"   |IOSTANDARD=LVTTL;
+NET "dram_ba_0"     LOC="R14"   |IOSTANDARD=LVTTL;
+NET "dram_cs_n" LOC="R1"  |IOSTANDARD=LVTTL;
+NET "dram_ras_n"    LOC="R2"    |IOSTANDARD=LVTTL;
+NET "dram_cas_n"    LOC="T4"    |IOSTANDARD=LVTTL;
+NET "dram_we_n"     LOC="R5"    |IOSTANDARD=LVTTL;
+NET "dram_ldqm"    LOC="T5"    |IOSTANDARD=LVTTL;
+NET "dram_addr<0>"    LOC="T15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<1>"    LOC="R16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<2>"    LOC="P15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<3>"    LOC="P16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<4>"    LOC="N16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<5>"    LOC="M15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<6>"    LOC="M16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<7>"    LOC="L16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<8>"    LOC="K15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<9>"    LOC="K16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<10>"   LOC="R15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<11>"   LOC="J16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<12>"   LOC="H15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<0>"    LOC="T13"   |IOSTANDARD=LVTTL;
+NET "dram_dq<1>"    LOC="T12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<2>"    LOC="R12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<3>"    LOC="T9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<4>"    LOC="R9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<5>"    LOC="T7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<6>"    LOC="R7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<7>"    LOC="T6"    |IOSTANDARD=LVTTL;
+NET "dram_dq<8>"    LOC="F16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<9>"    LOC="E15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<10>"   LOC="E16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<11>"   LOC="D16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<12>"   LOC="B16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<13>"   LOC="B15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<14>"   LOC="C16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<15>"   LOC="C15"   |IOSTANDARD=LVTTL;
+#Created by Constraints Editor (xc6slx25-ftg256-3) - 2016/12/08
+INST "dram_addr(0)" TNM = dram_addr;
+INST "dram_addr(1)" TNM = dram_addr;
+INST "dram_addr(2)" TNM = dram_addr;
+INST "dram_addr(3)" TNM = dram_addr;
+INST "dram_addr(4)" TNM = dram_addr;
+INST "dram_addr(5)" TNM = dram_addr;
+INST "dram_addr(6)" TNM = dram_addr;
+INST "dram_addr(7)" TNM = dram_addr;
+INST "dram_addr(8)" TNM = dram_addr;
+INST "dram_addr(9)" TNM = dram_addr;
+INST "dram_addr(10)" TNM = dram_addr;
+INST "dram_addr(11)" TNM = dram_addr;
+INST "dram_addr(12)" TNM = dram_addr;
+INST "dram_addr(0)" TNM = dram_out;
+INST "dram_addr(1)" TNM = dram_out;
+INST "dram_addr(2)" TNM = dram_out;
+INST "dram_addr(3)" TNM = dram_out;
+INST "dram_addr(4)" TNM = dram_out;
+INST "dram_addr(5)" TNM = dram_out;
+INST "dram_addr(6)" TNM = dram_out;
+INST "dram_addr(7)" TNM = dram_out;
+INST "dram_addr(8)" TNM = dram_out;
+INST "dram_addr(9)" TNM = dram_out;
+INST "dram_addr(10)" TNM = dram_out;
+INST "dram_addr(11)" TNM = dram_out;
+INST "dram_addr(12)" TNM = dram_out;
+INST "dram_ba_0" TNM = dram_out;
+INST "dram_ba_1" TNM = dram_out;
+INST "dram_cas_n" TNM = dram_out;
+INST "dram_cke" TNM = dram_out;
+#INST "dram_clk" TNM = dram_out;
+INST "dram_cs_n" TNM = dram_out;
+INST "dram_dq(0)" TNM = dram_out;
+INST "dram_dq(1)" TNM = dram_out;
+INST "dram_dq(2)" TNM = dram_out;
+INST "dram_dq(3)" TNM = dram_out;
+INST "dram_dq(4)" TNM = dram_out;
+INST "dram_dq(5)" TNM = dram_out;
+INST "dram_dq(6)" TNM = dram_out;
+INST "dram_dq(7)" TNM = dram_out;
+INST "dram_dq(8)" TNM = dram_out;
+INST "dram_dq(9)" TNM = dram_out;
+INST "dram_dq(10)" TNM = dram_out;
+INST "dram_dq(11)" TNM = dram_out;
+INST "dram_dq(12)" TNM = dram_out;
+INST "dram_dq(13)" TNM = dram_out;
+INST "dram_dq(14)" TNM = dram_out;
+INST "dram_dq(15)" TNM = dram_out;
+INST "dram_ldqm" TNM = dram_out;
+INST "dram_ras_n" TNM = dram_out;
+INST "dram_udqm" TNM = dram_out;
+INST "dram_we_n" TNM = dram_out;
+TIMEGRP "dram_out" OFFSET = OUT 12 ns AFTER "CLK50";
+INST "dram_dq(0)" TNM = dram_in;
+INST "dram_dq(1)" TNM = dram_in;
+INST "dram_dq(2)" TNM = dram_in;
+INST "dram_dq(3)" TNM = dram_in;
+INST "dram_dq(4)" TNM = dram_in;
+INST "dram_dq(5)" TNM = dram_in;
+INST "dram_dq(6)" TNM = dram_in;
+INST "dram_dq(7)" TNM = dram_in;
+INST "dram_dq(8)" TNM = dram_in;
+INST "dram_dq(9)" TNM = dram_in;
+INST "dram_dq(10)" TNM = dram_in;
+INST "dram_dq(11)" TNM = dram_in;
+INST "dram_dq(12)" TNM = dram_in;
+INST "dram_dq(13)" TNM = dram_in;
+INST "dram_dq(14)" TNM = dram_in;
+INST "dram_dq(15)" TNM = dram_in;
+TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE "CLK50" RISING;
+
+# FTDI
+NET "FTDI_RXF"   LOC="N3" | IOSTANDARD=LVTTL;
+NET "FTDI_TXE"   LOC="N1" | IOSTANDARD=LVTTL;
+NET "FTDI_SIWUA" LOC="M3" | IOSTANDARD=LVTTL;
+NET "FTDI_WR"    LOC="M2" | IOSTANDARD=LVTTL;
+NET "FTDI_RD"    LOC="M1" | IOSTANDARD=LVTTL;
+NET "FTDI_D<0>"  LOC="M7" | IOSTANDARD=LVTTL;
+NET "FTDI_D<1>"  LOC="N6" | IOSTANDARD=LVTTL;
+NET "FTDI_D<2>"  LOC="M6" | IOSTANDARD=LVTTL;
+NET "FTDI_D<3>"  LOC="P5" | IOSTANDARD=LVTTL;
+NET "FTDI_D<4>"  LOC="N5" | IOSTANDARD=LVTTL;
+NET "FTDI_D<5>"  LOC="P4" | IOSTANDARD=LVTTL;
+NET "FTDI_D<6>"  LOC="P2" | IOSTANDARD=LVTTL;
+NET "FTDI_D<7>" LOC="P1" | IOSTANDARD=LVTTL;
diff --git a/designs/Leon3-MiniSpartan6p/Makefile b/designs/Leon3-MiniSpartan6p/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/Makefile
@@ -0,0 +1,77 @@
+VHDLIB=../..
+SELFDIR := $(dir $(lastword $(MAKEFILE_LIST)))
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=leon3mp
+BOARD=MiniSpartan6p
+DESIGN=leon3-MiniSpartan6p
+include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+#UCF=$(VHDLIB)/boards/$(BOARD)/default.ucf
+UCF=$(VHDLIB)/boards/$(BOARD)/with-fifo.ucf
+UCF_PLANAHEAD=$(UCF)
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+XSTOPT=-uc leon3mp.xcf
+SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
+
+
+VHDLOPTSYNFILES = sdctrl16.vhd config.vhd leon3mp.vhd
+
+VHDLSIMFILES=mt48lc16m16a2.vhd testbench.vhd
+
+SIMTOP=testbench
+SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
+
+TECHLIBS = unisim
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann  usbhc  opencores fmf ftlib gsi
+
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs can pwm greth coremp7 ac97 atf \
+	grlfpc \
+	./dsp/lpp_fft_rtax \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lpp_sim/CY7C1061DV33 \
+	./lpp_uart \
+	./dsp/lpp_fft \
+	./lpp_leon3_soc \
+	./lpp_debug_lfr
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd \
+	lpp_lfr_ms_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd \
+	lpp_lfr_ms.vhd \
+	lpp_lfr_sim_pkg.vhd \
+	mtie_maps.vhd \
+	ftsrctrlc.vhd \
+	ftsdctrl.vhd \
+	ftsrctrl8.vhd \
+	ftmctrl.vhd \
+	ftsdctrl64.vhd \
+	ftahbram.vhd \
+	ftahbram2.vhd \
+	sramft.vhd \
+	nandfctrlx.vhd
+
+include $(GRLIB)/bin/Makefile
+
+##################  project specific targets ##########################
+
+load-ram:
+	xc3sprog -c ftdi -p0 leon3mp.bit
+
+load-flash:
+	xc3sprog -c ftdi -p0 $(VHDLIB)/boards/$(BOARD)/bscan_spi_s6lx25_ftg256.bit
+	xc3sprog -c ftdi -I leon3mp.bit
diff --git a/designs/Leon3-MiniSpartan6p/README.md b/designs/Leon3-MiniSpartan6p/README.md
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/README.md
@@ -0,0 +1,66 @@
+This LEON3 design is tailored to the Scarab Hardware [MiniSpartan6+](https://www.scarabhardware.com/minispartan6/) board.
+
+Simulation and synthesis
+------------------------
+
+This design tries to use as much as possible free (as in freedom) tools and at least free (as in free beer) when impossible.
+
+
+Note that the simulation doesn't work as expected yet.
+
+
+To build the design:
+```bash
+make ise
+```
+
+To load into FPGA RAM:
+```bash
+make load-ram
+```
+
+To load into FPGA Flash:
+```bash
+make load-flash
+```
+
+Design specifics
+----------------
+
+* The AHB and processor is clocked from the 50 MHz clock.
+
+* The SDRAM is working with the sdctrl16 memory controller taken from leon3-altera-de2-ep2c35 design.
+
+* The UART DSU interface ie enabled and connected to interface B of ft2232H chip.
+  Start GRMON with -uart /dev/ttyUSB1
+
+* Output from GRMON2 should look similar to this:
+
+```bash
+  GRMON2 LEON debug monitor v2.0.80-beta 64-bit eval version
+  
+  Copyright (C) 2016 Cobham Gaisler - All rights reserved.
+  For latest updates, go to http://www.gaisler.com/
+  Comments or bug-reports to support@gaisler.com
+  
+  This eval version will expire on 18/04/2017
+
+  using port /dev/ttyUSB1 @ 115200 baud
+  GRLIB build version: 4164
+  Detected frequency:  50 MHz
+  
+  Component                            Vendor
+  LEON3 SPARC V8 Processor             Cobham Gaisler
+  AHB Debug UART                       Cobham Gaisler
+  AHB/APB Bridge                       Cobham Gaisler
+  LEON3 Debug Support Unit             Cobham Gaisler
+  PC133 SDRAM Controller               Cobham Gaisler
+  Multi-processor Interrupt Ctrl.      Cobham Gaisler
+  Modular Timer Unit                   Cobham Gaisler
+  General Purpose I/O port             Cobham Gaisler
+  
+  Use command 'info sys' to print a detailed report of attached cores
+
+grmon2> 
+
+```
\ No newline at end of file
diff --git a/designs/Leon3-MiniSpartan6p/config.vhd b/designs/Leon3-MiniSpartan6p/config.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/config.vhd
@@ -0,0 +1,166 @@
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+-- Technology and synthesis options
+  constant CFG_FABTECH : integer := spartan6;
+  constant CFG_MEMTECH : integer := spartan6;
+  constant CFG_PADTECH : integer := spartan6;
+  constant CFG_TRANSTECH : integer := GTP0;
+  constant CFG_NOASYNC : integer := 0;
+  constant CFG_SCAN : integer := 0;
+-- Clock generator
+  constant CFG_CLKTECH : integer := spartan6;
+  constant CFG_CLKMUL : integer := (3);
+  constant CFG_CLKDIV : integer := (2);
+  constant CFG_OCLKDIV : integer := 1;
+  constant CFG_OCLKBDIV : integer := 0;
+  constant CFG_OCLKCDIV : integer := 0;
+  constant CFG_PCIDLL : integer := 0;
+  constant CFG_PCISYSCLK: integer := 0;
+  constant CFG_CLK_NOFB : integer := 0;
+-- LEON3 processor core
+  constant CFG_LEON3 : integer := 1;
+  constant CFG_NCPU : integer := (1);
+  constant CFG_NWIN : integer := (8);
+  constant CFG_V8 : integer := 2 + 4*0;
+  constant CFG_MAC : integer := 0;
+  constant CFG_BP : integer := 1;
+  constant CFG_SVT : integer := 1;
+  constant CFG_RSTADDR : integer := 16#00000#;
+  constant CFG_LDDEL : integer := (2);
+  constant CFG_NOTAG : integer := 1;
+  constant CFG_NWP : integer := (0);
+  constant CFG_PWD : integer := 0*2;
+  constant CFG_FPU : integer := 0 + 16*0 + 32*0;
+  constant CFG_GRFPUSH : integer := 0;
+  constant CFG_ICEN : integer := 1;
+  constant CFG_ISETS : integer := 1;
+  constant CFG_ISETSZ : integer := 8;
+  constant CFG_ILINE : integer := 8;
+  constant CFG_IREPL : integer := 0;
+  constant CFG_ILOCK : integer := 0;
+  constant CFG_ILRAMEN : integer := 0;
+  constant CFG_ILRAMADDR: integer := 16#8E#;
+  constant CFG_ILRAMSZ : integer := 1;
+  constant CFG_DCEN : integer := 1;
+  constant CFG_DSETS : integer := 1;
+  constant CFG_DSETSZ : integer := 8;
+  constant CFG_DLINE : integer := 8;
+  constant CFG_DREPL : integer := 0;
+  constant CFG_DLOCK : integer := 0;
+  constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
+  constant CFG_DFIXED : integer := 16#0#;
+  constant CFG_DLRAMEN : integer := 0;
+  constant CFG_DLRAMADDR: integer := 16#8F#;
+  constant CFG_DLRAMSZ : integer := 1;
+  constant CFG_MMUEN : integer := 0;
+  constant CFG_ITLBNUM : integer := 8;
+  constant CFG_DTLBNUM : integer := 2;
+  constant CFG_TLB_TYPE : integer := 1 + 0*2;
+  constant CFG_TLB_REP : integer := 1;
+  constant CFG_MMU_PAGE : integer := 0;
+  constant CFG_DSU : integer := 1;
+  constant CFG_ITBSZ : integer := 0 + 64*0;
+  constant CFG_ATBSZ : integer := 0;
+  constant CFG_AHBPF : integer := 0;
+  constant CFG_LEON3FT_EN : integer := 0;
+  constant CFG_IUFT_EN : integer := 0;
+  constant CFG_FPUFT_EN : integer := 0;
+  constant CFG_RF_ERRINJ : integer := 0;
+  constant CFG_CACHE_FT_EN : integer := 0;
+  constant CFG_CACHE_ERRINJ : integer := 0;
+  constant CFG_LEON3_NETLIST: integer := 0;
+  constant CFG_DISAS : integer := 0 + 0;
+  constant CFG_PCLOW : integer := 2;
+  constant CFG_STAT_ENABLE : integer := 0;
+  constant CFG_STAT_CNT : integer := 1;
+  constant CFG_STAT_NMAX : integer := 0;
+  constant CFG_STAT_DSUEN : integer := 0;
+  constant CFG_NP_ASI : integer := 0;
+  constant CFG_WRPSR : integer := 0;
+  constant CFG_ALTWIN : integer := 0;
+  constant CFG_REX : integer := 0;
+-- AMBA settings
+  constant CFG_DEFMST : integer := (0);
+  constant CFG_RROBIN : integer := 1;
+  constant CFG_SPLIT : integer := 1;
+  constant CFG_FPNPEN : integer := 0;
+  constant CFG_AHBIO : integer := 16#FFF#;
+  constant CFG_APBADDR : integer := 16#800#;
+  constant CFG_AHB_MON : integer := 0;
+  constant CFG_AHB_MONERR : integer := 0;
+  constant CFG_AHB_MONWAR : integer := 0;
+  constant CFG_AHB_DTRACE : integer := 0;
+-- DSU UART
+  constant CFG_AHB_UART : integer := 0;
+-- JTAG based DSU interface
+  constant CFG_AHB_JTAG : integer := 1;
+-- Xilinx MIG
+  constant CFG_MIG_DDR2 : integer := 1;
+  constant CFG_MIG_RANKS : integer := (1);
+  constant CFG_MIG_COLBITS : integer := (10);
+  constant CFG_MIG_ROWBITS : integer := (13);
+  constant CFG_MIG_BANKBITS: integer := (2);
+  constant CFG_MIG_HMASK : integer := 16#FC0#;
+-- AHB ROM
+  constant CFG_AHBROMEN : integer := 1;
+  constant CFG_AHBROPIP : integer := 0;
+  constant CFG_AHBRODDR : integer := 16#000#;
+  constant CFG_ROMADDR : integer := 16#100#;
+  constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
+-- AHB RAM
+  constant CFG_AHBRAMEN : integer := 1;
+  constant CFG_AHBRSZ : integer := 4;
+  constant CFG_AHBRADDR : integer := 16#A00#;
+  constant CFG_AHBRPIPE : integer := 0;
+-- UART 1
+  constant CFG_UART1_ENABLE : integer := 1;
+  constant CFG_UART1_FIFO : integer := 4;
+-- LEON3 interrupt controller
+  constant CFG_IRQ3_ENABLE : integer := 1;
+  constant CFG_IRQ3_NSEC : integer := 0;
+-- Modular timer
+  constant CFG_GPT_ENABLE : integer := 1;
+  constant CFG_GPT_NTIM : integer := (2);
+  constant CFG_GPT_SW : integer := (8);
+  constant CFG_GPT_TW : integer := (32);
+  constant CFG_GPT_IRQ : integer := (8);
+  constant CFG_GPT_SEPIRQ : integer := 1;
+  constant CFG_GPT_WDOGEN : integer := 0;
+  constant CFG_GPT_WDOG : integer := 16#0#;
+-- GPIO port
+  constant CFG_GRGPIO_ENABLE : integer := 0;
+  constant CFG_GRGPIO_IMASK : integer := 16#0000#;
+  constant CFG_GRGPIO_WIDTH : integer := 1;
+
+-- SPI controller
+  constant CFG_SPICTRL_ENABLE : integer := 1;
+  constant CFG_SPICTRL_NUM : integer := (1);
+  constant CFG_SPICTRL_SLVS : integer := (1);
+  constant CFG_SPICTRL_FIFO : integer := (2);
+  constant CFG_SPICTRL_SLVREG : integer := 1;
+  constant CFG_SPICTRL_ODMODE : integer := 1;
+  constant CFG_SPICTRL_AM : integer := 0;
+  constant CFG_SPICTRL_ASEL : integer := 0;
+  constant CFG_SPICTRL_TWEN : integer := 0;
+  constant CFG_SPICTRL_MAXWLEN : integer := (0);
+  constant CFG_SPICTRL_SYNCRAM : integer := 0;
+  constant CFG_SPICTRL_FT : integer := 0;
+
+-- GRLIB debugging
+  constant CFG_DUART : integer := 0;
+
+
+  constant CFG_AHB_FTDI : integer := 1;
+  constant CFG_FTDI_LOOPBACK : integer := 0;
+end;
diff --git a/designs/Leon3-MiniSpartan6p/leon3mp.vhd b/designs/Leon3-MiniSpartan6p/leon3mp.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/leon3mp.vhd
@@ -0,0 +1,340 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.NUMERIC_STD.ALL;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library techmap;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+use gaisler.jtag.all;
+--pragma translate_off
+use gaisler.sim.all;
+--pragma translate_on
+library lpp;
+use lpp.lpp_usb.all;
+
+use work.config.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity leon3mp is
+  generic (
+    fabtech  : integer := CFG_FABTECH;
+    memtech  : integer := CFG_MEMTECH;
+    padtech  : integer := CFG_PADTECH;
+    clktech  : integer := CFG_CLKTECH;
+    disas    : integer := CFG_DISAS;     -- Enable disassembly to console
+    dbguart  : integer := CFG_DUART;     -- Print UART on console
+    pclow    : integer := CFG_PCLOW
+    );
+  port (
+    CLK50  : in std_logic;
+    LEDS   : inout std_logic_vector(7 downto 0);
+    SW     : in std_logic_vector(4 downto 1);
+    dram_addr : out std_logic_vector(12 downto 0);
+    dram_ba_0	: out std_logic;
+    dram_ba_1	: out std_logic;
+    dram_dq	: inout std_logic_vector(15 downto 0);
+
+    dram_clk  	: out std_logic;
+    dram_cke  	: out std_logic;
+    dram_cs_n  	: out std_logic;
+    dram_we_n  	: out std_logic;        	-- sdram write enable
+    dram_ras_n  : out std_logic;               	-- sdram ras
+    dram_cas_n  : out std_logic;               	-- sdram cas
+    dram_ldqm	  : out std_logic;		-- sdram ldqm
+    dram_udqm	  : out std_logic;		-- sdram udqm
+    uart_txd  	: out std_logic;		-- DSU tx data
+    uart_rxd  	: in  std_logic;		-- DSU rx data
+
+    FTDI_RXF    : in  std_logic;
+    FTDI_TXE    : in  std_logic;
+    FTDI_SIWUA  : out std_logic;
+    FTDI_WR     : out std_logic;
+    FTDI_RD     : out std_logic;
+    FTDI_D      : inout std_logic_vector(7 downto 0)
+
+    );
+end;
+
+architecture rtl of leon3mp is
+  signal resetn : std_logic;
+  signal clkm, rstn, rstraw, rst : std_logic;
+  signal clkm_inv : std_logic := '0';
+
+  signal cptr :  std_logic_vector(29 downto 0);
+  constant BOARD_FREQ : integer := 25000;                                -- CLK input frequency in KHz
+  constant CPU_FREQ   : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
+  signal sdi   : sdctrl_in_type;
+  signal sdo   : sdctrl_out_type;
+
+--AMBA bus standard interface signals--
+  signal apbi  : apb_slv_in_type;
+  signal apbo  : apb_slv_out_vector := (others => apb_none);
+  signal ahbsi : ahb_slv_in_type;
+  signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+  signal ahbmi : ahb_mst_in_type;
+  signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+  signal tck, tckn, tms, tdi, tdo : std_ulogic;
+
+  signal cgi : clkgen_in_type;
+  signal cgo : clkgen_out_type;
+
+  signal dui : uart_in_type;
+  signal duo : uart_out_type;
+
+  signal irqi : irq_in_vector(0 to CFG_NCPU-1);
+  signal irqo : irq_out_vector(0 to CFG_NCPU-1);
+
+  signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
+  signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
+
+  signal dsui : dsu_in_type;
+  signal dsuo : dsu_out_type;
+
+
+  signal gpti : gptimer_in_type;
+
+  signal gpioi_0 : gpio_in_type;
+  signal gpioo_0 : gpio_out_type;
+
+  signal dsubren : std_logic :='0';
+
+
+  signal FTDI_D_in   :  std_logic_vector(7 downto 0);
+  signal FTDI_D_out  :  std_logic_vector(7 downto 0);
+  signal FTDI_drive  :  std_logic;
+
+
+  component sdctrl16
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end component;
+
+begin
+  resetn <= SW(1);
+
+  clk_pad : clkpad generic map (tech => padtech) port map (CLK50, clkm);
+  clkm_inv <= not clkm;
+
+  resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
+  rst0 : rstgen			-- reset generator (reset is active LOW)
+    port map (rst, clkm, '1', rstn, rstraw);
+
+
+----------------------------------------------------------------------
+---  AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
+  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+	nahbm => CFG_NCPU+CFG_AHB_FTDI+CFG_AHB_UART+CFG_AHB_JTAG, nahbs => 8)
+
+  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+-----  LEON3 processor and DSU ---------------------------------------
+----------------------------------------------------------------------
+
+  cpu : for i in 0 to CFG_NCPU-1 generate
+    nosh : if CFG_GRFPUSH = 0 generate
+      u0 : leon3s 		-- LEON3 processor
+      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
+	0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
+	0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
+      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+    		irqi(i), irqo(i), dbgi(i), dbgo(i));
+    end generate;
+  end generate;
+
+  --ledr[0] lit when leon 3 debugvector signals error
+  dsugen : if CFG_DSU = 1 generate
+    dsu0 : dsu3			-- LEON3 Debug Support Unit (slave)
+    generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+       ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+    port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+    dsui.enable <= '1';
+
+  end generate;
+  nodsu : if CFG_DSU = 0 generate
+    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; --no timer freeze, no light.
+  end generate;
+
+  dcomgen : if CFG_AHB_UART = 1 generate
+    dcom0: ahbuart		-- Debug UART
+    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
+    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
+  end generate;
+  uart_txd <= duo.txd;
+  dui.rxd <= uart_rxd;
+
+  ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
+  ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
+    port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
+             open, open, open, open, open, open, open, '0');
+  end generate;
+
+
+----------------------------------------------------------------------
+---  Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+
+    sdc : sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#, -- hmask => 16#C00#,
+	      ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
+	      sdbits => 16, pageburst => 2)
+      port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
+      sa_pad : outpadv generic map (width => 13, tech => padtech)
+	   port map (dram_addr, sdo.address(14 downto 2));
+      ba0_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_0, sdo.address(15));
+      ba1_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_1, sdo.address(16));
+      sd_pad : iopadvv generic map (width => 16, tech => padtech)
+	   port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
+      sdcke_pad : outpad generic map (tech => padtech)
+	   port map (dram_cke, sdo.sdcke(0));
+      sdwen_pad : outpad generic map (tech => padtech)
+	   port map (dram_we_n, sdo.sdwen);
+      sdcsn_pad : outpad generic map (tech => padtech)
+	   port map (dram_cs_n, sdo.sdcsn(0));
+      sdras_pad : outpad generic map (tech => padtech)
+	   port map (dram_ras_n, sdo.rasn);
+      sdcas_pad : outpad generic map (tech => padtech)
+	   port map (dram_cas_n, sdo.casn);
+      sdldqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_ldqm, sdo.dqm(0) );
+      sdudqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_udqm, sdo.dqm(1));
+      dram_clk_pad : outpad generic map (tech => padtech)
+	   port map (dram_clk, clkm_inv);
+
+----------------------------------------------------------------------
+---  APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+  apb0 : apbctrl				-- AHB/APB bridge
+  generic map (hindex => 1, haddr => CFG_APBADDR)
+  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
+
+----------------------------------------------------------------------------------------
+
+  irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+    irqctrl0 : irqmp			-- interrupt controller
+      generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
+      port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+  end generate;
+  irq3 : if CFG_IRQ3_ENABLE = 0 generate
+    x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate;
+    apbo(2) <= apb_none;
+  end generate;
+
+  --Timer unit, generates interrupts when a timer underflow.
+  gpt : if CFG_GPT_ENABLE /= 0 generate
+    timer0 : gptimer 			-- timer unit
+    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+	nbits => CFG_GPT_TW)
+    port map (rstn, clkm, apbi, apbo(3), gpti, open);
+    gpti <= gpti_dhalt_drive(dsuo.tstop);
+  end generate;
+  notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GR GPIO0 unit
+    grgpio0: grgpio
+      generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => 8)
+      port map( rstn, clkm, apbi, apbo(9), gpioi_0, gpioo_0);
+      pio_pads : for i in 0 to 7 generate
+        pio_pad : iopad generic map (tech => padtech)
+            port map (LEDS(i), gpioo_0.dout(i), gpioo_0.oen(i), gpioi_0.din(i));
+      end generate;
+  end generate;
+  nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none;
+    LEDS(5 downto 0)  <= FTDI_D_in(5 downto 0);
+    LEDS(7 downto 6)  <= FTDI_RXF & FTDI_TXE;
+
+  end generate;
+
+ahb_ftdi0: if CFG_AHB_FTDI /=0 generate
+  ftdi_dcom: ahb_ftdi_fifo
+    generic map (oepol => 0 , hindex => CFG_NCPU+CFG_AHB_FTDI+CFG_AHB_UART+CFG_AHB_JTAG )
+    port map (
+      clk  => clkm,
+      rstn => rstn,
+      ahbi => ahbmi,
+      ahbo => ahbmo(CFG_NCPU+CFG_AHB_FTDI+CFG_AHB_UART+CFG_AHB_JTAG),
+
+      FTDI_RXF     => FTDI_RXF,
+      FTDI_TXE     => FTDI_TXE,
+      FTDI_SIWUA   => FTDI_SIWUA,
+      FTDI_WR      => FTDI_WR,
+      FTDI_RD      => FTDI_RD,
+      FTDI_D_in    => FTDI_D_in,
+      FTDI_D_out   => FTDI_D_out,
+      FTDI_D_drive => FTDI_drive
+  );
+end generate;
+
+ftdi_loopback0: if CFG_FTDI_LOOPBACK /=0 generate
+  ftdi_loopback: ftdi_async_fifo_loopback
+    generic map (oepol => 0 )
+    port map (
+      clk  => clkm,
+      rstn => rstn,
+
+      FTDI_RXF     => FTDI_RXF,
+      FTDI_TXE     => FTDI_TXE,
+      FTDI_SIWUA   => FTDI_SIWUA,
+      FTDI_WR      => FTDI_WR,
+      FTDI_RD      => FTDI_RD,
+      FTDI_D_in    => FTDI_D_in,
+      FTDI_D_out   => FTDI_D_out,
+      FTDI_D_drive => FTDI_drive
+  );
+end generate;
+
+
+fifo_pad : iopadv generic map (width => 8, tech => padtech)
+	   port map (FTDI_D(7 downto 0), FTDI_D_out(7 downto 0), FTDI_drive, FTDI_D_in(7 downto 0));
+
+
+
+end rtl;
+
diff --git a/designs/Leon3-MiniSpartan6p/leon3mp.xcf b/designs/Leon3-MiniSpartan6p/leon3mp.xcf
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/leon3mp.xcf
@@ -0,0 +1,4 @@
+
+NET CLK50 	PERIOD = 20.0 ;
+
+
diff --git a/designs/Leon3-MiniSpartan6p/mt48lc16m16a2.vhd b/designs/Leon3-MiniSpartan6p/mt48lc16m16a2.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/mt48lc16m16a2.vhd
@@ -0,0 +1,1550 @@
+
+--*****************************************************************************
+--
+-- Micron Semiconductor Products, Inc.
+--
+-- Copyright 1997, Micron Semiconductor Products, Inc.
+-- All rights reserved.
+--
+--*****************************************************************************
+
+-- pragma translate_off
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use std.textio.all;
+
+PACKAGE mti_pkg IS
+
+    FUNCTION  To_StdLogic (s : BIT) RETURN STD_LOGIC;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
+    PROCEDURE TO_BITVECTOR  (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
+
+
+END mti_pkg;
+
+PACKAGE BODY mti_pkg IS
+
+    -- Convert BIT to STD_LOGIC
+    FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
+    BEGIN
+            CASE s IS
+                WHEN '0' => RETURN ('0');
+                WHEN '1' => RETURN ('1');
+                WHEN OTHERS => RETURN ('0');
+            END CASE;
+    END;
+
+    -- Convert STD_LOGIC to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        IF input = '1' THEN
+            result := weight;
+        ELSE
+            result := 0;                                            -- if unknowns, default to logic 0
+        END IF;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert BIT_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert STD_LOGIC_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Conver INTEGER to BIT_VECTOR
+    PROCEDURE  TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
+    VARIABLE work,offset,outputlen,j : INTEGER := 0;
+    BEGIN
+        --length of vector
+        IF output'LENGTH > 32 THEN		--'
+            outputlen := 32;
+            offset := output'LENGTH - 32;		--'
+            IF input >= 0 THEN
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '0';		--'
+                END LOOP;
+            ELSE
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '1';		--'		
+                END LOOP;
+            END IF;
+        ELSE
+            outputlen := output'LENGTH; 		--'
+        END IF;
+        --positive value
+        IF (input >= 0) THEN
+            work := input;
+            j := outputlen - 1;
+            FOR i IN 1 to 32 LOOP
+                IF j >= 0 then
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    END IF;
+                END IF;
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '0'; 		--'
+            END IF;
+        --negative value
+        ELSE
+            work := (-input) - 1;
+            j := outputlen - 1;
+            FOR i IN 1 TO 32 LOOP
+                IF j>= 0 THEN
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    END IF;
+                END IF;    
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '1'; 		--'
+            END IF;
+        END IF;
+    END TO_BITVECTOR;
+
+END mti_pkg;   
+
+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT48LC16M16A2.VHD
+--       Version: 0.0g
+--          Date: June 29th, 2000
+--         Model: Behavioral
+--     Simulator: Model Technology (PC version 5.3 PE)
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256Mb SDRAM
+--
+--    Limitation: - Doesn't check for 4096-cycle refresh 		--'
+--
+--          Note: - Set simulator resolution to "ps" accuracy
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev   Author          Phone         Date        Changes
+--  ----  ----------------------------  ----------  -------------------------------------
+--  0.0g  Son Huynh       208-368-3825  06/29/2000  Add Load/Dump memory array
+--        Micron Technology Inc.                    Modify tWR + tRAS timing check
+--
+--  0.0f  Son Huynh       208-368-3825  07/08/1999  Fix tWR = 1 Clk + 7.5 ns (Auto)
+--        Micron Technology Inc.                    Fix tWR = 15 ns (Manual)
+--                                                  Fix tRP (Autoprecharge to AutoRefresh)
+--
+--  0.0c  Son P. Huynh    208-368-3825  04/08/1999  Fix tWR + tRP in Write with AP
+--        Micron Technology Inc.                    Fix tRC check in Load Mode Register
+--
+--  0.0b  Son P. Huynh    208-368-3825  01/06/1998  Derive from 64Mb SDRAM model
+--        Micron Technology Inc.
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY STD;
+    USE STD.TEXTIO.ALL;
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY WORK;
+    USE WORK.MTI_PKG.ALL;
+    use std.textio.all;
+
+library grlib;
+use grlib.stdlib.all;
+use grlib.stdio.all;
+
+ENTITY mt48lc16m16a2 IS
+    GENERIC (
+        -- Timing Parameters for -75 (PC133) and CAS Latency = 2
+        tAC       : TIME    :=  6.0 ns;
+        tHZ       : TIME    :=  7.0 ns;
+        tOH       : TIME    :=  2.7 ns;
+        tMRD      : INTEGER :=  2;          -- 2 Clk Cycles
+        tRAS      : TIME    := 44.0 ns;
+        tRC       : TIME    := 66.0 ns;
+        tRCD      : TIME    := 20.0 ns;
+        tRP       : TIME    := 20.0 ns;
+        tRRD      : TIME    := 15.0 ns;
+        tWRa      : TIME    :=  7.5 ns;     -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
+        tWRp      : TIME    := 15.0 ns;     -- A2 Version - Precharge mode only (15 ns)
+
+        tAH       : TIME    :=  0.8 ns;
+        tAS       : TIME    :=  1.5 ns;
+        tCH       : TIME    :=  2.5 ns;
+        tCL       : TIME    :=  2.5 ns;
+        tCK       : TIME    := 10.0 ns;
+        tDH       : TIME    :=  0.8 ns;
+        tDS       : TIME    :=  1.5 ns;
+        tCKH      : TIME    :=  0.8 ns;
+        tCKS      : TIME    :=  1.5 ns;
+        tCMH      : TIME    :=  0.8 ns;
+        tCMS      : TIME    :=  1.5 ns;
+
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        col_bits  : INTEGER :=  9;
+        index     : INTEGER :=  0;
+	fname     : string := "ram.srec"	-- File to read from
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        Ba    : IN    STD_LOGIC_VECTOR := "00";
+        Clk   : IN    STD_LOGIC := '0';
+        Cke   : IN    STD_LOGIC := '1';
+        Cs_n  : IN    STD_LOGIC := '1';
+        Ras_n : IN    STD_LOGIC := '1';
+        Cas_n : IN    STD_LOGIC := '1';
+        We_n  : IN    STD_LOGIC := '1';
+        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
+    );
+END mt48lc16m16a2;
+
+ARCHITECTURE behave OF mt48lc16m16a2 IS
+    TYPE   State       IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
+    TYPE   Array4xI    IS ARRAY (3 DOWNTO 0) OF INTEGER;
+    TYPE   Array4xT    IS ARRAY (3 DOWNTO 0) OF TIME;
+    TYPE   Array4xB    IS ARRAY (3 DOWNTO 0) OF BIT;
+    TYPE   Array4x2BV  IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
+    TYPE   Array4xCBV  IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
+    TYPE   Array_state IS ARRAY (4 DOWNTO 0) OF State;
+    SIGNAL Operation : State := NOP;
+    SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
+    SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
+    SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
+    SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
+    SIGNAL Write_burst_mode : BIT := '0';
+    SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
+
+    -- Checking internal wires
+    SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
+    SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
+    SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+
+BEGIN
+    -- CS# Decode
+    WITH Cs_n SELECT
+        Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        We_in  <= TO_BIT (We_n,  '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <=     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
+    Prech_enable    <= NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <=     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <=     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_1  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+
+    -- Write Burst Mode
+    Write_burst_mode <= Mode_reg(9);
+
+    -- RAS Clock for checking tWR and tRP
+    PROCESS
+        variable Clk0, Clk1 : integer := 0;
+    begin
+        RAS_clk <= '1';
+        wait for 0.5 ns;
+        RAS_clk <= '0';
+        wait for 0.5 ns;
+        if Clk0 > 100 or Clk1 > 100 then
+            wait;
+        else
+            if Clk = '1' and Cke = '1' then
+                Clk0 := 0;
+                Clk1 := Clk1 + 1;
+            elsif Clk = '0' and Cke = '1' then
+                Clk0 := Clk0 + 1;
+                Clk1 := 0;
+            end if;
+        end if;
+    END PROCESS;
+
+    -- System Clock
+    int_clk : PROCESS (Clk)
+        begin
+            IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN 		--'
+                CkeZ <= TO_BIT(Cke, '1');
+            END IF;
+            Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
+    END PROCESS;
+
+    state_register : PROCESS
+        -- NOTE: The extra bits in RAM_TYPE is for checking memory access.  A logic 1 means
+        --       the location is in use.  This will be checked when doing memory DUMP.
+        TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
+        TYPE ram_pntr IS ACCESS ram_type;
+        TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
+        VARIABLE Bank0 : ram_stor;
+        VARIABLE Bank1 : ram_stor;
+        VARIABLE Bank2 : ram_stor;
+        VARIABLE Bank3 : ram_stor;
+        VARIABLE Row_index, Col_index : INTEGER := 0;
+        VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
+
+        VARIABLE Col_addr : Array4xCBV;
+        VARIABLE Bank_addr : Array4x2BV;
+        VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
+
+        VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Burst_counter : INTEGER := 0;
+
+        VARIABLE Command : Array_state;
+        VARIABLE Bank_precharge : Array4x2BV;
+        VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
+
+        VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
+
+        -- Timing Check
+        VARIABLE MRD_chk : INTEGER := 0;
+        VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
+        VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+
+        -- Load and Dumb variables
+        FILE     file_load : TEXT open read_mode is fname;   -- Data load
+        FILE     file_dump : TEXT open write_mode is "dumpdata.txt";   -- Data dump
+        VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
+        VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
+        VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
+        VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
+        VARIABLE i, j      : INTEGER;
+        VARIABLE good_load : BOOLEAN;
+        VARIABLE l         : LINE;
+	variable load : std_logic := '1';
+	variable dump : std_logic := '0';
+	variable ch   : character;
+	variable rectype : bit_vector(3 downto 0);
+	variable recaddr : bit_vector(31 downto 0);
+	variable reclen : bit_vector(7 downto 0);
+	variable recdata : bit_vector(0 to 16*8-1);
+
+        -- Initialize empty rows
+        PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW ram_type;                  -- Open new row for access
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP            -- Filled row with zeros
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+            
+        -- Burst Counter
+        PROCEDURE Burst_decode IS
+            VARIABLE Col_int : INTEGER := 0;
+            VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance Burst Counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Col_int := TO_INTEGER(Col);
+                Col_int := Col_int + 1;
+                TO_BITVECTOR (Col_int, Col_temp);
+            ELSIF Mode_reg (3) = '1' THEN
+                TO_BITVECTOR (Burst_counter, Col_vec);
+                Col_temp (2) :=  Col_vec (2) XOR Col_brst (2);
+                Col_temp (1) :=  Col_vec (1) XOR Col_brst (1);
+                Col_temp (0) :=  Col_vec (0) XOR Col_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Col (0) := Col_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
+            ELSE
+                Col := Col_temp;
+            END IF;
+
+            -- Burst Read Single Write
+            IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
+                Data_in_enable := '0';
+            END IF;
+
+            -- Data counter
+            IF Burst_length_1 = '1' THEN
+                IF Burst_counter >= 1 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk, RAS_clk;
+        IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN 		--'
+            -- Internal Command Pipeline
+            Command(0) := Command(1);
+            Command(1) := Command(2);
+            Command(2) := Command(3);
+            Command(3) := NOP;
+            
+            Col_addr(0) := Col_addr(1);
+            Col_addr(1) := Col_addr(2);
+            Col_addr(2) := Col_addr(3);
+            Col_addr(3) := (OTHERS => '0');
+            
+            Bank_addr(0) := Bank_addr(1);
+            Bank_addr(1) := Bank_addr(2);
+            Bank_addr(2) := Bank_addr(3);
+            Bank_addr(3) := "00";
+
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := "00";
+
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := '0';
+            
+            -- Operation Decode (Optional for showing current command on posedge clock / debug feature)
+            IF Active_enable = '1' THEN
+                Operation <= ACT;
+            ELSIF Aref_enable = '1' THEN
+                Operation <= A_REF;
+            ELSIF Burst_term = '1' THEN
+                Operation <= BST;
+            ELSIF Mode_reg_enable = '1' THEN
+                Operation <= LMR;
+            ELSIF Prech_enable = '1' THEN
+                Operation <= PRECH;
+            ELSIF Read_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= READ;
+                ELSE
+                    Operation <= READ_A;
+                END IF;
+            ELSIF Write_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= WRITE;
+                ELSE
+                    Operation <= WRITE_A;
+                END IF;
+            ELSE
+                Operation <= NOP;
+            END IF;
+            
+            -- Dqm pipeline for Read
+            Dqm_reg0 := Dqm_reg1;
+            Dqm_reg1 := TO_BITVECTOR(Dqm);
+
+            -- Read or Write with Auto Precharge Counter
+            IF Auto_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Auto_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Auto_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Auto_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+            
+            -- Auto Precharge Timer for tWR
+            if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
+                if (Count_precharge(0) = 1) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 1) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 1) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 1) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_2 = '1') then
+                if (Count_precharge(0) = 2) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 2) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 2) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 2) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_4 = '1') then
+                if (Count_precharge(0) = 4) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 4) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 4) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 4) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_8 = '1') then
+                if (Count_precharge(0) = 8) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 8) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 8) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 8) then
+                    Count_time(3) := NOW;
+                end if;
+            end if;
+
+            -- tMRD Counter
+            MRD_chk := MRD_chk + 1;
+
+            -- tWR Counter
+            WR_counter(0) := WR_counter(0) + 1;
+            WR_counter(1) := WR_counter(1) + 1;
+            WR_counter(2) := WR_counter(2) + 1;
+            WR_counter(3) := WR_counter(3) + 1;
+
+
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- Precharge to Auto Refresh
+                ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- All banks must be idle before refresh
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All banks must be Precharge before Auto Refresh"
+                        SEVERITY WARNING;
+                END IF;
+                -- Record current tRC time
+                RC_chk := NOW;
+            END IF;
+            
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                Mode_reg <= TO_BITVECTOR (Addr);
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All bank must be Precharge before Load Mode Register"
+                        SEVERITY WARNING;
+                END IF;
+                -- REF to LMR
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- LMR to LMR
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- Record current tMRD time
+                MRD_chk := 0;
+            END IF;
+            
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    -- Precharge to Active Bank 0
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '1' THEN
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    -- Precharge to Active Bank 1
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '1' THEN
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    -- Precharge to Active Bank 2
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '1' THEN
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    -- Precharge to Active Bank 3
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+                ELSIF Ba = "00" AND Pc_b0 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 0 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 1 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 2 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 3 is not Precharged"
+                        SEVERITY WARNING;
+                END IF;
+                -- Active Bank A to Active Bank B
+                IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
+                    ASSERT (FALSE)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                -- LMR to ACT
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Activate"
+                    SEVERITY WARNING;
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Activate"
+                    SEVERITY WARNING;
+                -- Record variable for checking violation
+                RRD_chk := NOW;
+                Previous_bank := TO_BITVECTOR (Ba);
+            END IF;
+            
+            -- Precharge Block
+            IF Prech_enable = '1' THEN
+                IF Addr(10) = '1' THEN
+                    Pc_b0 := '1'; 
+                    Pc_b1 := '1'; 
+                    Pc_b2 := '1'; 
+                    Pc_b3 := '1';
+                    Act_b0 := '0';
+                    Act_b1 := '0';
+                    Act_b2 := '0';
+                    Act_b3 := '0';
+                    RP_chk0 := NOW;
+                    RP_chk1 := NOW;
+                    RP_chk2 := NOW;
+                    RP_chk3 := NOW;
+                    -- Activate to Precharge all banks
+                    ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
+                        REPORT "tRAS violation during Precharge all banks"
+                        SEVERITY WARNING;
+                    -- tWR violation check for Write
+                    IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
+                        (NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
+                        ASSERT (FALSE)
+                            REPORT "tWR violation during Precharge ALL banks"
+                            SEVERITY WARNING;
+                    END IF;
+                ELSIF Addr(10) = '0' THEN
+                    IF Ba = "00" THEN
+                        Pc_b0 := '1';
+                        Act_b0 := '0';
+                        RP_chk0 := NOW;
+                        -- Activate to Precharge bank 0
+                        ASSERT (NOW - RAS_chk0 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 0"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "01" THEN
+                        Pc_b1 := '1';
+                        Act_b1 := '0';
+                        RP_chk1 := NOW;
+                        -- Activate to Precharge bank 1
+                        ASSERT (NOW - RAS_chk1 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 1"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "10" THEN
+                        Pc_b2 := '1';
+                        Act_b2 := '0';
+                        RP_chk2 := NOW;
+                        -- Activate to Precharge bank 2
+                        ASSERT (NOW - RAS_chk2 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 2"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "11" THEN
+                        Pc_b3 := '1';
+                        Act_b3 := '0';
+                        RP_chk3 := NOW;
+                        -- Activate to Precharge bank 3
+                        ASSERT (NOW - RAS_chk3 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 3"
+                            SEVERITY WARNING;
+                    END IF;
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+                -- Terminate a Write Immediately (if same bank or all banks)
+                IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Precharge Command Pipeline for READ
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := PRECH;
+                    Bank_precharge(2) := TO_BITVECTOR (Ba);
+                    A10_precharge(2) := TO_BIT(Addr(10));
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := PRECH;
+                    Bank_precharge(1) := TO_BITVECTOR (Ba);
+                    A10_precharge(1) := TO_BIT(Addr(10));
+                END IF;
+            END IF;
+            
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Terminate a Write immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Terminate a Read depend on CAS Latency
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := BST;
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := BST;
+                END IF;
+            END IF;
+            
+            -- Read, Write, Column Latch
+            IF Read_enable = '1' OR Write_enable = '1' THEN
+                -- Check to see if bank is open (ACT) for Read or Write
+                IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
+                    ASSERT (FALSE)
+                        REPORT "Cannot Read or Write - Bank is not Activated"
+                        SEVERITY WARNING;
+                END IF;
+                -- Activate to Read or Write
+                IF Ba = "00" THEN
+                    ASSERT (NOW - RCD_chk0 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" THEN
+                    ASSERT (NOW - RCD_chk1 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" THEN
+                    ASSERT (NOW - RCD_chk2 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" THEN
+                    ASSERT (NOW - RCD_chk3 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 3"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Read Command
+                IF Read_enable = '1' THEN
+                    -- CAS Latency Pipeline
+                    IF Cas_latency_3 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(2) := READ_A;
+                        ELSE
+                            Command(2) := READ;
+                        END IF;
+                        Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (2) := TO_BITVECTOR (Ba);
+                    ELSIF Cas_latency_2 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(1) := READ_A;
+                        ELSE
+                            Command(1) := READ;
+                        END IF;
+                        Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (1) := TO_BITVECTOR (Ba);
+                    END IF;
+
+                    -- Read intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                -- Write Command
+                ELSIF Write_enable = '1' THEN
+                    IF Addr(10) = '1' THEN
+                        Command(0) := WRITE_A;
+                    ELSE
+                        Command(0) := WRITE;
+                    END IF;
+                    Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                    Bank_addr (0) := TO_BITVECTOR (Ba);
+
+                    -- Write intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                    -- Write interrupt a Read (terminate Read immediately)
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+
+                -- Interrupt a Write with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Interrupt a Read with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Read or Write with Auto Precharge
+                IF Addr(10) = '1' THEN
+                    Auto_precharge (TO_INTEGER(Ba)) := '1';
+                    Count_precharge (TO_INTEGER(Ba)) := 0;
+                    RW_Interrupt_Bank := TO_BitVector(Ba);
+                    IF Read_enable = '1' THEN
+                        Read_precharge (TO_INTEGER(Ba)) := '1';
+                    ELSIF Write_enable = '1' THEN
+                        Write_precharge (TO_INTEGER(Ba)) := '1';
+                    END IF;
+                END IF;
+            END IF;
+            
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  BL/2 cycles after command
+            --      and 2.  Meet tRAS requirement
+            --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+            IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
+                IF (((NOW - RAS_chk0 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(0) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(0) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(0) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
+                     (RW_interrupt_read(0) = '1')) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Auto_precharge(0) := '0';
+                    Read_precharge(0) := '0';
+                    RW_interrupt_read(0) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
+                IF (((NOW - RAS_chk1 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(1) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(1) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(1) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
+                     (RW_interrupt_read(1) = '1')) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Auto_precharge(1) := '0';
+                    Read_precharge(1) := '0';
+                    RW_interrupt_read(1) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
+                IF (((NOW - RAS_chk2 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(2) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(2) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(2) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
+                     (RW_interrupt_read(2) = '1')) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Auto_precharge(2) := '0';
+                    Read_precharge(2) := '0';
+                    RW_interrupt_read(2) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
+                IF (((NOW - RAS_chk3 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(3) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(3) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(3) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
+                     (RW_interrupt_read(3) = '1')) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Auto_precharge(3) := '0';
+                    Read_precharge(3) := '0';
+                    RW_interrupt_read(3) := '0';
+                END IF;
+            END IF;
+            
+            -- Internal Precharge or Bst
+            IF Command(0) = PRECH THEN                          -- PRECH terminate a read if same bank or all banks
+                IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Command(0) = BST THEN                         -- BST terminate a read regardless of bank
+                IF Data_out_enable = '1' THEN
+                    Data_out_enable := '0';
+                END IF;
+            END IF;
+
+            IF Data_out_enable = '0' THEN
+                Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
+            END IF;
+
+            -- Detect Read or Write Command
+            IF Command(0) = READ OR Command(0) = READ_A THEN
+                Bank := Bank_addr (0);
+                Col := Col_addr (0);
+                Col_brst := Col_addr (0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '0';
+                Data_out_enable := '1';
+            ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
+                Bank := Bank_addr(0);
+                Col := Col_addr(0);
+                Col_brst := Col_addr(0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '1';
+                Data_out_enable := '0';
+            END IF;
+
+            -- DQ (Driver / Receiver)
+            Row_index := TO_INTEGER (Row);
+            Col_index := TO_INTEGER (Col);
+            IF Data_in_enable = '1' THEN
+                IF Dqm /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    END IF;
+                    WR_chkp(TO_INTEGER(Bank)) := NOW;
+                    WR_counter(TO_INTEGER(Bank)) := 0;
+                END IF;
+                Burst_decode;
+            ELSIF Data_out_enable = '1' THEN
+                IF Dqm_reg0 /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    END IF;
+                ELSE
+                      Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
+                END IF;
+                Burst_decode;
+            END IF;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN 		--'
+            Operation <= LOAD_FILE;
+	    load := '0';
+--            ASSERT (FALSE) REPORT "Reading memory array from file.  This operation may take several minutes.  Please wait..."
+--                SEVERITY NOTE;
+            WHILE NOT endfile(file_load) LOOP
+                readline(file_load, l);
+                read(l, ch);
+                if (ch /= 'S') or (ch /= 's') then
+                  hread(l, rectype);
+                  hread(l, reclen);
+		  recaddr := (others => '0');
+		  case rectype is 
+		  when "0001" =>
+                    hread(l, recaddr(15 downto 0));
+		  when "0010" =>
+                    hread(l, recaddr(23 downto 0));
+		  when "0011" =>
+                    hread(l, recaddr);
+		    recaddr(31 downto 24) := (others => '0');
+		  when others => next;
+		  end case;
+                  hread(l, recdata);
+
+	 	  if index < 32 then
+		    Bank_Load := recaddr(25 downto 24);
+		    Rows_Load := recaddr(23 downto 11);
+		    Cols_Load := recaddr(10 downto 2);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 3 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 3 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 3 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 3 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    END IF;
+		  elsif(index < 1024) then
+		    Bank_Load := recaddr(26 downto 25);
+		    Rows_Load := recaddr(24 downto 12);
+		    Cols_Load := recaddr(11 downto 3);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 1 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 1 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 1 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 1 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    END IF;
+                  else
+		    Bank_Load := recaddr(22 downto 21);
+		    Rows_Load := '0' & recaddr(20 downto 9);
+		    Cols_Load := '0' & recaddr(8 downto 1);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 7 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 7 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 7 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 7 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    END IF;
+                  END IF;
+                END IF;
+            END LOOP;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN 		--'
+            Operation <= DUMP_FILE;
+            ASSERT (FALSE) REPORT "Writing memory array to file.  This operation may take several minutes.  Please wait..."
+                SEVERITY NOTE;
+            WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# BA ROWS          COLS      DQ")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# -- ------------- --------- ----------------")); 		--'
+            WRITELINE (file_dump, l);
+            -- Dumping Bank 0
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank0 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("00"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 1
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank1 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("01"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 2
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank2 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("10"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 3
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank3 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("11"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+        END IF;
+
+        -- Write with AutoPrecharge Calculation
+        --      The device start internal precharge when:
+        --          1.  tWR cycles after command
+        --      and 2.  Meet tRAS requirement
+        --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+        IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
+            IF (((NOW - RAS_chk0 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
+                Auto_precharge(0) := '0';
+                Write_precharge(0) := '0';
+                RW_interrupt_write(0) := '0';
+                Pc_b0 := '1';
+                Act_b0 := '0';
+                RP_chk0 := NOW;
+                ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
+            IF (((NOW - RAS_chk1 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
+                 (RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
+                Auto_precharge(1) := '0';
+                Write_precharge(1) := '0';
+                RW_interrupt_write(1) := '0';
+                Pc_b1 := '1';
+                Act_b1 := '0';
+                RP_chk1 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
+            IF (((NOW - RAS_chk2 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
+                 (RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
+                Auto_precharge(2) := '0';
+                Write_precharge(2) := '0';
+                RW_interrupt_write(2) := '0';
+                Pc_b2 := '1';
+                Act_b2 := '0';
+                RP_chk2 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
+            IF (((NOW - RAS_chk3 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
+                Auto_precharge(3) := '0';
+                Write_precharge(3) := '0';
+                RW_interrupt_write(3) := '0';
+                Pc_b3 := '1';
+                Act_b3 := '0';
+                RP_chk3 := NOW;
+            END IF;
+        END IF;
+
+        -- Checking internal wires (Optional for debug purpose)
+        Pre_chk (0) <= Pc_b0;
+        Pre_chk (1) <= Pc_b1;
+        Pre_chk (2) <= Pc_b2;
+        Pre_chk (3) <= Pc_b3;
+        Act_chk (0) <= Act_b0;
+        Act_chk (1) <= Act_b1;
+        Act_chk (2) <= Act_b2;
+        Act_chk (3) <= Act_b3;
+        Dq_in_chk   <= Data_in_enable;
+        Dq_out_chk  <= Data_out_enable;
+        Bank_chk    <= Bank;
+        Row_chk     <= Row;
+        Col_chk     <= Col;
+    END PROCESS;    
+                    
+                    
+    -- Clock timing checks
+--    Clock_check : PROCESS
+--        VARIABLE Clk_low, Clk_high : TIME := 0 ns;
+--    BEGIN       
+--        WAIT ON Clk;
+--        IF (Clk = '1' AND NOW >= 10 ns) THEN
+--            ASSERT (NOW - Clk_low >= tCL)
+--                REPORT "tCL violation"
+--                SEVERITY WARNING;
+--            ASSERT (NOW - Clk_high >= tCK)
+--                REPORT "tCK violation"
+--                SEVERITY WARNING;
+--            Clk_high := NOW;
+--        ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
+--            ASSERT (NOW - Clk_high >= tCH)
+--                REPORT "tCH violation"
+--                SEVERITY WARNING;
+--            Clk_low := NOW;
+--        END IF;
+--    END PROCESS;    
+                    
+    -- Setup timing checks
+    Setup_check : PROCESS
+    BEGIN       
+	wait;
+        WAIT ON Clk;
+        IF Clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tCKS) 		--'
+                REPORT "CKE Setup time violation -- tCKS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "RAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "WE# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT >= tCMS) 		--'
+                REPORT "Dqm Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tAS) 		--'
+                REPORT "ADDR Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tAS) 		--'
+                REPORT "BA Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Dq'LAST_EVENT >= tDS) 		--'
+                REPORT "Dq Setup time violation -- tDS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    -- Hold timing checks
+    Hold_check : PROCESS
+    BEGIN
+	wait;
+        WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
+        IF Clk'DELAYED (tCKH) = '1' THEN 		--'
+            ASSERT(Cke'LAST_EVENT > tCKH) 		--'
+                REPORT "CKE Hold time violation -- tCKH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tCMH) = '1' THEN 		--'
+            ASSERT(Cs_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT > tCMH) 		--'
+                REPORT "RAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT > tCMH) 		--'
+                REPORT "WE# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT > tCMH) 		--'
+                REPORT "Dqm Hold time violation -- tCMH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tAH) = '1' THEN 		--'
+            ASSERT(Addr'LAST_EVENT > tAH) 		--'
+                REPORT "ADDR Hold time violation -- tAH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT > tAH) 		--'
+                REPORT "BA Hold time violation -- tAH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tDH) = '1' THEN 		--'
+            ASSERT(Dq'LAST_EVENT > tDH) 		--'
+                REPORT "Dq Hold time violation -- tDH"
+                SEVERITY WARNING;
+        END IF;
+    END PROCESS;
+
+END behave;
+
+-- pragma translate_on
+
diff --git a/designs/Leon3-MiniSpartan6p/sdctrl16.vhd b/designs/Leon3-MiniSpartan6p/sdctrl16.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/sdctrl16.vhd
@@ -0,0 +1,1053 @@
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+-----------------------------------------------------------------------------
+-- Entity:  sdctrl16
+-- File:    sdctrl16.vhd
+-- Author:  Jiri Gaisler - Gaisler Research
+-- Modified by: Daniel Bengtsson & Richard Fång
+-- Description: 16- and 32-bit SDRAM memory controller.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+library gaisler;
+use grlib.devices.all;
+use gaisler.memctrl.all;
+
+entity sdctrl16 is
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end;
+
+architecture rtl of sdctrl16 is
+
+constant WPROTEN   : boolean := wprot = 1;
+constant SDINVCLK  : boolean := invclk = 1;
+constant BUS16    : boolean := (sdbits = 16);
+constant BUS32    : boolean := (sdbits = 32);
+constant BUS64    : boolean := (sdbits = 64);
+
+constant REVISION  : integer := 1;
+
+constant PM_PD    : std_logic_vector(2 downto 0) := "001";
+constant PM_SR    : std_logic_vector(2 downto 0) := "010";
+constant PM_DPD   : std_logic_vector(2 downto 0) := "101";
+
+constant std_rammask: Std_Logic_Vector(31 downto 20) :=
+                        Conv_Std_Logic_Vector(hmask, 12);
+
+constant hconfig : ahb_config_type := (
+  0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
+  4 => ahb_membar(haddr, '1', '1', hmask),
+  5 => ahb_iobar(ioaddr, iomask),
+  others => zero32);
+
+type mcycletype is (midle, active, leadout);
+type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
+                     wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
+                     sref, pd, dpd);
+type icycletype is (iidle, pre, ref, lmode, emode, finish);
+
+-- sdram configuration register
+
+type sdram_cfg_type is record
+  command         : std_logic_vector(2 downto 0);
+  csize           : std_logic_vector(1 downto 0);
+  bsize           : std_logic_vector(2 downto 0);
+  casdel          : std_ulogic;  -- CAS to data delay: 2/3 clock cycles
+  trfc            : std_logic_vector(2 downto 0);
+  trp             : std_ulogic;  -- precharge to activate: 2/3 clock cycles
+  refresh         : std_logic_vector(14 downto 0);
+  renable         : std_ulogic;
+  pageburst       : std_ulogic;
+  mobileen        : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
+  ds              : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
+  tcsr            : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
+  pasr            : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
+  pmode           : std_logic_vector(2 downto 0); -- Power-Saving mode
+  txsr            : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
+  cke             : std_ulogic; -- Clock enable
+end record;
+
+-- local registers
+
+type reg_type is record
+  hready        : std_ulogic;
+  hsel          : std_ulogic;
+  bdrive        : std_ulogic;
+  nbdrive       : std_ulogic;
+  burst         : std_ulogic;
+  wprothit      : std_ulogic;
+  hio           : std_ulogic;
+  startsd       : std_ulogic;
+  lhw           : std_ulogic; --Lower halfword
+
+  mstate        : mcycletype;
+  sdstate       : sdcycletype;
+  cmstate       : mcycletype;
+  istate        : icycletype;
+  icnt          : std_logic_vector(2 downto 0);
+
+  haddr         : std_logic_vector(31 downto 0);
+  hrdata        : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
+  hwdata        : std_logic_vector(31 downto 0);
+  hwrite        : std_ulogic;
+  htrans        : std_logic_vector(1 downto 0);
+  hresp         : std_logic_vector(1 downto 0);
+  size          : std_logic_vector(1 downto 0);
+
+  cfg           : sdram_cfg_type;
+  trfc          : std_logic_vector(3 downto 0);
+  refresh       : std_logic_vector(14 downto 0);
+  sdcsn         : std_logic_vector(1  downto 0);
+  sdwen         : std_ulogic;
+  rasn          : std_ulogic;
+  casn          : std_ulogic;
+  dqm           : std_logic_vector(7 downto 0);
+  address       : std_logic_vector(16 downto 2);  -- memory address
+  bsel          : std_ulogic;
+
+  idlecnt       : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
+  sref_tmpcom   : std_logic_vector(2 downto 0); -- Save SD command when exit sref
+end record;
+
+signal r, ri : reg_type;
+signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
+attribute syn_preserve : boolean;
+attribute syn_preserve of rbdrive : signal is true;
+
+begin
+
+  ctrl : process(rst, ahbsi, r, sdi, rbdrive)
+  variable v       : reg_type;                      -- local variables for registers
+  variable startsd : std_ulogic;
+  variable dataout : std_logic_vector(31 downto 0); -- data from memory
+  variable regsd   : std_logic_vector(31 downto 0); -- data from registers
+  variable dqm     : std_logic_vector(7 downto 0);
+  variable raddr   : std_logic_vector(12 downto 0);
+  variable adec    : std_ulogic;
+  variable rams    : std_logic_vector(1 downto 0);
+  variable ba      : std_logic_vector(1 downto 0);
+  variable haddr   : std_logic_vector(31 downto 0);
+  variable dout    : std_logic_vector(31 downto 0);
+  variable hsize   : std_logic_vector(1 downto 0);
+  variable hwrite  : std_ulogic;
+  variable htrans  : std_logic_vector(1 downto 0);
+  variable hready  : std_ulogic;
+  variable vbdrive : std_logic_vector(31 downto 0);
+  variable bdrive  : std_ulogic;
+  variable lline    : std_logic_vector(2 downto 0);
+  variable lineburst : boolean;
+  variable haddr_tmp : std_logic_vector(31 downto 0);
+  variable arefresh : std_logic;
+  variable hwdata  : std_logic_vector(31 downto 0);
+
+  begin
+
+-- Variable default settings to avoid latches
+
+    v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
+    if BUS16 then
+      if (r.lhw = '1') then --muxes read data to correct part of the register.
+        v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
+      else
+        v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
+      end if;
+    else
+      v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
+      v.hrdata(31 downto 0) := sdi.data(31 downto 0);
+    end if;
+    hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
+    lline := not r.cfg.casdel &  r.cfg.casdel &  r.cfg.casdel;
+    if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
+      lineburst := true;
+    else lineburst := false; end if;
+
+
+    if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
+      v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
+      v.htrans := ahbsi.htrans;
+      if ahbsi.htrans(1) = '1' then
+        v.hio := ahbsi.hmbsel(1);
+        v.hsel := '1'; v.hready := v.hio;
+      end if;
+      v.haddr := ahbsi.haddr;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+
+    if (r.hsel = '1') and (ahbsi.hready = '0') then
+      haddr := r.haddr;  hsize := r.size;
+      htrans := r.htrans; hwrite := r.hwrite;
+    else
+      haddr := ahbsi.haddr;  hsize := ahbsi.hsize(1 downto 0);
+      htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+    if fast = 1 then haddr := r.haddr; end if;
+
+    if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
+
+-- main state
+    if BUS16 then
+      case r.size is
+      when "00" => --bytesize
+        case r.haddr(0) is
+        when '0' => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when others => dqm := "11111100"; --halfword, word
+      end case;
+    else
+      case r.size is
+      when "00" =>
+        case r.haddr(1 downto 0) is
+        when "00" => dqm := "11110111";
+        when "01" => dqm := "11111011";
+        when "10" => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when "01" =>
+        if r.haddr(1) = '0' then dqm := "11110011"; else  dqm := "11111100"; end if;
+      when others => dqm := "11110000";
+      end case;
+    end if;
+--
+--      case r.size is
+--      when "00" =>
+--        case r.haddr(1 downto 0) is
+--        when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
+--        when "01" => dqm := "11111110"; lhw := '0';
+--        when "10" => dqm := "11111101"; lhw := '1';
+--        when others => dqm := "11111110"; lhw := '1';
+--        end case;
+--      when "01" =>
+--        dqm := "11111100";
+--        if r.haddr(1) = '0' then
+--          lhw := '0';
+--        else
+--          lhw := '1';
+--	end if;
+--    when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
+--      end case;
+--
+    if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
+
+-- main FSM
+
+    case r.mstate is
+    when midle =>
+      if ((v.hsel and htrans(1) and not v.hio) = '1') then
+        if (r.sdstate = sidle) and (r.cfg.command = "000")
+           and (r.cmstate = midle) and (v.hio = '0')
+        then
+          if fast = 0 then startsd := '1';  else v.startsd := '1'; end if;
+          v.mstate := active;
+        elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
+           and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
+        then
+          v.startsd := '1';
+          if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
+            v.hresp := HRESP_ERROR;
+          else
+            v.mstate := active;
+          end if;
+        end if;
+      end if;
+    when others => null;
+    end case;
+
+    startsd := startsd or r.startsd;
+
+-- generate row and column address size
+
+    if BUS16 then
+      case r.cfg.csize is
+      when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
+      when "01" => raddr := haddr(22 downto 10);
+      when "10" => raddr := haddr(23 downto 11);
+      when others =>
+        if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
+        else raddr := haddr(24 downto 12); end if;
+      end case;
+    else
+      case r.cfg.csize is
+      when "00" => raddr := haddr(22 downto 10);
+      when "01" => raddr := haddr(23 downto 11);
+      when "10" => raddr := haddr(24 downto 12);
+      when others =>
+        if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
+        else raddr := haddr(25 downto 13); end if;
+      end case;
+    end if;
+
+-- generate bank address
+--    if BUS16 then --011
+--      ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
+--            genmux(r.cfg.bsize, haddr(25 downto 18));
+--    else
+      ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
+            genmux(r.cfg.bsize, haddr(27 downto 20));
+ --   end if;
+
+-- generate chip select
+
+    if BUS64 then
+      adec := genmux(r.cfg.bsize, haddr(30 downto 23));
+      v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
+    else
+      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+    end if;
+--    elsif BUS32 then
+--      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+--    else
+--      adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
+--    end if;
+
+    rams := adec & not adec;
+
+-- sdram access FSM
+
+    if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
+
+    if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
+
+    case r.sdstate is
+
+    when sidle =>
+      if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
+      --  if BUS16 then
+      --    v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
+      --  else
+          v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
+      --  end if;
+        v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
+        v.startsd := '0';
+      elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
+            and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
+        case r.cfg.pmode is
+        when PM_SR =>
+          v.cfg.cke := '0'; v.sdstate := sref;
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
+        when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
+        when PM_DPD =>
+          v.cfg.cke := '0'; v.sdstate := dpd;
+          v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
+        when others =>
+        end case;
+      end if;
+
+    when act1 =>
+      v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+      if r.cfg.casdel = '1' then v.sdstate := act2; else
+        v.sdstate := act3;
+        if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
+          v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+        end if;
+      end if;
+      if WPROTEN then
+        v.wprothit := sdi.wprot;
+        if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
+      end if;
+
+    when act2 =>
+      v.sdstate := act3;
+      if not BUS16 then
+        v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+      end if;
+      if WPROTEN and (r.wprothit = '1') then
+        v.hresp := HRESP_ERROR; v.hready := '0';
+      end if;
+
+    when act3 =>
+      v.casn := '0';
+      if BUS16 then --HW adress needed to memory
+        v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+--        v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+	v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
+      else
+        v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      end if;
+      v.dqm := dqm; v.burst := r.hready; -- ??
+
+      if r.hwrite = '1' then
+
+        if BUS16 then --16 bit
+          if r.size(1) = '1' then --word
+            v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
+            v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
+            v.sdstate := act3_16; -- goto state for second part of word transfer
+        --  v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
+          else --halfword or byte
+            v.sdstate := act3_16; v.hready := '1';
+          end if;
+        else --32 bit or 64
+          v.sdstate := wr1;
+          if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
+        end if;
+        v.sdwen := '0'; v.bdrive := '0'; --write
+        if WPROTEN and (r.wprothit = '1') then
+          v.hresp := HRESP_ERROR; v.hready := '1';
+          if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
+          v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
+        end if;
+      else v.sdstate := rd1; end if;
+
+    when act3_16 => --handle 16 bit and WORD write
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
+      v.lhw := '1';
+      if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
+        v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
+        if( ahbsi.htrans = "11" and
+            not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
+            not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
+          v.sdstate := wr1_16;
+        end if;
+      elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      else -- complete single write
+        v.hready := '1';
+        v.sdstate := act3_16; --gick till wr1 förut
+      end if;
+
+    when wr1_16 =>
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
+      v.lhw := r.haddr(1);
+      v.sdstate := act3_16;
+      v.hready := '1';
+
+    when wr1 =>
+      v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
+         and not (WPROTEN and (r.wprothit = '1'))
+      then
+        v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
+        if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
+          v.hready := '0';
+        end if;
+      else
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      end if;
+
+    when wr2 =>
+      if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
+      v.sdstate := wr3;
+
+    when wr3 =>
+      if (r.cfg.trp = '1') then
+        v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
+      else
+        v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when wr4 =>
+      v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
+      if (r.cfg.trp = '1') then v.sdstate := wr5;
+      else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+
+    when wr5 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+
+    when rd1 => --first read applied to sdram
+      v.casn := '1'; v.sdstate := rd7; --nop
+      if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
+        if lineburst and (ahbsi.htrans = "11") then
+          if r.haddr(4 downto 2) = "111" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
+            v.address(4 downto 2) := "000"; v.casn := '0';
+	  end if;
+        end if;
+      end if;
+
+    when rd7 =>
+      v.casn := '1'; --nop
+      if BUS16 then
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
+          elsif lineburst then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      else -- 32 bit or larger
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
+          elsif lineburst then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      end if;
+
+    when rd2 =>
+      v.casn := '1'; v.sdstate := rd3;
+      if BUS16 then
+        if ahbsi.htrans /= "11" then
+          v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+          --note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
+        end if;
+      else
+        if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+        elsif lineburst then
+          if r.haddr(4 downto 2) = "101" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
+      v.casn := '1'; --if read before cas makes nop else if pre => no difference
+      if BUS16 then
+        --note if read is for halfwor or byte we dont want to read a second time but exit.
+        --if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
+    --    if r.size(1) = '1' then --word v.hready := not r.size(1)
+    --      v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
+    --      v.lhw := '1'; -- read low 16 next state
+    --    else --HW or byte
+    --      v.sdstate := rd4_16; v.hready := '1';
+    --    end if;
+        v.sdstate := rd4_16;
+        v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
+        v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
+          if r.haddr(3 downto 1) = "100" then
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      else --32 bit or larger
+        v.sdstate := rd4; v.hready := '1';
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
+          if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
+      --v.hready := '1';
+      v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
+      v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
+      v.casn := '1';
+      --quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
+      if (ahbsi.htrans /= "11" and (r.hready = '1')) or
+         ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
+        --v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
+        v.dqm := (others => '1');
+        if r.sdcsn /= "11" then --not prechargeing
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
+        else--exit
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
+        if r.cfg.casdel = '0' then
+          if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        else
+          if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4 =>
+      v.hready := '1'; v.casn := '1';
+      if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
+      then
+        v.hready := '0'; v.dqm := (others => '1');
+        if (r.sdcsn /= "11") then
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
+        else
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then
+        if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
+          v.address(9 downto 5) := r.address(9 downto 5) + 1;
+          v.address(4 downto 2) := "000"; v.casn := '0';
+        end if;
+      end if;
+
+    when rd5 =>
+      if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
+      v.casn := '1';
+
+    when rd6 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
+
+    when sref =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
+        if r.trfc = "0000" then -- Minimum duration (= tRAS)
+          v.cfg.cke := '1';
+          v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
+        end if;
+        if r.cfg.cke = '1' then
+          if (r.idlecnt = "0000") then -- tXSR ns with NOP
+            v.sdstate := sidle;
+            v.idlecnt := (others => '1');
+            v.sref_tmpcom := r.cfg.command;
+            v.cfg.command := "100";
+          end if;
+        else
+          v.idlecnt := r.cfg.txsr;
+        end if;
+      end if;
+
+    when pd =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
+        v.cfg.cke := '1';
+        v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when dpd =>
+      v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
+      v.cfg.renable := '0';
+      if (startsd = '1' and r.hio = '0') then
+        v.hready := '1'; -- ack all accesses with Error response
+        v.startsd := '0';
+        v.hresp := HRESP_ERROR;
+      elsif r.cfg.pmode /= PM_DPD then
+        v.cfg.cke := '1';
+        if r.cfg.cke = '1' then
+          v.sdstate := sidle;
+          v.idlecnt := (others => '1');
+          v.cfg.renable := '1';
+        end if;
+      end if;
+
+    when others =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+    end case;
+
+-- sdram commands
+
+    case r.cmstate is
+    when midle =>
+      if r.sdstate = sidle then
+        case r.cfg.command is
+        when "010" => -- precharge
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
+          v.address(12) := '1'; v.cmstate := active;
+        when "100" => -- auto-refresh
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.cmstate := active;
+        when "110" => -- Lodad Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          if lineburst then
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
+          else
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
+          end if;
+        when "111" => -- Load Ext-Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
+                                    & r.cfg.pasr(2 downto 0);
+        when others => null;
+        end case;
+      end if;
+    when active =>
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
+      v.sdwen := '1'; --v.cfg.command := "000";
+      v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
+      v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+    when leadout =>
+      if r.trfc = "0000" then v.cmstate := midle; end if;
+
+    end case;
+
+-- sdram init
+
+    case r.istate is
+    when iidle =>
+      v.cfg.cke := '1';
+      if r.cfg.renable = '1' and r.cfg.cke = '1' then
+        v.cfg.command := "010"; v.istate := pre;
+      end if;
+    when pre =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
+      end if;
+    when ref =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.icnt := r.icnt - 1;
+        if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
+      end if;
+    when lmode =>
+      if r.cfg.command = "000" then
+        if r.cfg.mobileen = "11" then
+          v.cfg.command := "111"; v.istate := emode;
+        else
+          v.istate := finish;
+        end if;
+      end if;
+    when emode =>
+      if r.cfg.command = "000" then
+        v.istate := finish;
+      end if;
+    when others =>
+      if r.cfg.renable = '0' and r.sdstate /= dpd then
+        v.istate := iidle;
+      end if;
+    end case;
+
+    if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
+      if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
+    end if;
+
+    if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
+
+-- second part of main fsm
+
+    case r.mstate is
+    when active =>
+      if v.hready = '1' then
+        v.mstate := midle;
+      end if;
+    when others => null;
+    end case;
+
+-- sdram refresh counter
+
+-- pragma translate_off
+    if not is_x(r.cfg.refresh) then
+-- pragma translate_on
+      if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
+        v.refresh := r.refresh - 1;
+        if (v.refresh(14) and not r.refresh(14))  = '1' then
+          v.refresh := r.cfg.refresh;
+          v.cfg.command := "100";
+          arefresh := '1';
+        end if;
+      end if;
+-- pragma translate_off
+    end if;
+-- pragma translate_on
+
+-- AHB register access
+-- if writing to IO space config regs. Just mapping write data to all config values in config reg
+    if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
+      if r.haddr(3 downto 2) = "00" then
+        if pageburst = 2 then v.cfg.pageburst :=  hwdata(17); end if;
+        v.cfg.command   :=  hwdata(20 downto 18);
+        v.cfg.csize     :=  hwdata(22 downto 21);
+        v.cfg.bsize     :=  hwdata(25 downto 23);
+        v.cfg.casdel    :=  hwdata(26);
+        v.cfg.trfc      :=  hwdata(29 downto 27);
+        v.cfg.trp       :=  hwdata(30);
+        v.cfg.renable   :=  hwdata(31);
+        v.cfg.refresh   :=  hwdata(14 downto 0);
+        v.refresh       :=  (others => '0');
+      elsif r.haddr(3 downto 2) = "01" then
+        if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
+        if r.cfg.pmode = "000" then
+          v.cfg.cke               :=  hwdata(30);
+        end if;
+        if r.cfg.mobileen(1) = '1' then
+          v.cfg.txsr              :=  hwdata(23 downto 20);
+          v.cfg.pmode             :=  hwdata(18 downto 16);
+          v.cfg.ds(3 downto 2)    :=  hwdata( 6 downto  5);
+          v.cfg.tcsr(3 downto 2)  :=  hwdata( 4 downto  3);
+          v.cfg.pasr(5 downto 3)  :=  hwdata( 2 downto  0);
+        end if;
+      end if;
+    end if;
+
+    -- Disable CS and DPD when Mobile SDR is Disabled
+    if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
+
+    -- Update EMR when ds, tcsr or pasr change
+    if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
+      if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
+      end if;
+      if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
+      end if;
+      if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
+        v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
+      end if;
+    end if;
+
+    regsd := (others => '0');
+    --reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
+    if r.haddr(3 downto 2) = "00" then
+      regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
+                             r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
+      if not lineburst then regsd(17) := '1'; end if;
+      regsd(16) := r.cfg.mobileen(1);
+      if BUS64 then regsd(15) := '1'; end if;
+      regsd(14 downto 0) := r.cfg.refresh;
+    elsif r.haddr(3 downto 2) = "01" then
+      regsd(31) := r.cfg.mobileen(0);
+      regsd(30) := r.cfg.cke;
+      regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
+                            r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
+    end if;
+
+    if (r.hsel and r.hio) = '1' then dout := regsd;
+    else
+      if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
+      else dout := r.hrdata(31 downto 0); end if;
+    end if;
+
+    v.nbdrive := not v.bdrive;
+
+    if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
+    else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
+
+-- reset
+
+    if rst = '0' then
+      v.sdstate       := sidle;
+      v.mstate        := midle;
+      v.istate        := iidle;
+      v.cmstate       := midle;
+      v.hsel          := '0';
+      v.cfg.command   := "000";
+      v.cfg.csize     := "01";
+      v.cfg.bsize     := "011";
+      v.cfg.casdel    :=  '1';
+      v.cfg.trfc      := "111";
+      if pwron = 1 then v.cfg.renable :=  '1';
+      else v.cfg.renable :=  '0'; end if;
+      v.cfg.trp       :=  '1';
+      v.dqm           := (others => '1');
+      v.sdwen         := '1';
+      v.rasn          := '1';
+      v.casn          := '1';
+      v.hready        := '1';
+      v.bsel          := '0';
+      v.startsd       := '0';
+      if (pageburst = 2) then
+        v.cfg.pageburst   :=  '0';
+      end if;
+      if mobile >= 2 then v.cfg.mobileen := "11";
+      elsif mobile = 1 then v.cfg.mobileen := "10";
+      else v.cfg.mobileen := "00"; end if;
+      v.cfg.txsr      := (others => '1');
+      v.cfg.pmode     := (others => '0');
+      v.cfg.ds        := (others => '0');
+      v.cfg.tcsr      := (others => '0');
+      v.cfg.pasr      := (others => '0');
+      if mobile >= 2 then v.cfg.cke := '0';
+      else v.cfg.cke       := '1'; end if;
+      v.sref_tmpcom   := "000";
+      v.idlecnt := (others => '1');
+    end if;
+
+    ri <= v;
+    ribdrive <= vbdrive;
+
+    ahbso.hready  <= r.hready;
+    ahbso.hresp   <= r.hresp;
+    ahbso.hrdata  <= ahbdrivedata(dout);
+
+  end process;
+
+  --sdo.sdcke     <= (others => '1');
+  sdo.sdcke     <= (others => r.cfg.cke);
+  ahbso.hconfig <= hconfig;
+  ahbso.hirq    <= (others => '0');
+  ahbso.hindex  <= hindex;
+  ahbso.hsplit  <= (others => '0');
+
+  -- Quick hack to get rid of undriven signal warnings. Check this for future
+  -- merge with main sdctrl.
+  drivehack : block
+  begin
+    sdo.qdrive <= '0';
+    sdo.nbdrive <= '0';
+    sdo.ce <= '0';
+    sdo.moben <= '0';
+    sdo.cal_rst <= '0';
+    sdo.oct <= '0';
+    sdo.xsdcsn <= (others => '1');
+    sdo.data(127 downto 16) <= (others => '0');
+    sdo.cb <= (others => '0');
+    sdo.ba <= (others => '0');
+    sdo.sdck <= (others => '0');
+    sdo.cal_en <= (others => '0');
+    sdo.cal_inc <= (others => '0');
+    sdo.cal_pll <= (others => '0');
+    sdo.odt <= (others => '0');
+    sdo.conf <= (others => '0');
+    sdo.vcbdrive <= (others => '0');
+    sdo.dqs_gate <= '0';
+    sdo.cbdqm <= (others => '0');
+    sdo.cbcal_en <= (others => '0');
+    sdo.cbcal_inc <= (others => '0');
+    sdo.read_pend <= (others => '0');
+    sdo.regwdata <= (others => '0');
+    sdo.regwrite <= (others => '0');
+  end block drivehack;
+
+  regs : process(clk, rst) begin
+    if rising_edge(clk) then
+      r <= ri; rbdrive <= ribdrive;
+      if rst = '0' then r.icnt <= (others => '0'); end if;
+    end if;
+    if (rst = '0') then
+      r.sdcsn  <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
+      if oepol = 0 then rbdrive <= (others => '1');
+      else rbdrive <= (others => '0'); end if;
+    end if;
+  end process;
+
+  rgen : if not SDINVCLK generate
+    sdo.address  <= r.address;
+    sdo.bdrive   <= r.nbdrive when oepol = 1 else r.bdrive;
+    sdo.vbdrive  <= zero32 & rbdrive;
+    sdo.sdcsn    <= r.sdcsn;
+    sdo.sdwen    <= r.sdwen;
+    sdo.dqm      <= "11111111" & r.dqm;
+    sdo.rasn     <= r.rasn;
+    sdo.casn     <= r.casn;
+
+    mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
+      sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
+    end generate;
+
+    wrdata : if not BUS16 generate
+      drivebus: for i in 0 to sdbits/64 generate
+        sdo.data(31+32*i downto 32*i) <= r.hwdata;
+      end generate;
+    end generate;
+  end generate;
+
+  ngen : if SDINVCLK generate
+    nregs : process(clk, rst) begin
+      if falling_edge(clk) then
+        sdo.address  <= r.address;
+        if oepol = 1 then sdo.bdrive <= r.nbdrive;
+        else sdo.bdrive <= r.bdrive; end if;
+        sdo.vbdrive  <= zero32 & rbdrive;
+        sdo.sdcsn    <= r.sdcsn;
+        sdo.sdwen    <= r.sdwen;
+        sdo.dqm      <= "11111111" & r.dqm;
+        sdo.rasn     <= r.rasn;
+        sdo.casn     <= r.casn;
+        if BUS16 then --mux data depending on Low/High HW
+          if (r.lhw ='1') then
+            sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
+          else
+            sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
+          end if;
+        end if;
+
+        if not BUS16 then
+          for i in 0 to sdbits/64 loop
+            sdo.data(31+32*i downto 32*i) <= r.hwdata;
+          end loop;
+        end if;
+      end if;
+      if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
+    end process;
+  end generate;
+
+-- pragma translate_off
+  bootmsg : report_version
+  generic map ("sdctrl16" & tost(hindex) &
+    ": PC133 SDRAM controller rev " & tost(REVISION));
+-- pragma translate_on
+
+end;
+
diff --git a/designs/Leon3-MiniSpartan6p/testbench.vhd b/designs/Leon3-MiniSpartan6p/testbench.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Leon3-MiniSpartan6p/testbench.vhd
@@ -0,0 +1,224 @@
+------------------------------------------------------------------------------
+--  LEON3 Demonstration design test bench
+--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+use work.debug.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+library grlib;
+use grlib.stdlib.all;
+
+use work.config.all;	-- configuration
+
+
+entity testbench is
+  generic (
+    fabtech   : integer := CFG_FABTECH;
+    memtech   : integer := CFG_MEMTECH;
+    padtech   : integer := CFG_PADTECH;
+    clktech   : integer := CFG_CLKTECH;
+    disas     : integer := CFG_DISAS;	-- Enable disassembly to console
+    dbguart   : integer := CFG_DUART;	-- Print UART on console
+    pclow     : integer := CFG_PCLOW;
+
+    clkperiod : integer := 20;		-- system clock period
+    romdepth  : integer := 22		-- rom address depth (flash 4 MB)
+ --   sramwidth  : integer := 32;		-- ram data width (8/16/32)
+ --   sramdepth  : integer := 20;		-- ram address depth
+ --   srambanks  : integer := 2		-- number of ram banks
+  );
+end;
+
+architecture behav of testbench is
+
+constant promfile  : string := "prom.srec";  -- rom contents
+constant sramfile  : string := "ram.srec";  -- ram contents
+constant sdramfile : string := "ram.srec"; -- sdram contents
+
+
+signal SW     : std_logic_vector(4 downto 1);
+signal clk : std_logic := '0';
+signal Rst    : std_logic := '0';			-- Reset
+constant ct : integer := clkperiod/2;
+
+signal address  : std_logic_vector(21 downto 0);
+signal data     : std_logic_vector(31 downto 24);
+
+signal romsn    : std_logic;
+signal oen      : std_logic;
+signal writen   : std_logic;
+signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
+signal dsurst   : std_logic;
+signal error    : std_logic;
+
+signal sdcke    : std_logic;
+signal sdcsn    : std_logic;
+signal sdwen    : std_logic;                       -- write en
+signal sdrasn   : std_logic;                       -- row addr stb
+signal sdcasn   : std_logic;                       -- col addr stb
+signal dram_ldqm : std_logic;
+signal dram_udqm : std_logic;
+signal sdclk    : std_logic;
+signal dram_ba  : std_logic_vector(1 downto 0);
+
+signal FTDI_RXF    :  std_logic;
+signal FTDI_TXE    :  std_logic;
+signal FTDI_SIWUA  :  std_logic;
+signal FTDI_WR     :  std_logic;
+signal FTDI_RD     :  std_logic;
+signal FTDI_D      :  std_logic_vector(7 downto 0):=(others=>'Z');
+
+constant lresp : boolean := false;
+
+
+signal sa      	: std_logic_vector(12 downto 0);
+signal sd   	: std_logic_vector(15 downto 0);
+
+
+begin
+
+  clk <= not clk after ct * 1 ns; --50 MHz clk
+  rst <= dsurst; --reset
+  dsuen <= '1';
+  dsubre <= '1'; -- inverted on the board
+  sw(1) <= rst;
+
+  d3 : entity work.leon3mp
+        generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
+        port map (
+            CLK50  => clk,
+            LEDS   => open,
+            SW     => SW,
+            dram_addr => sa,
+            dram_ba_0	=> dram_ba(0),
+            dram_ba_1	=> dram_ba(1),
+            dram_dq	=> sd(15 downto 0),
+            dram_clk  	=> sdclk,
+            dram_cke  	=> sdcke,
+            dram_cs_n   => sdcsn,
+            dram_we_n  	=> sdwen,
+            dram_ras_n  => sdrasn,
+            dram_cas_n  => sdcasn,
+            dram_ldqm	  => dram_ldqm,
+            dram_udqm	  => dram_udqm,
+            uart_txd  	=> dsutx,
+            uart_rxd  	=> dsurx,
+
+            FTDI_RXF    => FTDI_RXF,
+            FTDI_TXE    => FTDI_TXE,
+            FTDI_SIWUA  => FTDI_SIWUA,
+            FTDI_WR     => FTDI_WR,
+            FTDI_RD     => FTDI_RD,
+            FTDI_D      => FTDI_D
+            );
+
+    u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 9, index => 1024, fname => sdramfile)
+	PORT MAP(
+            Dq => sd(15 downto 0), Addr => sa(12 downto 0),
+            Ba => dram_ba, Clk => sdclk, Cke => sdcke,
+            Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
+            Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
+
+
+
+  error <= 'H';			  -- ERROR pull-up
+
+   iuerr : process
+   begin
+     wait for 2500 ns;
+     if to_x01(error) = '1' then wait on error; end if;
+     assert (to_x01(error) = '1')
+       report "*** IU in error mode, simulation halted ***"
+         severity failure ;
+   end process;
+
+  data <= buskeep(data) after 5 ns;
+  sd <= buskeep(sd) after 5 ns;
+
+  testftdi : process
+    procedure ftdi_write(signal FTDI_RXF : out std_logic; signal FTDI_RD : in std_logic;  value : integer; signal FTDI_D: out std_logic_vector(7 downto 0)) is
+    begin
+        FTDI_RXF <= '0';
+        wait until FTDI_RD = '0';
+        wait for 14 ns;
+        FTDI_D <= conv_std_logic_vector(value,8);
+        wait for 16 ns;
+        FTDI_D <= (others=>'Z');
+        wait until FTDI_RD = '1';
+        FTDI_RXF <= '1';
+        wait for 3 ns;
+    end;
+    procedure dcom_ftdi_write_reg(signal FTDI_RXF : out std_logic; signal FTDI_RD : in std_logic; address : std_logic_vector(31 downto 0); value :  std_logic_vector(31 downto 0); signal FTDI_D: out std_logic_vector(7 downto 0)) is
+    begin
+        ftdi_write(FTDI_RXF,FTDI_RD,16#C0#,FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(31 downto 24))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(23 downto 16))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(15 downto 8))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(7 downto 0))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(value(31 downto 24))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(value(23 downto 16))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(value(15 downto 8))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(value(7 downto 0))),FTDI_D);
+
+    end;
+    procedure dcom_ftdi_read_reg(signal FTDI_RXF : out std_logic; signal FTDI_RD : in std_logic; address : std_logic_vector(31 downto 0); signal FTDI_D: out std_logic_vector(7 downto 0)) is
+    begin
+        ftdi_write(FTDI_RXF,FTDI_RD,16#80#,FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(31 downto 24))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(23 downto 16))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(15 downto 8))),FTDI_D);
+        ftdi_write(FTDI_RXF,FTDI_RD,to_integer(UNSIGNED(address(7 downto 0))),FTDI_D);
+    end;
+    begin
+      FTDI_D <= (others=>'Z');
+      dsurst <= '0';
+      FTDI_RXF <= '1';
+      wait for 100 ns;
+      dsurst <= '1';
+      wait for 100 ns;
+      dcom_ftdi_read_reg(FTDI_RXF,FTDI_RD,X"80000000",FTDI_D);
+      dcom_ftdi_read_reg(FTDI_RXF,FTDI_RD,X"80000004",FTDI_D);
+      dcom_ftdi_read_reg(FTDI_RXF,FTDI_RD,X"80000008",FTDI_D);
+      dcom_ftdi_read_reg(FTDI_RXF,FTDI_RD,X"8000000C",FTDI_D);
+      dcom_ftdi_read_reg(FTDI_RXF,FTDI_RD,X"80000010",FTDI_D);
+      wait;
+ end process;
+
+ txe: process
+  begin
+    FTDI_TXE <= '0';
+    wait until FTDI_WR = '0';
+    wait for 14 ns;
+    FTDI_TXE <= '1';
+    wait for 49 ns;
+ end process;
+end ;
+
diff --git a/designs/SPWBrick-MiniSpartan6p/Makefile b/designs/SPWBrick-MiniSpartan6p/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/Makefile
@@ -0,0 +1,77 @@
+VHDLIB=../..
+SELFDIR := $(dir $(lastword $(MAKEFILE_LIST)))
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=leon3mp
+BOARD=MiniSpartan6p
+DESIGN=leon3-MiniSpartan6p
+include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=withSPW.ucf
+UCF_PLANAHEAD=$(UCF)
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+XSTOPT=-uc leon3mp.xcf
+SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
+
+
+VHDLOPTSYNFILES = sdctrl16.vhd config.vhd leon3mp.vhd
+
+VHDLSIMFILES=mt48lc16m16a2.vhd testbench.vhd
+
+SIMTOP=testbench
+SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
+
+TECHLIBS = unisim
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann  usbhc fmf ftlib gsi
+
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs can pwm greth coremp7 ac97 atf \
+	grlfpc \
+	./dsp/lpp_fft_rtax \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lpp_sim/CY7C1061DV33 \
+	./lpp_uart \
+	./lpp_usb \
+	./dsp/lpp_fft \
+	./lpp_leon3_soc \
+	./lpp_debug_lfr
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd \
+	lpp_lfr_ms_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd \
+	lpp_lfr_ms.vhd \
+	lpp_lfr_sim_pkg.vhd \
+	mtie_maps.vhd \
+	ftsrctrlc.vhd \
+	ftsdctrl.vhd \
+	ftsrctrl8.vhd \
+	ftmctrl.vhd \
+	ftsdctrl64.vhd \
+	ftahbram.vhd \
+	ftahbram2.vhd \
+	sramft.vhd \
+	nandfctrlx.vhd
+
+include $(GRLIB)/bin/Makefile
+
+##################  project specific targets ##########################
+
+load-ram:
+	xc3sprog -c ftdi -p0 leon3mp.bit
+
+load-flash:
+	xc3sprog -c ftdi -p0 $(VHDLIB)/boards/$(BOARD)/bscan_spi_s6lx25_ftg256.bit
+	xc3sprog -c ftdi -I leon3mp.bit
diff --git a/designs/SPWBrick-MiniSpartan6p/README.md b/designs/SPWBrick-MiniSpartan6p/README.md
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/README.md
@@ -0,0 +1,66 @@
+This LEON3 design is tailored to the Scarab Hardware [MiniSpartan6+](https://www.scarabhardware.com/minispartan6/) board.
+
+Simulation and synthesis
+------------------------
+
+This design tries to use as much as possible free (as in freedom) tools and at least free (as in free beer) when impossible.
+
+
+Note that the simulation doesn't work as expected yet.
+
+
+To build the design:
+```bash
+make ise
+```
+
+To load into FPGA RAM:
+```bash
+make load-ram
+```
+
+To load into FPGA Flash:
+```bash
+make load-flash
+```
+
+Design specifics
+----------------
+
+* The AHB and processor is clocked from the 50 MHz clock.
+
+* The SDRAM is working with the sdctrl16 memory controller taken from leon3-altera-de2-ep2c35 design.
+
+* The UART DSU interface ie enabled and connected to interface B of ft2232H chip.
+  Start GRMON with -uart /dev/ttyUSB1
+
+* Output from GRMON2 should look similar to this:
+
+```bash
+  GRMON2 LEON debug monitor v2.0.80-beta 64-bit eval version
+  
+  Copyright (C) 2016 Cobham Gaisler - All rights reserved.
+  For latest updates, go to http://www.gaisler.com/
+  Comments or bug-reports to support@gaisler.com
+  
+  This eval version will expire on 18/04/2017
+
+  using port /dev/ttyUSB1 @ 115200 baud
+  GRLIB build version: 4164
+  Detected frequency:  50 MHz
+  
+  Component                            Vendor
+  LEON3 SPARC V8 Processor             Cobham Gaisler
+  AHB Debug UART                       Cobham Gaisler
+  AHB/APB Bridge                       Cobham Gaisler
+  LEON3 Debug Support Unit             Cobham Gaisler
+  PC133 SDRAM Controller               Cobham Gaisler
+  Multi-processor Interrupt Ctrl.      Cobham Gaisler
+  Modular Timer Unit                   Cobham Gaisler
+  General Purpose I/O port             Cobham Gaisler
+  
+  Use command 'info sys' to print a detailed report of attached cores
+
+grmon2> 
+
+```
\ No newline at end of file
diff --git a/designs/SPWBrick-MiniSpartan6p/SPW_Pinout.txt b/designs/SPWBrick-MiniSpartan6p/SPW_Pinout.txt
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/SPW_Pinout.txt
@@ -0,0 +1,11 @@
+F0 -> L46P   -> DOUT+  -> 9 -> Grey
+F1 -> L46N   -> DOUT-  -> 5 -> Yellow
+
+F5 -> L40P   -> SOUT+  -> 8 -> Violet
+F7 -> L40N   -> SOUT-  -> 4 -> Orange
+
+F3 -> L53P   -> SIN+  -> 2 -> Brown
+F6 -> L53N   -> SIN-  -> 7 -> Blue
+
+F9  -> L39N   -> DIN-  -> 6 -> Green
+F10 -> L39P   -> DIN+  -> 1 -> Black
diff --git a/designs/SPWBrick-MiniSpartan6p/config.vhd b/designs/SPWBrick-MiniSpartan6p/config.vhd
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/config.vhd
@@ -0,0 +1,162 @@
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+-- Technology and synthesis options
+  constant CFG_FABTECH : integer := spartan6;
+  constant CFG_MEMTECH : integer := spartan6;
+  constant CFG_PADTECH : integer := spartan6;
+  constant CFG_TRANSTECH : integer := GTP0;
+  constant CFG_NOASYNC : integer := 0;
+  constant CFG_SCAN : integer := 0;
+-- Clock generator
+  constant CFG_CLKTECH : integer := spartan6;
+  constant CFG_CLKMUL : integer := (3);
+  constant CFG_CLKDIV : integer := (2);
+  constant CFG_OCLKDIV : integer := 1;
+  constant CFG_OCLKBDIV : integer := 0;
+  constant CFG_OCLKCDIV : integer := 0;
+  constant CFG_PCIDLL : integer := 0;
+  constant CFG_PCISYSCLK: integer := 0;
+  constant CFG_CLK_NOFB : integer := 0;
+-- LEON3 processor core
+  constant CFG_LEON3 : integer := 1;
+  constant CFG_NCPU : integer := (1);
+  constant CFG_NWIN : integer := (8);
+  constant CFG_V8 : integer := 2 + 4*0;
+  constant CFG_MAC : integer := 0;
+  constant CFG_BP : integer := 1;
+  constant CFG_SVT : integer := 1;
+  constant CFG_RSTADDR : integer := 16#00000#;
+  constant CFG_LDDEL : integer := (2);
+  constant CFG_NOTAG : integer := 1;
+  constant CFG_NWP : integer := (0);
+  constant CFG_PWD : integer := 0*2;
+  constant CFG_FPU : integer := 0 + 16*0 + 32*0;
+  constant CFG_GRFPUSH : integer := 0;
+  constant CFG_ICEN : integer := 1;
+  constant CFG_ISETS : integer := 1;
+  constant CFG_ISETSZ : integer := 8;
+  constant CFG_ILINE : integer := 8;
+  constant CFG_IREPL : integer := 0;
+  constant CFG_ILOCK : integer := 0;
+  constant CFG_ILRAMEN : integer := 0;
+  constant CFG_ILRAMADDR: integer := 16#8E#;
+  constant CFG_ILRAMSZ : integer := 1;
+  constant CFG_DCEN : integer := 1;
+  constant CFG_DSETS : integer := 1;
+  constant CFG_DSETSZ : integer := 8;
+  constant CFG_DLINE : integer := 8;
+  constant CFG_DREPL : integer := 0;
+  constant CFG_DLOCK : integer := 0;
+  constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
+  constant CFG_DFIXED : integer := 16#0#;
+  constant CFG_DLRAMEN : integer := 0;
+  constant CFG_DLRAMADDR: integer := 16#8F#;
+  constant CFG_DLRAMSZ : integer := 1;
+  constant CFG_MMUEN : integer := 0;
+  constant CFG_ITLBNUM : integer := 8;
+  constant CFG_DTLBNUM : integer := 2;
+  constant CFG_TLB_TYPE : integer := 1 + 0*2;
+  constant CFG_TLB_REP : integer := 1;
+  constant CFG_MMU_PAGE : integer := 0;
+  constant CFG_DSU : integer := 1;
+  constant CFG_ITBSZ : integer := 0 + 64*0;
+  constant CFG_ATBSZ : integer := 0;
+  constant CFG_AHBPF : integer := 0;
+  constant CFG_LEON3FT_EN : integer := 0;
+  constant CFG_IUFT_EN : integer := 0;
+  constant CFG_FPUFT_EN : integer := 0;
+  constant CFG_RF_ERRINJ : integer := 0;
+  constant CFG_CACHE_FT_EN : integer := 0;
+  constant CFG_CACHE_ERRINJ : integer := 0;
+  constant CFG_LEON3_NETLIST: integer := 0;
+  constant CFG_DISAS : integer := 0 + 0;
+  constant CFG_PCLOW : integer := 2;
+  constant CFG_STAT_ENABLE : integer := 0;
+  constant CFG_STAT_CNT : integer := 1;
+  constant CFG_STAT_NMAX : integer := 0;
+  constant CFG_STAT_DSUEN : integer := 0;
+  constant CFG_NP_ASI : integer := 0;
+  constant CFG_WRPSR : integer := 0;
+  constant CFG_ALTWIN : integer := 0;
+  constant CFG_REX : integer := 0;
+-- AMBA settings
+  constant CFG_DEFMST : integer := (0);
+  constant CFG_RROBIN : integer := 1;
+  constant CFG_SPLIT : integer := 1;
+  constant CFG_FPNPEN : integer := 0;
+  constant CFG_AHBIO : integer := 16#FFF#;
+  constant CFG_APBADDR : integer := 16#800#;
+  constant CFG_AHB_MON : integer := 0;
+  constant CFG_AHB_MONERR : integer := 0;
+  constant CFG_AHB_MONWAR : integer := 0;
+  constant CFG_AHB_DTRACE : integer := 0;
+-- DSU UART
+  constant CFG_AHB_UART : integer := 1;
+-- JTAG based DSU interface
+  constant CFG_AHB_JTAG : integer := 1;
+-- Xilinx MIG
+  constant CFG_MIG_DDR2 : integer := 1;
+  constant CFG_MIG_RANKS : integer := (1);
+  constant CFG_MIG_COLBITS : integer := (10);
+  constant CFG_MIG_ROWBITS : integer := (13);
+  constant CFG_MIG_BANKBITS: integer := (2);
+  constant CFG_MIG_HMASK : integer := 16#FC0#;
+-- AHB ROM
+  constant CFG_AHBROMEN : integer := 1;
+  constant CFG_AHBROPIP : integer := 0;
+  constant CFG_AHBRODDR : integer := 16#000#;
+  constant CFG_ROMADDR : integer := 16#100#;
+  constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
+-- AHB RAM
+  constant CFG_AHBRAMEN : integer := 1;
+  constant CFG_AHBRSZ : integer := 4;
+  constant CFG_AHBRADDR : integer := 16#A00#;
+  constant CFG_AHBRPIPE : integer := 0;
+-- UART 1
+  constant CFG_UART1_ENABLE : integer := 1;
+  constant CFG_UART1_FIFO : integer := 4;
+-- LEON3 interrupt controller
+  constant CFG_IRQ3_ENABLE : integer := 1;
+  constant CFG_IRQ3_NSEC : integer := 0;
+-- Modular timer
+  constant CFG_GPT_ENABLE : integer := 1;
+  constant CFG_GPT_NTIM : integer := (2);
+  constant CFG_GPT_SW : integer := (8);
+  constant CFG_GPT_TW : integer := (32);
+  constant CFG_GPT_IRQ : integer := (8);
+  constant CFG_GPT_SEPIRQ : integer := 1;
+  constant CFG_GPT_WDOGEN : integer := 0;
+  constant CFG_GPT_WDOG : integer := 16#0#;
+-- GPIO port
+  constant CFG_GRGPIO_ENABLE : integer := 1;
+  constant CFG_GRGPIO_IMASK : integer := 16#0000#;
+  constant CFG_GRGPIO_WIDTH : integer := 1;
+
+-- SPI controller
+  constant CFG_SPICTRL_ENABLE : integer := 1;
+  constant CFG_SPICTRL_NUM : integer := (1);
+  constant CFG_SPICTRL_SLVS : integer := (1);
+  constant CFG_SPICTRL_FIFO : integer := (2);
+  constant CFG_SPICTRL_SLVREG : integer := 1;
+  constant CFG_SPICTRL_ODMODE : integer := 1;
+  constant CFG_SPICTRL_AM : integer := 0;
+  constant CFG_SPICTRL_ASEL : integer := 0;
+  constant CFG_SPICTRL_TWEN : integer := 0;
+  constant CFG_SPICTRL_MAXWLEN : integer := (0);
+  constant CFG_SPICTRL_SYNCRAM : integer := 0;
+  constant CFG_SPICTRL_FT : integer := 0;
+
+-- GRLIB debugging
+  constant CFG_DUART : integer := 0;
+end;
diff --git a/designs/SPWBrick-MiniSpartan6p/leon3mp.vhd b/designs/SPWBrick-MiniSpartan6p/leon3mp.vhd
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/leon3mp.vhd
@@ -0,0 +1,350 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.NUMERIC_STD.ALL;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library techmap;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+--pragma translate_off
+use gaisler.sim.all;
+--pragma translate_on
+library opencores;
+use opencores.spwpkg.all;
+use opencores.spwambapkg.all;
+
+use work.config.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity leon3mp is
+  generic (
+    fabtech  : integer := CFG_FABTECH;
+    memtech  : integer := CFG_MEMTECH;
+    padtech  : integer := CFG_PADTECH;
+    clktech  : integer := CFG_CLKTECH;
+    disas    : integer := CFG_DISAS;     -- Enable disassembly to console
+    dbguart  : integer := CFG_DUART;     -- Print UART on console
+    pclow    : integer := CFG_PCLOW
+    );
+  port (
+    CLK50  : in std_logic;
+    LEDS   : inout std_logic_vector(7 downto 0);
+    SW     : in std_logic_vector(4 downto 1);
+    dram_addr : out std_logic_vector(12 downto 0);
+    dram_ba_0	: out std_logic;
+    dram_ba_1	: out std_logic;
+    dram_dq	: inout std_logic_vector(15 downto 0);
+
+    dram_clk  	: out std_logic;
+    dram_cke  	: out std_logic;
+    dram_cs_n  	: out std_logic;
+    dram_we_n  	: out std_logic;        	-- sdram write enable
+    dram_ras_n  : out std_logic;               	-- sdram ras
+    dram_cas_n  : out std_logic;               	-- sdram cas
+    dram_ldqm	  : out std_logic;		-- sdram ldqm
+    dram_udqm	  : out std_logic;		-- sdram udqm
+    uart_txd  	: out std_logic;		-- DSU tx data
+    uart_rxd  	: in  std_logic;		-- DSU rx data
+
+    spw_rxdp      : in  std_logic;
+    spw_rxdn      : in  std_logic;
+    spw_rxsp      : in  std_logic;
+    spw_rxsn      : in  std_logic;
+    spw_txdp      : out std_logic;
+    spw_txdn      : out std_logic;
+    spw_txsp      : out std_logic;
+    spw_txsn      : out std_logic
+    );
+end;
+
+architecture rtl of leon3mp is
+  signal resetn : std_logic;
+  signal clkm, rstn, rstraw, rst : std_logic;
+  signal clkm_inv : std_logic := '0';
+
+  signal cptr :  std_logic_vector(29 downto 0);
+  constant BOARD_FREQ : integer := 25000;                                -- CLK input frequency in KHz
+  constant CPU_FREQ   : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
+  signal sdi   : sdctrl_in_type;
+  signal sdo   : sdctrl_out_type;
+
+--AMBA bus standard interface signals--
+  signal apbi  : apb_slv_in_type;
+  signal apbo  : apb_slv_out_vector := (others => apb_none);
+  signal ahbsi : ahb_slv_in_type;
+  signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+  signal ahbmi : ahb_mst_in_type;
+  signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+  signal cgi : clkgen_in_type;
+  signal cgo : clkgen_out_type;
+
+  signal dui : uart_in_type;
+  signal duo : uart_out_type;
+
+  signal irqi : irq_in_vector(0 to CFG_NCPU-1);
+  signal irqo : irq_out_vector(0 to CFG_NCPU-1);
+
+  signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
+  signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
+
+  signal dsui : dsu_in_type;
+  signal dsuo : dsu_out_type;
+
+
+  signal gpti : gptimer_in_type;
+  signal gpto : gptimer_out_type;
+
+  signal gpioi_0 : gpio_in_type;
+  signal gpioo_0 : gpio_out_type;
+
+  signal dsubren : std_logic :='0';
+
+  signal spw_di: std_logic;
+  signal spw_si: std_logic;
+  signal spw_do: std_logic;
+  signal spw_so: std_logic;
+  signal spw_tick_in: std_logic;
+
+  component sdctrl16
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end component;
+
+begin
+  resetn <= SW(1);
+
+  clk_pad : clkpad generic map (tech => padtech) port map (CLK50, clkm);
+  clkm_inv <= not clkm;
+
+  resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
+  rst0 : rstgen			-- reset generator (reset is active LOW)
+    port map (rst, clkm, '1', rstn, rstraw);
+
+
+----------------------------------------------------------------------
+---  AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
+  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+	nahbm => CFG_NCPU+CFG_AHB_UART+1, nahbs => 8)
+
+  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+-----  LEON3 processor and DSU ---------------------------------------
+----------------------------------------------------------------------
+
+  cpu : for i in 0 to CFG_NCPU-1 generate
+    nosh : if CFG_GRFPUSH = 0 generate
+      u0 : leon3s 		-- LEON3 processor
+      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
+	0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
+	0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
+      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+    		irqi(i), irqo(i), dbgi(i), dbgo(i));
+    end generate;
+  end generate;
+
+  --ledr[0] lit when leon 3 debugvector signals error
+  dsugen : if CFG_DSU = 1 generate
+    dsu0 : dsu3			-- LEON3 Debug Support Unit (slave)
+    generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+       ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+    port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+    dsui.enable <= '1';
+
+  end generate;
+  nodsu : if CFG_DSU = 0 generate
+    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; --no timer freeze, no light.
+  end generate;
+
+  dcomgen : if CFG_AHB_UART = 1 generate
+    dcom0: ahbuart		-- Debug UART
+    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
+    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
+  end generate;
+  uart_txd <= duo.txd;
+  dui.rxd <= uart_rxd;
+
+
+----------------------------------------------------------------------
+---  Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+
+    sdc : sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#, -- hmask => 16#C00#,
+	      ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
+	      sdbits => 16, pageburst => 2)
+      port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
+      sa_pad : outpadv generic map (width => 13, tech => padtech)
+	   port map (dram_addr, sdo.address(14 downto 2));
+      ba0_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_0, sdo.address(15));
+      ba1_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_1, sdo.address(16));
+      sd_pad : iopadvv generic map (width => 16, tech => padtech)
+	   port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
+      sdcke_pad : outpad generic map (tech => padtech)
+	   port map (dram_cke, sdo.sdcke(0));
+      sdwen_pad : outpad generic map (tech => padtech)
+	   port map (dram_we_n, sdo.sdwen);
+      sdcsn_pad : outpad generic map (tech => padtech)
+	   port map (dram_cs_n, sdo.sdcsn(0));
+      sdras_pad : outpad generic map (tech => padtech)
+	   port map (dram_ras_n, sdo.rasn);
+      sdcas_pad : outpad generic map (tech => padtech)
+	   port map (dram_cas_n, sdo.casn);
+      sdldqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_ldqm, sdo.dqm(0) );
+      sdudqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_udqm, sdo.dqm(1));
+      dram_clk_pad : outpad generic map (tech => padtech)
+	   port map (dram_clk, clkm_inv);
+
+----------------------------------------------------------------------
+---  APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+  apb0 : apbctrl				-- AHB/APB bridge
+  generic map (hindex => 1, haddr => CFG_APBADDR)
+  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
+
+----------------------------------------------------------------------------------------
+
+    irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+    irqctrl0 : irqmp			-- interrupt controller
+    generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
+    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+  end generate;
+  irq3 : if CFG_IRQ3_ENABLE = 0 generate
+    x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate;
+    apbo(2) <= apb_none;
+  end generate;
+
+  --Timer unit, generates interrupts when a timer underflow.
+  gpt : if CFG_GPT_ENABLE /= 0 generate
+    timer0 : gptimer 			-- timer unit
+    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+	nbits => CFG_GPT_TW)
+    port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
+    gpti <= gpti_dhalt_drive(dsuo.tstop);
+  end generate;
+  notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+    gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GR GPIO0 unit
+    grgpio0: grgpio
+      generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => 8)
+      port map( rstn, clkm, apbi, apbo(9), gpioi_0, gpioo_0);
+      pio_pads : for i in 0 to 7 generate
+        pio_pad : iopad generic map (tech => padtech)
+            port map (LEDS(i), gpioo_0.dout(i), gpioo_0.oen(i), gpioi_0.din(i));
+      end generate;
+  end generate;
+  nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
+
+
+-----------------------------------------------------------------------
+---  SpaceWire Light --------------------------------------------------
+-----------------------------------------------------------------------
+
+   spw0: spwamba
+      generic map (
+         tech        => memtech,
+         hindex      => 2,
+         pindex      => 10,
+         paddr       => 10,
+         pirq        => 10,
+         sysfreq     => 50.0e6,
+         txclkfreq   => 10.0e6,
+         rximpl      => impl_generic,
+         rxchunk     => 1,
+         tximpl      => impl_generic,
+         timecodegen => true,
+         rxfifosize  => 11,
+         txfifosize  => 11,
+         desctablesize => 10,
+         maxburst    => 3 )
+      port map (
+         clk     => clkm,
+         rxclk   => clkm,
+         txclk   => clkm,
+         rstn    => rstn,
+         apbi    => apbi,
+         apbo    => apbo(10),
+         ahbi    => ahbmi,
+         ahbo    => ahbmo(2),
+         tick_in => spw_tick_in,
+         tick_out => open,
+         spw_di  => spw_di,
+         spw_si  => spw_si,
+         spw_do  => spw_do,
+         spw_so  => spw_so );
+
+   spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
+
+   spw_rxd_pad: inpad_ds
+      generic map (padtech, lvds, x33v)
+      port map (spw_rxdp, spw_rxdn, spw_di);
+   spw_rxs_pad: inpad_ds
+      generic map (padtech, lvds, x33v)
+      port map (spw_rxsp, spw_rxsn, spw_si);
+   -- spw_txd_pad: outpad_ds
+   --    generic map (padtech, lvds, x33v)
+   --    port map (spw_txdp, spw_txdn, spw_do, '0');
+   -- spw_txs_pad: outpad_ds
+   --    generic map (padtech, lvds, x33v)
+   --    port map (spw_txsp, spw_txsn, spw_so, '0');
+
+
+spw_txdp_pad : outpad generic map (tech => padtech)
+	   port map (spw_txdp, spw_do);
+spw_txdn_pad : outpad generic map (tech => padtech)
+	   port map (spw_txdn, not spw_do);
+
+spw_txsp_pad : outpad generic map (tech => padtech)
+	   port map (spw_txsp, spw_so);
+spw_txsn_pad : outpad generic map (tech => padtech)
+	   port map (spw_txsn, not spw_so);
+
+end rtl;
+
diff --git a/designs/SPWBrick-MiniSpartan6p/leon3mp.xcf b/designs/SPWBrick-MiniSpartan6p/leon3mp.xcf
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/leon3mp.xcf
@@ -0,0 +1,4 @@
+
+NET CLK50 	PERIOD = 20.0 ;
+
+
diff --git a/designs/SPWBrick-MiniSpartan6p/mt48lc16m16a2.vhd b/designs/SPWBrick-MiniSpartan6p/mt48lc16m16a2.vhd
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/mt48lc16m16a2.vhd
@@ -0,0 +1,1550 @@
+
+--*****************************************************************************
+--
+-- Micron Semiconductor Products, Inc.
+--
+-- Copyright 1997, Micron Semiconductor Products, Inc.
+-- All rights reserved.
+--
+--*****************************************************************************
+
+-- pragma translate_off
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use std.textio.all;
+
+PACKAGE mti_pkg IS
+
+    FUNCTION  To_StdLogic (s : BIT) RETURN STD_LOGIC;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
+    PROCEDURE TO_BITVECTOR  (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
+
+
+END mti_pkg;
+
+PACKAGE BODY mti_pkg IS
+
+    -- Convert BIT to STD_LOGIC
+    FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
+    BEGIN
+            CASE s IS
+                WHEN '0' => RETURN ('0');
+                WHEN '1' => RETURN ('1');
+                WHEN OTHERS => RETURN ('0');
+            END CASE;
+    END;
+
+    -- Convert STD_LOGIC to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        IF input = '1' THEN
+            result := weight;
+        ELSE
+            result := 0;                                            -- if unknowns, default to logic 0
+        END IF;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert BIT_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert STD_LOGIC_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Conver INTEGER to BIT_VECTOR
+    PROCEDURE  TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
+    VARIABLE work,offset,outputlen,j : INTEGER := 0;
+    BEGIN
+        --length of vector
+        IF output'LENGTH > 32 THEN		--'
+            outputlen := 32;
+            offset := output'LENGTH - 32;		--'
+            IF input >= 0 THEN
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '0';		--'
+                END LOOP;
+            ELSE
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '1';		--'		
+                END LOOP;
+            END IF;
+        ELSE
+            outputlen := output'LENGTH; 		--'
+        END IF;
+        --positive value
+        IF (input >= 0) THEN
+            work := input;
+            j := outputlen - 1;
+            FOR i IN 1 to 32 LOOP
+                IF j >= 0 then
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    END IF;
+                END IF;
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '0'; 		--'
+            END IF;
+        --negative value
+        ELSE
+            work := (-input) - 1;
+            j := outputlen - 1;
+            FOR i IN 1 TO 32 LOOP
+                IF j>= 0 THEN
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    END IF;
+                END IF;    
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '1'; 		--'
+            END IF;
+        END IF;
+    END TO_BITVECTOR;
+
+END mti_pkg;   
+
+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT48LC16M16A2.VHD
+--       Version: 0.0g
+--          Date: June 29th, 2000
+--         Model: Behavioral
+--     Simulator: Model Technology (PC version 5.3 PE)
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256Mb SDRAM
+--
+--    Limitation: - Doesn't check for 4096-cycle refresh 		--'
+--
+--          Note: - Set simulator resolution to "ps" accuracy
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev   Author          Phone         Date        Changes
+--  ----  ----------------------------  ----------  -------------------------------------
+--  0.0g  Son Huynh       208-368-3825  06/29/2000  Add Load/Dump memory array
+--        Micron Technology Inc.                    Modify tWR + tRAS timing check
+--
+--  0.0f  Son Huynh       208-368-3825  07/08/1999  Fix tWR = 1 Clk + 7.5 ns (Auto)
+--        Micron Technology Inc.                    Fix tWR = 15 ns (Manual)
+--                                                  Fix tRP (Autoprecharge to AutoRefresh)
+--
+--  0.0c  Son P. Huynh    208-368-3825  04/08/1999  Fix tWR + tRP in Write with AP
+--        Micron Technology Inc.                    Fix tRC check in Load Mode Register
+--
+--  0.0b  Son P. Huynh    208-368-3825  01/06/1998  Derive from 64Mb SDRAM model
+--        Micron Technology Inc.
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY STD;
+    USE STD.TEXTIO.ALL;
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY WORK;
+    USE WORK.MTI_PKG.ALL;
+    use std.textio.all;
+
+library grlib;
+use grlib.stdlib.all;
+use grlib.stdio.all;
+
+ENTITY mt48lc16m16a2 IS
+    GENERIC (
+        -- Timing Parameters for -75 (PC133) and CAS Latency = 2
+        tAC       : TIME    :=  6.0 ns;
+        tHZ       : TIME    :=  7.0 ns;
+        tOH       : TIME    :=  2.7 ns;
+        tMRD      : INTEGER :=  2;          -- 2 Clk Cycles
+        tRAS      : TIME    := 44.0 ns;
+        tRC       : TIME    := 66.0 ns;
+        tRCD      : TIME    := 20.0 ns;
+        tRP       : TIME    := 20.0 ns;
+        tRRD      : TIME    := 15.0 ns;
+        tWRa      : TIME    :=  7.5 ns;     -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
+        tWRp      : TIME    := 15.0 ns;     -- A2 Version - Precharge mode only (15 ns)
+
+        tAH       : TIME    :=  0.8 ns;
+        tAS       : TIME    :=  1.5 ns;
+        tCH       : TIME    :=  2.5 ns;
+        tCL       : TIME    :=  2.5 ns;
+        tCK       : TIME    := 10.0 ns;
+        tDH       : TIME    :=  0.8 ns;
+        tDS       : TIME    :=  1.5 ns;
+        tCKH      : TIME    :=  0.8 ns;
+        tCKS      : TIME    :=  1.5 ns;
+        tCMH      : TIME    :=  0.8 ns;
+        tCMS      : TIME    :=  1.5 ns;
+
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        col_bits  : INTEGER :=  9;
+        index     : INTEGER :=  0;
+	fname     : string := "ram.srec"	-- File to read from
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        Ba    : IN    STD_LOGIC_VECTOR := "00";
+        Clk   : IN    STD_LOGIC := '0';
+        Cke   : IN    STD_LOGIC := '1';
+        Cs_n  : IN    STD_LOGIC := '1';
+        Ras_n : IN    STD_LOGIC := '1';
+        Cas_n : IN    STD_LOGIC := '1';
+        We_n  : IN    STD_LOGIC := '1';
+        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
+    );
+END mt48lc16m16a2;
+
+ARCHITECTURE behave OF mt48lc16m16a2 IS
+    TYPE   State       IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
+    TYPE   Array4xI    IS ARRAY (3 DOWNTO 0) OF INTEGER;
+    TYPE   Array4xT    IS ARRAY (3 DOWNTO 0) OF TIME;
+    TYPE   Array4xB    IS ARRAY (3 DOWNTO 0) OF BIT;
+    TYPE   Array4x2BV  IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
+    TYPE   Array4xCBV  IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
+    TYPE   Array_state IS ARRAY (4 DOWNTO 0) OF State;
+    SIGNAL Operation : State := NOP;
+    SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
+    SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
+    SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
+    SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
+    SIGNAL Write_burst_mode : BIT := '0';
+    SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
+
+    -- Checking internal wires
+    SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
+    SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
+    SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+
+BEGIN
+    -- CS# Decode
+    WITH Cs_n SELECT
+        Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        We_in  <= TO_BIT (We_n,  '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <=     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
+    Prech_enable    <= NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <=     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <=     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_1  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+
+    -- Write Burst Mode
+    Write_burst_mode <= Mode_reg(9);
+
+    -- RAS Clock for checking tWR and tRP
+    PROCESS
+        variable Clk0, Clk1 : integer := 0;
+    begin
+        RAS_clk <= '1';
+        wait for 0.5 ns;
+        RAS_clk <= '0';
+        wait for 0.5 ns;
+        if Clk0 > 100 or Clk1 > 100 then
+            wait;
+        else
+            if Clk = '1' and Cke = '1' then
+                Clk0 := 0;
+                Clk1 := Clk1 + 1;
+            elsif Clk = '0' and Cke = '1' then
+                Clk0 := Clk0 + 1;
+                Clk1 := 0;
+            end if;
+        end if;
+    END PROCESS;
+
+    -- System Clock
+    int_clk : PROCESS (Clk)
+        begin
+            IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN 		--'
+                CkeZ <= TO_BIT(Cke, '1');
+            END IF;
+            Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
+    END PROCESS;
+
+    state_register : PROCESS
+        -- NOTE: The extra bits in RAM_TYPE is for checking memory access.  A logic 1 means
+        --       the location is in use.  This will be checked when doing memory DUMP.
+        TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
+        TYPE ram_pntr IS ACCESS ram_type;
+        TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
+        VARIABLE Bank0 : ram_stor;
+        VARIABLE Bank1 : ram_stor;
+        VARIABLE Bank2 : ram_stor;
+        VARIABLE Bank3 : ram_stor;
+        VARIABLE Row_index, Col_index : INTEGER := 0;
+        VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
+
+        VARIABLE Col_addr : Array4xCBV;
+        VARIABLE Bank_addr : Array4x2BV;
+        VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
+
+        VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Burst_counter : INTEGER := 0;
+
+        VARIABLE Command : Array_state;
+        VARIABLE Bank_precharge : Array4x2BV;
+        VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
+
+        VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
+
+        -- Timing Check
+        VARIABLE MRD_chk : INTEGER := 0;
+        VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
+        VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+
+        -- Load and Dumb variables
+        FILE     file_load : TEXT open read_mode is fname;   -- Data load
+        FILE     file_dump : TEXT open write_mode is "dumpdata.txt";   -- Data dump
+        VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
+        VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
+        VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
+        VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
+        VARIABLE i, j      : INTEGER;
+        VARIABLE good_load : BOOLEAN;
+        VARIABLE l         : LINE;
+	variable load : std_logic := '1';
+	variable dump : std_logic := '0';
+	variable ch   : character;
+	variable rectype : bit_vector(3 downto 0);
+	variable recaddr : bit_vector(31 downto 0);
+	variable reclen : bit_vector(7 downto 0);
+	variable recdata : bit_vector(0 to 16*8-1);
+
+        -- Initialize empty rows
+        PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW ram_type;                  -- Open new row for access
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP            -- Filled row with zeros
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+            
+        -- Burst Counter
+        PROCEDURE Burst_decode IS
+            VARIABLE Col_int : INTEGER := 0;
+            VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance Burst Counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Col_int := TO_INTEGER(Col);
+                Col_int := Col_int + 1;
+                TO_BITVECTOR (Col_int, Col_temp);
+            ELSIF Mode_reg (3) = '1' THEN
+                TO_BITVECTOR (Burst_counter, Col_vec);
+                Col_temp (2) :=  Col_vec (2) XOR Col_brst (2);
+                Col_temp (1) :=  Col_vec (1) XOR Col_brst (1);
+                Col_temp (0) :=  Col_vec (0) XOR Col_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Col (0) := Col_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
+            ELSE
+                Col := Col_temp;
+            END IF;
+
+            -- Burst Read Single Write
+            IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
+                Data_in_enable := '0';
+            END IF;
+
+            -- Data counter
+            IF Burst_length_1 = '1' THEN
+                IF Burst_counter >= 1 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk, RAS_clk;
+        IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN 		--'
+            -- Internal Command Pipeline
+            Command(0) := Command(1);
+            Command(1) := Command(2);
+            Command(2) := Command(3);
+            Command(3) := NOP;
+            
+            Col_addr(0) := Col_addr(1);
+            Col_addr(1) := Col_addr(2);
+            Col_addr(2) := Col_addr(3);
+            Col_addr(3) := (OTHERS => '0');
+            
+            Bank_addr(0) := Bank_addr(1);
+            Bank_addr(1) := Bank_addr(2);
+            Bank_addr(2) := Bank_addr(3);
+            Bank_addr(3) := "00";
+
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := "00";
+
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := '0';
+            
+            -- Operation Decode (Optional for showing current command on posedge clock / debug feature)
+            IF Active_enable = '1' THEN
+                Operation <= ACT;
+            ELSIF Aref_enable = '1' THEN
+                Operation <= A_REF;
+            ELSIF Burst_term = '1' THEN
+                Operation <= BST;
+            ELSIF Mode_reg_enable = '1' THEN
+                Operation <= LMR;
+            ELSIF Prech_enable = '1' THEN
+                Operation <= PRECH;
+            ELSIF Read_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= READ;
+                ELSE
+                    Operation <= READ_A;
+                END IF;
+            ELSIF Write_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= WRITE;
+                ELSE
+                    Operation <= WRITE_A;
+                END IF;
+            ELSE
+                Operation <= NOP;
+            END IF;
+            
+            -- Dqm pipeline for Read
+            Dqm_reg0 := Dqm_reg1;
+            Dqm_reg1 := TO_BITVECTOR(Dqm);
+
+            -- Read or Write with Auto Precharge Counter
+            IF Auto_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Auto_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Auto_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Auto_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+            
+            -- Auto Precharge Timer for tWR
+            if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
+                if (Count_precharge(0) = 1) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 1) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 1) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 1) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_2 = '1') then
+                if (Count_precharge(0) = 2) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 2) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 2) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 2) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_4 = '1') then
+                if (Count_precharge(0) = 4) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 4) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 4) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 4) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_8 = '1') then
+                if (Count_precharge(0) = 8) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 8) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 8) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 8) then
+                    Count_time(3) := NOW;
+                end if;
+            end if;
+
+            -- tMRD Counter
+            MRD_chk := MRD_chk + 1;
+
+            -- tWR Counter
+            WR_counter(0) := WR_counter(0) + 1;
+            WR_counter(1) := WR_counter(1) + 1;
+            WR_counter(2) := WR_counter(2) + 1;
+            WR_counter(3) := WR_counter(3) + 1;
+
+
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- Precharge to Auto Refresh
+                ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- All banks must be idle before refresh
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All banks must be Precharge before Auto Refresh"
+                        SEVERITY WARNING;
+                END IF;
+                -- Record current tRC time
+                RC_chk := NOW;
+            END IF;
+            
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                Mode_reg <= TO_BITVECTOR (Addr);
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All bank must be Precharge before Load Mode Register"
+                        SEVERITY WARNING;
+                END IF;
+                -- REF to LMR
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- LMR to LMR
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- Record current tMRD time
+                MRD_chk := 0;
+            END IF;
+            
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    -- Precharge to Active Bank 0
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '1' THEN
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    -- Precharge to Active Bank 1
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '1' THEN
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    -- Precharge to Active Bank 2
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '1' THEN
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    -- Precharge to Active Bank 3
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+                ELSIF Ba = "00" AND Pc_b0 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 0 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 1 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 2 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 3 is not Precharged"
+                        SEVERITY WARNING;
+                END IF;
+                -- Active Bank A to Active Bank B
+                IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
+                    ASSERT (FALSE)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                -- LMR to ACT
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Activate"
+                    SEVERITY WARNING;
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Activate"
+                    SEVERITY WARNING;
+                -- Record variable for checking violation
+                RRD_chk := NOW;
+                Previous_bank := TO_BITVECTOR (Ba);
+            END IF;
+            
+            -- Precharge Block
+            IF Prech_enable = '1' THEN
+                IF Addr(10) = '1' THEN
+                    Pc_b0 := '1'; 
+                    Pc_b1 := '1'; 
+                    Pc_b2 := '1'; 
+                    Pc_b3 := '1';
+                    Act_b0 := '0';
+                    Act_b1 := '0';
+                    Act_b2 := '0';
+                    Act_b3 := '0';
+                    RP_chk0 := NOW;
+                    RP_chk1 := NOW;
+                    RP_chk2 := NOW;
+                    RP_chk3 := NOW;
+                    -- Activate to Precharge all banks
+                    ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
+                        REPORT "tRAS violation during Precharge all banks"
+                        SEVERITY WARNING;
+                    -- tWR violation check for Write
+                    IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
+                        (NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
+                        ASSERT (FALSE)
+                            REPORT "tWR violation during Precharge ALL banks"
+                            SEVERITY WARNING;
+                    END IF;
+                ELSIF Addr(10) = '0' THEN
+                    IF Ba = "00" THEN
+                        Pc_b0 := '1';
+                        Act_b0 := '0';
+                        RP_chk0 := NOW;
+                        -- Activate to Precharge bank 0
+                        ASSERT (NOW - RAS_chk0 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 0"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "01" THEN
+                        Pc_b1 := '1';
+                        Act_b1 := '0';
+                        RP_chk1 := NOW;
+                        -- Activate to Precharge bank 1
+                        ASSERT (NOW - RAS_chk1 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 1"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "10" THEN
+                        Pc_b2 := '1';
+                        Act_b2 := '0';
+                        RP_chk2 := NOW;
+                        -- Activate to Precharge bank 2
+                        ASSERT (NOW - RAS_chk2 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 2"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "11" THEN
+                        Pc_b3 := '1';
+                        Act_b3 := '0';
+                        RP_chk3 := NOW;
+                        -- Activate to Precharge bank 3
+                        ASSERT (NOW - RAS_chk3 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 3"
+                            SEVERITY WARNING;
+                    END IF;
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+                -- Terminate a Write Immediately (if same bank or all banks)
+                IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Precharge Command Pipeline for READ
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := PRECH;
+                    Bank_precharge(2) := TO_BITVECTOR (Ba);
+                    A10_precharge(2) := TO_BIT(Addr(10));
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := PRECH;
+                    Bank_precharge(1) := TO_BITVECTOR (Ba);
+                    A10_precharge(1) := TO_BIT(Addr(10));
+                END IF;
+            END IF;
+            
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Terminate a Write immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Terminate a Read depend on CAS Latency
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := BST;
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := BST;
+                END IF;
+            END IF;
+            
+            -- Read, Write, Column Latch
+            IF Read_enable = '1' OR Write_enable = '1' THEN
+                -- Check to see if bank is open (ACT) for Read or Write
+                IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
+                    ASSERT (FALSE)
+                        REPORT "Cannot Read or Write - Bank is not Activated"
+                        SEVERITY WARNING;
+                END IF;
+                -- Activate to Read or Write
+                IF Ba = "00" THEN
+                    ASSERT (NOW - RCD_chk0 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" THEN
+                    ASSERT (NOW - RCD_chk1 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" THEN
+                    ASSERT (NOW - RCD_chk2 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" THEN
+                    ASSERT (NOW - RCD_chk3 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 3"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Read Command
+                IF Read_enable = '1' THEN
+                    -- CAS Latency Pipeline
+                    IF Cas_latency_3 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(2) := READ_A;
+                        ELSE
+                            Command(2) := READ;
+                        END IF;
+                        Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (2) := TO_BITVECTOR (Ba);
+                    ELSIF Cas_latency_2 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(1) := READ_A;
+                        ELSE
+                            Command(1) := READ;
+                        END IF;
+                        Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (1) := TO_BITVECTOR (Ba);
+                    END IF;
+
+                    -- Read intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                -- Write Command
+                ELSIF Write_enable = '1' THEN
+                    IF Addr(10) = '1' THEN
+                        Command(0) := WRITE_A;
+                    ELSE
+                        Command(0) := WRITE;
+                    END IF;
+                    Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                    Bank_addr (0) := TO_BITVECTOR (Ba);
+
+                    -- Write intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                    -- Write interrupt a Read (terminate Read immediately)
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+
+                -- Interrupt a Write with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Interrupt a Read with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Read or Write with Auto Precharge
+                IF Addr(10) = '1' THEN
+                    Auto_precharge (TO_INTEGER(Ba)) := '1';
+                    Count_precharge (TO_INTEGER(Ba)) := 0;
+                    RW_Interrupt_Bank := TO_BitVector(Ba);
+                    IF Read_enable = '1' THEN
+                        Read_precharge (TO_INTEGER(Ba)) := '1';
+                    ELSIF Write_enable = '1' THEN
+                        Write_precharge (TO_INTEGER(Ba)) := '1';
+                    END IF;
+                END IF;
+            END IF;
+            
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  BL/2 cycles after command
+            --      and 2.  Meet tRAS requirement
+            --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+            IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
+                IF (((NOW - RAS_chk0 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(0) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(0) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(0) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
+                     (RW_interrupt_read(0) = '1')) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Auto_precharge(0) := '0';
+                    Read_precharge(0) := '0';
+                    RW_interrupt_read(0) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
+                IF (((NOW - RAS_chk1 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(1) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(1) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(1) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
+                     (RW_interrupt_read(1) = '1')) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Auto_precharge(1) := '0';
+                    Read_precharge(1) := '0';
+                    RW_interrupt_read(1) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
+                IF (((NOW - RAS_chk2 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(2) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(2) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(2) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
+                     (RW_interrupt_read(2) = '1')) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Auto_precharge(2) := '0';
+                    Read_precharge(2) := '0';
+                    RW_interrupt_read(2) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
+                IF (((NOW - RAS_chk3 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(3) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(3) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(3) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
+                     (RW_interrupt_read(3) = '1')) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Auto_precharge(3) := '0';
+                    Read_precharge(3) := '0';
+                    RW_interrupt_read(3) := '0';
+                END IF;
+            END IF;
+            
+            -- Internal Precharge or Bst
+            IF Command(0) = PRECH THEN                          -- PRECH terminate a read if same bank or all banks
+                IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Command(0) = BST THEN                         -- BST terminate a read regardless of bank
+                IF Data_out_enable = '1' THEN
+                    Data_out_enable := '0';
+                END IF;
+            END IF;
+
+            IF Data_out_enable = '0' THEN
+                Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
+            END IF;
+
+            -- Detect Read or Write Command
+            IF Command(0) = READ OR Command(0) = READ_A THEN
+                Bank := Bank_addr (0);
+                Col := Col_addr (0);
+                Col_brst := Col_addr (0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '0';
+                Data_out_enable := '1';
+            ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
+                Bank := Bank_addr(0);
+                Col := Col_addr(0);
+                Col_brst := Col_addr(0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '1';
+                Data_out_enable := '0';
+            END IF;
+
+            -- DQ (Driver / Receiver)
+            Row_index := TO_INTEGER (Row);
+            Col_index := TO_INTEGER (Col);
+            IF Data_in_enable = '1' THEN
+                IF Dqm /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    END IF;
+                    WR_chkp(TO_INTEGER(Bank)) := NOW;
+                    WR_counter(TO_INTEGER(Bank)) := 0;
+                END IF;
+                Burst_decode;
+            ELSIF Data_out_enable = '1' THEN
+                IF Dqm_reg0 /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    END IF;
+                ELSE
+                      Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
+                END IF;
+                Burst_decode;
+            END IF;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN 		--'
+            Operation <= LOAD_FILE;
+	    load := '0';
+--            ASSERT (FALSE) REPORT "Reading memory array from file.  This operation may take several minutes.  Please wait..."
+--                SEVERITY NOTE;
+            WHILE NOT endfile(file_load) LOOP
+                readline(file_load, l);
+                read(l, ch);
+                if (ch /= 'S') or (ch /= 's') then
+                  hread(l, rectype);
+                  hread(l, reclen);
+		  recaddr := (others => '0');
+		  case rectype is 
+		  when "0001" =>
+                    hread(l, recaddr(15 downto 0));
+		  when "0010" =>
+                    hread(l, recaddr(23 downto 0));
+		  when "0011" =>
+                    hread(l, recaddr);
+		    recaddr(31 downto 24) := (others => '0');
+		  when others => next;
+		  end case;
+                  hread(l, recdata);
+
+	 	  if index < 32 then
+		    Bank_Load := recaddr(25 downto 24);
+		    Rows_Load := recaddr(23 downto 11);
+		    Cols_Load := recaddr(10 downto 2);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 3 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 3 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 3 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 3 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    END IF;
+		  elsif(index < 1024) then
+		    Bank_Load := recaddr(26 downto 25);
+		    Rows_Load := recaddr(24 downto 12);
+		    Cols_Load := recaddr(11 downto 3);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 1 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 1 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 1 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 1 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    END IF;
+                  else
+		    Bank_Load := recaddr(22 downto 21);
+		    Rows_Load := '0' & recaddr(20 downto 9);
+		    Cols_Load := '0' & recaddr(8 downto 1);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 7 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 7 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 7 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 7 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    END IF;
+                  END IF;
+                END IF;
+            END LOOP;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN 		--'
+            Operation <= DUMP_FILE;
+            ASSERT (FALSE) REPORT "Writing memory array to file.  This operation may take several minutes.  Please wait..."
+                SEVERITY NOTE;
+            WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# BA ROWS          COLS      DQ")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# -- ------------- --------- ----------------")); 		--'
+            WRITELINE (file_dump, l);
+            -- Dumping Bank 0
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank0 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("00"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 1
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank1 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("01"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 2
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank2 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("10"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 3
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank3 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("11"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+        END IF;
+
+        -- Write with AutoPrecharge Calculation
+        --      The device start internal precharge when:
+        --          1.  tWR cycles after command
+        --      and 2.  Meet tRAS requirement
+        --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+        IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
+            IF (((NOW - RAS_chk0 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
+                Auto_precharge(0) := '0';
+                Write_precharge(0) := '0';
+                RW_interrupt_write(0) := '0';
+                Pc_b0 := '1';
+                Act_b0 := '0';
+                RP_chk0 := NOW;
+                ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
+            IF (((NOW - RAS_chk1 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
+                 (RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
+                Auto_precharge(1) := '0';
+                Write_precharge(1) := '0';
+                RW_interrupt_write(1) := '0';
+                Pc_b1 := '1';
+                Act_b1 := '0';
+                RP_chk1 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
+            IF (((NOW - RAS_chk2 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
+                 (RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
+                Auto_precharge(2) := '0';
+                Write_precharge(2) := '0';
+                RW_interrupt_write(2) := '0';
+                Pc_b2 := '1';
+                Act_b2 := '0';
+                RP_chk2 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
+            IF (((NOW - RAS_chk3 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
+                Auto_precharge(3) := '0';
+                Write_precharge(3) := '0';
+                RW_interrupt_write(3) := '0';
+                Pc_b3 := '1';
+                Act_b3 := '0';
+                RP_chk3 := NOW;
+            END IF;
+        END IF;
+
+        -- Checking internal wires (Optional for debug purpose)
+        Pre_chk (0) <= Pc_b0;
+        Pre_chk (1) <= Pc_b1;
+        Pre_chk (2) <= Pc_b2;
+        Pre_chk (3) <= Pc_b3;
+        Act_chk (0) <= Act_b0;
+        Act_chk (1) <= Act_b1;
+        Act_chk (2) <= Act_b2;
+        Act_chk (3) <= Act_b3;
+        Dq_in_chk   <= Data_in_enable;
+        Dq_out_chk  <= Data_out_enable;
+        Bank_chk    <= Bank;
+        Row_chk     <= Row;
+        Col_chk     <= Col;
+    END PROCESS;    
+                    
+                    
+    -- Clock timing checks
+--    Clock_check : PROCESS
+--        VARIABLE Clk_low, Clk_high : TIME := 0 ns;
+--    BEGIN       
+--        WAIT ON Clk;
+--        IF (Clk = '1' AND NOW >= 10 ns) THEN
+--            ASSERT (NOW - Clk_low >= tCL)
+--                REPORT "tCL violation"
+--                SEVERITY WARNING;
+--            ASSERT (NOW - Clk_high >= tCK)
+--                REPORT "tCK violation"
+--                SEVERITY WARNING;
+--            Clk_high := NOW;
+--        ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
+--            ASSERT (NOW - Clk_high >= tCH)
+--                REPORT "tCH violation"
+--                SEVERITY WARNING;
+--            Clk_low := NOW;
+--        END IF;
+--    END PROCESS;    
+                    
+    -- Setup timing checks
+    Setup_check : PROCESS
+    BEGIN       
+	wait;
+        WAIT ON Clk;
+        IF Clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tCKS) 		--'
+                REPORT "CKE Setup time violation -- tCKS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "RAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "WE# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT >= tCMS) 		--'
+                REPORT "Dqm Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tAS) 		--'
+                REPORT "ADDR Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tAS) 		--'
+                REPORT "BA Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Dq'LAST_EVENT >= tDS) 		--'
+                REPORT "Dq Setup time violation -- tDS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    -- Hold timing checks
+    Hold_check : PROCESS
+    BEGIN
+	wait;
+        WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
+        IF Clk'DELAYED (tCKH) = '1' THEN 		--'
+            ASSERT(Cke'LAST_EVENT > tCKH) 		--'
+                REPORT "CKE Hold time violation -- tCKH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tCMH) = '1' THEN 		--'
+            ASSERT(Cs_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT > tCMH) 		--'
+                REPORT "RAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT > tCMH) 		--'
+                REPORT "WE# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT > tCMH) 		--'
+                REPORT "Dqm Hold time violation -- tCMH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tAH) = '1' THEN 		--'
+            ASSERT(Addr'LAST_EVENT > tAH) 		--'
+                REPORT "ADDR Hold time violation -- tAH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT > tAH) 		--'
+                REPORT "BA Hold time violation -- tAH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tDH) = '1' THEN 		--'
+            ASSERT(Dq'LAST_EVENT > tDH) 		--'
+                REPORT "Dq Hold time violation -- tDH"
+                SEVERITY WARNING;
+        END IF;
+    END PROCESS;
+
+END behave;
+
+-- pragma translate_on
+
diff --git a/designs/SPWBrick-MiniSpartan6p/opencores.xml b/designs/SPWBrick-MiniSpartan6p/opencores.xml
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/opencores.xml
@@ -0,0 +1,69 @@
+<?xml version='1.0' encoding='utf-8'?>
+<soc name="Leon">
+ <peripheral vid="8" name="SpaceWire Light" pid="305">
+   <register name="Control register" addOffset="0">
+     <bitField size="1" offset="0" name="Reset" mode="3" desc="Write '1' to reset SPWAMBA core (auto-clear)."/>
+     <bitField size="1" offset="1" name="Reset DMA" mode="3" desc="Write '1' to reset DMA engines (auto-clear)."/>
+     <bitField name="Link Start" offset="2" size="1" mode="3" desc="Link start signal. '1' = actively try to start a SpaceWire link."/>
+     <bitField name="Link Auto Start" offset="3" size="1" mode="3" desc="Link autostart signal. '1' = start link after receiving NULL from other side."/>
+     <bitField name="Link Disable" offset="4" size="1" mode="3" desc="Link disable signal. '1' = shut down current link and do not establish new link."/>
+     <bitField name="Time Code EN" offset="5" size="1" mode="3" desc="Allow time-code transmission through tick_in signal."/>
+     <bitField name="Restart RX DMA" offset="6" size="1" mode="3" desc="Write '1' to (re-)start RX DMA (auto-clear)."/>
+     <bitField name="Restart TX DMA" offset="7" size="1" mode="3" desc="Write '1' to (re-)start TX DMA (auto-clear)."/>
+     <bitField name="Cancel TX DMA" offset="8" size="1" mode="3" desc="Write '1' to cancel running TX DMA and discard data from TX FIFO (auto-clear)."/>
+     <bitField name="Link Up/Down IE" offset="9" size="1" mode="3" desc="Enable interrupt on link up/down."/>
+     <bitField name="Time Code IE" offset="10" size="1" mode="3" desc="Enable interrupt on time code received."/>
+     <bitField name="RXDESCIE" offset="11" size="1" mode="3" desc="Enable interrupt on completed RX descriptor with IE='1'."/>
+     <bitField name="TXDESCIE" offset="12" size="1" mode="3" desc="Enable interrupt on completed TX descriptor with IE='1'."/>
+     <bitField name="RXIE" offset="13" size="1" mode="3" desc="Enable interrupt on RX packet received."/>
+     <bitField name="DescSz" offset="24" size="4" mode="1" desc="Value of desctablesize generic (read-only)."/>
+   </register>
+   <register name="Status register" addOffset="4">
+     <bitField size="2" offset="0" name="LSTAT" mode="1" desc="Link status: 0=off, 1=started, 2=connecting, 3=run (read-only)."/>
+     <bitField size="1" offset="2" name="DISCERR" mode="3" desc="Got disconnect error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="3" name="PARERR" mode="3" desc="Got parity error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="4" name="ESCERR" mode="3" desc="Got escape error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="5" name="CREDERR" mode="3" desc="Got credit error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="6" name="RXDMA" mode="1" desc="RX DMA running (read-only)."/>
+     <bitField size="1" offset="7" name="RXDMA" mode="1" desc="TX DMA running (read-only)."/>
+     <bitField size="1" offset="8" name="AHBERR" mode="1" desc="AHB error occurred (sticky, reset DMA engine to clear)."/>
+     <bitField size="1" offset="9" name="UNUSED" mode="3" desc="unused"/>
+     <bitField size="1" offset="10" name="TIMECODE" mode="3" desc="Received time-code (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="11" name="RXDESCCOMP" mode="3" desc="Completed RX descriptor with IE='1' (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="12" name="TXDESCCOMP" mode="3" desc="Completed TX descriptor with IE='1' (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="13" name="RECPACKT" mode="3" desc="Received packet (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="14" name="RXE" mode="1" desc="RX buffer is empty and last packet has been completely transfered to RX DMA (read-only)."/>
+   </register>
+   <register name="Transmission clock scaler" addOffset="8">
+     <bitField size="8" offset="0" name="N" mode="3" desc="Clock division factor minus 1. The actual TX bit rate is determined by (txclk frequency) / (scaler + 1).
+During the handshake phase, this register is ignored and the TX bit rate is forced to 10 Mbit. After reset, this
+register defaults to the scaler value needed for 10 Mbit."/>
+   </register>
+   <register name="Time-code register" addOffset="12">
+     <bitField size="6" offset="0" name="Address" mode="1" desc="Last received time-code value (read-only)."/>
+     <bitField size="2" offset="6" name="Address" mode="1" desc="Control bits received with last time-code (read-only)."/>
+     <bitField size="6" offset="12" name="Address" mode="3" desc="Time-code value to send on next tick_in (auto-increment)."/>
+     <bitField size="2" offset="14" name="Address" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="1" offset="15" name="Address" mode="3" desc="Write '1' to send a time-code immediately (auto-clear)."/>
+   </register>
+   <register name="Descriptor pointer for RX DMA" addOffset="16">
+     <bitField size="3" offset="0" name="DATA" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="10" offset="3" name="DATA" mode="3" desc="Descriptor index (auto-increment)."/>
+     <bitField size="19" offset="13" name="DATA" mode="3" desc="Fixed address bits of descriptor table."/>
+   </register>
+   <register name="Descriptor pointer for TX DMA" addOffset="20">
+     <bitField size="3" offset="0" name="DATA" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="10" offset="3" name="DATA" mode="3" desc="Descriptor index (auto-increment)."/>
+     <bitField size="19" offset="13" name="DATA" mode="3" desc="Fixed address bits of descriptor table."/>
+   </register>
+ </peripheral>
+</soc>
+
+
+
+
+
+
+
+
+
diff --git a/designs/SPWBrick-MiniSpartan6p/sdctrl16.vhd b/designs/SPWBrick-MiniSpartan6p/sdctrl16.vhd
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/sdctrl16.vhd
@@ -0,0 +1,1053 @@
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+-----------------------------------------------------------------------------
+-- Entity:  sdctrl16
+-- File:    sdctrl16.vhd
+-- Author:  Jiri Gaisler - Gaisler Research
+-- Modified by: Daniel Bengtsson & Richard Fång
+-- Description: 16- and 32-bit SDRAM memory controller.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+library gaisler;
+use grlib.devices.all;
+use gaisler.memctrl.all;
+
+entity sdctrl16 is
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end;
+
+architecture rtl of sdctrl16 is
+
+constant WPROTEN   : boolean := wprot = 1;
+constant SDINVCLK  : boolean := invclk = 1;
+constant BUS16    : boolean := (sdbits = 16);
+constant BUS32    : boolean := (sdbits = 32);
+constant BUS64    : boolean := (sdbits = 64);
+
+constant REVISION  : integer := 1;
+
+constant PM_PD    : std_logic_vector(2 downto 0) := "001";
+constant PM_SR    : std_logic_vector(2 downto 0) := "010";
+constant PM_DPD   : std_logic_vector(2 downto 0) := "101";
+
+constant std_rammask: Std_Logic_Vector(31 downto 20) :=
+                        Conv_Std_Logic_Vector(hmask, 12);
+
+constant hconfig : ahb_config_type := (
+  0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
+  4 => ahb_membar(haddr, '1', '1', hmask),
+  5 => ahb_iobar(ioaddr, iomask),
+  others => zero32);
+
+type mcycletype is (midle, active, leadout);
+type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
+                     wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
+                     sref, pd, dpd);
+type icycletype is (iidle, pre, ref, lmode, emode, finish);
+
+-- sdram configuration register
+
+type sdram_cfg_type is record
+  command         : std_logic_vector(2 downto 0);
+  csize           : std_logic_vector(1 downto 0);
+  bsize           : std_logic_vector(2 downto 0);
+  casdel          : std_ulogic;  -- CAS to data delay: 2/3 clock cycles
+  trfc            : std_logic_vector(2 downto 0);
+  trp             : std_ulogic;  -- precharge to activate: 2/3 clock cycles
+  refresh         : std_logic_vector(14 downto 0);
+  renable         : std_ulogic;
+  pageburst       : std_ulogic;
+  mobileen        : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
+  ds              : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
+  tcsr            : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
+  pasr            : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
+  pmode           : std_logic_vector(2 downto 0); -- Power-Saving mode
+  txsr            : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
+  cke             : std_ulogic; -- Clock enable
+end record;
+
+-- local registers
+
+type reg_type is record
+  hready        : std_ulogic;
+  hsel          : std_ulogic;
+  bdrive        : std_ulogic;
+  nbdrive       : std_ulogic;
+  burst         : std_ulogic;
+  wprothit      : std_ulogic;
+  hio           : std_ulogic;
+  startsd       : std_ulogic;
+  lhw           : std_ulogic; --Lower halfword
+
+  mstate        : mcycletype;
+  sdstate       : sdcycletype;
+  cmstate       : mcycletype;
+  istate        : icycletype;
+  icnt          : std_logic_vector(2 downto 0);
+
+  haddr         : std_logic_vector(31 downto 0);
+  hrdata        : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
+  hwdata        : std_logic_vector(31 downto 0);
+  hwrite        : std_ulogic;
+  htrans        : std_logic_vector(1 downto 0);
+  hresp         : std_logic_vector(1 downto 0);
+  size          : std_logic_vector(1 downto 0);
+
+  cfg           : sdram_cfg_type;
+  trfc          : std_logic_vector(3 downto 0);
+  refresh       : std_logic_vector(14 downto 0);
+  sdcsn         : std_logic_vector(1  downto 0);
+  sdwen         : std_ulogic;
+  rasn          : std_ulogic;
+  casn          : std_ulogic;
+  dqm           : std_logic_vector(7 downto 0);
+  address       : std_logic_vector(16 downto 2);  -- memory address
+  bsel          : std_ulogic;
+
+  idlecnt       : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
+  sref_tmpcom   : std_logic_vector(2 downto 0); -- Save SD command when exit sref
+end record;
+
+signal r, ri : reg_type;
+signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
+attribute syn_preserve : boolean;
+attribute syn_preserve of rbdrive : signal is true;
+
+begin
+
+  ctrl : process(rst, ahbsi, r, sdi, rbdrive)
+  variable v       : reg_type;                      -- local variables for registers
+  variable startsd : std_ulogic;
+  variable dataout : std_logic_vector(31 downto 0); -- data from memory
+  variable regsd   : std_logic_vector(31 downto 0); -- data from registers
+  variable dqm     : std_logic_vector(7 downto 0);
+  variable raddr   : std_logic_vector(12 downto 0);
+  variable adec    : std_ulogic;
+  variable rams    : std_logic_vector(1 downto 0);
+  variable ba      : std_logic_vector(1 downto 0);
+  variable haddr   : std_logic_vector(31 downto 0);
+  variable dout    : std_logic_vector(31 downto 0);
+  variable hsize   : std_logic_vector(1 downto 0);
+  variable hwrite  : std_ulogic;
+  variable htrans  : std_logic_vector(1 downto 0);
+  variable hready  : std_ulogic;
+  variable vbdrive : std_logic_vector(31 downto 0);
+  variable bdrive  : std_ulogic;
+  variable lline    : std_logic_vector(2 downto 0);
+  variable lineburst : boolean;
+  variable haddr_tmp : std_logic_vector(31 downto 0);
+  variable arefresh : std_logic;
+  variable hwdata  : std_logic_vector(31 downto 0);
+
+  begin
+
+-- Variable default settings to avoid latches
+
+    v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
+    if BUS16 then
+      if (r.lhw = '1') then --muxes read data to correct part of the register.
+        v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
+      else
+        v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
+      end if;
+    else
+      v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
+      v.hrdata(31 downto 0) := sdi.data(31 downto 0);
+    end if;
+    hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
+    lline := not r.cfg.casdel &  r.cfg.casdel &  r.cfg.casdel;
+    if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
+      lineburst := true;
+    else lineburst := false; end if;
+
+
+    if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
+      v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
+      v.htrans := ahbsi.htrans;
+      if ahbsi.htrans(1) = '1' then
+        v.hio := ahbsi.hmbsel(1);
+        v.hsel := '1'; v.hready := v.hio;
+      end if;
+      v.haddr := ahbsi.haddr;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+
+    if (r.hsel = '1') and (ahbsi.hready = '0') then
+      haddr := r.haddr;  hsize := r.size;
+      htrans := r.htrans; hwrite := r.hwrite;
+    else
+      haddr := ahbsi.haddr;  hsize := ahbsi.hsize(1 downto 0);
+      htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+    if fast = 1 then haddr := r.haddr; end if;
+
+    if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
+
+-- main state
+    if BUS16 then
+      case r.size is
+      when "00" => --bytesize
+        case r.haddr(0) is
+        when '0' => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when others => dqm := "11111100"; --halfword, word
+      end case;
+    else
+      case r.size is
+      when "00" =>
+        case r.haddr(1 downto 0) is
+        when "00" => dqm := "11110111";
+        when "01" => dqm := "11111011";
+        when "10" => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when "01" =>
+        if r.haddr(1) = '0' then dqm := "11110011"; else  dqm := "11111100"; end if;
+      when others => dqm := "11110000";
+      end case;
+    end if;
+--
+--      case r.size is
+--      when "00" =>
+--        case r.haddr(1 downto 0) is
+--        when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
+--        when "01" => dqm := "11111110"; lhw := '0';
+--        when "10" => dqm := "11111101"; lhw := '1';
+--        when others => dqm := "11111110"; lhw := '1';
+--        end case;
+--      when "01" =>
+--        dqm := "11111100";
+--        if r.haddr(1) = '0' then
+--          lhw := '0';
+--        else
+--          lhw := '1';
+--	end if;
+--    when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
+--      end case;
+--
+    if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
+
+-- main FSM
+
+    case r.mstate is
+    when midle =>
+      if ((v.hsel and htrans(1) and not v.hio) = '1') then
+        if (r.sdstate = sidle) and (r.cfg.command = "000")
+           and (r.cmstate = midle) and (v.hio = '0')
+        then
+          if fast = 0 then startsd := '1';  else v.startsd := '1'; end if;
+          v.mstate := active;
+        elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
+           and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
+        then
+          v.startsd := '1';
+          if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
+            v.hresp := HRESP_ERROR;
+          else
+            v.mstate := active;
+          end if;
+        end if;
+      end if;
+    when others => null;
+    end case;
+
+    startsd := startsd or r.startsd;
+
+-- generate row and column address size
+
+    if BUS16 then
+      case r.cfg.csize is
+      when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
+      when "01" => raddr := haddr(22 downto 10);
+      when "10" => raddr := haddr(23 downto 11);
+      when others =>
+        if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
+        else raddr := haddr(24 downto 12); end if;
+      end case;
+    else
+      case r.cfg.csize is
+      when "00" => raddr := haddr(22 downto 10);
+      when "01" => raddr := haddr(23 downto 11);
+      when "10" => raddr := haddr(24 downto 12);
+      when others =>
+        if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
+        else raddr := haddr(25 downto 13); end if;
+      end case;
+    end if;
+
+-- generate bank address
+--    if BUS16 then --011
+--      ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
+--            genmux(r.cfg.bsize, haddr(25 downto 18));
+--    else
+      ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
+            genmux(r.cfg.bsize, haddr(27 downto 20));
+ --   end if;
+
+-- generate chip select
+
+    if BUS64 then
+      adec := genmux(r.cfg.bsize, haddr(30 downto 23));
+      v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
+    else
+      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+    end if;
+--    elsif BUS32 then
+--      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+--    else
+--      adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
+--    end if;
+
+    rams := adec & not adec;
+
+-- sdram access FSM
+
+    if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
+
+    if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
+
+    case r.sdstate is
+
+    when sidle =>
+      if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
+      --  if BUS16 then
+      --    v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
+      --  else
+          v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
+      --  end if;
+        v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
+        v.startsd := '0';
+      elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
+            and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
+        case r.cfg.pmode is
+        when PM_SR =>
+          v.cfg.cke := '0'; v.sdstate := sref;
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
+        when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
+        when PM_DPD =>
+          v.cfg.cke := '0'; v.sdstate := dpd;
+          v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
+        when others =>
+        end case;
+      end if;
+
+    when act1 =>
+      v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+      if r.cfg.casdel = '1' then v.sdstate := act2; else
+        v.sdstate := act3;
+        if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
+          v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+        end if;
+      end if;
+      if WPROTEN then
+        v.wprothit := sdi.wprot;
+        if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
+      end if;
+
+    when act2 =>
+      v.sdstate := act3;
+      if not BUS16 then
+        v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+      end if;
+      if WPROTEN and (r.wprothit = '1') then
+        v.hresp := HRESP_ERROR; v.hready := '0';
+      end if;
+
+    when act3 =>
+      v.casn := '0';
+      if BUS16 then --HW adress needed to memory
+        v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+--        v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+	v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
+      else
+        v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      end if;
+      v.dqm := dqm; v.burst := r.hready; -- ??
+
+      if r.hwrite = '1' then
+
+        if BUS16 then --16 bit
+          if r.size(1) = '1' then --word
+            v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
+            v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
+            v.sdstate := act3_16; -- goto state for second part of word transfer
+        --  v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
+          else --halfword or byte
+            v.sdstate := act3_16; v.hready := '1';
+          end if;
+        else --32 bit or 64
+          v.sdstate := wr1;
+          if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
+        end if;
+        v.sdwen := '0'; v.bdrive := '0'; --write
+        if WPROTEN and (r.wprothit = '1') then
+          v.hresp := HRESP_ERROR; v.hready := '1';
+          if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
+          v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
+        end if;
+      else v.sdstate := rd1; end if;
+
+    when act3_16 => --handle 16 bit and WORD write
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
+      v.lhw := '1';
+      if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
+        v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
+        if( ahbsi.htrans = "11" and
+            not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
+            not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
+          v.sdstate := wr1_16;
+        end if;
+      elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      else -- complete single write
+        v.hready := '1';
+        v.sdstate := act3_16; --gick till wr1 förut
+      end if;
+
+    when wr1_16 =>
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
+      v.lhw := r.haddr(1);
+      v.sdstate := act3_16;
+      v.hready := '1';
+
+    when wr1 =>
+      v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
+         and not (WPROTEN and (r.wprothit = '1'))
+      then
+        v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
+        if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
+          v.hready := '0';
+        end if;
+      else
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      end if;
+
+    when wr2 =>
+      if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
+      v.sdstate := wr3;
+
+    when wr3 =>
+      if (r.cfg.trp = '1') then
+        v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
+      else
+        v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when wr4 =>
+      v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
+      if (r.cfg.trp = '1') then v.sdstate := wr5;
+      else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+
+    when wr5 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+
+    when rd1 => --first read applied to sdram
+      v.casn := '1'; v.sdstate := rd7; --nop
+      if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
+        if lineburst and (ahbsi.htrans = "11") then
+          if r.haddr(4 downto 2) = "111" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
+            v.address(4 downto 2) := "000"; v.casn := '0';
+	  end if;
+        end if;
+      end if;
+
+    when rd7 =>
+      v.casn := '1'; --nop
+      if BUS16 then
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
+          elsif lineburst then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      else -- 32 bit or larger
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
+          elsif lineburst then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      end if;
+
+    when rd2 =>
+      v.casn := '1'; v.sdstate := rd3;
+      if BUS16 then
+        if ahbsi.htrans /= "11" then
+          v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+          --note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
+        end if;
+      else
+        if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+        elsif lineburst then
+          if r.haddr(4 downto 2) = "101" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
+      v.casn := '1'; --if read before cas makes nop else if pre => no difference
+      if BUS16 then
+        --note if read is for halfwor or byte we dont want to read a second time but exit.
+        --if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
+    --    if r.size(1) = '1' then --word v.hready := not r.size(1)
+    --      v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
+    --      v.lhw := '1'; -- read low 16 next state
+    --    else --HW or byte
+    --      v.sdstate := rd4_16; v.hready := '1';
+    --    end if;
+        v.sdstate := rd4_16;
+        v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
+        v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
+          if r.haddr(3 downto 1) = "100" then
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      else --32 bit or larger
+        v.sdstate := rd4; v.hready := '1';
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
+          if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
+      --v.hready := '1';
+      v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
+      v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
+      v.casn := '1';
+      --quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
+      if (ahbsi.htrans /= "11" and (r.hready = '1')) or
+         ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
+        --v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
+        v.dqm := (others => '1');
+        if r.sdcsn /= "11" then --not prechargeing
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
+        else--exit
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
+        if r.cfg.casdel = '0' then
+          if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        else
+          if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4 =>
+      v.hready := '1'; v.casn := '1';
+      if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
+      then
+        v.hready := '0'; v.dqm := (others => '1');
+        if (r.sdcsn /= "11") then
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
+        else
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then
+        if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
+          v.address(9 downto 5) := r.address(9 downto 5) + 1;
+          v.address(4 downto 2) := "000"; v.casn := '0';
+        end if;
+      end if;
+
+    when rd5 =>
+      if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
+      v.casn := '1';
+
+    when rd6 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
+
+    when sref =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
+        if r.trfc = "0000" then -- Minimum duration (= tRAS)
+          v.cfg.cke := '1';
+          v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
+        end if;
+        if r.cfg.cke = '1' then
+          if (r.idlecnt = "0000") then -- tXSR ns with NOP
+            v.sdstate := sidle;
+            v.idlecnt := (others => '1');
+            v.sref_tmpcom := r.cfg.command;
+            v.cfg.command := "100";
+          end if;
+        else
+          v.idlecnt := r.cfg.txsr;
+        end if;
+      end if;
+
+    when pd =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
+        v.cfg.cke := '1';
+        v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when dpd =>
+      v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
+      v.cfg.renable := '0';
+      if (startsd = '1' and r.hio = '0') then
+        v.hready := '1'; -- ack all accesses with Error response
+        v.startsd := '0';
+        v.hresp := HRESP_ERROR;
+      elsif r.cfg.pmode /= PM_DPD then
+        v.cfg.cke := '1';
+        if r.cfg.cke = '1' then
+          v.sdstate := sidle;
+          v.idlecnt := (others => '1');
+          v.cfg.renable := '1';
+        end if;
+      end if;
+
+    when others =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+    end case;
+
+-- sdram commands
+
+    case r.cmstate is
+    when midle =>
+      if r.sdstate = sidle then
+        case r.cfg.command is
+        when "010" => -- precharge
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
+          v.address(12) := '1'; v.cmstate := active;
+        when "100" => -- auto-refresh
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.cmstate := active;
+        when "110" => -- Lodad Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          if lineburst then
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
+          else
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
+          end if;
+        when "111" => -- Load Ext-Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
+                                    & r.cfg.pasr(2 downto 0);
+        when others => null;
+        end case;
+      end if;
+    when active =>
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
+      v.sdwen := '1'; --v.cfg.command := "000";
+      v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
+      v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+    when leadout =>
+      if r.trfc = "0000" then v.cmstate := midle; end if;
+
+    end case;
+
+-- sdram init
+
+    case r.istate is
+    when iidle =>
+      v.cfg.cke := '1';
+      if r.cfg.renable = '1' and r.cfg.cke = '1' then
+        v.cfg.command := "010"; v.istate := pre;
+      end if;
+    when pre =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
+      end if;
+    when ref =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.icnt := r.icnt - 1;
+        if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
+      end if;
+    when lmode =>
+      if r.cfg.command = "000" then
+        if r.cfg.mobileen = "11" then
+          v.cfg.command := "111"; v.istate := emode;
+        else
+          v.istate := finish;
+        end if;
+      end if;
+    when emode =>
+      if r.cfg.command = "000" then
+        v.istate := finish;
+      end if;
+    when others =>
+      if r.cfg.renable = '0' and r.sdstate /= dpd then
+        v.istate := iidle;
+      end if;
+    end case;
+
+    if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
+      if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
+    end if;
+
+    if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
+
+-- second part of main fsm
+
+    case r.mstate is
+    when active =>
+      if v.hready = '1' then
+        v.mstate := midle;
+      end if;
+    when others => null;
+    end case;
+
+-- sdram refresh counter
+
+-- pragma translate_off
+    if not is_x(r.cfg.refresh) then
+-- pragma translate_on
+      if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
+        v.refresh := r.refresh - 1;
+        if (v.refresh(14) and not r.refresh(14))  = '1' then
+          v.refresh := r.cfg.refresh;
+          v.cfg.command := "100";
+          arefresh := '1';
+        end if;
+      end if;
+-- pragma translate_off
+    end if;
+-- pragma translate_on
+
+-- AHB register access
+-- if writing to IO space config regs. Just mapping write data to all config values in config reg
+    if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
+      if r.haddr(3 downto 2) = "00" then
+        if pageburst = 2 then v.cfg.pageburst :=  hwdata(17); end if;
+        v.cfg.command   :=  hwdata(20 downto 18);
+        v.cfg.csize     :=  hwdata(22 downto 21);
+        v.cfg.bsize     :=  hwdata(25 downto 23);
+        v.cfg.casdel    :=  hwdata(26);
+        v.cfg.trfc      :=  hwdata(29 downto 27);
+        v.cfg.trp       :=  hwdata(30);
+        v.cfg.renable   :=  hwdata(31);
+        v.cfg.refresh   :=  hwdata(14 downto 0);
+        v.refresh       :=  (others => '0');
+      elsif r.haddr(3 downto 2) = "01" then
+        if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
+        if r.cfg.pmode = "000" then
+          v.cfg.cke               :=  hwdata(30);
+        end if;
+        if r.cfg.mobileen(1) = '1' then
+          v.cfg.txsr              :=  hwdata(23 downto 20);
+          v.cfg.pmode             :=  hwdata(18 downto 16);
+          v.cfg.ds(3 downto 2)    :=  hwdata( 6 downto  5);
+          v.cfg.tcsr(3 downto 2)  :=  hwdata( 4 downto  3);
+          v.cfg.pasr(5 downto 3)  :=  hwdata( 2 downto  0);
+        end if;
+      end if;
+    end if;
+
+    -- Disable CS and DPD when Mobile SDR is Disabled
+    if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
+
+    -- Update EMR when ds, tcsr or pasr change
+    if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
+      if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
+      end if;
+      if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
+      end if;
+      if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
+        v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
+      end if;
+    end if;
+
+    regsd := (others => '0');
+    --reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
+    if r.haddr(3 downto 2) = "00" then
+      regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
+                             r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
+      if not lineburst then regsd(17) := '1'; end if;
+      regsd(16) := r.cfg.mobileen(1);
+      if BUS64 then regsd(15) := '1'; end if;
+      regsd(14 downto 0) := r.cfg.refresh;
+    elsif r.haddr(3 downto 2) = "01" then
+      regsd(31) := r.cfg.mobileen(0);
+      regsd(30) := r.cfg.cke;
+      regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
+                            r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
+    end if;
+
+    if (r.hsel and r.hio) = '1' then dout := regsd;
+    else
+      if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
+      else dout := r.hrdata(31 downto 0); end if;
+    end if;
+
+    v.nbdrive := not v.bdrive;
+
+    if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
+    else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
+
+-- reset
+
+    if rst = '0' then
+      v.sdstate       := sidle;
+      v.mstate        := midle;
+      v.istate        := iidle;
+      v.cmstate       := midle;
+      v.hsel          := '0';
+      v.cfg.command   := "000";
+      v.cfg.csize     := "01";
+      v.cfg.bsize     := "011";
+      v.cfg.casdel    :=  '1';
+      v.cfg.trfc      := "111";
+      if pwron = 1 then v.cfg.renable :=  '1';
+      else v.cfg.renable :=  '0'; end if;
+      v.cfg.trp       :=  '1';
+      v.dqm           := (others => '1');
+      v.sdwen         := '1';
+      v.rasn          := '1';
+      v.casn          := '1';
+      v.hready        := '1';
+      v.bsel          := '0';
+      v.startsd       := '0';
+      if (pageburst = 2) then
+        v.cfg.pageburst   :=  '0';
+      end if;
+      if mobile >= 2 then v.cfg.mobileen := "11";
+      elsif mobile = 1 then v.cfg.mobileen := "10";
+      else v.cfg.mobileen := "00"; end if;
+      v.cfg.txsr      := (others => '1');
+      v.cfg.pmode     := (others => '0');
+      v.cfg.ds        := (others => '0');
+      v.cfg.tcsr      := (others => '0');
+      v.cfg.pasr      := (others => '0');
+      if mobile >= 2 then v.cfg.cke := '0';
+      else v.cfg.cke       := '1'; end if;
+      v.sref_tmpcom   := "000";
+      v.idlecnt := (others => '1');
+    end if;
+
+    ri <= v;
+    ribdrive <= vbdrive;
+
+    ahbso.hready  <= r.hready;
+    ahbso.hresp   <= r.hresp;
+    ahbso.hrdata  <= ahbdrivedata(dout);
+
+  end process;
+
+  --sdo.sdcke     <= (others => '1');
+  sdo.sdcke     <= (others => r.cfg.cke);
+  ahbso.hconfig <= hconfig;
+  ahbso.hirq    <= (others => '0');
+  ahbso.hindex  <= hindex;
+  ahbso.hsplit  <= (others => '0');
+
+  -- Quick hack to get rid of undriven signal warnings. Check this for future
+  -- merge with main sdctrl.
+  drivehack : block
+  begin
+    sdo.qdrive <= '0';
+    sdo.nbdrive <= '0';
+    sdo.ce <= '0';
+    sdo.moben <= '0';
+    sdo.cal_rst <= '0';
+    sdo.oct <= '0';
+    sdo.xsdcsn <= (others => '1');
+    sdo.data(127 downto 16) <= (others => '0');
+    sdo.cb <= (others => '0');
+    sdo.ba <= (others => '0');
+    sdo.sdck <= (others => '0');
+    sdo.cal_en <= (others => '0');
+    sdo.cal_inc <= (others => '0');
+    sdo.cal_pll <= (others => '0');
+    sdo.odt <= (others => '0');
+    sdo.conf <= (others => '0');
+    sdo.vcbdrive <= (others => '0');
+    sdo.dqs_gate <= '0';
+    sdo.cbdqm <= (others => '0');
+    sdo.cbcal_en <= (others => '0');
+    sdo.cbcal_inc <= (others => '0');
+    sdo.read_pend <= (others => '0');
+    sdo.regwdata <= (others => '0');
+    sdo.regwrite <= (others => '0');
+  end block drivehack;
+
+  regs : process(clk, rst) begin
+    if rising_edge(clk) then
+      r <= ri; rbdrive <= ribdrive;
+      if rst = '0' then r.icnt <= (others => '0'); end if;
+    end if;
+    if (rst = '0') then
+      r.sdcsn  <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
+      if oepol = 0 then rbdrive <= (others => '1');
+      else rbdrive <= (others => '0'); end if;
+    end if;
+  end process;
+
+  rgen : if not SDINVCLK generate
+    sdo.address  <= r.address;
+    sdo.bdrive   <= r.nbdrive when oepol = 1 else r.bdrive;
+    sdo.vbdrive  <= zero32 & rbdrive;
+    sdo.sdcsn    <= r.sdcsn;
+    sdo.sdwen    <= r.sdwen;
+    sdo.dqm      <= "11111111" & r.dqm;
+    sdo.rasn     <= r.rasn;
+    sdo.casn     <= r.casn;
+
+    mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
+      sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
+    end generate;
+
+    wrdata : if not BUS16 generate
+      drivebus: for i in 0 to sdbits/64 generate
+        sdo.data(31+32*i downto 32*i) <= r.hwdata;
+      end generate;
+    end generate;
+  end generate;
+
+  ngen : if SDINVCLK generate
+    nregs : process(clk, rst) begin
+      if falling_edge(clk) then
+        sdo.address  <= r.address;
+        if oepol = 1 then sdo.bdrive <= r.nbdrive;
+        else sdo.bdrive <= r.bdrive; end if;
+        sdo.vbdrive  <= zero32 & rbdrive;
+        sdo.sdcsn    <= r.sdcsn;
+        sdo.sdwen    <= r.sdwen;
+        sdo.dqm      <= "11111111" & r.dqm;
+        sdo.rasn     <= r.rasn;
+        sdo.casn     <= r.casn;
+        if BUS16 then --mux data depending on Low/High HW
+          if (r.lhw ='1') then
+            sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
+          else
+            sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
+          end if;
+        end if;
+
+        if not BUS16 then
+          for i in 0 to sdbits/64 loop
+            sdo.data(31+32*i downto 32*i) <= r.hwdata;
+          end loop;
+        end if;
+      end if;
+      if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
+    end process;
+  end generate;
+
+-- pragma translate_off
+  bootmsg : report_version
+  generic map ("sdctrl16" & tost(hindex) &
+    ": PC133 SDRAM controller rev " & tost(REVISION));
+-- pragma translate_on
+
+end;
+
diff --git a/designs/SPWBrick-MiniSpartan6p/testbench.vhd b/designs/SPWBrick-MiniSpartan6p/testbench.vhd
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/testbench.vhd
@@ -0,0 +1,200 @@
+------------------------------------------------------------------------------
+--  LEON3 Demonstration design test bench
+--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+use work.debug.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+library grlib;
+use grlib.stdlib.all;
+
+use work.config.all;	-- configuration
+
+
+entity testbench is
+  generic (
+    fabtech   : integer := CFG_FABTECH;
+    memtech   : integer := CFG_MEMTECH;
+    padtech   : integer := CFG_PADTECH;
+    clktech   : integer := CFG_CLKTECH;
+    disas     : integer := CFG_DISAS;	-- Enable disassembly to console
+    dbguart   : integer := CFG_DUART;	-- Print UART on console
+    pclow     : integer := CFG_PCLOW;
+
+    clkperiod : integer := 20;		-- system clock period
+    romdepth  : integer := 22		-- rom address depth (flash 4 MB)
+ --   sramwidth  : integer := 32;		-- ram data width (8/16/32)
+ --   sramdepth  : integer := 20;		-- ram address depth
+ --   srambanks  : integer := 2		-- number of ram banks
+  );
+end;
+
+architecture behav of testbench is
+
+constant promfile  : string := "prom.srec";  -- rom contents
+constant sramfile  : string := "ram.srec";  -- ram contents
+constant sdramfile : string := "ram.srec"; -- sdram contents
+
+
+signal SW     : std_logic_vector(4 downto 1);
+signal clk : std_logic := '0';
+signal Rst    : std_logic := '0';			-- Reset
+constant ct : integer := clkperiod/2;
+
+signal address  : std_logic_vector(21 downto 0);
+signal data     : std_logic_vector(31 downto 24);
+
+signal romsn    : std_logic;
+signal oen      : std_logic;
+signal writen   : std_logic;
+signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
+signal dsurst   : std_logic;
+signal error    : std_logic;
+
+signal sdcke    : std_logic;
+signal sdcsn    : std_logic;
+signal sdwen    : std_logic;                       -- write en
+signal sdrasn   : std_logic;                       -- row addr stb
+signal sdcasn   : std_logic;                       -- col addr stb
+signal dram_ldqm : std_logic;
+signal dram_udqm : std_logic;
+signal sdclk    : std_logic;
+signal dram_ba  : std_logic_vector(1 downto 0);
+
+
+
+constant lresp : boolean := false;
+
+
+signal sa      	: std_logic_vector(12 downto 0);
+signal sd   	: std_logic_vector(15 downto 0);
+
+
+begin
+
+  clk <= not clk after ct * 1 ns; --50 MHz clk
+  rst <= dsurst; --reset
+  dsuen <= '1';
+  dsubre <= '1'; -- inverted on the board
+  sw(1) <= rst;
+
+  d3 : entity work.leon3mp
+        generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
+        port map (
+            CLK50  => clk,
+            LEDS   => open,
+            SW     => SW,
+            dram_addr => sa,
+            dram_ba_0	=> dram_ba(0),
+            dram_ba_1	=> dram_ba(1),
+            dram_dq	=> sd(15 downto 0),
+            dram_clk  	=> sdclk,
+            dram_cke  	=> sdcke,
+            dram_cs_n   => sdcsn,
+            dram_we_n  	=> sdwen,
+            dram_ras_n  => sdrasn,
+            dram_cas_n  => sdcasn,
+            dram_ldqm	  => dram_ldqm,
+            dram_udqm	  => dram_udqm,
+            uart_txd  	=> dsutx,
+            uart_rxd  	=> dsurx);
+
+    u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 9, index => 1024, fname => sdramfile)
+	PORT MAP(
+            Dq => sd(15 downto 0), Addr => sa(12 downto 0),
+            Ba => dram_ba, Clk => sdclk, Cke => sdcke,
+            Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
+            Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
+
+
+
+  error <= 'H';			  -- ERROR pull-up
+
+   iuerr : process
+   begin
+     wait for 2500 ns;
+     if to_x01(error) = '1' then wait on error; end if;
+     assert (to_x01(error) = '1')
+       report "*** IU in error mode, simulation halted ***"
+         severity failure ;
+   end process;
+
+  data <= buskeep(data) after 5 ns;
+  sd <= buskeep(sd) after 5 ns;
+
+  dsucom : process
+    variable w32 : std_logic_vector(31 downto 0);
+    constant txp : time := 160 * 1 ns;
+    procedure writeReg(signal dsutx : out std_logic;  address : integer; value : integer) is
+    begin
+        txc(dsutx, 16#c0#, txp); --control byte
+        txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)),  address, txp); --adress
+        txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data
+    end;
+
+    procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic;  address : integer; value: out std_logic_vector) is
+
+    begin
+        txc(dsutx, 16#a0#, txp); --control byte
+        txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
+        rxi(dsurx, value, txp, lresp); --write data
+    end;
+
+    procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
+    variable c8  : std_logic_vector(7 downto 0);
+    begin
+        dsutx <= '1';
+    dsurst <= '0'; --reset low
+    wait for 500 ns;
+    dsurst <= '1'; --reset high
+    --wait; --evig w8
+    wait for 5000 ns;
+    txc(dsutx, 16#55#, txp);
+    --dsucfg(dsutx, dsurx);
+    writeReg(dsutx,16#40000000#,16#12345678#);
+    writeReg(dsutx,16#40000004#,16#22222222#);
+    writeReg(dsutx,16#40000008#,16#33333333#);
+    writeReg(dsutx,16#4000000C#,16#44444444#);
+
+    readReg(dsurx,dsutx,16#40000000#,w32);
+    readReg(dsurx,dsutx,16#40000004#,w32);
+    readReg(dsurx,dsutx,16#40000008#,w32);
+    readReg(dsurx,dsutx,16#4000000C#,w32);
+
+    end;
+
+  begin
+  dsucfg(dsutx, dsurx);
+
+
+    wait;
+ end process;
+end ;
+
diff --git a/designs/SPWBrick-MiniSpartan6p/withSPW.ucf b/designs/SPWBrick-MiniSpartan6p/withSPW.ucf
new file mode 100644
--- /dev/null
+++ b/designs/SPWBrick-MiniSpartan6p/withSPW.ucf
@@ -0,0 +1,143 @@
+# Clocks
+NET "CLK50" PERIOD = 20 ns |LOC = "K3";
+#NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
+# LEDs
+NET "LEDS<0>" LOC="P11" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<1>" LOC="N9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<2>" LOC="M9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<3>" LOC="P9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<4>" LOC="T8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<5>" LOC="N8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<6>" LOC="P8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<7>" LOC="P7"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+
+# DIP Switches
+NET "SW<1>"   LOC="L1" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<2>"   LOC="L3" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<3>"   LOC="L4" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<4>"   LOC="L5" |IOSTANDARD=LVTTL |PULLUP;
+
+NET "uart_rxd"  LOC="M7" |IOSTANDARD=LVTTL;
+NET "uart_txd"  LOC="N6" |IOSTANDARD=LVTTL;
+
+# SDRAM
+NET "dram_udqm"    LOC="F15"   |IOSTANDARD=LVTTL;
+NET "dram_clk" LOC="G16" |IOSTANDARD=LVTTL;
+NET "dram_cke"     LOC="H16"   |IOSTANDARD=LVTTL;
+NET "dram_ba_1"     LOC="T14"   |IOSTANDARD=LVTTL;
+NET "dram_ba_0"     LOC="R14"   |IOSTANDARD=LVTTL;
+NET "dram_cs_n" LOC="R1"  |IOSTANDARD=LVTTL;
+NET "dram_ras_n"    LOC="R2"    |IOSTANDARD=LVTTL;
+NET "dram_cas_n"    LOC="T4"    |IOSTANDARD=LVTTL;
+NET "dram_we_n"     LOC="R5"    |IOSTANDARD=LVTTL;
+NET "dram_ldqm"    LOC="T5"    |IOSTANDARD=LVTTL;
+NET "dram_addr<0>"    LOC="T15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<1>"    LOC="R16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<2>"    LOC="P15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<3>"    LOC="P16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<4>"    LOC="N16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<5>"    LOC="M15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<6>"    LOC="M16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<7>"    LOC="L16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<8>"    LOC="K15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<9>"    LOC="K16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<10>"   LOC="R15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<11>"   LOC="J16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<12>"   LOC="H15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<0>"    LOC="T13"   |IOSTANDARD=LVTTL;
+NET "dram_dq<1>"    LOC="T12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<2>"    LOC="R12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<3>"    LOC="T9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<4>"    LOC="R9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<5>"    LOC="T7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<6>"    LOC="R7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<7>"    LOC="T6"    |IOSTANDARD=LVTTL;
+NET "dram_dq<8>"    LOC="F16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<9>"    LOC="E15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<10>"   LOC="E16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<11>"   LOC="D16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<12>"   LOC="B16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<13>"   LOC="B15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<14>"   LOC="C16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<15>"   LOC="C15"   |IOSTANDARD=LVTTL;
+#Created by Constraints Editor (xc6slx25-ftg256-3) - 2016/12/08
+INST "dram_addr(0)" TNM = dram_addr;
+INST "dram_addr(1)" TNM = dram_addr;
+INST "dram_addr(2)" TNM = dram_addr;
+INST "dram_addr(3)" TNM = dram_addr;
+INST "dram_addr(4)" TNM = dram_addr;
+INST "dram_addr(5)" TNM = dram_addr;
+INST "dram_addr(6)" TNM = dram_addr;
+INST "dram_addr(7)" TNM = dram_addr;
+INST "dram_addr(8)" TNM = dram_addr;
+INST "dram_addr(9)" TNM = dram_addr;
+INST "dram_addr(10)" TNM = dram_addr;
+INST "dram_addr(11)" TNM = dram_addr;
+INST "dram_addr(12)" TNM = dram_addr;
+INST "dram_addr(0)" TNM = dram_out;
+INST "dram_addr(1)" TNM = dram_out;
+INST "dram_addr(2)" TNM = dram_out;
+INST "dram_addr(3)" TNM = dram_out;
+INST "dram_addr(4)" TNM = dram_out;
+INST "dram_addr(5)" TNM = dram_out;
+INST "dram_addr(6)" TNM = dram_out;
+INST "dram_addr(7)" TNM = dram_out;
+INST "dram_addr(8)" TNM = dram_out;
+INST "dram_addr(9)" TNM = dram_out;
+INST "dram_addr(10)" TNM = dram_out;
+INST "dram_addr(11)" TNM = dram_out;
+INST "dram_addr(12)" TNM = dram_out;
+INST "dram_ba_0" TNM = dram_out;
+INST "dram_ba_1" TNM = dram_out;
+INST "dram_cas_n" TNM = dram_out;
+INST "dram_cke" TNM = dram_out;
+#INST "dram_clk" TNM = dram_out;
+INST "dram_cs_n" TNM = dram_out;
+INST "dram_dq(0)" TNM = dram_out;
+INST "dram_dq(1)" TNM = dram_out;
+INST "dram_dq(2)" TNM = dram_out;
+INST "dram_dq(3)" TNM = dram_out;
+INST "dram_dq(4)" TNM = dram_out;
+INST "dram_dq(5)" TNM = dram_out;
+INST "dram_dq(6)" TNM = dram_out;
+INST "dram_dq(7)" TNM = dram_out;
+INST "dram_dq(8)" TNM = dram_out;
+INST "dram_dq(9)" TNM = dram_out;
+INST "dram_dq(10)" TNM = dram_out;
+INST "dram_dq(11)" TNM = dram_out;
+INST "dram_dq(12)" TNM = dram_out;
+INST "dram_dq(13)" TNM = dram_out;
+INST "dram_dq(14)" TNM = dram_out;
+INST "dram_dq(15)" TNM = dram_out;
+INST "dram_ldqm" TNM = dram_out;
+INST "dram_ras_n" TNM = dram_out;
+INST "dram_udqm" TNM = dram_out;
+INST "dram_we_n" TNM = dram_out;
+TIMEGRP "dram_out" OFFSET = OUT 12 ns AFTER "CLK50";
+INST "dram_dq(0)" TNM = dram_in;
+INST "dram_dq(1)" TNM = dram_in;
+INST "dram_dq(2)" TNM = dram_in;
+INST "dram_dq(3)" TNM = dram_in;
+INST "dram_dq(4)" TNM = dram_in;
+INST "dram_dq(5)" TNM = dram_in;
+INST "dram_dq(6)" TNM = dram_in;
+INST "dram_dq(7)" TNM = dram_in;
+INST "dram_dq(8)" TNM = dram_in;
+INST "dram_dq(9)" TNM = dram_in;
+INST "dram_dq(10)" TNM = dram_in;
+INST "dram_dq(11)" TNM = dram_in;
+INST "dram_dq(12)" TNM = dram_in;
+INST "dram_dq(13)" TNM = dram_in;
+INST "dram_dq(14)" TNM = dram_in;
+INST "dram_dq(15)" TNM = dram_in;
+TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE "CLK50" RISING;
+
+
+NET "spw_rxdp" LOC = "h2";# | IOSTANDARD = LVDS_33;
+NET "spw_rxdn" LOC = "h1";# | IOSTANDARD = LVDS_33;
+NET "spw_rxsp" LOC = "f4";# | IOSTANDARD = LVDS_33;
+NET "spw_rxsn" LOC = "f3";#  | IOSTANDARD = LVDS_33;
+NET "spw_txdp" LOC = "e2";# | IOSTANDARD = LVTTL;
+NET "spw_txdn" LOC = "e1";# | IOSTANDARD = LVTTL;
+NET "spw_txsp" LOC = "g3";# | IOSTANDARD = LVTTL;
+NET "spw_txsn" LOC = "g1";# | IOSTANDARD = LVTTL;
diff --git a/designs/Timegen2/Makefile b/designs/Timegen2/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/Makefile
@@ -0,0 +1,77 @@
+VHDLIB=../..
+SELFDIR := $(dir $(lastword $(MAKEFILE_LIST)))
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=leon3mp
+BOARD=MiniSpartan6p
+DESIGN=leon3-MiniSpartan6p
+include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=withSPW.ucf
+UCF_PLANAHEAD=$(UCF)
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+XSTOPT=-uc leon3mp.xcf
+SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
+
+
+VHDLOPTSYNFILES = sdctrl16.vhd config.vhd leon3mp.vhd
+
+VHDLSIMFILES=mt48lc16m16a2.vhd testbench.vhd
+
+SIMTOP=testbench
+SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
+BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
+
+TECHLIBS = unisim
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann  usbhc fmf ftlib gsi
+
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs can pwm greth coremp7 ac97 atf \
+	grlfpc \
+	./dsp/lpp_fft_rtax \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lpp_sim/CY7C1061DV33 \
+	./lpp_uart \
+	./lpp_usb \
+	./dsp/lpp_fft \
+	./lpp_leon3_soc \
+	./lpp_debug_lfr
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd \
+	lpp_lfr_ms_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd \
+	lpp_lfr_ms.vhd \
+	lpp_lfr_sim_pkg.vhd \
+	mtie_maps.vhd \
+	ftsrctrlc.vhd \
+	ftsdctrl.vhd \
+	ftsrctrl8.vhd \
+	ftmctrl.vhd \
+	ftsdctrl64.vhd \
+	ftahbram.vhd \
+	ftahbram2.vhd \
+	sramft.vhd \
+	nandfctrlx.vhd
+
+include $(GRLIB)/bin/Makefile
+
+##################  project specific targets ##########################
+
+load-ram:
+	xc3sprog -c ftdi -p0 leon3mp.bit
+
+load-flash:
+	xc3sprog -c ftdi -p0 $(VHDLIB)/boards/$(BOARD)/bscan_spi_s6lx25_ftg256.bit
+	xc3sprog -c ftdi -I leon3mp.bit
diff --git a/designs/Timegen2/README.md b/designs/Timegen2/README.md
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/README.md
@@ -0,0 +1,66 @@
+This LEON3 design is tailored to the Scarab Hardware [MiniSpartan6+](https://www.scarabhardware.com/minispartan6/) board.
+
+Simulation and synthesis
+------------------------
+
+This design tries to use as much as possible free (as in freedom) tools and at least free (as in free beer) when impossible.
+
+
+Note that the simulation doesn't work as expected yet.
+
+
+To build the design:
+```bash
+make ise
+```
+
+To load into FPGA RAM:
+```bash
+make load-ram
+```
+
+To load into FPGA Flash:
+```bash
+make load-flash
+```
+
+Design specifics
+----------------
+
+* The AHB and processor is clocked from the 50 MHz clock.
+
+* The SDRAM is working with the sdctrl16 memory controller taken from leon3-altera-de2-ep2c35 design.
+
+* The UART DSU interface ie enabled and connected to interface B of ft2232H chip.
+  Start GRMON with -uart /dev/ttyUSB1
+
+* Output from GRMON2 should look similar to this:
+
+```bash
+  GRMON2 LEON debug monitor v2.0.80-beta 64-bit eval version
+  
+  Copyright (C) 2016 Cobham Gaisler - All rights reserved.
+  For latest updates, go to http://www.gaisler.com/
+  Comments or bug-reports to support@gaisler.com
+  
+  This eval version will expire on 18/04/2017
+
+  using port /dev/ttyUSB1 @ 115200 baud
+  GRLIB build version: 4164
+  Detected frequency:  50 MHz
+  
+  Component                            Vendor
+  LEON3 SPARC V8 Processor             Cobham Gaisler
+  AHB Debug UART                       Cobham Gaisler
+  AHB/APB Bridge                       Cobham Gaisler
+  LEON3 Debug Support Unit             Cobham Gaisler
+  PC133 SDRAM Controller               Cobham Gaisler
+  Multi-processor Interrupt Ctrl.      Cobham Gaisler
+  Modular Timer Unit                   Cobham Gaisler
+  General Purpose I/O port             Cobham Gaisler
+  
+  Use command 'info sys' to print a detailed report of attached cores
+
+grmon2> 
+
+```
\ No newline at end of file
diff --git a/designs/Timegen2/SPW_Pinout.txt b/designs/Timegen2/SPW_Pinout.txt
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/SPW_Pinout.txt
@@ -0,0 +1,11 @@
+F0 -> L46P   -> DOUT+  -> 9 -> Grey
+F1 -> L46N   -> DOUT-  -> 5 -> Yellow
+
+F5 -> L40P   -> SOUT+  -> 8 -> Violet
+F7 -> L40N   -> SOUT-  -> 4 -> Orange
+
+F3 -> L53P   -> SIN+  -> 2 -> Brown
+F6 -> L53N   -> SIN-  -> 7 -> Blue
+
+F9  -> L39N   -> DIN-  -> 6 -> Green
+F10 -> L39P   -> DIN+  -> 1 -> Black
diff --git a/designs/Timegen2/config.vhd b/designs/Timegen2/config.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/config.vhd
@@ -0,0 +1,162 @@
+
+
+
+-----------------------------------------------------------------------------
+-- LEON3 Demonstration design test bench configuration
+-- Copyright (C) 2009 Aeroflex Gaisler
+------------------------------------------------------------------------------
+
+
+library techmap;
+use techmap.gencomp.all;
+
+package config is
+-- Technology and synthesis options
+  constant CFG_FABTECH : integer := spartan6;
+  constant CFG_MEMTECH : integer := spartan6;
+  constant CFG_PADTECH : integer := spartan6;
+  constant CFG_TRANSTECH : integer := GTP0;
+  constant CFG_NOASYNC : integer := 0;
+  constant CFG_SCAN : integer := 0;
+-- Clock generator
+  constant CFG_CLKTECH : integer := spartan6;
+  constant CFG_CLKMUL : integer := (3);
+  constant CFG_CLKDIV : integer := (2);
+  constant CFG_OCLKDIV : integer := 1;
+  constant CFG_OCLKBDIV : integer := 0;
+  constant CFG_OCLKCDIV : integer := 0;
+  constant CFG_PCIDLL : integer := 0;
+  constant CFG_PCISYSCLK: integer := 0;
+  constant CFG_CLK_NOFB : integer := 0;
+-- LEON3 processor core
+  constant CFG_LEON3 : integer := 1;
+  constant CFG_NCPU : integer := (1);
+  constant CFG_NWIN : integer := (8);
+  constant CFG_V8 : integer := 2 + 4*0;
+  constant CFG_MAC : integer := 0;
+  constant CFG_BP : integer := 1;
+  constant CFG_SVT : integer := 1;
+  constant CFG_RSTADDR : integer := 16#00000#;
+  constant CFG_LDDEL : integer := (2);
+  constant CFG_NOTAG : integer := 1;
+  constant CFG_NWP : integer := (0);
+  constant CFG_PWD : integer := 0*2;
+  constant CFG_FPU : integer := 0 + 16*0 + 32*0;
+  constant CFG_GRFPUSH : integer := 0;
+  constant CFG_ICEN : integer := 1;
+  constant CFG_ISETS : integer := 1;
+  constant CFG_ISETSZ : integer := 8;
+  constant CFG_ILINE : integer := 8;
+  constant CFG_IREPL : integer := 0;
+  constant CFG_ILOCK : integer := 0;
+  constant CFG_ILRAMEN : integer := 0;
+  constant CFG_ILRAMADDR: integer := 16#8E#;
+  constant CFG_ILRAMSZ : integer := 1;
+  constant CFG_DCEN : integer := 1;
+  constant CFG_DSETS : integer := 1;
+  constant CFG_DSETSZ : integer := 8;
+  constant CFG_DLINE : integer := 8;
+  constant CFG_DREPL : integer := 0;
+  constant CFG_DLOCK : integer := 0;
+  constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
+  constant CFG_DFIXED : integer := 16#0#;
+  constant CFG_DLRAMEN : integer := 0;
+  constant CFG_DLRAMADDR: integer := 16#8F#;
+  constant CFG_DLRAMSZ : integer := 1;
+  constant CFG_MMUEN : integer := 0;
+  constant CFG_ITLBNUM : integer := 8;
+  constant CFG_DTLBNUM : integer := 2;
+  constant CFG_TLB_TYPE : integer := 1 + 0*2;
+  constant CFG_TLB_REP : integer := 1;
+  constant CFG_MMU_PAGE : integer := 0;
+  constant CFG_DSU : integer := 1;
+  constant CFG_ITBSZ : integer := 0 + 64*0;
+  constant CFG_ATBSZ : integer := 0;
+  constant CFG_AHBPF : integer := 0;
+  constant CFG_LEON3FT_EN : integer := 0;
+  constant CFG_IUFT_EN : integer := 0;
+  constant CFG_FPUFT_EN : integer := 0;
+  constant CFG_RF_ERRINJ : integer := 0;
+  constant CFG_CACHE_FT_EN : integer := 0;
+  constant CFG_CACHE_ERRINJ : integer := 0;
+  constant CFG_LEON3_NETLIST: integer := 0;
+  constant CFG_DISAS : integer := 0 + 0;
+  constant CFG_PCLOW : integer := 2;
+  constant CFG_STAT_ENABLE : integer := 0;
+  constant CFG_STAT_CNT : integer := 1;
+  constant CFG_STAT_NMAX : integer := 0;
+  constant CFG_STAT_DSUEN : integer := 0;
+  constant CFG_NP_ASI : integer := 0;
+  constant CFG_WRPSR : integer := 0;
+  constant CFG_ALTWIN : integer := 0;
+  constant CFG_REX : integer := 0;
+-- AMBA settings
+  constant CFG_DEFMST : integer := (0);
+  constant CFG_RROBIN : integer := 1;
+  constant CFG_SPLIT : integer := 1;
+  constant CFG_FPNPEN : integer := 0;
+  constant CFG_AHBIO : integer := 16#FFF#;
+  constant CFG_APBADDR : integer := 16#800#;
+  constant CFG_AHB_MON : integer := 0;
+  constant CFG_AHB_MONERR : integer := 0;
+  constant CFG_AHB_MONWAR : integer := 0;
+  constant CFG_AHB_DTRACE : integer := 0;
+-- DSU UART
+  constant CFG_AHB_UART : integer := 1;
+-- JTAG based DSU interface
+  constant CFG_AHB_JTAG : integer := 1;
+-- Xilinx MIG
+  constant CFG_MIG_DDR2 : integer := 1;
+  constant CFG_MIG_RANKS : integer := (1);
+  constant CFG_MIG_COLBITS : integer := (10);
+  constant CFG_MIG_ROWBITS : integer := (13);
+  constant CFG_MIG_BANKBITS: integer := (2);
+  constant CFG_MIG_HMASK : integer := 16#FC0#;
+-- AHB ROM
+  constant CFG_AHBROMEN : integer := 1;
+  constant CFG_AHBROPIP : integer := 0;
+  constant CFG_AHBRODDR : integer := 16#000#;
+  constant CFG_ROMADDR : integer := 16#100#;
+  constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
+-- AHB RAM
+  constant CFG_AHBRAMEN : integer := 1;
+  constant CFG_AHBRSZ : integer := 4;
+  constant CFG_AHBRADDR : integer := 16#A00#;
+  constant CFG_AHBRPIPE : integer := 0;
+-- UART 1
+  constant CFG_UART1_ENABLE : integer := 1;
+  constant CFG_UART1_FIFO : integer := 4;
+-- LEON3 interrupt controller
+  constant CFG_IRQ3_ENABLE : integer := 1;
+  constant CFG_IRQ3_NSEC : integer := 0;
+-- Modular timer
+  constant CFG_GPT_ENABLE : integer := 1;
+  constant CFG_GPT_NTIM : integer := (2);
+  constant CFG_GPT_SW : integer := (8);
+  constant CFG_GPT_TW : integer := (32);
+  constant CFG_GPT_IRQ : integer := (8);
+  constant CFG_GPT_SEPIRQ : integer := 1;
+  constant CFG_GPT_WDOGEN : integer := 0;
+  constant CFG_GPT_WDOG : integer := 16#0#;
+-- GPIO port
+  constant CFG_GRGPIO_ENABLE : integer := 1;
+  constant CFG_GRGPIO_IMASK : integer := 16#0000#;
+  constant CFG_GRGPIO_WIDTH : integer := 1;
+
+-- SPI controller
+  constant CFG_SPICTRL_ENABLE : integer := 1;
+  constant CFG_SPICTRL_NUM : integer := (1);
+  constant CFG_SPICTRL_SLVS : integer := (1);
+  constant CFG_SPICTRL_FIFO : integer := (2);
+  constant CFG_SPICTRL_SLVREG : integer := 1;
+  constant CFG_SPICTRL_ODMODE : integer := 1;
+  constant CFG_SPICTRL_AM : integer := 0;
+  constant CFG_SPICTRL_ASEL : integer := 0;
+  constant CFG_SPICTRL_TWEN : integer := 0;
+  constant CFG_SPICTRL_MAXWLEN : integer := (0);
+  constant CFG_SPICTRL_SYNCRAM : integer := 0;
+  constant CFG_SPICTRL_FT : integer := 0;
+
+-- GRLIB debugging
+  constant CFG_DUART : integer := 0;
+end;
diff --git a/designs/Timegen2/leon3mp.vhd b/designs/Timegen2/leon3mp.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/leon3mp.vhd
@@ -0,0 +1,425 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.NUMERIC_STD.ALL;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library techmap;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+--pragma translate_off
+use gaisler.sim.all;
+--pragma translate_on
+library opencores;
+use opencores.spwpkg.all;
+use opencores.spwambapkg.all;
+LIBRARY lpp;
+USE lpp.general_purpose.ALL;
+use lpp.lpp_amba.all;
+USE lpp.lpp_lfr_management.ALL;
+
+use work.config.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity leon3mp is
+  generic (
+    fabtech  : integer := CFG_FABTECH;
+    memtech  : integer := CFG_MEMTECH;
+    padtech  : integer := CFG_PADTECH;
+    clktech  : integer := CFG_CLKTECH;
+    disas    : integer := CFG_DISAS;     -- Enable disassembly to console
+    dbguart  : integer := CFG_DUART;     -- Print UART on console
+    pclow    : integer := CFG_PCLOW
+    );
+  port (
+    CLK50  : in std_logic;
+    LEDS   : inout std_logic_vector(7 downto 0);
+    SW     : in std_logic_vector(4 downto 1);
+    dram_addr : out std_logic_vector(12 downto 0);
+    dram_ba_0	: out std_logic;
+    dram_ba_1	: out std_logic;
+    dram_dq	: inout std_logic_vector(15 downto 0);
+
+    dram_clk  	: out std_logic;
+    dram_cke  	: out std_logic;
+    dram_cs_n  	: out std_logic;
+    dram_we_n  	: out std_logic;        	-- sdram write enable
+    dram_ras_n  : out std_logic;               	-- sdram ras
+    dram_cas_n  : out std_logic;               	-- sdram cas
+    dram_ldqm	  : out std_logic;		-- sdram ldqm
+    dram_udqm	  : out std_logic;		-- sdram udqm
+    uart_txd  	: out std_logic;		-- DSU tx data
+    uart_rxd  	: in  std_logic;		-- DSU rx data
+
+    spw_rxdp      : in  std_logic;
+    spw_rxdn      : in  std_logic;
+    spw_rxsp      : in  std_logic;
+    spw_rxsn      : in  std_logic;
+    spw_txdp      : out std_logic;
+    spw_txdn      : out std_logic;
+    spw_txsp      : out std_logic;
+    spw_txsn      : out std_logic
+    );
+end;
+
+architecture rtl of leon3mp is
+  signal resetn : std_logic;
+  signal clkm, rstn, rstraw, rst : std_logic;
+  signal clk_50   : std_logic := '0';
+  signal clkm_inv : std_logic := '0';
+
+  signal cptr :  std_logic_vector(29 downto 0);
+  constant BOARD_FREQ : integer := 25000;                                -- CLK input frequency in KHz
+  constant CPU_FREQ   : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
+  signal sdi   : sdctrl_in_type;
+  signal sdo   : sdctrl_out_type;
+
+--AMBA bus standard interface signals--
+  signal apbi  : apb_slv_in_type;
+  signal apbo  : apb_slv_out_vector := (others => apb_none);
+  signal ahbsi : ahb_slv_in_type;
+  signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
+  signal ahbmi : ahb_mst_in_type;
+  signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
+
+  signal cgi : clkgen_in_type;
+  signal cgo : clkgen_out_type;
+
+  signal dui : uart_in_type;
+  signal duo : uart_out_type;
+
+  signal irqi : irq_in_vector(0 to CFG_NCPU-1);
+  signal irqo : irq_out_vector(0 to CFG_NCPU-1);
+
+  signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
+  signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
+
+  signal dsui : dsu_in_type;
+  signal dsuo : dsu_out_type;
+
+
+  signal gpti : gptimer_in_type;
+  signal gpto : gptimer_out_type;
+
+  signal gpioi_0 : gpio_in_type;
+  signal gpioo_0 : gpio_out_type;
+
+  signal dsubren : std_logic :='0';
+
+  signal spw_di: std_logic;
+  signal spw_si: std_logic;
+  signal spw_do: std_logic;
+  signal spw_so: std_logic;
+  signal spw_tick_in: std_logic;
+  signal spw_tick_out: std_logic;
+
+  -- AdvancedTrigger
+  SIGNAL Trigger     :  STD_LOGIC;
+  SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+  component sdctrl16
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end component;
+
+begin
+  resetn <= SW(1);
+
+  clk_pad : clkpad generic map (tech => padtech) port map (CLK50, clk_50);
+  process(clk_50)
+  begin
+  if clk_50'event and clk_50='1' then
+    clkm <= not clkm;
+  end if;
+  end process;
+  clkm_inv <= not clkm;
+
+  resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
+  rst0 : rstgen			-- reset generator (reset is active LOW)
+    port map (rst, clkm, '1', rstn, rstraw);
+
+
+----------------------------------------------------------------------
+---  AHB CONTROLLER --------------------------------------------------
+----------------------------------------------------------------------
+
+  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
+  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
+	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+	nahbm => CFG_NCPU+CFG_AHB_UART+1, nahbs => 8)
+
+  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+-----  LEON3 processor and DSU ---------------------------------------
+----------------------------------------------------------------------
+
+  cpu : for i in 0 to CFG_NCPU-1 generate
+    nosh : if CFG_GRFPUSH = 0 generate
+      u0 : leon3s 		-- LEON3 processor
+      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
+	0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
+	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
+	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
+        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
+        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
+	0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
+      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
+    		irqi(i), irqo(i), dbgi(i), dbgo(i));
+    end generate;
+  end generate;
+
+  --ledr[0] lit when leon 3 debugvector signals error
+  dsugen : if CFG_DSU = 1 generate
+    dsu0 : dsu3			-- LEON3 Debug Support Unit (slave)
+    generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
+       ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
+    port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
+    dsui.enable <= '1';
+
+  end generate;
+  nodsu : if CFG_DSU = 0 generate
+    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; --no timer freeze, no light.
+  end generate;
+
+  dcomgen : if CFG_AHB_UART = 1 generate
+    dcom0: ahbuart		-- Debug UART
+    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
+    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
+  end generate;
+  uart_txd <= duo.txd;
+  dui.rxd <= uart_rxd;
+
+
+----------------------------------------------------------------------
+---  Memory controllers ----------------------------------------------
+----------------------------------------------------------------------
+
+
+    sdc : sdctrl16 generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#, -- hmask => 16#C00#,
+	      ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
+	      sdbits => 16, pageburst => 2)
+      port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
+      sa_pad : outpadv generic map (width => 13, tech => padtech)
+	   port map (dram_addr, sdo.address(14 downto 2));
+      ba0_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_0, sdo.address(15));
+      ba1_pad : outpad generic map (tech => padtech)
+	   port map (dram_ba_1, sdo.address(16));
+      sd_pad : iopadvv generic map (width => 16, tech => padtech)
+	   port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
+      sdcke_pad : outpad generic map (tech => padtech)
+	   port map (dram_cke, sdo.sdcke(0));
+      sdwen_pad : outpad generic map (tech => padtech)
+	   port map (dram_we_n, sdo.sdwen);
+      sdcsn_pad : outpad generic map (tech => padtech)
+	   port map (dram_cs_n, sdo.sdcsn(0));
+      sdras_pad : outpad generic map (tech => padtech)
+	   port map (dram_ras_n, sdo.rasn);
+      sdcas_pad : outpad generic map (tech => padtech)
+	   port map (dram_cas_n, sdo.casn);
+      sdldqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_ldqm, sdo.dqm(0) );
+      sdudqm_pad : outpad generic map (tech => padtech)
+	   port map (dram_udqm, sdo.dqm(1));
+      dram_clk_pad : outpad generic map (tech => padtech)
+	   port map (dram_clk, clkm_inv);
+
+----------------------------------------------------------------------
+---  APB Bridge and various periherals -------------------------------
+----------------------------------------------------------------------
+
+  apb0 : apbctrl				-- AHB/APB bridge
+  generic map (hindex => 1, haddr => CFG_APBADDR)
+  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
+
+----------------------------------------------------------------------------------------
+
+    irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
+    irqctrl0 : irqmp			-- interrupt controller
+    generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
+    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
+  end generate;
+  irq3 : if CFG_IRQ3_ENABLE = 0 generate
+    x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate;
+    apbo(2) <= apb_none;
+  end generate;
+
+  --Timer unit, generates interrupts when a timer underflow.
+  gpt : if CFG_GPT_ENABLE /= 0 generate
+    timer0 : gptimer 			-- timer unit
+    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
+	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
+	nbits => CFG_GPT_TW)
+    port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
+    gpti <= gpti_dhalt_drive(dsuo.tstop);
+  end generate;
+  notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
+
+    gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GR GPIO0 unit
+    grgpio0: grgpio
+      generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => 4)
+      port map( rstn, clkm, apbi, apbo(9), gpioi_0, gpioo_0);
+      pio_pads : for i in 0 to 3 generate
+        pio_pad : iopad generic map (tech => padtech)
+            port map (LEDS(i), gpioo_0.dout(i), gpioo_0.oen(i), gpioi_0.din(i));
+      end generate;
+  end generate;
+  nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
+
+
+-------------------------------------------------------------------------------
+-- APB_LFR_MANAGEMENT ---------------------------------------------------------
+-------------------------------------------------------------------------------
+  apb_lfr_management_1 : apb_lfr_management
+    GENERIC MAP (
+      tech             => fabtech,
+      pindex           => 6,
+      paddr            => 6,
+      pmask            => 16#fff#,
+      NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
+    PORT MAP (
+      clk25MHz         => clkm,
+      resetn_25MHz     => rstn,
+      grspw_tick       => spw_tick_out,
+      apbi             => apbi,
+      apbo             => apbo(6),
+      HK_sample        => X"0000",
+      HK_val           => '0',
+      HK_sel           => OPEN,
+      DAC_SDO          => OPEN,
+      DAC_SCK          => OPEN,
+      DAC_SYNC         => OPEN,
+      DAC_CAL_EN       => OPEN,
+      coarse_time      => coarse_time,
+      fine_time        => fine_time,
+      LFR_soft_rstn    => OPEN
+      );
+
+----------------------------------------------------------------------
+---  APB_ADVANCED_TRIGGER  -----------------------------------------------------------
+----------------------------------------------------------------------
+advtrig0: APB_ADVANCED_TRIGGER
+  generic map(
+    pindex   => 5,
+    paddr    => 5)
+  port map(
+    rstn   => rstn,
+    clk    => clkm,
+    apbi   => apbi,
+    apbo   => apbo(5),
+
+    SPW_Tickout => spw_tick_out,
+    CoarseTime  => coarse_time,
+    FineTime    => fine_time,
+
+    Trigger    => Trigger
+    );
+
+
+  DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (LEDS(4), Trigger);
+  DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (LEDS(5), Trigger);
+  DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (LEDS(6), Trigger);
+  DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (LEDS(7), Trigger);
+
+-----------------------------------------------------------------------
+---  SpaceWire Light --------------------------------------------------
+-----------------------------------------------------------------------
+
+   spw0: spwamba
+      generic map (
+         tech        => memtech,
+         hindex      => 2,
+         pindex      => 10,
+         paddr       => 10,
+         pirq        => 10,
+         sysfreq     => 25.0e6,
+         txclkfreq   => 50.0e6,
+         rximpl      => impl_fast,
+         rxchunk     => 1,
+         tximpl      => impl_fast,
+         timecodegen => true,
+         rxfifosize  => 11,
+         txfifosize  => 11,
+         desctablesize => 10,
+         maxburst    => 3 )
+      port map (
+         clk     => clkm,
+         rxclk   => clk_50,
+         txclk   => clk_50,
+         rstn    => rstn,
+         apbi    => apbi,
+         apbo    => apbo(10),
+         ahbi    => ahbmi,
+         ahbo    => ahbmo(2),
+         tick_in => spw_tick_in,
+         tick_out => spw_tick_out,
+         spw_di  => spw_di,
+         spw_si  => spw_si,
+         spw_do  => spw_do,
+         spw_so  => spw_so );
+
+   spw_tick_in <= gpto.tick(2) when CFG_GPT_ENABLE /= 0 else '0';
+
+   spw_rxd_pad: inpad_ds
+      generic map (padtech, lvds, x33v)
+      port map (spw_rxdp, spw_rxdn, spw_di);
+   spw_rxs_pad: inpad_ds
+      generic map (padtech, lvds, x33v)
+      port map (spw_rxsp, spw_rxsn, spw_si);
+   -- spw_txd_pad: outpad_ds
+   --    generic map (padtech, lvds, x33v)
+   --    port map (spw_txdp, spw_txdn, spw_do, '0');
+   -- spw_txs_pad: outpad_ds
+   --    generic map (padtech, lvds, x33v)
+   --    port map (spw_txsp, spw_txsn, spw_so, '0');
+
+
+spw_txdp_pad : outpad generic map (tech => padtech)
+	   port map (spw_txdp, spw_do);
+spw_txdn_pad : outpad generic map (tech => padtech)
+	   port map (spw_txdn, not spw_do);
+
+spw_txsp_pad : outpad generic map (tech => padtech)
+	   port map (spw_txsp, spw_so);
+spw_txsn_pad : outpad generic map (tech => padtech)
+	   port map (spw_txsn, not spw_so);
+
+end rtl;
+
diff --git a/designs/Timegen2/leon3mp.xcf b/designs/Timegen2/leon3mp.xcf
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/leon3mp.xcf
@@ -0,0 +1,4 @@
+
+NET CLK50 	PERIOD = 20.0 ;
+
+
diff --git a/designs/Timegen2/mt48lc16m16a2.vhd b/designs/Timegen2/mt48lc16m16a2.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/mt48lc16m16a2.vhd
@@ -0,0 +1,1550 @@
+
+--*****************************************************************************
+--
+-- Micron Semiconductor Products, Inc.
+--
+-- Copyright 1997, Micron Semiconductor Products, Inc.
+-- All rights reserved.
+--
+--*****************************************************************************
+
+-- pragma translate_off
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use std.textio.all;
+
+PACKAGE mti_pkg IS
+
+    FUNCTION  To_StdLogic (s : BIT) RETURN STD_LOGIC;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
+    PROCEDURE TO_BITVECTOR  (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
+
+
+END mti_pkg;
+
+PACKAGE BODY mti_pkg IS
+
+    -- Convert BIT to STD_LOGIC
+    FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
+    BEGIN
+            CASE s IS
+                WHEN '0' => RETURN ('0');
+                WHEN '1' => RETURN ('1');
+                WHEN OTHERS => RETURN ('0');
+            END CASE;
+    END;
+
+    -- Convert STD_LOGIC to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        IF input = '1' THEN
+            result := weight;
+        ELSE
+            result := 0;                                            -- if unknowns, default to logic 0
+        END IF;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert BIT_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Convert STD_LOGIC_VECTOR to INTEGER
+    FUNCTION  TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
+    VARIABLE result : INTEGER := 0;
+    VARIABLE weight : INTEGER := 1;
+    BEGIN
+        FOR i IN input'LOW TO input'HIGH LOOP
+            IF input(i) = '1' THEN
+                result := result + weight;
+            ELSE
+                result := result + 0;                               -- if unknowns, default to logic 0
+            END IF;
+            weight := weight * 2;
+        END LOOP;
+        RETURN result;
+    END TO_INTEGER;
+
+    -- Conver INTEGER to BIT_VECTOR
+    PROCEDURE  TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
+    VARIABLE work,offset,outputlen,j : INTEGER := 0;
+    BEGIN
+        --length of vector
+        IF output'LENGTH > 32 THEN		--'
+            outputlen := 32;
+            offset := output'LENGTH - 32;		--'
+            IF input >= 0 THEN
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '0';		--'
+                END LOOP;
+            ELSE
+                FOR i IN offset-1 DOWNTO 0 LOOP
+                    output(output'HIGH - i) := '1';		--'		
+                END LOOP;
+            END IF;
+        ELSE
+            outputlen := output'LENGTH; 		--'
+        END IF;
+        --positive value
+        IF (input >= 0) THEN
+            work := input;
+            j := outputlen - 1;
+            FOR i IN 1 to 32 LOOP
+                IF j >= 0 then
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    END IF;
+                END IF;
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '0'; 		--'
+            END IF;
+        --negative value
+        ELSE
+            work := (-input) - 1;
+            j := outputlen - 1;
+            FOR i IN 1 TO 32 LOOP
+                IF j>= 0 THEN
+                    IF (work MOD 2) = 0 THEN 
+                        output(output'HIGH-j-offset) := '1'; 		--'
+                    ELSE
+                        output(output'HIGH-j-offset) := '0'; 		--'
+                    END IF;
+                END IF;    
+                work := work / 2;
+                j := j - 1;
+            END LOOP;
+            IF outputlen = 32 THEN
+                output(output'HIGH) := '1'; 		--'
+            END IF;
+        END IF;
+    END TO_BITVECTOR;
+
+END mti_pkg;   
+
+-----------------------------------------------------------------------------------------
+--
+--     File Name: MT48LC16M16A2.VHD
+--       Version: 0.0g
+--          Date: June 29th, 2000
+--         Model: Behavioral
+--     Simulator: Model Technology (PC version 5.3 PE)
+--
+--  Dependencies: None
+--
+--        Author: Son P. Huynh
+--         Email: sphuynh@micron.com
+--         Phone: (208) 368-3825
+--       Company: Micron Technology, Inc.
+--   Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
+--
+--   Description: Micron 256Mb SDRAM
+--
+--    Limitation: - Doesn't check for 4096-cycle refresh 		--'
+--
+--          Note: - Set simulator resolution to "ps" accuracy
+--
+--    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
+--                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
+--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
+--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
+--
+--                Copyright (c) 1998 Micron Semiconductor Products, Inc.
+--                All rights researved
+--
+--  Rev   Author          Phone         Date        Changes
+--  ----  ----------------------------  ----------  -------------------------------------
+--  0.0g  Son Huynh       208-368-3825  06/29/2000  Add Load/Dump memory array
+--        Micron Technology Inc.                    Modify tWR + tRAS timing check
+--
+--  0.0f  Son Huynh       208-368-3825  07/08/1999  Fix tWR = 1 Clk + 7.5 ns (Auto)
+--        Micron Technology Inc.                    Fix tWR = 15 ns (Manual)
+--                                                  Fix tRP (Autoprecharge to AutoRefresh)
+--
+--  0.0c  Son P. Huynh    208-368-3825  04/08/1999  Fix tWR + tRP in Write with AP
+--        Micron Technology Inc.                    Fix tRC check in Load Mode Register
+--
+--  0.0b  Son P. Huynh    208-368-3825  01/06/1998  Derive from 64Mb SDRAM model
+--        Micron Technology Inc.
+--
+-----------------------------------------------------------------------------------------
+
+LIBRARY STD;
+    USE STD.TEXTIO.ALL;
+LIBRARY IEEE;
+    USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY WORK;
+    USE WORK.MTI_PKG.ALL;
+    use std.textio.all;
+
+library grlib;
+use grlib.stdlib.all;
+use grlib.stdio.all;
+
+ENTITY mt48lc16m16a2 IS
+    GENERIC (
+        -- Timing Parameters for -75 (PC133) and CAS Latency = 2
+        tAC       : TIME    :=  6.0 ns;
+        tHZ       : TIME    :=  7.0 ns;
+        tOH       : TIME    :=  2.7 ns;
+        tMRD      : INTEGER :=  2;          -- 2 Clk Cycles
+        tRAS      : TIME    := 44.0 ns;
+        tRC       : TIME    := 66.0 ns;
+        tRCD      : TIME    := 20.0 ns;
+        tRP       : TIME    := 20.0 ns;
+        tRRD      : TIME    := 15.0 ns;
+        tWRa      : TIME    :=  7.5 ns;     -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
+        tWRp      : TIME    := 15.0 ns;     -- A2 Version - Precharge mode only (15 ns)
+
+        tAH       : TIME    :=  0.8 ns;
+        tAS       : TIME    :=  1.5 ns;
+        tCH       : TIME    :=  2.5 ns;
+        tCL       : TIME    :=  2.5 ns;
+        tCK       : TIME    := 10.0 ns;
+        tDH       : TIME    :=  0.8 ns;
+        tDS       : TIME    :=  1.5 ns;
+        tCKH      : TIME    :=  0.8 ns;
+        tCKS      : TIME    :=  1.5 ns;
+        tCMH      : TIME    :=  0.8 ns;
+        tCMS      : TIME    :=  1.5 ns;
+
+        addr_bits : INTEGER := 13;
+        data_bits : INTEGER := 16;
+        col_bits  : INTEGER :=  9;
+        index     : INTEGER :=  0;
+	fname     : string := "ram.srec"	-- File to read from
+    );
+    PORT (
+        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
+        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        Ba    : IN    STD_LOGIC_VECTOR := "00";
+        Clk   : IN    STD_LOGIC := '0';
+        Cke   : IN    STD_LOGIC := '1';
+        Cs_n  : IN    STD_LOGIC := '1';
+        Ras_n : IN    STD_LOGIC := '1';
+        Cas_n : IN    STD_LOGIC := '1';
+        We_n  : IN    STD_LOGIC := '1';
+        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
+    );
+END mt48lc16m16a2;
+
+ARCHITECTURE behave OF mt48lc16m16a2 IS
+    TYPE   State       IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
+    TYPE   Array4xI    IS ARRAY (3 DOWNTO 0) OF INTEGER;
+    TYPE   Array4xT    IS ARRAY (3 DOWNTO 0) OF TIME;
+    TYPE   Array4xB    IS ARRAY (3 DOWNTO 0) OF BIT;
+    TYPE   Array4x2BV  IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
+    TYPE   Array4xCBV  IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
+    TYPE   Array_state IS ARRAY (4 DOWNTO 0) OF State;
+    SIGNAL Operation : State := NOP;
+    SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
+    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
+    SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
+    SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
+    SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
+    SIGNAL Write_burst_mode : BIT := '0';
+    SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
+
+    -- Checking internal wires
+    SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
+    SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
+    SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
+    SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+
+BEGIN
+    -- CS# Decode
+    WITH Cs_n SELECT
+        Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    WITH Cs_n SELECT
+        We_in  <= TO_BIT (We_n,  '1') WHEN '0',
+                  '1' WHEN '1',
+                  '1' WHEN OTHERS;
+    
+    -- Commands Decode
+    Active_enable   <= NOT(Ras_in) AND     Cas_in  AND     We_in;
+    Aref_enable     <= NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
+    Burst_term      <=     Ras_in  AND     Cas_in  AND NOT(We_in);
+    Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
+    Prech_enable    <= NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
+    Read_enable     <=     Ras_in  AND NOT(Cas_in) AND     We_in;
+    Write_enable    <=     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
+
+    -- Burst Length Decode
+    Burst_length_1  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
+    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
+    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
+    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
+
+    -- CAS Latency Decode
+    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
+    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
+
+    -- Write Burst Mode
+    Write_burst_mode <= Mode_reg(9);
+
+    -- RAS Clock for checking tWR and tRP
+    PROCESS
+        variable Clk0, Clk1 : integer := 0;
+    begin
+        RAS_clk <= '1';
+        wait for 0.5 ns;
+        RAS_clk <= '0';
+        wait for 0.5 ns;
+        if Clk0 > 100 or Clk1 > 100 then
+            wait;
+        else
+            if Clk = '1' and Cke = '1' then
+                Clk0 := 0;
+                Clk1 := Clk1 + 1;
+            elsif Clk = '0' and Cke = '1' then
+                Clk0 := Clk0 + 1;
+                Clk1 := 0;
+            end if;
+        end if;
+    END PROCESS;
+
+    -- System Clock
+    int_clk : PROCESS (Clk)
+        begin
+            IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN 		--'
+                CkeZ <= TO_BIT(Cke, '1');
+            END IF;
+            Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
+    END PROCESS;
+
+    state_register : PROCESS
+        -- NOTE: The extra bits in RAM_TYPE is for checking memory access.  A logic 1 means
+        --       the location is in use.  This will be checked when doing memory DUMP.
+        TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
+        TYPE ram_pntr IS ACCESS ram_type;
+        TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
+        VARIABLE Bank0 : ram_stor;
+        VARIABLE Bank1 : ram_stor;
+        VARIABLE Bank2 : ram_stor;
+        VARIABLE Bank3 : ram_stor;
+        VARIABLE Row_index, Col_index : INTEGER := 0;
+        VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
+
+        VARIABLE Col_addr : Array4xCBV;
+        VARIABLE Bank_addr : Array4x2BV;
+        VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
+
+        VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        VARIABLE Burst_counter : INTEGER := 0;
+
+        VARIABLE Command : Array_state;
+        VARIABLE Bank_precharge : Array4x2BV;
+        VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
+        VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
+        VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
+
+        VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
+        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
+        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
+
+        -- Timing Check
+        VARIABLE MRD_chk : INTEGER := 0;
+        VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
+        VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
+        VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
+        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
+        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
+        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
+
+        -- Load and Dumb variables
+        FILE     file_load : TEXT open read_mode is fname;   -- Data load
+        FILE     file_dump : TEXT open write_mode is "dumpdata.txt";   -- Data dump
+        VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
+        VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
+        VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
+        VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
+        VARIABLE i, j      : INTEGER;
+        VARIABLE good_load : BOOLEAN;
+        VARIABLE l         : LINE;
+	variable load : std_logic := '1';
+	variable dump : std_logic := '0';
+	variable ch   : character;
+	variable rectype : bit_vector(3 downto 0);
+	variable recaddr : bit_vector(31 downto 0);
+	variable reclen : bit_vector(7 downto 0);
+	variable recdata : bit_vector(0 to 16*8-1);
+
+        -- Initialize empty rows
+        PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
+            VARIABLE i, j : INTEGER := 0;
+        BEGIN
+            IF Bank = "00" THEN
+                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
+                    Bank0 (Row_index) := NEW ram_type;                  -- Open new row for access
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP            -- Filled row with zeros
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank0 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "01" THEN
+                IF Bank1 (Row_index) = NULL THEN
+                    Bank1 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank1 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "10" THEN
+                IF Bank2 (Row_index) = NULL THEN
+                    Bank2 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank2 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            ELSIF Bank = "11" THEN
+                IF Bank3 (Row_index) = NULL THEN
+                    Bank3 (Row_index) := NEW ram_type;
+                    FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
+                        FOR j IN (data_bits) DOWNTO 0 LOOP
+                            Bank3 (Row_index) (i) (j) := '0';
+                        END LOOP;
+                    END LOOP;
+                END IF;
+            END IF;
+        END;
+            
+        -- Burst Counter
+        PROCEDURE Burst_decode IS
+            VARIABLE Col_int : INTEGER := 0;
+            VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
+        BEGIN
+            -- Advance Burst Counter
+            Burst_counter := Burst_counter + 1;
+
+            -- Burst Type
+            IF Mode_reg (3) = '0' THEN
+                Col_int := TO_INTEGER(Col);
+                Col_int := Col_int + 1;
+                TO_BITVECTOR (Col_int, Col_temp);
+            ELSIF Mode_reg (3) = '1' THEN
+                TO_BITVECTOR (Burst_counter, Col_vec);
+                Col_temp (2) :=  Col_vec (2) XOR Col_brst (2);
+                Col_temp (1) :=  Col_vec (1) XOR Col_brst (1);
+                Col_temp (0) :=  Col_vec (0) XOR Col_brst (0);
+            END IF;
+
+            -- Burst Length
+            IF Burst_length_2 = '1' THEN
+                Col (0) := Col_temp (0);
+            ELSIF Burst_length_4 = '1' THEN
+                Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
+            ELSIF Burst_length_8 = '1' THEN
+                Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
+            ELSE
+                Col := Col_temp;
+            END IF;
+
+            -- Burst Read Single Write
+            IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
+                Data_in_enable := '0';
+            END IF;
+
+            -- Data counter
+            IF Burst_length_1 = '1' THEN
+                IF Burst_counter >= 1 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_2 = '1' THEN
+                IF Burst_counter >= 2 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_4 = '1' THEN
+                IF Burst_counter >= 4 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Burst_length_8 = '1' THEN
+                IF Burst_counter >= 8 THEN
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    ELSIF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            END IF;
+        END;
+
+    BEGIN
+        WAIT ON Sys_clk, RAS_clk;
+        IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN 		--'
+            -- Internal Command Pipeline
+            Command(0) := Command(1);
+            Command(1) := Command(2);
+            Command(2) := Command(3);
+            Command(3) := NOP;
+            
+            Col_addr(0) := Col_addr(1);
+            Col_addr(1) := Col_addr(2);
+            Col_addr(2) := Col_addr(3);
+            Col_addr(3) := (OTHERS => '0');
+            
+            Bank_addr(0) := Bank_addr(1);
+            Bank_addr(1) := Bank_addr(2);
+            Bank_addr(2) := Bank_addr(3);
+            Bank_addr(3) := "00";
+
+            Bank_precharge(0) := Bank_precharge(1);
+            Bank_precharge(1) := Bank_precharge(2);
+            Bank_precharge(2) := Bank_precharge(3);
+            Bank_precharge(3) := "00";
+
+            A10_precharge(0) := A10_precharge(1);
+            A10_precharge(1) := A10_precharge(2);
+            A10_precharge(2) := A10_precharge(3);
+            A10_precharge(3) := '0';
+            
+            -- Operation Decode (Optional for showing current command on posedge clock / debug feature)
+            IF Active_enable = '1' THEN
+                Operation <= ACT;
+            ELSIF Aref_enable = '1' THEN
+                Operation <= A_REF;
+            ELSIF Burst_term = '1' THEN
+                Operation <= BST;
+            ELSIF Mode_reg_enable = '1' THEN
+                Operation <= LMR;
+            ELSIF Prech_enable = '1' THEN
+                Operation <= PRECH;
+            ELSIF Read_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= READ;
+                ELSE
+                    Operation <= READ_A;
+                END IF;
+            ELSIF Write_enable = '1' THEN
+                IF Addr(10) = '0' THEN
+                    Operation <= WRITE;
+                ELSE
+                    Operation <= WRITE_A;
+                END IF;
+            ELSE
+                Operation <= NOP;
+            END IF;
+            
+            -- Dqm pipeline for Read
+            Dqm_reg0 := Dqm_reg1;
+            Dqm_reg1 := TO_BITVECTOR(Dqm);
+
+            -- Read or Write with Auto Precharge Counter
+            IF Auto_precharge (0) = '1' THEN
+                Count_precharge (0) := Count_precharge (0) + 1;
+            END IF;
+            IF Auto_precharge (1) = '1' THEN
+                Count_precharge (1) := Count_precharge (1) + 1;
+            END IF;
+            IF Auto_precharge (2) = '1' THEN
+                Count_precharge (2) := Count_precharge (2) + 1;
+            END IF;
+            IF Auto_precharge (3) = '1' THEN
+                Count_precharge (3) := Count_precharge (3) + 1;
+            END IF;
+            
+            -- Auto Precharge Timer for tWR
+            if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
+                if (Count_precharge(0) = 1) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 1) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 1) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 1) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_2 = '1') then
+                if (Count_precharge(0) = 2) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 2) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 2) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 2) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_4 = '1') then
+                if (Count_precharge(0) = 4) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 4) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 4) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 4) then
+                    Count_time(3) := NOW;
+                end if;
+            elsif (Burst_length_8 = '1') then
+                if (Count_precharge(0) = 8) then
+                    Count_time(0) := NOW;
+                end if;
+                if (Count_precharge(1) = 8) then
+                    Count_time(1) := NOW;
+                end if;
+                if (Count_precharge(2) = 8) then
+                    Count_time(2) := NOW;
+                end if;
+                if (Count_precharge(3) = 8) then
+                    Count_time(3) := NOW;
+                end if;
+            end if;
+
+            -- tMRD Counter
+            MRD_chk := MRD_chk + 1;
+
+            -- tWR Counter
+            WR_counter(0) := WR_counter(0) + 1;
+            WR_counter(1) := WR_counter(1) + 1;
+            WR_counter(2) := WR_counter(2) + 1;
+            WR_counter(3) := WR_counter(3) + 1;
+
+
+            -- Auto Refresh
+            IF Aref_enable = '1' THEN
+                -- Auto Refresh to Auto Refresh
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- Precharge to Auto Refresh
+                ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
+                    REPORT "tRP violation during Auto Refresh"
+                    SEVERITY WARNING;
+                -- All banks must be idle before refresh
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All banks must be Precharge before Auto Refresh"
+                        SEVERITY WARNING;
+                END IF;
+                -- Record current tRC time
+                RC_chk := NOW;
+            END IF;
+            
+            -- Load Mode Register
+            IF Mode_reg_enable = '1' THEN
+                Mode_reg <= TO_BITVECTOR (Addr);
+                IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
+                    ASSERT (FALSE)
+                        REPORT "All bank must be Precharge before Load Mode Register"
+                        SEVERITY WARNING;
+                END IF;
+                -- REF to LMR
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- LMR to LMR
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Load Mode Register"
+                    SEVERITY WARNING;
+                -- Record current tMRD time
+                MRD_chk := 0;
+            END IF;
+            
+            -- Active Block (latch Bank and Row Address)
+            IF Active_enable = '1' THEN
+                IF Ba = "00" AND Pc_b0 = '1' THEN
+                    Act_b0 := '1';
+                    Pc_b0 := '0';
+                    B0_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk0 := NOW;
+                    RAS_chk0 := NOW;
+                    -- Precharge to Active Bank 0
+                    ASSERT (NOW - RP_chk0 >= tRP)
+                        REPORT "tRP violation during Activate Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '1' THEN
+                    Act_b1 := '1';
+                    Pc_b1 := '0';
+                    B1_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk1 := NOW;
+                    RAS_chk1 := NOW;
+                    -- Precharge to Active Bank 1
+                    ASSERT (NOW - RP_chk1 >= tRP)
+                        REPORT "tRP violation during Activate Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '1' THEN
+                    Act_b2 := '1';
+                    Pc_b2 := '0';
+                    B2_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk2 := NOW;
+                    RAS_chk2 := NOW;
+                    -- Precharge to Active Bank 2
+                    ASSERT (NOW - RP_chk2 >= tRP)
+                        REPORT "tRP violation during Activate Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '1' THEN
+                    Act_b3 := '1';
+                    Pc_b3 := '0';
+                    B3_row_addr := TO_BITVECTOR (Addr);
+                    RCD_chk3 := NOW;
+                    RAS_chk3 := NOW;
+                    -- Precharge to Active Bank 3
+                    ASSERT (NOW - RP_chk3 >= tRP)
+                        REPORT "tRP violation during Activate Bank 3"
+                        SEVERITY WARNING;
+                ELSIF Ba = "00" AND Pc_b0 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 0 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" AND Pc_b1 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 1 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" AND Pc_b2 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 2 is not Precharged"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" AND Pc_b3 = '0' THEN
+                    ASSERT (FALSE)
+                        REPORT "Bank 3 is not Precharged"
+                        SEVERITY WARNING;
+                END IF;
+                -- Active Bank A to Active Bank B
+                IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
+                    ASSERT (FALSE)
+                        REPORT "tRRD violation during Activate"
+                        SEVERITY WARNING;
+                END IF;
+                -- LMR to ACT
+                ASSERT (MRD_chk >= tMRD)
+                    REPORT "tMRD violation during Activate"
+                    SEVERITY WARNING;
+                -- AutoRefresh to Activate
+                ASSERT (NOW - RC_chk >= tRC)
+                    REPORT "tRC violation during Activate"
+                    SEVERITY WARNING;
+                -- Record variable for checking violation
+                RRD_chk := NOW;
+                Previous_bank := TO_BITVECTOR (Ba);
+            END IF;
+            
+            -- Precharge Block
+            IF Prech_enable = '1' THEN
+                IF Addr(10) = '1' THEN
+                    Pc_b0 := '1'; 
+                    Pc_b1 := '1'; 
+                    Pc_b2 := '1'; 
+                    Pc_b3 := '1';
+                    Act_b0 := '0';
+                    Act_b1 := '0';
+                    Act_b2 := '0';
+                    Act_b3 := '0';
+                    RP_chk0 := NOW;
+                    RP_chk1 := NOW;
+                    RP_chk2 := NOW;
+                    RP_chk3 := NOW;
+                    -- Activate to Precharge all banks
+                    ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
+                        REPORT "tRAS violation during Precharge all banks"
+                        SEVERITY WARNING;
+                    -- tWR violation check for Write
+                    IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
+                        (NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
+                        ASSERT (FALSE)
+                            REPORT "tWR violation during Precharge ALL banks"
+                            SEVERITY WARNING;
+                    END IF;
+                ELSIF Addr(10) = '0' THEN
+                    IF Ba = "00" THEN
+                        Pc_b0 := '1';
+                        Act_b0 := '0';
+                        RP_chk0 := NOW;
+                        -- Activate to Precharge bank 0
+                        ASSERT (NOW - RAS_chk0 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 0"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "01" THEN
+                        Pc_b1 := '1';
+                        Act_b1 := '0';
+                        RP_chk1 := NOW;
+                        -- Activate to Precharge bank 1
+                        ASSERT (NOW - RAS_chk1 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 1"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "10" THEN
+                        Pc_b2 := '1';
+                        Act_b2 := '0';
+                        RP_chk2 := NOW;
+                        -- Activate to Precharge bank 2
+                        ASSERT (NOW - RAS_chk2 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 2"
+                            SEVERITY WARNING;
+                    ELSIF Ba = "11" THEN
+                        Pc_b3 := '1';
+                        Act_b3 := '0';
+                        RP_chk3 := NOW;
+                        -- Activate to Precharge bank 3
+                        ASSERT (NOW - RAS_chk3 >= tRAS)
+                            REPORT "tRAS violation during Precharge bank 3"
+                            SEVERITY WARNING;
+                    END IF;
+                    -- tWR violation check for Write
+                    ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
+                        REPORT "tWR violation during Precharge"
+                        SEVERITY WARNING;
+                END IF;
+                -- Terminate a Write Immediately (if same bank or all banks)
+                IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Precharge Command Pipeline for READ
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := PRECH;
+                    Bank_precharge(2) := TO_BITVECTOR (Ba);
+                    A10_precharge(2) := TO_BIT(Addr(10));
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := PRECH;
+                    Bank_precharge(1) := TO_BITVECTOR (Ba);
+                    A10_precharge(1) := TO_BIT(Addr(10));
+                END IF;
+            END IF;
+            
+            -- Burst Terminate
+            IF Burst_term = '1' THEN
+                -- Terminate a Write immediately
+                IF Data_in_enable = '1' THEN
+                    Data_in_enable := '0';
+                END IF;
+                -- Terminate a Read depend on CAS Latency
+                IF CAS_latency_3 = '1' THEN
+                    Command(2) := BST;
+                ELSIF CAS_latency_2 = '1' THEN
+                    Command(1) := BST;
+                END IF;
+            END IF;
+            
+            -- Read, Write, Column Latch
+            IF Read_enable = '1' OR Write_enable = '1' THEN
+                -- Check to see if bank is open (ACT) for Read or Write
+                IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
+                    ASSERT (FALSE)
+                        REPORT "Cannot Read or Write - Bank is not Activated"
+                        SEVERITY WARNING;
+                END IF;
+                -- Activate to Read or Write
+                IF Ba = "00" THEN
+                    ASSERT (NOW - RCD_chk0 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 0"
+                        SEVERITY WARNING;
+                ELSIF Ba = "01" THEN
+                    ASSERT (NOW - RCD_chk1 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 1"
+                        SEVERITY WARNING;
+                ELSIF Ba = "10" THEN
+                    ASSERT (NOW - RCD_chk2 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 2"
+                        SEVERITY WARNING;
+                ELSIF Ba = "11" THEN
+                    ASSERT (NOW - RCD_chk3 >= tRCD)
+                        REPORT "tRCD violation during Read or Write to Bank 3"
+                        SEVERITY WARNING;
+                END IF;
+
+                -- Read Command
+                IF Read_enable = '1' THEN
+                    -- CAS Latency Pipeline
+                    IF Cas_latency_3 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(2) := READ_A;
+                        ELSE
+                            Command(2) := READ;
+                        END IF;
+                        Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (2) := TO_BITVECTOR (Ba);
+                    ELSIF Cas_latency_2 = '1' THEN
+                        IF Addr(10) = '1' THEN
+                            Command(1) := READ_A;
+                        ELSE
+                            Command(1) := READ;
+                        END IF;
+                        Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                        Bank_addr (1) := TO_BITVECTOR (Ba);
+                    END IF;
+
+                    -- Read intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                -- Write Command
+                ELSIF Write_enable = '1' THEN
+                    IF Addr(10) = '1' THEN
+                        Command(0) := WRITE_A;
+                    ELSE
+                        Command(0) := WRITE;
+                    END IF;
+                    Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
+                    Bank_addr (0) := TO_BITVECTOR (Ba);
+
+                    -- Write intterupt a Write (terminate Write immediately)
+                    IF Data_in_enable = '1' THEN
+                        Data_in_enable := '0';
+                    END IF;
+
+                    -- Write interrupt a Read (terminate Read immediately)
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+
+                -- Interrupt a Write with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Interrupt a Read with Auto Precharge
+                IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
+                    RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
+                END IF;
+
+                -- Read or Write with Auto Precharge
+                IF Addr(10) = '1' THEN
+                    Auto_precharge (TO_INTEGER(Ba)) := '1';
+                    Count_precharge (TO_INTEGER(Ba)) := 0;
+                    RW_Interrupt_Bank := TO_BitVector(Ba);
+                    IF Read_enable = '1' THEN
+                        Read_precharge (TO_INTEGER(Ba)) := '1';
+                    ELSIF Write_enable = '1' THEN
+                        Write_precharge (TO_INTEGER(Ba)) := '1';
+                    END IF;
+                END IF;
+            END IF;
+            
+            -- Read with AutoPrecharge Calculation
+            --      The device start internal precharge when:
+            --          1.  BL/2 cycles after command
+            --      and 2.  Meet tRAS requirement
+            --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+            IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
+                IF (((NOW - RAS_chk0 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(0) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(0) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(0) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
+                     (RW_interrupt_read(0) = '1')) THEN
+                    Pc_b0 := '1';
+                    Act_b0 := '0';
+                    RP_chk0 := NOW;
+                    Auto_precharge(0) := '0';
+                    Read_precharge(0) := '0';
+                    RW_interrupt_read(0) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
+                IF (((NOW - RAS_chk1 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(1) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(1) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(1) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
+                     (RW_interrupt_read(1) = '1')) THEN
+                    Pc_b1 := '1';
+                    Act_b1 := '0';
+                    RP_chk1 := NOW;
+                    Auto_precharge(1) := '0';
+                    Read_precharge(1) := '0';
+                    RW_interrupt_read(1) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
+                IF (((NOW - RAS_chk2 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(2) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(2) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(2) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
+                     (RW_interrupt_read(2) = '1')) THEN
+                    Pc_b2 := '1';
+                    Act_b2 := '0';
+                    RP_chk2 := NOW;
+                    Auto_precharge(2) := '0';
+                    Read_precharge(2) := '0';
+                    RW_interrupt_read(2) := '0';
+                END IF;
+            END IF;
+            IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
+                IF (((NOW - RAS_chk3 >= tRAS) AND
+                    ((Burst_length_1 = '1' AND Count_precharge(3) >= 1)  OR
+                     (Burst_length_2 = '1' AND Count_precharge(3) >= 2)  OR
+                     (Burst_length_4 = '1' AND Count_precharge(3) >= 4)  OR
+                     (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
+                     (RW_interrupt_read(3) = '1')) THEN
+                    Pc_b3 := '1';
+                    Act_b3 := '0';
+                    RP_chk3 := NOW;
+                    Auto_precharge(3) := '0';
+                    Read_precharge(3) := '0';
+                    RW_interrupt_read(3) := '0';
+                END IF;
+            END IF;
+            
+            -- Internal Precharge or Bst
+            IF Command(0) = PRECH THEN                          -- PRECH terminate a read if same bank or all banks
+                IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
+                    IF Data_out_enable = '1' THEN
+                        Data_out_enable := '0';
+                    END IF;
+                END IF;
+            ELSIF Command(0) = BST THEN                         -- BST terminate a read regardless of bank
+                IF Data_out_enable = '1' THEN
+                    Data_out_enable := '0';
+                END IF;
+            END IF;
+
+            IF Data_out_enable = '0' THEN
+                Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
+            END IF;
+
+            -- Detect Read or Write Command
+            IF Command(0) = READ OR Command(0) = READ_A THEN
+                Bank := Bank_addr (0);
+                Col := Col_addr (0);
+                Col_brst := Col_addr (0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '0';
+                Data_out_enable := '1';
+            ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
+                Bank := Bank_addr(0);
+                Col := Col_addr(0);
+                Col_brst := Col_addr(0);
+                IF Bank_addr (0) = "00" THEN
+                    Row := B0_row_addr;
+                ELSIF Bank_addr (0) = "01" THEN
+                    Row := B1_row_addr;
+                ELSIF Bank_addr (0) = "10" THEN
+                    Row := B2_row_addr;
+                ELSE
+                    Row := B3_row_addr;
+                END IF;
+                Burst_counter := 0;
+                Data_in_enable := '1';
+                Data_out_enable := '0';
+            END IF;
+
+            -- DQ (Driver / Receiver)
+            Row_index := TO_INTEGER (Row);
+            Col_index := TO_INTEGER (Col);
+            IF Data_in_enable = '1' THEN
+                IF Dqm /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm = "01" THEN
+                            Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
+                        ELSIF Dqm = "10" THEN
+                            Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
+                        ELSE
+                            Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
+                        END IF;
+                        Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
+                    END IF;
+                    WR_chkp(TO_INTEGER(Bank)) := NOW;
+                    WR_counter(TO_INTEGER(Bank)) := 0;
+                END IF;
+                Burst_decode;
+            ELSIF Data_out_enable = '1' THEN
+                IF Dqm_reg0 /= "11" THEN
+                    Init_mem (Bank, Row_index);
+                    IF Bank = "00" THEN
+                        Dq_temp := Bank0 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "01" THEN
+                        Dq_temp := Bank1 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "10" THEN
+                        Dq_temp := Bank2 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    ELSIF Bank = "11" THEN
+                        Dq_temp := Bank3 (Row_index) (Col_index);
+                        IF Dqm_reg0 = "00" THEN
+                            Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
+                        ELSIF Dqm_reg0 = "01" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
+                            Dq (7 DOWNTO 0)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                        ELSIF Dqm_reg0 = "10" THEN
+                            Dq (15 DOWNTO 8)  <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
+                            Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
+                        END IF;
+                    END IF;
+                ELSE
+                      Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
+                END IF;
+                Burst_decode;
+            END IF;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN 		--'
+            Operation <= LOAD_FILE;
+	    load := '0';
+--            ASSERT (FALSE) REPORT "Reading memory array from file.  This operation may take several minutes.  Please wait..."
+--                SEVERITY NOTE;
+            WHILE NOT endfile(file_load) LOOP
+                readline(file_load, l);
+                read(l, ch);
+                if (ch /= 'S') or (ch /= 's') then
+                  hread(l, rectype);
+                  hread(l, reclen);
+		  recaddr := (others => '0');
+		  case rectype is 
+		  when "0001" =>
+                    hread(l, recaddr(15 downto 0));
+		  when "0010" =>
+                    hread(l, recaddr(23 downto 0));
+		  when "0011" =>
+                    hread(l, recaddr);
+		    recaddr(31 downto 24) := (others => '0');
+		  when others => next;
+		  end case;
+                  hread(l, recdata);
+
+	 	  if index < 32 then
+		    Bank_Load := recaddr(25 downto 24);
+		    Rows_Load := recaddr(23 downto 11);
+		    Cols_Load := recaddr(10 downto 2);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 3 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 3 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 3 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 3 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
+		      end loop;
+                    END IF;
+		  elsif(index < 1024) then
+		    Bank_Load := recaddr(26 downto 25);
+		    Rows_Load := recaddr(24 downto 12);
+		    Cols_Load := recaddr(11 downto 3);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 1 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 1 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 1 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 1 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
+		      end loop;
+                    END IF;
+                  else
+		    Bank_Load := recaddr(22 downto 21);
+		    Rows_Load := '0' & recaddr(20 downto 9);
+		    Cols_Load := '0' & recaddr(8 downto 1);
+                    Init_Mem (Bank_Load, To_Integer(Rows_Load));
+                    IF Bank_Load = "00" THEN
+		      for i in 0 to 7 loop
+                        Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "01" THEN
+		      for i in 0 to 7 loop
+                        Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "10" THEN
+		      for i in 0 to 7 loop
+                        Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    ELSIF Bank_Load = "11" THEN
+		      for i in 0 to 7 loop
+                        Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
+		      end loop;
+                    END IF;
+                  END IF;
+                END IF;
+            END LOOP;
+        ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN 		--'
+            Operation <= DUMP_FILE;
+            ASSERT (FALSE) REPORT "Writing memory array to file.  This operation may take several minutes.  Please wait..."
+                SEVERITY NOTE;
+            WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# BA ROWS          COLS      DQ")); 		--'
+            WRITELINE (file_dump, l);
+            WRITE (l, string'("# -- ------------- --------- ----------------")); 		--'
+            WRITELINE (file_dump, l);
+            -- Dumping Bank 0
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank0 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("00"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 1
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank1 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("01"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 2
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank2 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("10"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+            -- Dumping Bank 3
+            FOR i IN 0 TO 2**addr_bits -1 LOOP
+                -- Check if ROW is NULL
+                IF Bank3 (i) /= NULL THEN
+                    For j IN 0 TO 2**col_bits - 1 LOOP
+                        -- Check if COL is NULL
+                        NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
+                        WRITE (l, string'("11"), right, 4); 		--'
+                        WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
+                        WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
+                        WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
+                        WRITELINE (file_dump, l);
+                    END LOOP;
+                END IF;
+            END LOOP;
+        END IF;
+
+        -- Write with AutoPrecharge Calculation
+        --      The device start internal precharge when:
+        --          1.  tWR cycles after command
+        --      and 2.  Meet tRAS requirement
+        --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)
+        IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
+            IF (((NOW - RAS_chk0 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
+                Auto_precharge(0) := '0';
+                Write_precharge(0) := '0';
+                RW_interrupt_write(0) := '0';
+                Pc_b0 := '1';
+                Act_b0 := '0';
+                RP_chk0 := NOW;
+                ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
+            IF (((NOW - RAS_chk1 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
+                 (RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
+                Auto_precharge(1) := '0';
+                Write_precharge(1) := '0';
+                RW_interrupt_write(1) := '0';
+                Pc_b1 := '1';
+                Act_b1 := '0';
+                RP_chk1 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
+            IF (((NOW - RAS_chk2 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
+                 (RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
+                Auto_precharge(2) := '0';
+                Write_precharge(2) := '0';
+                RW_interrupt_write(2) := '0';
+                Pc_b2 := '1';
+                Act_b2 := '0';
+                RP_chk2 := NOW;
+            END IF;
+        END IF;
+        IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
+            IF (((NOW - RAS_chk3 >= tRAS) AND
+               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_2 = '1'                             AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_4 = '1'                             AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa)  OR
+                 (Burst_length_8 = '1'                             AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
+                 (RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
+                Auto_precharge(3) := '0';
+                Write_precharge(3) := '0';
+                RW_interrupt_write(3) := '0';
+                Pc_b3 := '1';
+                Act_b3 := '0';
+                RP_chk3 := NOW;
+            END IF;
+        END IF;
+
+        -- Checking internal wires (Optional for debug purpose)
+        Pre_chk (0) <= Pc_b0;
+        Pre_chk (1) <= Pc_b1;
+        Pre_chk (2) <= Pc_b2;
+        Pre_chk (3) <= Pc_b3;
+        Act_chk (0) <= Act_b0;
+        Act_chk (1) <= Act_b1;
+        Act_chk (2) <= Act_b2;
+        Act_chk (3) <= Act_b3;
+        Dq_in_chk   <= Data_in_enable;
+        Dq_out_chk  <= Data_out_enable;
+        Bank_chk    <= Bank;
+        Row_chk     <= Row;
+        Col_chk     <= Col;
+    END PROCESS;    
+                    
+                    
+    -- Clock timing checks
+--    Clock_check : PROCESS
+--        VARIABLE Clk_low, Clk_high : TIME := 0 ns;
+--    BEGIN       
+--        WAIT ON Clk;
+--        IF (Clk = '1' AND NOW >= 10 ns) THEN
+--            ASSERT (NOW - Clk_low >= tCL)
+--                REPORT "tCL violation"
+--                SEVERITY WARNING;
+--            ASSERT (NOW - Clk_high >= tCK)
+--                REPORT "tCK violation"
+--                SEVERITY WARNING;
+--            Clk_high := NOW;
+--        ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
+--            ASSERT (NOW - Clk_high >= tCH)
+--                REPORT "tCH violation"
+--                SEVERITY WARNING;
+--            Clk_low := NOW;
+--        END IF;
+--    END PROCESS;    
+                    
+    -- Setup timing checks
+    Setup_check : PROCESS
+    BEGIN       
+	wait;
+        WAIT ON Clk;
+        IF Clk = '1' THEN
+            ASSERT(Cke'LAST_EVENT >= tCKS) 		--'
+                REPORT "CKE Setup time violation -- tCKS"
+                SEVERITY WARNING;
+            ASSERT(Cs_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "CAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "RAS# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT >= tCMS) 		--'
+                REPORT "WE# Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT >= tCMS) 		--'
+                REPORT "Dqm Setup time violation -- tCMS"
+                SEVERITY WARNING;
+            ASSERT(Addr'LAST_EVENT >= tAS) 		--'
+                REPORT "ADDR Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT >= tAS) 		--'
+                REPORT "BA Setup time violation -- tAS"
+                SEVERITY WARNING;
+            ASSERT(Dq'LAST_EVENT >= tDS) 		--'
+                REPORT "Dq Setup time violation -- tDS"
+                SEVERITY WARNING;
+        END IF;   
+    END PROCESS;
+
+    -- Hold timing checks
+    Hold_check : PROCESS
+    BEGIN
+	wait;
+        WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
+        IF Clk'DELAYED (tCKH) = '1' THEN 		--'
+            ASSERT(Cke'LAST_EVENT > tCKH) 		--'
+                REPORT "CKE Hold time violation -- tCKH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tCMH) = '1' THEN 		--'
+            ASSERT(Cs_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Cas_n'LAST_EVENT > tCMH) 		--'
+                REPORT "CAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Ras_n'LAST_EVENT > tCMH) 		--'
+                REPORT "RAS# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(We_n'LAST_EVENT > tCMH) 		--'
+                REPORT "WE# Hold time violation -- tCMH"
+                SEVERITY WARNING;
+            ASSERT(Dqm'LAST_EVENT > tCMH) 		--'
+                REPORT "Dqm Hold time violation -- tCMH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tAH) = '1' THEN 		--'
+            ASSERT(Addr'LAST_EVENT > tAH) 		--'
+                REPORT "ADDR Hold time violation -- tAH"
+                SEVERITY WARNING;
+            ASSERT(Ba'LAST_EVENT > tAH) 		--'
+                REPORT "BA Hold time violation -- tAH"
+                SEVERITY WARNING;
+        END IF;
+        IF Clk'DELAYED (tDH) = '1' THEN 		--'
+            ASSERT(Dq'LAST_EVENT > tDH) 		--'
+                REPORT "Dq Hold time violation -- tDH"
+                SEVERITY WARNING;
+        END IF;
+    END PROCESS;
+
+END behave;
+
+-- pragma translate_on
+
diff --git a/designs/Timegen2/opencores.xml b/designs/Timegen2/opencores.xml
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/opencores.xml
@@ -0,0 +1,69 @@
+<?xml version='1.0' encoding='utf-8'?>
+<soc name="Leon">
+ <peripheral vid="8" name="SpaceWire Light" pid="305">
+   <register name="Control register" addOffset="0">
+     <bitField size="1" offset="0" name="Reset" mode="3" desc="Write '1' to reset SPWAMBA core (auto-clear)."/>
+     <bitField size="1" offset="1" name="Reset DMA" mode="3" desc="Write '1' to reset DMA engines (auto-clear)."/>
+     <bitField name="Link Start" offset="2" size="1" mode="3" desc="Link start signal. '1' = actively try to start a SpaceWire link."/>
+     <bitField name="Link Auto Start" offset="3" size="1" mode="3" desc="Link autostart signal. '1' = start link after receiving NULL from other side."/>
+     <bitField name="Link Disable" offset="4" size="1" mode="3" desc="Link disable signal. '1' = shut down current link and do not establish new link."/>
+     <bitField name="Time Code EN" offset="5" size="1" mode="3" desc="Allow time-code transmission through tick_in signal."/>
+     <bitField name="Restart RX DMA" offset="6" size="1" mode="3" desc="Write '1' to (re-)start RX DMA (auto-clear)."/>
+     <bitField name="Restart TX DMA" offset="7" size="1" mode="3" desc="Write '1' to (re-)start TX DMA (auto-clear)."/>
+     <bitField name="Cancel TX DMA" offset="8" size="1" mode="3" desc="Write '1' to cancel running TX DMA and discard data from TX FIFO (auto-clear)."/>
+     <bitField name="Link Up/Down IE" offset="9" size="1" mode="3" desc="Enable interrupt on link up/down."/>
+     <bitField name="Time Code IE" offset="10" size="1" mode="3" desc="Enable interrupt on time code received."/>
+     <bitField name="RXDESCIE" offset="11" size="1" mode="3" desc="Enable interrupt on completed RX descriptor with IE='1'."/>
+     <bitField name="TXDESCIE" offset="12" size="1" mode="3" desc="Enable interrupt on completed TX descriptor with IE='1'."/>
+     <bitField name="RXIE" offset="13" size="1" mode="3" desc="Enable interrupt on RX packet received."/>
+     <bitField name="DescSz" offset="24" size="4" mode="1" desc="Value of desctablesize generic (read-only)."/>
+   </register>
+   <register name="Status register" addOffset="4">
+     <bitField size="2" offset="0" name="LSTAT" mode="1" desc="Link status: 0=off, 1=started, 2=connecting, 3=run (read-only)."/>
+     <bitField size="1" offset="2" name="DISCERR" mode="3" desc="Got disconnect error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="3" name="PARERR" mode="3" desc="Got parity error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="4" name="ESCERR" mode="3" desc="Got escape error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="5" name="CREDERR" mode="3" desc="Got credit error (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="6" name="RXDMA" mode="1" desc="RX DMA running (read-only)."/>
+     <bitField size="1" offset="7" name="RXDMA" mode="1" desc="TX DMA running (read-only)."/>
+     <bitField size="1" offset="8" name="AHBERR" mode="1" desc="AHB error occurred (sticky, reset DMA engine to clear)."/>
+     <bitField size="1" offset="9" name="UNUSED" mode="3" desc="unused"/>
+     <bitField size="1" offset="10" name="TIMECODE" mode="3" desc="Received time-code (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="11" name="RXDESCCOMP" mode="3" desc="Completed RX descriptor with IE='1' (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="12" name="TXDESCCOMP" mode="3" desc="Completed TX descriptor with IE='1' (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="13" name="RECPACKT" mode="3" desc="Received packet (sticky, write '1' to clear)."/>
+     <bitField size="1" offset="14" name="RXE" mode="1" desc="RX buffer is empty and last packet has been completely transfered to RX DMA (read-only)."/>
+   </register>
+   <register name="Transmission clock scaler" addOffset="8">
+     <bitField size="8" offset="0" name="N" mode="3" desc="Clock division factor minus 1. The actual TX bit rate is determined by (txclk frequency) / (scaler + 1).
+During the handshake phase, this register is ignored and the TX bit rate is forced to 10 Mbit. After reset, this
+register defaults to the scaler value needed for 10 Mbit."/>
+   </register>
+   <register name="Time-code register" addOffset="12">
+     <bitField size="6" offset="0" name="Address" mode="1" desc="Last received time-code value (read-only)."/>
+     <bitField size="2" offset="6" name="Address" mode="1" desc="Control bits received with last time-code (read-only)."/>
+     <bitField size="6" offset="12" name="Address" mode="3" desc="Time-code value to send on next tick_in (auto-increment)."/>
+     <bitField size="2" offset="14" name="Address" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="1" offset="15" name="Address" mode="3" desc="Write '1' to send a time-code immediately (auto-clear)."/>
+   </register>
+   <register name="Descriptor pointer for RX DMA" addOffset="16">
+     <bitField size="3" offset="0" name="DATA" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="10" offset="3" name="DATA" mode="3" desc="Descriptor index (auto-increment)."/>
+     <bitField size="19" offset="13" name="DATA" mode="3" desc="Fixed address bits of descriptor table."/>
+   </register>
+   <register name="Descriptor pointer for TX DMA" addOffset="20">
+     <bitField size="3" offset="0" name="DATA" mode="3" desc="Reserved, write as zero."/>
+     <bitField size="10" offset="3" name="DATA" mode="3" desc="Descriptor index (auto-increment)."/>
+     <bitField size="19" offset="13" name="DATA" mode="3" desc="Fixed address bits of descriptor table."/>
+   </register>
+ </peripheral>
+</soc>
+
+
+
+
+
+
+
+
+
diff --git a/designs/Timegen2/sdctrl16.vhd b/designs/Timegen2/sdctrl16.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/sdctrl16.vhd
@@ -0,0 +1,1053 @@
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+-----------------------------------------------------------------------------
+-- Entity:  sdctrl16
+-- File:    sdctrl16.vhd
+-- Author:  Jiri Gaisler - Gaisler Research
+-- Modified by: Daniel Bengtsson & Richard Fång
+-- Description: 16- and 32-bit SDRAM memory controller.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+library gaisler;
+use grlib.devices.all;
+use gaisler.memctrl.all;
+
+entity sdctrl16 is
+  generic (
+    hindex  : integer := 0;
+    haddr   : integer := 0;
+    hmask   : integer := 16#f00#;
+    ioaddr  : integer := 16#000#;
+    iomask  : integer := 16#fff#;
+    wprot   : integer := 0;
+    invclk  : integer := 0;
+    fast    : integer := 0;
+    pwron   : integer := 0;
+    sdbits  : integer := 16;
+    oepol   : integer := 0;
+    pageburst : integer := 0;
+    mobile  : integer := 0
+  );
+  port (
+    rst     : in  std_ulogic;
+    clk     : in  std_ulogic;
+    ahbsi   : in  ahb_slv_in_type;
+    ahbso   : out ahb_slv_out_type;
+    sdi     : in  sdctrl_in_type;
+    sdo     : out sdctrl_out_type
+  );
+end;
+
+architecture rtl of sdctrl16 is
+
+constant WPROTEN   : boolean := wprot = 1;
+constant SDINVCLK  : boolean := invclk = 1;
+constant BUS16    : boolean := (sdbits = 16);
+constant BUS32    : boolean := (sdbits = 32);
+constant BUS64    : boolean := (sdbits = 64);
+
+constant REVISION  : integer := 1;
+
+constant PM_PD    : std_logic_vector(2 downto 0) := "001";
+constant PM_SR    : std_logic_vector(2 downto 0) := "010";
+constant PM_DPD   : std_logic_vector(2 downto 0) := "101";
+
+constant std_rammask: Std_Logic_Vector(31 downto 20) :=
+                        Conv_Std_Logic_Vector(hmask, 12);
+
+constant hconfig : ahb_config_type := (
+  0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SDCTRL, 0, REVISION, 0),
+  4 => ahb_membar(haddr, '1', '1', hmask),
+  5 => ahb_iobar(ioaddr, iomask),
+  others => zero32);
+
+type mcycletype is (midle, active, leadout);
+type sdcycletype is (act1, act2, act3, act3_16, rd1, rd2, rd3, rd4, rd4_16, rd5, rd6, rd7, rd8,
+                     wr1, wr1_16, wr2, wr3, wr4, wr5, sidle,
+                     sref, pd, dpd);
+type icycletype is (iidle, pre, ref, lmode, emode, finish);
+
+-- sdram configuration register
+
+type sdram_cfg_type is record
+  command         : std_logic_vector(2 downto 0);
+  csize           : std_logic_vector(1 downto 0);
+  bsize           : std_logic_vector(2 downto 0);
+  casdel          : std_ulogic;  -- CAS to data delay: 2/3 clock cycles
+  trfc            : std_logic_vector(2 downto 0);
+  trp             : std_ulogic;  -- precharge to activate: 2/3 clock cycles
+  refresh         : std_logic_vector(14 downto 0);
+  renable         : std_ulogic;
+  pageburst       : std_ulogic;
+  mobileen        : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
+  ds              : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
+  tcsr            : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
+  pasr            : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
+  pmode           : std_logic_vector(2 downto 0); -- Power-Saving mode
+  txsr            : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
+  cke             : std_ulogic; -- Clock enable
+end record;
+
+-- local registers
+
+type reg_type is record
+  hready        : std_ulogic;
+  hsel          : std_ulogic;
+  bdrive        : std_ulogic;
+  nbdrive       : std_ulogic;
+  burst         : std_ulogic;
+  wprothit      : std_ulogic;
+  hio           : std_ulogic;
+  startsd       : std_ulogic;
+  lhw           : std_ulogic; --Lower halfword
+
+  mstate        : mcycletype;
+  sdstate       : sdcycletype;
+  cmstate       : mcycletype;
+  istate        : icycletype;
+  icnt          : std_logic_vector(2 downto 0);
+
+  haddr         : std_logic_vector(31 downto 0);
+  hrdata        : std_logic_vector((sdbits-1)+((16/sdbits)*16) downto 0);
+  hwdata        : std_logic_vector(31 downto 0);
+  hwrite        : std_ulogic;
+  htrans        : std_logic_vector(1 downto 0);
+  hresp         : std_logic_vector(1 downto 0);
+  size          : std_logic_vector(1 downto 0);
+
+  cfg           : sdram_cfg_type;
+  trfc          : std_logic_vector(3 downto 0);
+  refresh       : std_logic_vector(14 downto 0);
+  sdcsn         : std_logic_vector(1  downto 0);
+  sdwen         : std_ulogic;
+  rasn          : std_ulogic;
+  casn          : std_ulogic;
+  dqm           : std_logic_vector(7 downto 0);
+  address       : std_logic_vector(16 downto 2);  -- memory address
+  bsel          : std_ulogic;
+
+  idlecnt       : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
+  sref_tmpcom   : std_logic_vector(2 downto 0); -- Save SD command when exit sref
+end record;
+
+signal r, ri : reg_type;
+signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
+attribute syn_preserve : boolean;
+attribute syn_preserve of rbdrive : signal is true;
+
+begin
+
+  ctrl : process(rst, ahbsi, r, sdi, rbdrive)
+  variable v       : reg_type;                      -- local variables for registers
+  variable startsd : std_ulogic;
+  variable dataout : std_logic_vector(31 downto 0); -- data from memory
+  variable regsd   : std_logic_vector(31 downto 0); -- data from registers
+  variable dqm     : std_logic_vector(7 downto 0);
+  variable raddr   : std_logic_vector(12 downto 0);
+  variable adec    : std_ulogic;
+  variable rams    : std_logic_vector(1 downto 0);
+  variable ba      : std_logic_vector(1 downto 0);
+  variable haddr   : std_logic_vector(31 downto 0);
+  variable dout    : std_logic_vector(31 downto 0);
+  variable hsize   : std_logic_vector(1 downto 0);
+  variable hwrite  : std_ulogic;
+  variable htrans  : std_logic_vector(1 downto 0);
+  variable hready  : std_ulogic;
+  variable vbdrive : std_logic_vector(31 downto 0);
+  variable bdrive  : std_ulogic;
+  variable lline    : std_logic_vector(2 downto 0);
+  variable lineburst : boolean;
+  variable haddr_tmp : std_logic_vector(31 downto 0);
+  variable arefresh : std_logic;
+  variable hwdata  : std_logic_vector(31 downto 0);
+
+  begin
+
+-- Variable default settings to avoid latches
+
+    v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive; arefresh := '0';
+    if BUS16 then
+      if (r.lhw = '1') then --muxes read data to correct part of the register.
+        v.hrdata(sdbits-1 downto 0) := sdi.data(sdbits-1 downto 0);
+      else
+        v.hrdata((sdbits*2)-1 downto sdbits) := sdi.data(sdbits-1 downto 0);
+      end if;
+    else
+      v.hrdata(sdbits-1 downto sdbits-32) := sdi.data(sdbits-1 downto sdbits-32);
+      v.hrdata(31 downto 0) := sdi.data(31 downto 0);
+    end if;
+    hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); v.hwdata := hwdata;
+    lline := not r.cfg.casdel &  r.cfg.casdel &  r.cfg.casdel;
+    if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
+      lineburst := true;
+    else lineburst := false; end if;
+
+
+    if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
+      v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
+      v.htrans := ahbsi.htrans;
+      if ahbsi.htrans(1) = '1' then
+        v.hio := ahbsi.hmbsel(1);
+        v.hsel := '1'; v.hready := v.hio;
+      end if;
+      v.haddr := ahbsi.haddr;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        v.haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+
+    if (r.hsel = '1') and (ahbsi.hready = '0') then
+      haddr := r.haddr;  hsize := r.size;
+      htrans := r.htrans; hwrite := r.hwrite;
+    else
+      haddr := ahbsi.haddr;  hsize := ahbsi.hsize(1 downto 0);
+      htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
+      -- addr must be masked since address range can be smaller than
+      -- total banksize. this can result in wrong chip select being
+      -- asserted
+      for i in 31 downto 20 loop
+        haddr(i) := ahbsi.haddr(i) and not std_rammask(i);
+      end loop;
+    end if;
+    if fast = 1 then haddr := r.haddr; end if;
+
+    if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
+
+-- main state
+    if BUS16 then
+      case r.size is
+      when "00" => --bytesize
+        case r.haddr(0) is
+        when '0' => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when others => dqm := "11111100"; --halfword, word
+      end case;
+    else
+      case r.size is
+      when "00" =>
+        case r.haddr(1 downto 0) is
+        when "00" => dqm := "11110111";
+        when "01" => dqm := "11111011";
+        when "10" => dqm := "11111101";
+        when others => dqm := "11111110";
+        end case;
+      when "01" =>
+        if r.haddr(1) = '0' then dqm := "11110011"; else  dqm := "11111100"; end if;
+      when others => dqm := "11110000";
+      end case;
+    end if;
+--
+--      case r.size is
+--      when "00" =>
+--        case r.haddr(1 downto 0) is
+--        when "00" => dqm := "11111101"; lhw := '0'; --lhv := r.haddr(1)
+--        when "01" => dqm := "11111110"; lhw := '0';
+--        when "10" => dqm := "11111101"; lhw := '1';
+--        when others => dqm := "11111110"; lhw := '1';
+--        end case;
+--      when "01" =>
+--        dqm := "11111100";
+--        if r.haddr(1) = '0' then
+--          lhw := '0';
+--        else
+--          lhw := '1';
+--	end if;
+--    when others => dqm := "11111100"; --remember when word: lhw first 0 then 1
+--      end case;
+--
+    if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if;
+
+-- main FSM
+
+    case r.mstate is
+    when midle =>
+      if ((v.hsel and htrans(1) and not v.hio) = '1') then
+        if (r.sdstate = sidle) and (r.cfg.command = "000")
+           and (r.cmstate = midle) and (v.hio = '0')
+        then
+          if fast = 0 then startsd := '1';  else v.startsd := '1'; end if;
+          v.mstate := active;
+        elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
+           and (r.cfg.command = "000") and (r.cmstate = midle) and (v.hio = '0')
+        then
+          v.startsd := '1';
+          if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
+            v.hresp := HRESP_ERROR;
+          else
+            v.mstate := active;
+          end if;
+        end if;
+      end if;
+    when others => null;
+    end case;
+
+    startsd := startsd or r.startsd;
+
+-- generate row and column address size
+
+    if BUS16 then
+      case r.cfg.csize is
+      when "00" => raddr := haddr(21 downto 9);-- case to check for bursting over row limit, since 1 row is 512 byte.
+      when "01" => raddr := haddr(22 downto 10);
+      when "10" => raddr := haddr(23 downto 11);
+      when others =>
+        if r.cfg.bsize = "110" then raddr := haddr(25 downto 13); --tänk
+        else raddr := haddr(24 downto 12); end if;
+      end case;
+    else
+      case r.cfg.csize is
+      when "00" => raddr := haddr(22 downto 10);
+      when "01" => raddr := haddr(23 downto 11);
+      when "10" => raddr := haddr(24 downto 12);
+      when others =>
+        if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
+        else raddr := haddr(25 downto 13); end if;
+      end case;
+    end if;
+
+-- generate bank address
+--    if BUS16 then --011
+--      ba := genmux(r.cfg.bsize, haddr(26 downto 19)) &
+--            genmux(r.cfg.bsize, haddr(25 downto 18));
+--    else
+      ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
+            genmux(r.cfg.bsize, haddr(27 downto 20));
+ --   end if;
+
+-- generate chip select
+
+    if BUS64 then
+      adec := genmux(r.cfg.bsize, haddr(30 downto 23));
+      v.bsel := genmux(r.cfg.bsize, r.haddr(29 downto 22));
+    else
+      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+    end if;
+--    elsif BUS32 then
+--      adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
+--    else
+--      adec := genmux(r.cfg.bsize, haddr(27 downto 20)); v.bsel := '0';
+--    end if;
+
+    rams := adec & not adec;
+
+-- sdram access FSM
+
+    if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
+
+    if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
+
+    case r.sdstate is
+
+    when sidle =>
+      if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
+      --  if BUS16 then
+      --    v.address(16 downto 2) := '0' & ba & raddr(11 downto 0); --since 1 bit lower row => tot adress field 14 bits
+      --  else
+          v.address(16 downto 2) := ba & raddr; -- ba(16-15) & raddr(14-2) (2+13= 15 bits)
+      --  end if;
+        v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
+        v.startsd := '0';
+      elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
+            and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
+        case r.cfg.pmode is
+        when PM_SR =>
+          v.cfg.cke := '0'; v.sdstate := sref;
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
+        when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
+        when PM_DPD =>
+          v.cfg.cke := '0'; v.sdstate := dpd;
+          v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
+        when others =>
+        end case;
+      end if;
+
+    when act1 =>
+      v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+      if r.cfg.casdel = '1' then v.sdstate := act2; else
+        v.sdstate := act3;
+        if not BUS16 then -- needs if, otherwise it might clock in incorrect write data to state act3_16
+          v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+        end if;
+      end if;
+      if WPROTEN then
+        v.wprothit := sdi.wprot;
+        if sdi.wprot = '1' then v.hresp := HRESP_ERROR; end if;
+      end if;
+
+    when act2 =>
+      v.sdstate := act3;
+      if not BUS16 then
+        v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
+      end if;
+      if WPROTEN and (r.wprothit = '1') then
+        v.hresp := HRESP_ERROR; v.hready := '0';
+      end if;
+
+    when act3 =>
+      v.casn := '0';
+      if BUS16 then --HW adress needed to memory
+        v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+--        v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1); --only allowed to use tot adressbits - ba bits
+	v.lhw := r.haddr(1); -- 14-2 = 12 colummn bits => 13 downto 2
+      else
+        v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      end if;
+      v.dqm := dqm; v.burst := r.hready; -- ??
+
+      if r.hwrite = '1' then
+
+        if BUS16 then --16 bit
+          if r.size(1) = '1' then --word
+            v.hready := ahbsi.htrans(0) and ahbsi.htrans(1); --delayed this check 1 state to keep write data correct in act3_16
+            v.burst := ahbsi.htrans(0) and ahbsi.htrans(1);
+            v.sdstate := act3_16; -- goto state for second part of word transfer
+        --  v.lhw := '0'; --write MSB 16 bits to AMBA adress that ends with 00
+          else --halfword or byte
+            v.sdstate := act3_16; v.hready := '1';
+          end if;
+        else --32 bit or 64
+          v.sdstate := wr1;
+          if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
+        end if;
+        v.sdwen := '0'; v.bdrive := '0'; --write
+        if WPROTEN and (r.wprothit = '1') then
+          v.hresp := HRESP_ERROR; v.hready := '1';
+          if BUS16 then v.sdstate := act3_16; else v.sdstate := wr1; end if;
+          v.sdwen := '1'; v.bdrive := '1'; v.casn := '1'; --skip write, remember hready high in next state
+        end if;
+      else v.sdstate := rd1; end if;
+
+    when act3_16 => --handle 16 bit and WORD write
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '1';
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 2) & '1';
+      v.lhw := '1';
+      if (r.hready and r.burst) = '1' and not (WPROTEN and (r.wprothit = '1')) then
+        v.hready := '0'; --kolla på transfertyp nonseq om vi vill delaya nedankoll.
+        if( ahbsi.htrans = "11" and
+            not ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) and
+            not ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00") ) then
+          v.sdstate := wr1_16;
+        end if;
+      elsif r.burst = '1' or (r.hready and not r.burst) = '1' then --terminate burst or single write
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      else -- complete single write
+        v.hready := '1';
+        v.sdstate := act3_16; --gick till wr1 förut
+      end if;
+
+    when wr1_16 =>
+      v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 1);
+--      v.address(13 downto 2) := r.haddr(11) & '0' & r.haddr(10 downto 1);
+      v.lhw := r.haddr(1);
+      v.sdstate := act3_16;
+      v.hready := '1';
+
+    when wr1 =>
+      v.address(14 downto 2) := r.haddr(13 downto 12) & '0' & r.haddr(11 downto 2);
+      if (((r.burst and r.hready) = '1') and (r.htrans = "11"))
+         and not (WPROTEN and (r.wprothit = '1'))
+      then
+        v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
+        if ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
+          v.hready := '0';
+        end if;
+      else
+        v.sdstate := wr2; v.bdrive := '1'; v.casn := '1'; v.sdwen := '1';
+        v.dqm := (others => '1');
+      end if;
+
+    when wr2 =>
+      if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
+      v.sdstate := wr3;
+
+    when wr3 =>
+      if (r.cfg.trp = '1') then
+        v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
+      else
+        v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when wr4 =>
+      v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
+      if (r.cfg.trp = '1') then v.sdstate := wr5;
+      else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+
+    when wr5 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+
+    when rd1 => --first read applied to sdram
+      v.casn := '1'; v.sdstate := rd7; --nop
+      if not BUS16 then --starting adress cannot be XXXX...111 since we have word burst in this case. and lowest bit always 0.
+        if lineburst and (ahbsi.htrans = "11") then
+          if r.haddr(4 downto 2) = "111" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1; --adds only within 1KB limit.
+            v.address(4 downto 2) := "000"; v.casn := '0';
+	  end if;
+        end if;
+      end if;
+
+    when rd7 =>
+      v.casn := '1'; --nop
+      if BUS16 then
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if;
+          elsif lineburst then
+            if r.haddr(3 downto 1) = "110" then
+              v.address(10 downto 5) := r.address(10 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      else -- 32 bit or larger
+        if r.cfg.casdel = '1' then --casdel3
+          v.sdstate := rd2;
+          if lineburst and (ahbsi.htrans = "11") then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        else                       --casdel2
+          v.sdstate := rd3;
+          if ahbsi.htrans /= "11" then
+            if (r.trfc(3 downto 1) = "000") then v.rasn := '0'; v.sdwen := '0'; end if; --precharge
+          elsif lineburst then
+            if r.haddr(4 downto 2) = "110" then
+              v.address(9 downto 5) := r.address(9 downto 5) + 1;
+              v.address(4 downto 2) := "000"; v.casn := '0';
+            end if;
+          end if;
+        end if;
+      end if;
+
+    when rd2 =>
+      v.casn := '1'; v.sdstate := rd3;
+      if BUS16 then
+        if ahbsi.htrans /= "11" then
+          v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+          --note that DQM always has 2 cycle delay before blocking data. So NP if we fetch second HW
+        end if;
+      else
+        if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; v.dqm := (others => '1'); --precharge & DQM
+        elsif lineburst then
+          if r.haddr(4 downto 2) = "101" then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd3 => --first read data from sdram output v.lhw := r.haddr(1);
+      v.casn := '1'; --if read before cas makes nop else if pre => no difference
+      if BUS16 then
+        --note if read is for halfwor or byte we dont want to read a second time but exit.
+        --if the read is a word we need to change LHW to one since the next read should be muxed in next cylcle.
+    --    if r.size(1) = '1' then --word v.hready := not r.size(1)
+    --      v.sdstate := rd4_16; v.hready := '0'; --hready low since just first part of a word
+    --      v.lhw := '1'; -- read low 16 next state
+    --    else --HW or byte
+    --      v.sdstate := rd4_16; v.hready := '1';
+    --    end if;
+        v.sdstate := rd4_16;
+        v.lhw := not r.lhw; --r.lhw is 0 for word, we should invert for next half of word.For HW or Byte v.lhw does not matter.
+        v.hready := not r.size(1); --if word transfer the r.size(1) is 1 and hready goes low.If HW or byte r.size(1)=0 => hready=1
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and ((ahbsi.htrans = "11") and (r.cfg.casdel = '1')) then --only enter if cl3
+          if r.haddr(3 downto 1) = "100" then
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      else --32 bit or larger
+        v.sdstate := rd4; v.hready := '1';
+        if r.sdwen = '0' then
+          v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); -- make DSEL (NOP)
+        elsif lineburst and (ahbsi.htrans = "11") and (r.casn = '1') then
+          if r.haddr(4 downto 2) = ("10" & not r.cfg.casdel) then
+            v.address(9 downto 5) := r.address(9 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4_16 => --enter as word (r.hready is still 0) else 1. If hready one next transfer sampled into v.
+      --v.hready := '1';
+      v.hready := not r.hready;-- if Byte or HW exit with hready low. If word flip bit, makes correct exit with hready low.
+      v.lhw := not r.lhw; --r.lhw is one the first time we enter (taking care of second part of word)
+      v.casn := '1';
+      --quit on: Single transfer CL 2/3 (prcharge if CL 2 and timer was not 0)
+      if (ahbsi.htrans /= "11" and (r.hready = '1')) or
+         ((r.haddr(9) xor ahbsi.haddr(9)) = '1' and r.cfg.csize = "00" and r.hready = '1') or --probably dont have to check hready 1 since if 0 adresses equal.
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100") and (r.hready = '1')) then --quit on: ST W/HW/BYTE OR
+        --v.hready := '0'; --if Byte or HW exit with hready low, if ST word exit with high.
+        v.dqm := (others => '1');
+        if r.sdcsn /= "11" then --not prechargeing
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; --precharge
+        else--exit
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then --NOTE: r.casn = 1 makes sure its the first halfword of a word that is checked (hready low)
+        if r.cfg.casdel = '0' then
+          if (r.haddr(3 downto 1) = "100") and (r.casn = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        else
+          if (r.haddr(3 downto 1) = "010") and (r.hready = '1') then --lline = 011 if casdel =1, 100 if casdel= 0
+            v.address(10 downto 5) := r.address(10 downto 5) + 1;
+            v.address(4 downto 2) := "000"; v.casn := '0';
+          end if;
+        end if;
+      end if;
+
+    when rd4 =>
+      v.hready := '1'; v.casn := '1';
+      if (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
+         ((r.haddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
+      then
+        v.hready := '0'; v.dqm := (others => '1');
+        if (r.sdcsn /= "11") then
+          v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
+        else
+          if r.cfg.trp = '1' then v.sdstate := rd6;
+          else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+        end if;
+      elsif lineburst then
+        if (r.haddr(4 downto 2) = lline) and (r.casn = '1') then
+          v.address(9 downto 5) := r.address(9 downto 5) + 1;
+          v.address(4 downto 2) := "000"; v.casn := '0';
+        end if;
+      end if;
+
+    when rd5 =>
+      if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
+      v.casn := '1';
+
+    when rd6 =>
+      v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
+
+    when sref =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
+        if r.trfc = "0000" then -- Minimum duration (= tRAS)
+          v.cfg.cke := '1';
+          v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
+        end if;
+        if r.cfg.cke = '1' then
+          if (r.idlecnt = "0000") then -- tXSR ns with NOP
+            v.sdstate := sidle;
+            v.idlecnt := (others => '1');
+            v.sref_tmpcom := r.cfg.command;
+            v.cfg.command := "100";
+          end if;
+        else
+          v.idlecnt := r.cfg.txsr;
+        end if;
+      end if;
+
+    when pd =>
+      if (startsd = '1' and (r.hio = '0'))
+          or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
+        v.cfg.cke := '1';
+        v.sdstate := sidle;
+        v.idlecnt := (others => '1');
+      end if;
+
+    when dpd =>
+      v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
+      v.cfg.renable := '0';
+      if (startsd = '1' and r.hio = '0') then
+        v.hready := '1'; -- ack all accesses with Error response
+        v.startsd := '0';
+        v.hresp := HRESP_ERROR;
+      elsif r.cfg.pmode /= PM_DPD then
+        v.cfg.cke := '1';
+        if r.cfg.cke = '1' then
+          v.sdstate := sidle;
+          v.idlecnt := (others => '1');
+          v.cfg.renable := '1';
+        end if;
+      end if;
+
+    when others =>
+      v.sdstate := sidle; v.idlecnt := (others => '1');
+    end case;
+
+-- sdram commands
+
+    case r.cmstate is
+    when midle =>
+      if r.sdstate = sidle then
+        case r.cfg.command is
+        when "010" => -- precharge
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
+          v.address(12) := '1'; v.cmstate := active;
+        when "100" => -- auto-refresh
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.cmstate := active;
+        when "110" => -- Lodad Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          if lineburst then
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
+          else
+            v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
+          end if;
+        when "111" => -- Load Ext-Mode Reg
+          v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
+          v.sdwen := '0'; v.cmstate := active;
+          v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
+                                    & r.cfg.pasr(2 downto 0);
+        when others => null;
+        end case;
+      end if;
+    when active =>
+      v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
+      v.sdwen := '1'; --v.cfg.command := "000";
+      v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
+      v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
+    when leadout =>
+      if r.trfc = "0000" then v.cmstate := midle; end if;
+
+    end case;
+
+-- sdram init
+
+    case r.istate is
+    when iidle =>
+      v.cfg.cke := '1';
+      if r.cfg.renable = '1' and r.cfg.cke = '1' then
+        v.cfg.command := "010"; v.istate := pre;
+      end if;
+    when pre =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
+      end if;
+    when ref =>
+      if r.cfg.command = "000" then
+        v.cfg.command := "100"; v.icnt := r.icnt - 1;
+        if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
+      end if;
+    when lmode =>
+      if r.cfg.command = "000" then
+        if r.cfg.mobileen = "11" then
+          v.cfg.command := "111"; v.istate := emode;
+        else
+          v.istate := finish;
+        end if;
+      end if;
+    when emode =>
+      if r.cfg.command = "000" then
+        v.istate := finish;
+      end if;
+    when others =>
+      if r.cfg.renable = '0' and r.sdstate /= dpd then
+        v.istate := iidle;
+      end if;
+    end case;
+
+    if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
+      if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
+    end if;
+
+    if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
+
+-- second part of main fsm
+
+    case r.mstate is
+    when active =>
+      if v.hready = '1' then
+        v.mstate := midle;
+      end if;
+    when others => null;
+    end case;
+
+-- sdram refresh counter
+
+-- pragma translate_off
+    if not is_x(r.cfg.refresh) then
+-- pragma translate_on
+      if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
+        v.refresh := r.refresh - 1;
+        if (v.refresh(14) and not r.refresh(14))  = '1' then
+          v.refresh := r.cfg.refresh;
+          v.cfg.command := "100";
+          arefresh := '1';
+        end if;
+      end if;
+-- pragma translate_off
+    end if;
+-- pragma translate_on
+
+-- AHB register access
+-- if writing to IO space config regs. Just mapping write data to all config values in config reg
+    if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
+      if r.haddr(3 downto 2) = "00" then
+        if pageburst = 2 then v.cfg.pageburst :=  hwdata(17); end if;
+        v.cfg.command   :=  hwdata(20 downto 18);
+        v.cfg.csize     :=  hwdata(22 downto 21);
+        v.cfg.bsize     :=  hwdata(25 downto 23);
+        v.cfg.casdel    :=  hwdata(26);
+        v.cfg.trfc      :=  hwdata(29 downto 27);
+        v.cfg.trp       :=  hwdata(30);
+        v.cfg.renable   :=  hwdata(31);
+        v.cfg.refresh   :=  hwdata(14 downto 0);
+        v.refresh       :=  (others => '0');
+      elsif r.haddr(3 downto 2) = "01" then
+        if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := hwdata(31); end if;
+        if r.cfg.pmode = "000" then
+          v.cfg.cke               :=  hwdata(30);
+        end if;
+        if r.cfg.mobileen(1) = '1' then
+          v.cfg.txsr              :=  hwdata(23 downto 20);
+          v.cfg.pmode             :=  hwdata(18 downto 16);
+          v.cfg.ds(3 downto 2)    :=  hwdata( 6 downto  5);
+          v.cfg.tcsr(3 downto 2)  :=  hwdata( 4 downto  3);
+          v.cfg.pasr(5 downto 3)  :=  hwdata( 2 downto  0);
+        end if;
+      end if;
+    end if;
+
+    -- Disable CS and DPD when Mobile SDR is Disabled
+    if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
+
+    -- Update EMR when ds, tcsr or pasr change
+    if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
+      if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
+      end if;
+      if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
+        v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
+      end if;
+      if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
+        v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
+      end if;
+    end if;
+
+    regsd := (others => '0');
+    --reads out config registers (r/w does not matter) according to manual depending on address, notice generic determines data width.
+    if r.haddr(3 downto 2) = "00" then
+      regsd(31 downto 18) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
+                             r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
+      if not lineburst then regsd(17) := '1'; end if;
+      regsd(16) := r.cfg.mobileen(1);
+      if BUS64 then regsd(15) := '1'; end if;
+      regsd(14 downto 0) := r.cfg.refresh;
+    elsif r.haddr(3 downto 2) = "01" then
+      regsd(31) := r.cfg.mobileen(0);
+      regsd(30) := r.cfg.cke;
+      regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
+                            r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
+    end if;
+
+    if (r.hsel and r.hio) = '1' then dout := regsd;
+    else
+      if BUS64 and r.bsel = '1' then dout := r.hrdata(63 downto 32);
+      else dout := r.hrdata(31 downto 0); end if;
+    end if;
+
+    v.nbdrive := not v.bdrive;
+
+    if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
+    else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
+
+-- reset
+
+    if rst = '0' then
+      v.sdstate       := sidle;
+      v.mstate        := midle;
+      v.istate        := iidle;
+      v.cmstate       := midle;
+      v.hsel          := '0';
+      v.cfg.command   := "000";
+      v.cfg.csize     := "01";
+      v.cfg.bsize     := "011";
+      v.cfg.casdel    :=  '1';
+      v.cfg.trfc      := "111";
+      if pwron = 1 then v.cfg.renable :=  '1';
+      else v.cfg.renable :=  '0'; end if;
+      v.cfg.trp       :=  '1';
+      v.dqm           := (others => '1');
+      v.sdwen         := '1';
+      v.rasn          := '1';
+      v.casn          := '1';
+      v.hready        := '1';
+      v.bsel          := '0';
+      v.startsd       := '0';
+      if (pageburst = 2) then
+        v.cfg.pageburst   :=  '0';
+      end if;
+      if mobile >= 2 then v.cfg.mobileen := "11";
+      elsif mobile = 1 then v.cfg.mobileen := "10";
+      else v.cfg.mobileen := "00"; end if;
+      v.cfg.txsr      := (others => '1');
+      v.cfg.pmode     := (others => '0');
+      v.cfg.ds        := (others => '0');
+      v.cfg.tcsr      := (others => '0');
+      v.cfg.pasr      := (others => '0');
+      if mobile >= 2 then v.cfg.cke := '0';
+      else v.cfg.cke       := '1'; end if;
+      v.sref_tmpcom   := "000";
+      v.idlecnt := (others => '1');
+    end if;
+
+    ri <= v;
+    ribdrive <= vbdrive;
+
+    ahbso.hready  <= r.hready;
+    ahbso.hresp   <= r.hresp;
+    ahbso.hrdata  <= ahbdrivedata(dout);
+
+  end process;
+
+  --sdo.sdcke     <= (others => '1');
+  sdo.sdcke     <= (others => r.cfg.cke);
+  ahbso.hconfig <= hconfig;
+  ahbso.hirq    <= (others => '0');
+  ahbso.hindex  <= hindex;
+  ahbso.hsplit  <= (others => '0');
+
+  -- Quick hack to get rid of undriven signal warnings. Check this for future
+  -- merge with main sdctrl.
+  drivehack : block
+  begin
+    sdo.qdrive <= '0';
+    sdo.nbdrive <= '0';
+    sdo.ce <= '0';
+    sdo.moben <= '0';
+    sdo.cal_rst <= '0';
+    sdo.oct <= '0';
+    sdo.xsdcsn <= (others => '1');
+    sdo.data(127 downto 16) <= (others => '0');
+    sdo.cb <= (others => '0');
+    sdo.ba <= (others => '0');
+    sdo.sdck <= (others => '0');
+    sdo.cal_en <= (others => '0');
+    sdo.cal_inc <= (others => '0');
+    sdo.cal_pll <= (others => '0');
+    sdo.odt <= (others => '0');
+    sdo.conf <= (others => '0');
+    sdo.vcbdrive <= (others => '0');
+    sdo.dqs_gate <= '0';
+    sdo.cbdqm <= (others => '0');
+    sdo.cbcal_en <= (others => '0');
+    sdo.cbcal_inc <= (others => '0');
+    sdo.read_pend <= (others => '0');
+    sdo.regwdata <= (others => '0');
+    sdo.regwrite <= (others => '0');
+  end block drivehack;
+
+  regs : process(clk, rst) begin
+    if rising_edge(clk) then
+      r <= ri; rbdrive <= ribdrive;
+      if rst = '0' then r.icnt <= (others => '0'); end if;
+    end if;
+    if (rst = '0') then
+      r.sdcsn  <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
+      if oepol = 0 then rbdrive <= (others => '1');
+      else rbdrive <= (others => '0'); end if;
+    end if;
+  end process;
+
+  rgen : if not SDINVCLK generate
+    sdo.address  <= r.address;
+    sdo.bdrive   <= r.nbdrive when oepol = 1 else r.bdrive;
+    sdo.vbdrive  <= zero32 & rbdrive;
+    sdo.sdcsn    <= r.sdcsn;
+    sdo.sdwen    <= r.sdwen;
+    sdo.dqm      <= "11111111" & r.dqm;
+    sdo.rasn     <= r.rasn;
+    sdo.casn     <= r.casn;
+
+    mux16_wrdata : if BUS16 generate --mux data depending on Low/High HW
+      sdo.data(15 downto 0) <= r.hwdata(15 downto 0) when r.lhw = '1' else r.hwdata(31 downto 16);
+    end generate;
+
+    wrdata : if not BUS16 generate
+      drivebus: for i in 0 to sdbits/64 generate
+        sdo.data(31+32*i downto 32*i) <= r.hwdata;
+      end generate;
+    end generate;
+  end generate;
+
+  ngen : if SDINVCLK generate
+    nregs : process(clk, rst) begin
+      if falling_edge(clk) then
+        sdo.address  <= r.address;
+        if oepol = 1 then sdo.bdrive <= r.nbdrive;
+        else sdo.bdrive <= r.bdrive; end if;
+        sdo.vbdrive  <= zero32 & rbdrive;
+        sdo.sdcsn    <= r.sdcsn;
+        sdo.sdwen    <= r.sdwen;
+        sdo.dqm      <= "11111111" & r.dqm;
+        sdo.rasn     <= r.rasn;
+        sdo.casn     <= r.casn;
+        if BUS16 then --mux data depending on Low/High HW
+          if (r.lhw ='1') then
+            sdo.data(15 downto 0) <= r.hwdata(15 downto 0);
+          else
+            sdo.data(15 downto 0) <= r.hwdata(31 downto 16);
+          end if;
+        end if;
+
+        if not BUS16 then
+          for i in 0 to sdbits/64 loop
+            sdo.data(31+32*i downto 32*i) <= r.hwdata;
+          end loop;
+        end if;
+      end if;
+      if rst = '0' then sdo.sdcsn <= (others => '1'); end if;
+    end process;
+  end generate;
+
+-- pragma translate_off
+  bootmsg : report_version
+  generic map ("sdctrl16" & tost(hindex) &
+    ": PC133 SDRAM controller rev " & tost(REVISION));
+-- pragma translate_on
+
+end;
+
diff --git a/designs/Timegen2/testbench.vhd b/designs/Timegen2/testbench.vhd
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/testbench.vhd
@@ -0,0 +1,200 @@
+------------------------------------------------------------------------------
+--  LEON3 Demonstration design test bench
+--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+--  This file is a part of the GRLIB VHDL IP LIBRARY
+--  Copyright (C) 2003 - 2008, Gaisler Research
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler
+--  Copyright (C) 2015 - 2016, Cobham Gaisler
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 2 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+library ieee;
+use ieee.std_logic_1164.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.sim.all;
+use work.debug.all;
+library techmap;
+use techmap.gencomp.all;
+library micron;
+use micron.components.all;
+library grlib;
+use grlib.stdlib.all;
+
+use work.config.all;	-- configuration
+
+
+entity testbench is
+  generic (
+    fabtech   : integer := CFG_FABTECH;
+    memtech   : integer := CFG_MEMTECH;
+    padtech   : integer := CFG_PADTECH;
+    clktech   : integer := CFG_CLKTECH;
+    disas     : integer := CFG_DISAS;	-- Enable disassembly to console
+    dbguart   : integer := CFG_DUART;	-- Print UART on console
+    pclow     : integer := CFG_PCLOW;
+
+    clkperiod : integer := 20;		-- system clock period
+    romdepth  : integer := 22		-- rom address depth (flash 4 MB)
+ --   sramwidth  : integer := 32;		-- ram data width (8/16/32)
+ --   sramdepth  : integer := 20;		-- ram address depth
+ --   srambanks  : integer := 2		-- number of ram banks
+  );
+end;
+
+architecture behav of testbench is
+
+constant promfile  : string := "prom.srec";  -- rom contents
+constant sramfile  : string := "ram.srec";  -- ram contents
+constant sdramfile : string := "ram.srec"; -- sdram contents
+
+
+signal SW     : std_logic_vector(4 downto 1);
+signal clk : std_logic := '0';
+signal Rst    : std_logic := '0';			-- Reset
+constant ct : integer := clkperiod/2;
+
+signal address  : std_logic_vector(21 downto 0);
+signal data     : std_logic_vector(31 downto 24);
+
+signal romsn    : std_logic;
+signal oen      : std_logic;
+signal writen   : std_logic;
+signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
+signal dsurst   : std_logic;
+signal error    : std_logic;
+
+signal sdcke    : std_logic;
+signal sdcsn    : std_logic;
+signal sdwen    : std_logic;                       -- write en
+signal sdrasn   : std_logic;                       -- row addr stb
+signal sdcasn   : std_logic;                       -- col addr stb
+signal dram_ldqm : std_logic;
+signal dram_udqm : std_logic;
+signal sdclk    : std_logic;
+signal dram_ba  : std_logic_vector(1 downto 0);
+
+
+
+constant lresp : boolean := false;
+
+
+signal sa      	: std_logic_vector(12 downto 0);
+signal sd   	: std_logic_vector(15 downto 0);
+
+
+begin
+
+  clk <= not clk after ct * 1 ns; --50 MHz clk
+  rst <= dsurst; --reset
+  dsuen <= '1';
+  dsubre <= '1'; -- inverted on the board
+  sw(1) <= rst;
+
+  d3 : entity work.leon3mp
+        generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
+        port map (
+            CLK50  => clk,
+            LEDS   => open,
+            SW     => SW,
+            dram_addr => sa,
+            dram_ba_0	=> dram_ba(0),
+            dram_ba_1	=> dram_ba(1),
+            dram_dq	=> sd(15 downto 0),
+            dram_clk  	=> sdclk,
+            dram_cke  	=> sdcke,
+            dram_cs_n   => sdcsn,
+            dram_we_n  	=> sdwen,
+            dram_ras_n  => sdrasn,
+            dram_cas_n  => sdcasn,
+            dram_ldqm	  => dram_ldqm,
+            dram_udqm	  => dram_udqm,
+            uart_txd  	=> dsutx,
+            uart_rxd  	=> dsurx);
+
+    u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 9, index => 1024, fname => sdramfile)
+	PORT MAP(
+            Dq => sd(15 downto 0), Addr => sa(12 downto 0),
+            Ba => dram_ba, Clk => sdclk, Cke => sdcke,
+            Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
+            Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
+
+
+
+  error <= 'H';			  -- ERROR pull-up
+
+   iuerr : process
+   begin
+     wait for 2500 ns;
+     if to_x01(error) = '1' then wait on error; end if;
+     assert (to_x01(error) = '1')
+       report "*** IU in error mode, simulation halted ***"
+         severity failure ;
+   end process;
+
+  data <= buskeep(data) after 5 ns;
+  sd <= buskeep(sd) after 5 ns;
+
+  dsucom : process
+    variable w32 : std_logic_vector(31 downto 0);
+    constant txp : time := 160 * 1 ns;
+    procedure writeReg(signal dsutx : out std_logic;  address : integer; value : integer) is
+    begin
+        txc(dsutx, 16#c0#, txp); --control byte
+        txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)),  address, txp); --adress
+        txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data
+    end;
+
+    procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic;  address : integer; value: out std_logic_vector) is
+
+    begin
+        txc(dsutx, 16#a0#, txp); --control byte
+        txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress
+        rxi(dsurx, value, txp, lresp); --write data
+    end;
+
+    procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
+    variable c8  : std_logic_vector(7 downto 0);
+    begin
+        dsutx <= '1';
+    dsurst <= '0'; --reset low
+    wait for 500 ns;
+    dsurst <= '1'; --reset high
+    --wait; --evig w8
+    wait for 5000 ns;
+    txc(dsutx, 16#55#, txp);
+    --dsucfg(dsutx, dsurx);
+    writeReg(dsutx,16#40000000#,16#12345678#);
+    writeReg(dsutx,16#40000004#,16#22222222#);
+    writeReg(dsutx,16#40000008#,16#33333333#);
+    writeReg(dsutx,16#4000000C#,16#44444444#);
+
+    readReg(dsurx,dsutx,16#40000000#,w32);
+    readReg(dsurx,dsutx,16#40000004#,w32);
+    readReg(dsurx,dsutx,16#40000008#,w32);
+    readReg(dsurx,dsutx,16#4000000C#,w32);
+
+    end;
+
+  begin
+  dsucfg(dsutx, dsurx);
+
+
+    wait;
+ end process;
+end ;
+
diff --git a/designs/Timegen2/withSPW.ucf b/designs/Timegen2/withSPW.ucf
new file mode 100644
--- /dev/null
+++ b/designs/Timegen2/withSPW.ucf
@@ -0,0 +1,143 @@
+# Clocks
+NET "CLK50" PERIOD = 20 ns |LOC = "K3";
+#NET "CLK32" PERIOD = 31.25 ns | LOC = "J4";
+# LEDs
+NET "LEDS<0>" LOC="P11" |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<1>" LOC="N9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<2>" LOC="M9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<3>" LOC="P9"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<4>" LOC="T8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<5>" LOC="N8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<6>" LOC="P8"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+NET "LEDS<7>" LOC="P7"  |IOSTANDARD=LVTTL |DRIVE=8 |SLEW=SLOW;
+
+# DIP Switches
+NET "SW<1>"   LOC="L1" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<2>"   LOC="L3" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<3>"   LOC="L4" |IOSTANDARD=LVTTL |PULLUP;
+NET "SW<4>"   LOC="L5" |IOSTANDARD=LVTTL |PULLUP;
+
+NET "uart_rxd"  LOC="M7" |IOSTANDARD=LVTTL;
+NET "uart_txd"  LOC="N6" |IOSTANDARD=LVTTL;
+
+# SDRAM
+NET "dram_udqm"    LOC="F15"   |IOSTANDARD=LVTTL;
+NET "dram_clk" LOC="G16" |IOSTANDARD=LVTTL;
+NET "dram_cke"     LOC="H16"   |IOSTANDARD=LVTTL;
+NET "dram_ba_1"     LOC="T14"   |IOSTANDARD=LVTTL;
+NET "dram_ba_0"     LOC="R14"   |IOSTANDARD=LVTTL;
+NET "dram_cs_n" LOC="R1"  |IOSTANDARD=LVTTL;
+NET "dram_ras_n"    LOC="R2"    |IOSTANDARD=LVTTL;
+NET "dram_cas_n"    LOC="T4"    |IOSTANDARD=LVTTL;
+NET "dram_we_n"     LOC="R5"    |IOSTANDARD=LVTTL;
+NET "dram_ldqm"    LOC="T5"    |IOSTANDARD=LVTTL;
+NET "dram_addr<0>"    LOC="T15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<1>"    LOC="R16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<2>"    LOC="P15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<3>"    LOC="P16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<4>"    LOC="N16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<5>"    LOC="M15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<6>"    LOC="M16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<7>"    LOC="L16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<8>"    LOC="K15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<9>"    LOC="K16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<10>"   LOC="R15"   |IOSTANDARD=LVTTL;
+NET "dram_addr<11>"   LOC="J16"   |IOSTANDARD=LVTTL;
+NET "dram_addr<12>"   LOC="H15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<0>"    LOC="T13"   |IOSTANDARD=LVTTL;
+NET "dram_dq<1>"    LOC="T12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<2>"    LOC="R12"   |IOSTANDARD=LVTTL;
+NET "dram_dq<3>"    LOC="T9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<4>"    LOC="R9"    |IOSTANDARD=LVTTL;
+NET "dram_dq<5>"    LOC="T7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<6>"    LOC="R7"    |IOSTANDARD=LVTTL;
+NET "dram_dq<7>"    LOC="T6"    |IOSTANDARD=LVTTL;
+NET "dram_dq<8>"    LOC="F16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<9>"    LOC="E15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<10>"   LOC="E16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<11>"   LOC="D16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<12>"   LOC="B16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<13>"   LOC="B15"   |IOSTANDARD=LVTTL;
+NET "dram_dq<14>"   LOC="C16"   |IOSTANDARD=LVTTL;
+NET "dram_dq<15>"   LOC="C15"   |IOSTANDARD=LVTTL;
+#Created by Constraints Editor (xc6slx25-ftg256-3) - 2016/12/08
+INST "dram_addr(0)" TNM = dram_addr;
+INST "dram_addr(1)" TNM = dram_addr;
+INST "dram_addr(2)" TNM = dram_addr;
+INST "dram_addr(3)" TNM = dram_addr;
+INST "dram_addr(4)" TNM = dram_addr;
+INST "dram_addr(5)" TNM = dram_addr;
+INST "dram_addr(6)" TNM = dram_addr;
+INST "dram_addr(7)" TNM = dram_addr;
+INST "dram_addr(8)" TNM = dram_addr;
+INST "dram_addr(9)" TNM = dram_addr;
+INST "dram_addr(10)" TNM = dram_addr;
+INST "dram_addr(11)" TNM = dram_addr;
+INST "dram_addr(12)" TNM = dram_addr;
+INST "dram_addr(0)" TNM = dram_out;
+INST "dram_addr(1)" TNM = dram_out;
+INST "dram_addr(2)" TNM = dram_out;
+INST "dram_addr(3)" TNM = dram_out;
+INST "dram_addr(4)" TNM = dram_out;
+INST "dram_addr(5)" TNM = dram_out;
+INST "dram_addr(6)" TNM = dram_out;
+INST "dram_addr(7)" TNM = dram_out;
+INST "dram_addr(8)" TNM = dram_out;
+INST "dram_addr(9)" TNM = dram_out;
+INST "dram_addr(10)" TNM = dram_out;
+INST "dram_addr(11)" TNM = dram_out;
+INST "dram_addr(12)" TNM = dram_out;
+INST "dram_ba_0" TNM = dram_out;
+INST "dram_ba_1" TNM = dram_out;
+INST "dram_cas_n" TNM = dram_out;
+INST "dram_cke" TNM = dram_out;
+#INST "dram_clk" TNM = dram_out;
+INST "dram_cs_n" TNM = dram_out;
+INST "dram_dq(0)" TNM = dram_out;
+INST "dram_dq(1)" TNM = dram_out;
+INST "dram_dq(2)" TNM = dram_out;
+INST "dram_dq(3)" TNM = dram_out;
+INST "dram_dq(4)" TNM = dram_out;
+INST "dram_dq(5)" TNM = dram_out;
+INST "dram_dq(6)" TNM = dram_out;
+INST "dram_dq(7)" TNM = dram_out;
+INST "dram_dq(8)" TNM = dram_out;
+INST "dram_dq(9)" TNM = dram_out;
+INST "dram_dq(10)" TNM = dram_out;
+INST "dram_dq(11)" TNM = dram_out;
+INST "dram_dq(12)" TNM = dram_out;
+INST "dram_dq(13)" TNM = dram_out;
+INST "dram_dq(14)" TNM = dram_out;
+INST "dram_dq(15)" TNM = dram_out;
+INST "dram_ldqm" TNM = dram_out;
+INST "dram_ras_n" TNM = dram_out;
+INST "dram_udqm" TNM = dram_out;
+INST "dram_we_n" TNM = dram_out;
+TIMEGRP "dram_out" OFFSET = OUT 12 ns AFTER "CLK50";
+INST "dram_dq(0)" TNM = dram_in;
+INST "dram_dq(1)" TNM = dram_in;
+INST "dram_dq(2)" TNM = dram_in;
+INST "dram_dq(3)" TNM = dram_in;
+INST "dram_dq(4)" TNM = dram_in;
+INST "dram_dq(5)" TNM = dram_in;
+INST "dram_dq(6)" TNM = dram_in;
+INST "dram_dq(7)" TNM = dram_in;
+INST "dram_dq(8)" TNM = dram_in;
+INST "dram_dq(9)" TNM = dram_in;
+INST "dram_dq(10)" TNM = dram_in;
+INST "dram_dq(11)" TNM = dram_in;
+INST "dram_dq(12)" TNM = dram_in;
+INST "dram_dq(13)" TNM = dram_in;
+INST "dram_dq(14)" TNM = dram_in;
+INST "dram_dq(15)" TNM = dram_in;
+TIMEGRP "dram_in" OFFSET = IN 3 ns BEFORE "CLK50" RISING;
+
+
+NET "spw_rxdp" LOC = "h2";# | IOSTANDARD = LVDS_33;
+NET "spw_rxdn" LOC = "h1";# | IOSTANDARD = LVDS_33;
+NET "spw_rxsp" LOC = "f4";# | IOSTANDARD = LVDS_33;
+NET "spw_rxsn" LOC = "f3";#  | IOSTANDARD = LVDS_33;
+NET "spw_txdp" LOC = "e2";# | IOSTANDARD = LVTTL;
+NET "spw_txdn" LOC = "e1";# | IOSTANDARD = LVTTL;
+NET "spw_txsp" LOC = "g3";# | IOSTANDARD = LVTTL;
+NET "spw_txsn" LOC = "g1";# | IOSTANDARD = LVTTL;
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/.config.old b/designs/leon3-APB_LCD-digilent-xc3s1600e/.config.old
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/.config.old
+++ /dev/null
@@ -1,309 +0,0 @@
-#
-# Automatically generated make config: don't edit
-#
-
-#
-# Synthesis      
-#
-# CONFIG_SYN_INFERRED is not set
-# CONFIG_SYN_STRATIX is not set
-# CONFIG_SYN_STRATIXII is not set
-# CONFIG_SYN_STRATIXIII is not set
-# CONFIG_SYN_CYCLONEIII is not set
-# CONFIG_SYN_ALTERA is not set
-# CONFIG_SYN_AXCEL is not set
-# CONFIG_SYN_AXDSP is not set
-# CONFIG_SYN_PROASIC is not set
-# CONFIG_SYN_PROASICPLUS is not set
-# CONFIG_SYN_PROASIC3 is not set
-# CONFIG_SYN_PROASIC3E is not set
-# CONFIG_SYN_PROASIC3L is not set
-# CONFIG_SYN_IGLOO is not set
-# CONFIG_SYN_FUSION is not set
-# CONFIG_SYN_UT025CRH is not set
-# CONFIG_SYN_ATC18 is not set
-# CONFIG_SYN_ATC18RHA is not set
-# CONFIG_SYN_CMOS9SF is not set
-# CONFIG_SYN_CUSTOM1 is not set
-# CONFIG_SYN_EASIC90 is not set
-# CONFIG_SYN_IHP25 is not set
-# CONFIG_SYN_IHP25RH is not set
-# CONFIG_SYN_LATTICE is not set
-# CONFIG_SYN_ECLIPSE is not set
-# CONFIG_SYN_PEREGRINE is not set
-# CONFIG_SYN_RH_LIB18T is not set
-# CONFIG_SYN_RHUMC is not set
-# CONFIG_SYN_SMIC13 is not set
-# CONFIG_SYN_TM65GPLUS is not set
-# CONFIG_SYN_TSMC90 is not set
-# CONFIG_SYN_UMC is not set
-# CONFIG_SYN_SPARTAN2 is not set
-# CONFIG_SYN_SPARTAN3 is not set
-CONFIG_SYN_SPARTAN3E=y
-# CONFIG_SYN_SPARTAN6 is not set
-# CONFIG_SYN_VIRTEX is not set
-# CONFIG_SYN_VIRTEXE is not set
-# CONFIG_SYN_VIRTEX2 is not set
-# CONFIG_SYN_VIRTEX4 is not set
-# CONFIG_SYN_VIRTEX5 is not set
-# CONFIG_SYN_VIRTEX6 is not set
-# CONFIG_SYN_INFER_RAM is not set
-# CONFIG_SYN_INFER_PADS is not set
-# CONFIG_SYN_NO_ASYNC is not set
-# CONFIG_SYN_SCAN is not set
-
-#
-# Clock generation
-#
-# CONFIG_CLK_INFERRED is not set
-# CONFIG_CLK_HCLKBUF is not set
-# CONFIG_CLK_ALTDLL is not set
-# CONFIG_CLK_LATDLL is not set
-# CONFIG_CLK_PRO3PLL is not set
-# CONFIG_CLK_PRO3EPLL is not set
-# CONFIG_CLK_PRO3LPLL is not set
-# CONFIG_CLK_FUSPLL is not set
-# CONFIG_CLK_LIB18T is not set
-# CONFIG_CLK_RHUMC is not set
-# CONFIG_CLK_CLKDLL is not set
-CONFIG_CLK_DCM=y
-CONFIG_CLK_MUL=4
-CONFIG_CLK_DIV=5
-# CONFIG_PCI_CLKDLL is not set
-# CONFIG_CLK_NOFB is not set
-# CONFIG_PCI_SYSCLK is not set
-CONFIG_LEON3=y
-CONFIG_PROC_NUM=1
-
-#
-# Processor            
-#
-
-#
-# Integer unit                                           
-#
-CONFIG_IU_NWINDOWS=8
-CONFIG_IU_V8MULDIV=y
-# CONFIG_IU_MUL_LATENCY_2 is not set
-# CONFIG_IU_MUL_LATENCY_4 is not set
-CONFIG_IU_MUL_LATENCY_5=y
-# CONFIG_IU_MUL_MAC is not set
-CONFIG_IU_BP=y
-CONFIG_IU_SVT=y
-CONFIG_NOTAG=y
-CONFIG_IU_LDELAY=1
-CONFIG_IU_WATCHPOINTS=2
-CONFIG_PWD=y
-CONFIG_IU_RSTADDR=00000
-
-#
-# Floating-point unit
-#
-# CONFIG_FPU_ENABLE is not set
-
-#
-# Cache system
-#
-CONFIG_ICACHE_ENABLE=y
-# CONFIG_ICACHE_ASSO1 is not set
-CONFIG_ICACHE_ASSO2=y
-# CONFIG_ICACHE_ASSO3 is not set
-# CONFIG_ICACHE_ASSO4 is not set
-# CONFIG_ICACHE_SZ1 is not set
-# CONFIG_ICACHE_SZ2 is not set
-CONFIG_ICACHE_SZ4=y
-# CONFIG_ICACHE_SZ8 is not set
-# CONFIG_ICACHE_SZ16 is not set
-# CONFIG_ICACHE_SZ32 is not set
-# CONFIG_ICACHE_SZ64 is not set
-# CONFIG_ICACHE_SZ128 is not set
-# CONFIG_ICACHE_SZ256 is not set
-# CONFIG_ICACHE_LZ16 is not set
-CONFIG_ICACHE_LZ32=y
-CONFIG_ICACHE_ALGORND=y
-# CONFIG_ICACHE_ALGOLRR is not set
-# CONFIG_ICACHE_ALGOLRU is not set
-# CONFIG_ICACHE_LOCK is not set
-CONFIG_DCACHE_ENABLE=y
-# CONFIG_DCACHE_ASSO1 is not set
-CONFIG_DCACHE_ASSO2=y
-# CONFIG_DCACHE_ASSO3 is not set
-# CONFIG_DCACHE_ASSO4 is not set
-# CONFIG_DCACHE_SZ1 is not set
-# CONFIG_DCACHE_SZ2 is not set
-CONFIG_DCACHE_SZ4=y
-# CONFIG_DCACHE_SZ8 is not set
-# CONFIG_DCACHE_SZ16 is not set
-# CONFIG_DCACHE_SZ32 is not set
-# CONFIG_DCACHE_SZ64 is not set
-# CONFIG_DCACHE_SZ128 is not set
-# CONFIG_DCACHE_SZ256 is not set
-CONFIG_DCACHE_LZ16=y
-# CONFIG_DCACHE_LZ32 is not set
-CONFIG_DCACHE_ALGORND=y
-# CONFIG_DCACHE_ALGOLRR is not set
-# CONFIG_DCACHE_ALGOLRU is not set
-# CONFIG_DCACHE_LOCK is not set
-CONFIG_DCACHE_SNOOP=y
-# CONFIG_DCACHE_SNOOP_FAST is not set
-# CONFIG_DCACHE_SNOOP_SEPTAG is not set
-CONFIG_CACHE_FIXED=0
-
-#
-# MMU
-#
-CONFIG_MMU_ENABLE=y
-# CONFIG_MMU_COMBINED is not set
-CONFIG_MMU_SPLIT=y
-CONFIG_MMU_REPARRAY=y
-# CONFIG_MMU_REPINCREMENT is not set
-# CONFIG_MMU_I2 is not set
-# CONFIG_MMU_I4 is not set
-CONFIG_MMU_I8=y
-# CONFIG_MMU_I16 is not set
-# CONFIG_MMU_I32 is not set
-# CONFIG_MMU_D2 is not set
-# CONFIG_MMU_D4 is not set
-CONFIG_MMU_D8=y
-# CONFIG_MMU_D16 is not set
-# CONFIG_MMU_D32 is not set
-CONFIG_MMU_FASTWB=y
-CONFIG_MMU_PAGE_4K=y
-# CONFIG_MMU_PAGE_8K is not set
-# CONFIG_MMU_PAGE_16K is not set
-# CONFIG_MMU_PAGE_32K is not set
-# CONFIG_MMU_PAGE_PROG is not set
-
-#
-# Debug Support Unit        
-#
-CONFIG_DSU_ENABLE=y
-CONFIG_DSU_ITRACE=y
-# CONFIG_DSU_ITRACESZ1 is not set
-# CONFIG_DSU_ITRACESZ2 is not set
-CONFIG_DSU_ITRACESZ4=y
-# CONFIG_DSU_ITRACESZ8 is not set
-# CONFIG_DSU_ITRACESZ16 is not set
-CONFIG_DSU_ATRACE=y
-# CONFIG_DSU_ATRACESZ1 is not set
-# CONFIG_DSU_ATRACESZ2 is not set
-CONFIG_DSU_ATRACESZ4=y
-# CONFIG_DSU_ATRACESZ8 is not set
-# CONFIG_DSU_ATRACESZ16 is not set
-
-#
-# Fault-tolerance  
-#
-
-#
-# VHDL debug settings       
-#
-# CONFIG_IU_DISAS is not set
-# CONFIG_DEBUG_PC32 is not set
-
-#
-# AMBA configuration
-#
-CONFIG_AHB_DEFMST=0
-CONFIG_AHB_RROBIN=y
-# CONFIG_AHB_SPLIT is not set
-CONFIG_AHB_IOADDR=FFF
-CONFIG_APB_HADDR=800
-# CONFIG_AHB_MON is not set
-# CONFIG_AHB_DTRACE is not set
-
-#
-# Debug Link           
-#
-CONFIG_DSU_UART=y
-CONFIG_DSU_JTAG=y
-CONFIG_DSU_ETH=y
-# CONFIG_DSU_ETHSZ1 is not set
-CONFIG_DSU_ETHSZ2=y
-# CONFIG_DSU_ETHSZ4 is not set
-# CONFIG_DSU_ETHSZ8 is not set
-# CONFIG_DSU_ETHSZ16 is not set
-CONFIG_DSU_IPMSB=C0A8
-CONFIG_DSU_IPLSB=0033
-CONFIG_DSU_ETHMSB=020000
-CONFIG_DSU_ETHLSB=000018
-# CONFIG_DSU_ETH_PROG is not set
-
-#
-# Peripherals             
-#
-
-#
-# Memory controllers             
-#
-
-#
-# Leon2 memory controller        
-#
-CONFIG_MCTRL_LEON2=y
-# CONFIG_MCTRL_8BIT is not set
-CONFIG_MCTRL_16BIT=y
-# CONFIG_MCTRL_5CS is not set
-# CONFIG_MCTRL_SDRAM is not set
-
-#
-# DDR266 SDRAM controller             
-#
-CONFIG_DDRSP=y
-CONFIG_DDRSP_INIT=y
-CONFIG_DDRSP_FREQ=90
-CONFIG_DDRSP_COL=10
-CONFIG_DDRSP_MBYTE=64
-CONFIG_DDRSP_RSKEW=40
-
-#
-# On-chip RAM/ROM                 
-#
-# CONFIG_AHBROM_ENABLE is not set
-# CONFIG_AHBRAM_ENABLE is not set
-
-#
-# Ethernet             
-#
-CONFIG_GRETH_ENABLE=y
-# CONFIG_GRETH_GIGA is not set
-# CONFIG_GRETH_FIFO4 is not set
-# CONFIG_GRETH_FIFO8 is not set
-# CONFIG_GRETH_FIFO16 is not set
-CONFIG_GRETH_FIFO32=y
-# CONFIG_GRETH_FIFO64 is not set
-
-#
-# UARTs, timers and irq control         
-#
-CONFIG_UART1_ENABLE=y
-# CONFIG_UA1_FIFO1 is not set
-# CONFIG_UA1_FIFO2 is not set
-# CONFIG_UA1_FIFO4 is not set
-CONFIG_UA1_FIFO8=y
-# CONFIG_UA1_FIFO16 is not set
-# CONFIG_UA1_FIFO32 is not set
-CONFIG_IRQ3_ENABLE=y
-# CONFIG_IRQ3_SEC is not set
-CONFIG_GPT_ENABLE=y
-CONFIG_GPT_NTIM=2
-CONFIG_GPT_SW=8
-CONFIG_GPT_TW=32
-CONFIG_GPT_IRQ=8
-CONFIG_GPT_SEPIRQ=y
-# CONFIG_GPT_WDOGEN is not set
-CONFIG_GRGPIO_ENABLE=y
-CONFIG_GRGPIO_WIDTH=8
-CONFIG_GRGPIO_IMASK=0000
-
-#
-# Keybord and VGA interface
-#
-CONFIG_KBD_ENABLE=y
-# CONFIG_VGA_ENABLE is not set
-CONFIG_SVGA_ENABLE=y
-
-#
-# VHDL Debugging        
-#
-# CONFIG_DEBUG_UART is not set
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/APB_IIR_CEL.xst b/designs/leon3-APB_LCD-digilent-xc3s1600e/APB_IIR_CEL.xst
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/APB_IIR_CEL.xst
+++ /dev/null
@@ -1,5 +0,0 @@
-set -tmpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst/projnav.tmp"
-set -xsthdpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst"
-elaborate
--ifn APB_IIR_CEL.prj
--ifmt mixed
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_CTRLR.xst b/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_CTRLR.xst
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_CTRLR.xst
+++ /dev/null
@@ -1,5 +0,0 @@
-set -tmpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst/projnav.tmp"
-set -xsthdpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst"
-elaborate
--ifn IIR_CEL_CTRLR.prj
--ifmt mixed
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_FILTER.xst b/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_FILTER.xst
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/IIR_CEL_FILTER.xst
+++ /dev/null
@@ -1,5 +0,0 @@
-set -tmpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst/projnav.tmp"
-set -xsthdpdir "/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/xst"
-elaborate
--ifn IIR_CEL_FILTER.prj
--ifmt mixed
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/cds.lib b/designs/leon3-APB_LCD-digilent-xc3s1600e/cds.lib
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/cds.lib
+++ /dev/null
@@ -1,17 +0,0 @@
-include $CDS_INST_DIR/tools/inca/files/cds.lib
-DEFINE grlib xncsim/grlib 
-DEFINE unisim xncsim/unisim 
-DEFINE dw02 xncsim/dw02 
-DEFINE synplify xncsim/synplify 
-DEFINE techmap xncsim/techmap 
-DEFINE eth xncsim/eth 
-DEFINE gaisler xncsim/gaisler 
-DEFINE esa xncsim/esa 
-DEFINE fmf xncsim/fmf 
-DEFINE spansion xncsim/spansion 
-DEFINE gsi xncsim/gsi 
-DEFINE lpp xncsim/lpp 
-DEFINE cypress xncsim/cypress 
-DEFINE hynix xncsim/hynix 
-DEFINE micron xncsim/micron 
-DEFINE work xncsim/work 
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.asim b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.asim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.asim
+++ /dev/null
@@ -1,303 +0,0 @@
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/version.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/config.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/stdlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/stdio.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/testlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/util/util.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/sparc.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/sparc_disas.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/cpu_disas.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/modgen/multlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/modgen/leaves.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/amba.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/devices.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/defmst.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/apbctrl.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/ahbctrl.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb_tp.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/amba_tp.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_util.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_mst.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_slv.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahbs.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/simple_simprim.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VITAL.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/dw02/mul_dw_gen.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/unisim/grspwc2_unisim.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/unisim/grfpw_0_unisim.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/maps/grfpw_net.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/maps/syncram128.vhd
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-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/components.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/package_utility.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/cy7c1354b.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/cy7c1380d.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/HY5PS121621F.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/components.vhd
-	alog -quiet  -work micron ../../../../lib/micron/sdram/mobile_sdr.v
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/sdram/components.vhd
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/sdram/mt48lc16m16a2.vhd
-	alog -quiet  -work micron ../../../../lib/micron/ddr/ddr2.v
-	alog -quiet  -work micron ../../../../lib/micron/ddr/mobile_ddr.v
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/ddr/mt46v16m16.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/debug.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/grtestmod.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/cpu_disas.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.dc b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.dc
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.dc
+++ /dev/null
@@ -1,259 +0,0 @@
-sh mkdir synopsys
-sh mkdir synopsys/grlib 
-define_design_lib grlib -path synopsys/grlib 
-analyze -f VHDL -library grlib ../../lib/grlib/stdlib/version.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/stdlib/config.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/stdlib/stdlib.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/sparc/sparc.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/modgen/multlib.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/modgen/leaves.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/amba.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/devices.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/defmst.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/apbctrl.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/ahbctrl.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-analyze -f VHDL -library grlib ../../lib/grlib/amba/dma2ahb.vhd
-sh mkdir synopsys/unisim 
-define_design_lib unisim -path synopsys/unisim 
-sh mkdir synopsys/synplify 
-define_design_lib synplify -path synopsys/synplify 
-sh mkdir synopsys/techmap 
-define_design_lib techmap -path synopsys/techmap 
-analyze -f VHDL -library techmap ../../lib/techmap/gencomp/gencomp.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/gencomp/netcomp.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/inferred/memory_inferred.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/inferred/mul_inferred.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/allclkgen.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/allddr.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/allmem.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/allpads.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/alltap.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/clkgen.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/clkmux.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/clkand.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_ireg.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/ddr_oreg.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/ddrphy.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram64.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_2p.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram_dp.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncfifo.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/regfile_3p.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/tap.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/techbuf.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/nandtree.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/clkpad_ds.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad_ds.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/iodpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad_ds.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/lvds_combo.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/odpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad_ds.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/toutpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/skew_outpad.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/grspwc_net.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/grspwc2_net.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/grlfpw_net.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/grfpw_net.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/mul_61x61.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/ringosc.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/system_monitor.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/grgates.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/inpad_ddr.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/outpad_ddr.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/iopad_ddr.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram128bw.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram128.vhd
-analyze -f VHDL -library techmap ../../lib/techmap/maps/syncram156bw.vhd
-sh mkdir synopsys/eth 
-define_design_lib eth -path synopsys/eth 
-analyze -f VHDL -library eth ../../lib/eth/comp/ethcomp.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/greth_pkg.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/eth_rstgen.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/eth_ahb_mst.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/greth_tx.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/greth_rx.vhd
-analyze -f VHDL -library eth ../../lib/eth/core/grethc.vhd
-analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gen.vhd
-analyze -f VHDL -library eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-sh mkdir synopsys/gaisler 
-define_design_lib gaisler -path synopsys/gaisler 
-analyze -f VHDL -library gaisler ../../lib/gaisler/arith/arith.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/arith/mul32.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/arith/div32.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libmmu.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libiu.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libcache.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/libproc3.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cachemem.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmulru.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmutw.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/iu3.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/dsu3.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/proc3.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3s.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/irqmp.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/misc.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/rstgen.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/gptimer.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbram.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbmst.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grgpio.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbstat.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/logan.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbps2.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom_package.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/charrom.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/apbvga.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/svgactrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/spictrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/i2cslv.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grsysmon.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/gracectrl.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/grgpreg.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/net/net.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/uart.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/libdcom.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/apbuart.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/uart/ahbuart.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtag.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/greth/grethm.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-analyze -f VHDL -library gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-sh mkdir synopsys/esa 
-define_design_lib esa -path synopsys/esa 
-analyze -f VHDL -library esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-analyze -f VHDL -library esa ../../lib/esa/memoryctrl/mctrl.vhd
-sh mkdir synopsys/fmf 
-define_design_lib fmf -path synopsys/fmf 
-sh mkdir synopsys/spansion 
-define_design_lib spansion -path synopsys/spansion 
-sh mkdir synopsys/gsi 
-define_design_lib gsi -path synopsys/gsi 
-sh mkdir synopsys/lpp 
-define_design_lib lpp -path synopsys/lpp 
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Adder.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/ALU.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MAC.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/REG.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_uart/UART.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-analyze -f VHDL -library lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-sh mkdir synopsys/cypress 
-define_design_lib cypress -path synopsys/cypress 
-sh mkdir synopsys/hynix 
-define_design_lib hynix -path synopsys/hynix 
-sh mkdir synopsys/micron 
-define_design_lib micron -path synopsys/micron 
-sh mkdir synopsys/work 
-define_design_lib work -path synopsys/work 
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ghdl b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ghdl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ghdl
+++ /dev/null
@@ -1,316 +0,0 @@
-	mkdir gnu
-	mkdir gnu/grlib
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/stdlib/version.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/stdlib/config.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/stdlib/stdlib.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/stdlib/stdio.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/stdlib/testlib.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/util/util.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/sparc/sparc.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/sparc/sparc_disas.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/sparc/cpu_disas.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/modgen/multlib.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/modgen/leaves.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/amba.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/devices.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/defmst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/apbctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/ahbctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/dma2ahb.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/dma2ahb_tp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/amba_tp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_pkg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_util.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahb_mst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahb_slv.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahbs.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/grlib --work=grlib -Pgnu -Pgnu/grlib ../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	mkdir gnu/unisim
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/unisim --work=unisim -Pgnu -Pgnu/grlib -Pgnu/unisim ../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/unisim --work=unisim -Pgnu -Pgnu/grlib -Pgnu/unisim ../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/unisim --work=unisim -Pgnu -Pgnu/grlib -Pgnu/unisim ../../lib/tech/unisim/ise/simple_simprim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/unisim --work=unisim -Pgnu -Pgnu/grlib -Pgnu/unisim ../../lib/tech/unisim/ise/unisim_VITAL.vhd
-	mkdir gnu/dw02
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/dw02 --work=dw02 -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 ../../lib/tech/dw02/comp/DW02_components.vhd
-	mkdir gnu/synplify
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/synplify --work=synplify -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify ../../lib/synplify/sim/synplify.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/synplify --work=synplify -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify ../../lib/synplify/sim/synattr.vhd
-	mkdir gnu/techmap
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/gencomp/gencomp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/gencomp/netcomp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/inferred/memory_inferred.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/inferred/mul_inferred.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/memory_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/buffer_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/pads_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/clkgen_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/tap_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/ddr_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/ddr_phy_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/grspwc2_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/grusbhc_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/sysmon_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/mul_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/unisim/grfpw_0_unisim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/allclkgen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/allddr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/allmem.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/allpads.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/alltap.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/clkgen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/clkmux.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/clkand.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/ddr_ireg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/ddr_oreg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/ddrphy.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram64.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram_2p.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram_dp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncfifo.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/regfile_3p.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/tap.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/techbuf.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/nandtree.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/clkpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/clkpad_ds.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/inpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/inpad_ds.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/iodpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/iopad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/iopad_ds.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/lvds_combo.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/odpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/outpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/outpad_ds.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/toutpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/skew_outpad.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/grspwc_net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/grspwc2_net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/grlfpw_net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/grfpw_net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/mul_61x61.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/ringosc.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/system_monitor.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/grgates.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/inpad_ddr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/outpad_ddr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/iopad_ddr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram128bw.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram128.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/techmap --work=techmap -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap ../../lib/techmap/maps/syncram156bw.vhd
-	mkdir gnu/eth
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/comp/ethcomp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/greth_pkg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/eth_rstgen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/eth_ahb_mst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/greth_tx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/greth_rx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/core/grethc.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/wrapper/greth_gen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/eth --work=eth -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-	mkdir gnu/gaisler
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/arith/arith.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/arith/mul32.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/arith/div32.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/leon3.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/libmmu.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/libiu.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/libcache.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/libproc3.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/cachemem.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmulru.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmutw.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmu.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/iu3.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/dsu3.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/proc3.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/leon3s.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/irqmp.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/misc.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/rstgen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/gptimer.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbram.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/grgpio.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/logan.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/apbps2.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/charrom.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/apbvga.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/spictrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/wild.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/net/net.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/uart.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/libdcom.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/apbuart.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/dcom.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/sim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/sram.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/ata_device.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/sram16.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/phy.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/usbsim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/jtag.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/greth/greth.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/greth/grethm.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gaisler --work=gaisler -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	mkdir gnu/esa
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/esa --work=esa -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/esa --work=esa -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa ../../lib/esa/memoryctrl/mctrl.vhd
-	mkdir gnu/fmf
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/utilities/conversions.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/utilities/gen_utils.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/flash/flash.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/flash/s25fl064a.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/flash/m25p80.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/fmf --work=fmf -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf ../../lib/fmf/fifo/idt7202.vhd
-	mkdir gnu/spansion
-	mkdir gnu/gsi
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gsi --work=gsi -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi ../../lib/gsi/ssram/functions.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gsi --work=gsi -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi ../../lib/gsi/ssram/core_burst.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/gsi --work=gsi -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	mkdir gnu/lpp
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/REG.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
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-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/lpp --work=lpp -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	mkdir gnu/cypress
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/cypress --work=cypress -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress ../../lib/cypress/ssram/components.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/cypress --work=cypress -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress ../../lib/cypress/ssram/package_utility.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/cypress --work=cypress -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/cypress --work=cypress -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	mkdir gnu/hynix
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/hynix --work=hynix -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/hynix --work=hynix -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/hynix --work=hynix -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix ../../lib/hynix/ddr2/components.vhd
-	mkdir gnu/micron
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/micron --work=micron -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron ../../lib/micron/sdram/components.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/micron --work=micron -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/micron --work=micron -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron ../../lib/micron/ddr/mt46v16m16.vhd
-	mkdir gnu/work
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/work --work=work -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron -Pgnu/openchip -Pgnu/work ../../lib/work/debug/debug.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/work --work=work -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron -Pgnu/openchip -Pgnu/work ../../lib/work/debug/grtestmod.vhd
-	ghdl -a -fexplicit --ieee=synopsys  --workdir=gnu/work --work=work -Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron -Pgnu/openchip -Pgnu/work ../../lib/work/debug/cpu_disas.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ncsim b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ncsim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.ncsim
+++ /dev/null
@@ -1,320 +0,0 @@
-	mkdir xncsim
-	mkdir xncsim/grlib
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/version.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_pkg.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	mkdir xncsim/unisim
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/unisim_VPKG.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/unisim_VITAL.vhd
-	mkdir xncsim/dw02
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  dw02 ../../lib/tech/dw02/comp/DW02_components.vhd
-	mkdir xncsim/synplify
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  synplify ../../lib/synplify/sim/synplify.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  synplify ../../lib/synplify/sim/synattr.vhd
-	mkdir xncsim/techmap
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/gencomp/gencomp.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grspwc2_unisim.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/sysmon_unisim.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allclkgen.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allpads.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkmux.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncfifo.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/tap.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/techbuf.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iodpad.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iopad_ds.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/lvds_combo.vhd
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-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/toutpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/skew_outpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grspwc_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grspwc2_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grlfpw_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grfpw_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/mul_61x61.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/ringosc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/system_monitor.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grgates.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/inpad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/outpad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iopad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram128bw.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram128.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram156bw.vhd
-	mkdir xncsim/eth
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/comp/ethcomp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/eth_rstgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/eth_ahb_mst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_tx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_rx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/grethc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/wrapper/greth_gen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-	mkdir xncsim/gaisler
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/arith.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/mul32.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/div32.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libmmu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libiu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libcache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libproc3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/cachemem.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmulru.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutw.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/iu3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/dsu3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/proc3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3s.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/irqmp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/misc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/rstgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/gptimer.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grgpio.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/logan.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/apbps2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/charrom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/apbvga.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/spictrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/wild.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/net/net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/libdcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/apbuart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/dcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	ncvlog -nowarn DLCPTH -nocopyright  -work gaisler ../../lib/gaisler/sim/i2c_slave_model.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/ata_device.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sram16.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/phy.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/usbsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/greth.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/grethm.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	mkdir xncsim/esa
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  esa ../../lib/esa/memoryctrl/mctrl.vhd
-	mkdir xncsim/fmf
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/utilities/conversions.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/utilities/gen_utils.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/flash.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/s25fl064a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/m25p80.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/fifo/idt7202.vhd
-	mkdir xncsim/spansion
-	mkdir xncsim/gsi
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/functions.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/core_burst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	mkdir xncsim/lpp
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/UART.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	mkdir xncsim/cypress
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/components.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/package_utility.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	mkdir xncsim/hynix
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/components.vhd
-	mkdir xncsim/micron
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/sdram/mobile_sdr.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/sdram/components.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/ddr/ddr2.v
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/ddr/mobile_ddr.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/ddr/mt46v16m16.vhd
-	mkdir xncsim/work
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/debug.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/grtestmod.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/cpu_disas.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.rc b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.rc
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.rc
+++ /dev/null
@@ -1,229 +0,0 @@
-set_attribute input_pragma_keyword "cadence synopsys get2chip g2c fast ambit pragma"
-read_hdl -vhdl -lib grlib ../../lib/grlib/stdlib/version.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/stdlib/config.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/stdlib/stdlib.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/sparc/sparc.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/modgen/multlib.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/modgen/leaves.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/amba.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/devices.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/defmst.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/apbctrl.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/ahbctrl.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-read_hdl -vhdl -lib grlib ../../lib/grlib/amba/dma2ahb.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/gencomp/gencomp.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/gencomp/netcomp.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/inferred/memory_inferred.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/inferred/mul_inferred.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/allclkgen.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/allddr.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/allmem.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/allpads.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/alltap.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/clkgen.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/clkmux.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/clkand.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/ddr_ireg.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/ddr_oreg.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/ddrphy.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram64.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram_2p.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram_dp.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncfifo.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/regfile_3p.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/tap.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/techbuf.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/nandtree.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/clkpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/clkpad_ds.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/inpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/inpad_ds.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/iodpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/iopad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/iopad_ds.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/lvds_combo.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/odpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/outpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/outpad_ds.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/toutpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/skew_outpad.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/grspwc_net.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/grspwc2_net.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/grlfpw_net.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/grfpw_net.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/mul_61x61.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/ringosc.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/system_monitor.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/grgates.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/inpad_ddr.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/outpad_ddr.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/iopad_ddr.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram128bw.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram128.vhd
-read_hdl -vhdl -lib techmap ../../lib/techmap/maps/syncram156bw.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/comp/ethcomp.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/greth_pkg.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/eth_rstgen.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/eth_ahb_mst.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/greth_tx.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/greth_rx.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/core/grethc.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/wrapper/greth_gen.vhd
-read_hdl -vhdl -lib eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/arith/arith.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/arith/mul32.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/arith/div32.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/leon3.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/libmmu.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/libiu.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/libcache.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/libproc3.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/cachemem.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmulru.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmutw.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmu.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/iu3.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/dsu3.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/proc3.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/leon3s.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/irqmp.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/misc.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/rstgen.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/gptimer.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbram.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbmst.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/grgpio.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbstat.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/logan.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/apbps2.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/charrom_package.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/charrom.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/apbvga.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/svgactrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/spictrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/i2cslv.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/wild.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/grsysmon.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/gracectrl.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/grgpreg.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/net/net.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/uart.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/libdcom.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/apbuart.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/dcom.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/uart/ahbuart.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/jtag/jtag.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/greth/greth.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/greth/grethm.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-read_hdl -vhdl -lib gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
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diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.son b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.son
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.son
+++ /dev/null
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diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.synp b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.synp
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.synp
+++ /dev/null
@@ -1,240 +0,0 @@
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diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.vsim b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.vsim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.vsim
+++ /dev/null
@@ -1,303 +0,0 @@
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-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/misc.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/rstgen.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/gptimer.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grgpio.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/logan.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/apbps2.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/charrom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/apbvga.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/spictrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/wild.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/net/net.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/uart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/libdcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/apbuart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/dcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	vlog -quiet  -work gaisler ../../lib/gaisler/sim/i2c_slave_model.v
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/ata_device.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sram16.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/phy.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/usbsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtag.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/greth.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/grethm.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	vcom -quiet  -93  -work esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	vcom -quiet  -93  -work esa ../../lib/esa/memoryctrl/mctrl.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/utilities/conversions.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/utilities/gen_utils.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/flash.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/s25fl064a.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/m25p80.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/fifo/idt7202.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/functions.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/core_burst.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/UART.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/components.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/package_utility.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/components.vhd
-	vlog -quiet  -work micron ../../lib/micron/sdram/mobile_sdr.v
-	vcom -quiet  -93  -work micron ../../lib/micron/sdram/components.vhd
-	vcom -quiet  -93  -work micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	vlog -quiet  -work micron ../../lib/micron/ddr/ddr2.v
-	vlog -quiet  -work micron ../../lib/micron/ddr/mobile_ddr.v
-	vcom -quiet  -93  -work micron ../../lib/micron/ddr/mt46v16m16.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/debug.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/grtestmod.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/cpu_disas.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.xst b/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.xst
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/compile.xst
+++ /dev/null
@@ -1,240 +0,0 @@
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/stdlib/version.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/stdlib/config.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/stdlib/stdlib.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/sparc/sparc.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/modgen/multlib.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/modgen/leaves.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/amba.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/devices.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/defmst.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/apbctrl.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/ahbctrl.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/dma2ahb_pkg.vhd
-elaborate -ifmt vhdl -work_lib grlib -ifn ../../lib/grlib/amba/dma2ahb.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/gencomp/gencomp.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/gencomp/netcomp.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/inferred/memory_inferred.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/inferred/ddr_inferred.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/inferred/mul_inferred.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/memory_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/buffer_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/pads_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/clkgen_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/tap_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/ddr_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/ddr_phy_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/grspwc_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/grspwc2_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/grusbhc_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/sysmon_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/unisim/mul_unisim.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/allclkgen.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/allddr.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/allmem.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/allpads.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/alltap.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/clkgen.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/clkmux.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/clkand.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/ddr_ireg.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/ddr_oreg.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/ddrphy.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram64.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram_2p.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram_dp.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncfifo.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/regfile_3p.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/tap.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/techbuf.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/nandtree.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/clkpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/clkpad_ds.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/inpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/inpad_ds.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/iodpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/iopad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/iopad_ds.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/lvds_combo.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/odpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/outpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/outpad_ds.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/toutpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/skew_outpad.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/grspwc_net.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/grspwc2_net.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/grlfpw_net.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/grfpw_net.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/mul_61x61.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/cpu_disas_net.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/ringosc.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/system_monitor.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/grgates.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/inpad_ddr.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/outpad_ddr.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/iopad_ddr.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram128bw.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram128.vhd
-elaborate -ifmt vhdl -work_lib techmap -ifn ../../lib/techmap/maps/syncram156bw.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/comp/ethcomp.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/greth_pkg.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/eth_rstgen.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/eth_ahb_mst.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/greth_tx.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/greth_rx.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/core/grethc.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/wrapper/greth_gen.vhd
-elaborate -ifmt vhdl -work_lib eth -ifn ../../lib/eth/wrapper/greth_gbit_gen.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/arith/arith.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/arith/mul32.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/arith/div32.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/memctrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/sdctrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/sdctrl64.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/sdmctrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/srctrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/memctrl/spimctrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/leon3.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmuconfig.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmuiface.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/libmmu.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/libiu.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/libcache.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/libproc3.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/cachemem.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmu_icache.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmu_dcache.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmu_acache.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmutlbcam.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmulrue.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmulru.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmutlb.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmutw.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmu.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mmu_cache.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/cpu_disasx.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/iu3.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/grfpwx.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/mfpwx.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/grlfpwx.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/tbufmem.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/dsu3x.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/dsu3.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/proc3.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/leon3s.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/leon3cg.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/irqmp.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/grfpwxsh.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/grfpushwx.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/leon3/leon3sh.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/misc.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/rstgen.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/gptimer.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbram.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbdpram.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbtrace.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbtrace_mb.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbmst.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/grgpio.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbstat.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/logan.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/apbps2.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/charrom_package.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/charrom.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/apbvga.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/svgactrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/i2cmst_gen.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/spictrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/i2cslv.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/wild.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/wild2ahb.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/grsysmon.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/gracectrl.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/grgpreg.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahbmst2.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/misc/ahb_mst_iface.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/net/net.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/uart.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/libdcom.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/apbuart.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/dcom.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/dcom_uart.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/uart/ahbuart.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/jtag/jtag.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/jtag/libjtagcom.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/jtag/jtagcom.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/jtag/ahbjtag.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/greth/ethernet_mac.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/greth/greth.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/greth/greth_gbit.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/greth/grethm.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr_phy.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddrsp16a.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddrsp32a.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddrsp64a.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddrspa.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr2spa.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr2buf.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr2spax.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-elaborate -ifmt vhdl -work_lib gaisler -ifn ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-elaborate -ifmt vhdl -work_lib esa -ifn ../../lib/esa/memoryctrl/memoryctrl.vhd
-elaborate -ifmt vhdl -work_lib esa -ifn ../../lib/esa/memoryctrl/mctrl.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/Adder.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/ALU.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/Clk_divider.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/general_purpose.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MAC_REG.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MAC.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/Multiplier.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/MUX2.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/REG.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./general_purpose/Shifter.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_uart/APB_UART.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_uart/BaudGen.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_uart/UART.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-elaborate -ifmt vhdl -work_lib lpp -ifn ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/ghdl.path b/designs/leon3-APB_LCD-digilent-xc3s1600e/ghdl.path
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/ghdl.path
+++ /dev/null
@@ -1,1 +0,0 @@
--Pgnu -Pgnu/grlib -Pgnu/unisim -Pgnu/dw02 -Pgnu/synplify -Pgnu/techmap -Pgnu/spw -Pgnu/eth -Pgnu/opencores -Pgnu/ihp -Pgnu/core1553bbc -Pgnu/core1553brt -Pgnu/core1553brm -Pgnu/corePCIF -Pgnu/gr1553 -Pgnu/gaisler -Pgnu/esa -Pgnu/#nasa -Pgnu/gleichmann -Pgnu/fmf -Pgnu/spansion -Pgnu/gsi -Pgnu/lpp -Pgnu/cypress -Pgnu/hynix -Pgnu/micron -Pgnu/openchip -Pgnu/work
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/hdl.var b/designs/leon3-APB_LCD-digilent-xc3s1600e/hdl.var
deleted file mode 100644
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.projectmgr b/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.projectmgr
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.projectmgr
+++ /dev/null
@@ -1,395 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<!--This is an ISE project configuration file.-->
-<!--It holds project specific layout data for the projectmgr plugin.-->
-<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
-<Project version="2" owner="projectmgr" name="leon3mp" >
-   <!--This is an ISE project configuration file.-->
-   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
-      <ClosedNodes>
-         <ClosedNodesVersion>2</ClosedNodesVersion>
-         <ClosedNode>/Unassigned User Library Modules</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/ADD32 - A</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/AMBA_LCD_16x2_DRIVER - Behavioral</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/APB_CNA - ar_APB_CNA</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/APB_IIR_CEL - AR_APB_IIR_CEL/filter - IIR_CEL_FILTER - ar_IIR_CEL_FILTER/CTRLR - IIR_CEL_CTRLR - ar_IIR_CEL_CTRLR</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/APB_UART - ar_APB_UART</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/FILTER - ar_FILTER</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/FILTER_RAM_CTRLR - ar_FILTER_RAM_CTRLR</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/LCD_2x16_DRIVER - Behavioral</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/Wild2AHB - RTL</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/ahbdpram - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/ahbjtag_bsd - struct</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/ahbtrace - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/apbvga - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/clkmux - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/clkpad_ds - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/ddr2spa - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/greth_gbit_gen - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/greth_gen - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/grfpushwx - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/grspwc2_net - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/grspwc_net - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/grsysmon - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/grusbhc_unisim - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/i2cmst_gen - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/inpad_ddrv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/inpad_dsv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iodpadv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopad_ddrv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopad_ddrvv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopad_dsv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopad_dsvv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopadv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/iopadvv - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/leon3cg - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/leon3sh - rtl</ClosedNode>
-         <ClosedNode>/Unassigned User Library Modules/logan - rtl</ClosedNode>
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diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.xreport b/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.xreport
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/iseconfig/leon3mp.xreport
+++ /dev/null
@@ -1,217 +0,0 @@
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-    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
-    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
-    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
-    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
-    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
-    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
-    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
-    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
-   </view>
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.srr" label="Synplify Report" />
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.prec_log" label="Precision Report" />
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="leon3mp.bld" label="Translation Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Command Line" target="Command Line:" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
-   </view>
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="leon3mp_map.mrp" label="Map Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
-    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
-    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
-    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
-    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
-    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
-    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
-    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
-    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
-    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
-    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
-    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
-    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="leon3mp.par" label="Place and Route Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
-    <toc-item title="Router Information" target="Starting Router" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Clock Report" target="Generating Clock Report" />
-    <toc-item title="Timing Results" target="Timing Score:" />
-    <toc-item title="Final Summary" target="Peak Memory Usage:" />
-   </view>
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="leon3mp.twr" label="Post-PAR Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.rpt" label="CPLD Fitter Report (Text)" >
-    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
-    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
-    <toc-item title="Pin Resources" target="** Pin Resources **" />
-    <toc-item title="Global Resources" target="** Global Control Resources **" />
-   </view>
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="leon3mp.tim" label="CPLD Timing Report (Text)" >
-    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
-    <toc-item title="Performance Summary" target="Performance Summary:" />
-   </view>
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="leon3mp.pwr" label="Power Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Power summary" target="Power summary" />
-    <toc-item title="Thermal summary" target="Thermal summary" />
-   </view>
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="leon3mp.bgn" label="Bitgen Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
-    <toc-item title="Final Summary" target="DRC detected" />
-   </view>
-  </viewgroup>
-  <viewgroup label="Secondary Reports" >
-   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/leon3mp_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/leon3mp_translate.nlf" label="Post-Translate Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp_map.map" label="Map Log File" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Design Information" target="Design Information" />
-    <toc-item title="Design Summary" target="Design Summary" />
-   </view>
-   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.twr" label="Post-Map Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/leon3mp_map.nlf" label="Post-Map Simulation Model Report" />
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_map.psr" label="Physical Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="leon3mp_pad.txt" label="Pad Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="leon3mp.unroutes" label="Unroutes Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp_preroute.tsi" label="Post-Map Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.grf" label="Guide Results Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.dly" label="Asynchronous Delay Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.clk_rgn" label="Clock Region Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.tsi" label="Post-Place and Route Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/leon3mp_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="leon3mp_sta.nlf" label="Primetime Netlist Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="leon3mp.ibs" label="IBIS Model" >
-    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
-    <toc-item title="Component" target="Component " />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lck" label="Back-annotate Pin Report" >
-    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
-    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="leon3mp.lpc" label="Locked Pin Constraints" >
-    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
-    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
-   </view>
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/leon3mp_timesim.nlf" label="Post-Fit Simulation Model Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
-  </viewgroup>
- </body>
-</report-views>
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.qpf b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.qpf
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.qpf
+++ /dev/null
@@ -1,8 +0,0 @@
-#QUARTUS_VERSION = "4.1"
-#DATE = "17:39:37  December 03, 2004"
-
-
-# Revisions
-
-
-PROJECT_REVISION = leon3mp
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.rc b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.rc
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.rc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_attribute input_pragma_keyword "cadence synopsys get2chip g2c fast ambit pragma"
-include compile.rc
-
-read_hdl -vhdl -lib work config.vhd
-read_hdl -vhdl -lib work ahbrom.vhd
-read_hdl -vhdl -lib work leon3mp.vhd
-elaborate leon3mp
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xst b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xst
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xst
+++ /dev/null
@@ -1,56 +0,0 @@
-set -tmpdir "xst/projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn leon3mp.prj
--uc leon3mp.xcf
--ifmt mixed
--ofn leon3mp
--ofmt NGC
--p xc3s1600e-4-fg320
--top leon3mp
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter ()
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--verilog2001 YES
--fsm_extract NO
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract Yes
--resource_sharing YES
--async_to_sync NO
--mult_style Auto
--iobuf YES
--max_fanout 500
--bufg 24
--register_duplication YES
--register_balancing No
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Yes
--use_sync_set Yes
--use_sync_reset Yes
--iob True
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer.tcl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer.tcl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer.tcl
+++ /dev/null
@@ -1,33 +0,0 @@
-new_design -name "leon3mp" -family "Spartan3E" 
-set_device -die "xc3s1600e" -package " " -speed "-4" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "" -voltrange "" 
-if {[file exist leon3mp.pdc]} {
-import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf} -format "pdc" -abort_on_error "no" {leon3mp.pdc}
-} else {
-import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf}
-}
-compile -combine_register 1
-if {[file exist ]} {
-   import_aux -format "pdc" -abort_on_error "no" {}
-   pin_commit
-} else {
-   puts "WARNING: No PDC file imported."
-}
-if {[file exist ]} {
-   import_aux -format "sdc" -merge_timing "no" {}
-} else {
-   puts "WARNING: No SDC file imported."
-}
-save_design {leon3mp.adb}
-report -type status {./actel/report_status_pre.log}
-layout -timing_driven -incremental "OFF"
-save_design {leon3mp.adb}
-backannotate -dir {./actel} -name "leon3mp" -format "SDF" -language "VHDL93" -netlist
-report -type "timer" -analysis "max" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no"  {./actel/report_timer_max.txt}
-report -type "timer" -analysis "min" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no"  {./actel/report_timer_min.txt}
-report -type "pin" -listby "name" {./actel/report_pin_name.log}
-report -type "pin" -listby "number" {./actel/report_pin_number.log}
-report -type "datasheet" {./actel/report_datasheet.txt}
-export -format "pdb" -feature "prog_fpga" -io_state "Tri-State" {./actel/leon3mp.pdb}
-export -format log -diagnostic {./actel/report_log.log}
-report -type status {./actel/report_status_post.log}
-save_design {leon3mp.adb}
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer_act.tcl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer_act.tcl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_designer_act.tcl
+++ /dev/null
@@ -1,8 +0,0 @@
-new_design -name "leon3mp" -family "Spartan3E" 
-set_device -die "xc3s1600e" -package " " -speed "-4" -voltage "1.5" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "" -voltrange "" 
-if {[file exist leon3mp.pdc]} {
-import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf} -format "pdc" -abort_on_error "no" {leon3mp.pdc}
-} else {
-import_source -format "edif" -edif_flavor "GENERIC"  -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf}
-}
-save_design {leon3mp.adb}
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_ise.tcl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_ise.tcl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_ise.tcl
+++ /dev/null
@@ -1,521 +0,0 @@
-project new leon3mp.ise
-project set family "Spartan3E"
-project set device xc3s1600e
-project set speed -4
-project set package fg320
-puts "Adding files to project"
-lib_vhdl new grlib
-xfile add "../../lib/grlib/stdlib/version.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/stdlib/version.vhd"
-xfile add "../../lib/grlib/stdlib/config.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/stdlib/config.vhd"
-xfile add "../../lib/grlib/stdlib/stdlib.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/stdlib/stdlib.vhd"
-xfile add "../../lib/grlib/sparc/sparc.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/sparc/sparc.vhd"
-xfile add "../../lib/grlib/modgen/multlib.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/modgen/multlib.vhd"
-xfile add "../../lib/grlib/modgen/leaves.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/modgen/leaves.vhd"
-xfile add "../../lib/grlib/amba/amba.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/amba.vhd"
-xfile add "../../lib/grlib/amba/devices.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/devices.vhd"
-xfile add "../../lib/grlib/amba/defmst.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/defmst.vhd"
-xfile add "../../lib/grlib/amba/apbctrl.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/apbctrl.vhd"
-xfile add "../../lib/grlib/amba/ahbctrl.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/ahbctrl.vhd"
-xfile add "../../lib/grlib/amba/dma2ahb_pkg.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/dma2ahb_pkg.vhd"
-xfile add "../../lib/grlib/amba/dma2ahb.vhd" -lib_vhdl grlib
-puts "../../lib/grlib/amba/dma2ahb.vhd"
-lib_vhdl new unisim
-lib_vhdl new synplify
-lib_vhdl new techmap
-xfile add "../../lib/techmap/gencomp/gencomp.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/gencomp/gencomp.vhd"
-xfile add "../../lib/techmap/gencomp/netcomp.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/gencomp/netcomp.vhd"
-xfile add "../../lib/techmap/inferred/memory_inferred.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/inferred/memory_inferred.vhd"
-xfile add "../../lib/techmap/inferred/ddr_inferred.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/inferred/ddr_inferred.vhd"
-xfile add "../../lib/techmap/inferred/mul_inferred.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/inferred/mul_inferred.vhd"
-xfile add "../../lib/techmap/inferred/ddr_phy_inferred.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/inferred/ddr_phy_inferred.vhd"
-xfile add "../../lib/techmap/unisim/memory_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/memory_unisim.vhd"
-xfile add "../../lib/techmap/unisim/buffer_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/buffer_unisim.vhd"
-xfile add "../../lib/techmap/unisim/pads_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/pads_unisim.vhd"
-xfile add "../../lib/techmap/unisim/clkgen_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/clkgen_unisim.vhd"
-xfile add "../../lib/techmap/unisim/tap_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/tap_unisim.vhd"
-xfile add "../../lib/techmap/unisim/ddr_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/ddr_unisim.vhd"
-xfile add "../../lib/techmap/unisim/ddr_phy_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/ddr_phy_unisim.vhd"
-xfile add "../../lib/techmap/unisim/grspwc_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/grspwc_unisim.vhd"
-xfile add "../../lib/techmap/unisim/grspwc2_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/grspwc2_unisim.vhd"
-xfile add "../../lib/techmap/unisim/grusbhc_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/grusbhc_unisim.vhd"
-xfile add "../../lib/techmap/unisim/ssrctrl_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/ssrctrl_unisim.vhd"
-xfile add "../../lib/techmap/unisim/sysmon_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/sysmon_unisim.vhd"
-xfile add "../../lib/techmap/unisim/mul_unisim.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/unisim/mul_unisim.vhd"
-xfile add "../../lib/techmap/maps/allclkgen.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/allclkgen.vhd"
-xfile add "../../lib/techmap/maps/allddr.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/allddr.vhd"
-xfile add "../../lib/techmap/maps/allmem.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/allmem.vhd"
-xfile add "../../lib/techmap/maps/allpads.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/allpads.vhd"
-xfile add "../../lib/techmap/maps/alltap.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/alltap.vhd"
-xfile add "../../lib/techmap/maps/clkgen.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/clkgen.vhd"
-xfile add "../../lib/techmap/maps/clkmux.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/clkmux.vhd"
-xfile add "../../lib/techmap/maps/clkand.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/clkand.vhd"
-xfile add "../../lib/techmap/maps/ddr_ireg.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/ddr_ireg.vhd"
-xfile add "../../lib/techmap/maps/ddr_oreg.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/ddr_oreg.vhd"
-xfile add "../../lib/techmap/maps/ddrphy.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/ddrphy.vhd"
-xfile add "../../lib/techmap/maps/syncram.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram.vhd"
-xfile add "../../lib/techmap/maps/syncram64.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram64.vhd"
-xfile add "../../lib/techmap/maps/syncram_2p.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram_2p.vhd"
-xfile add "../../lib/techmap/maps/syncram_dp.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram_dp.vhd"
-xfile add "../../lib/techmap/maps/syncfifo.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncfifo.vhd"
-xfile add "../../lib/techmap/maps/regfile_3p.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/regfile_3p.vhd"
-xfile add "../../lib/techmap/maps/tap.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/tap.vhd"
-xfile add "../../lib/techmap/maps/techbuf.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/techbuf.vhd"
-xfile add "../../lib/techmap/maps/nandtree.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/nandtree.vhd"
-xfile add "../../lib/techmap/maps/clkpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/clkpad.vhd"
-xfile add "../../lib/techmap/maps/clkpad_ds.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/clkpad_ds.vhd"
-xfile add "../../lib/techmap/maps/inpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/inpad.vhd"
-xfile add "../../lib/techmap/maps/inpad_ds.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/inpad_ds.vhd"
-xfile add "../../lib/techmap/maps/iodpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/iodpad.vhd"
-xfile add "../../lib/techmap/maps/iopad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/iopad.vhd"
-xfile add "../../lib/techmap/maps/iopad_ds.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/iopad_ds.vhd"
-xfile add "../../lib/techmap/maps/lvds_combo.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/lvds_combo.vhd"
-xfile add "../../lib/techmap/maps/odpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/odpad.vhd"
-xfile add "../../lib/techmap/maps/outpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/outpad.vhd"
-xfile add "../../lib/techmap/maps/outpad_ds.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/outpad_ds.vhd"
-xfile add "../../lib/techmap/maps/toutpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/toutpad.vhd"
-xfile add "../../lib/techmap/maps/skew_outpad.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/skew_outpad.vhd"
-xfile add "../../lib/techmap/maps/grspwc_net.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/grspwc_net.vhd"
-xfile add "../../lib/techmap/maps/grspwc2_net.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/grspwc2_net.vhd"
-xfile add "../../lib/techmap/maps/grlfpw_net.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/grlfpw_net.vhd"
-xfile add "../../lib/techmap/maps/grfpw_net.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/grfpw_net.vhd"
-xfile add "../../lib/techmap/maps/mul_61x61.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/mul_61x61.vhd"
-xfile add "../../lib/techmap/maps/cpu_disas_net.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/cpu_disas_net.vhd"
-xfile add "../../lib/techmap/maps/ringosc.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/ringosc.vhd"
-xfile add "../../lib/techmap/maps/system_monitor.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/system_monitor.vhd"
-xfile add "../../lib/techmap/maps/grgates.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/grgates.vhd"
-xfile add "../../lib/techmap/maps/inpad_ddr.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/inpad_ddr.vhd"
-xfile add "../../lib/techmap/maps/outpad_ddr.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/outpad_ddr.vhd"
-xfile add "../../lib/techmap/maps/iopad_ddr.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/iopad_ddr.vhd"
-xfile add "../../lib/techmap/maps/syncram128bw.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram128bw.vhd"
-xfile add "../../lib/techmap/maps/syncram128.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram128.vhd"
-xfile add "../../lib/techmap/maps/syncram156bw.vhd" -lib_vhdl techmap
-puts "../../lib/techmap/maps/syncram156bw.vhd"
-lib_vhdl new eth
-xfile add "../../lib/eth/comp/ethcomp.vhd" -lib_vhdl eth
-puts "../../lib/eth/comp/ethcomp.vhd"
-xfile add "../../lib/eth/core/greth_pkg.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/greth_pkg.vhd"
-xfile add "../../lib/eth/core/eth_rstgen.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/eth_rstgen.vhd"
-xfile add "../../lib/eth/core/eth_ahb_mst.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/eth_ahb_mst.vhd"
-xfile add "../../lib/eth/core/greth_tx.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/greth_tx.vhd"
-xfile add "../../lib/eth/core/greth_rx.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/greth_rx.vhd"
-xfile add "../../lib/eth/core/grethc.vhd" -lib_vhdl eth
-puts "../../lib/eth/core/grethc.vhd"
-xfile add "../../lib/eth/wrapper/greth_gen.vhd" -lib_vhdl eth
-puts "../../lib/eth/wrapper/greth_gen.vhd"
-xfile add "../../lib/eth/wrapper/greth_gbit_gen.vhd" -lib_vhdl eth
-puts "../../lib/eth/wrapper/greth_gbit_gen.vhd"
-lib_vhdl new gaisler
-xfile add "../../lib/gaisler/arith/arith.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/arith/arith.vhd"
-xfile add "../../lib/gaisler/arith/mul32.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/arith/mul32.vhd"
-xfile add "../../lib/gaisler/arith/div32.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/arith/div32.vhd"
-xfile add "../../lib/gaisler/memctrl/memctrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/memctrl.vhd"
-xfile add "../../lib/gaisler/memctrl/sdctrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/sdctrl.vhd"
-xfile add "../../lib/gaisler/memctrl/sdctrl64.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/sdctrl64.vhd"
-xfile add "../../lib/gaisler/memctrl/sdmctrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/sdmctrl.vhd"
-xfile add "../../lib/gaisler/memctrl/srctrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/srctrl.vhd"
-xfile add "../../lib/gaisler/memctrl/spimctrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/memctrl/spimctrl.vhd"
-xfile add "../../lib/gaisler/leon3/leon3.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/leon3.vhd"
-xfile add "../../lib/gaisler/leon3/mmuconfig.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmuconfig.vhd"
-xfile add "../../lib/gaisler/leon3/mmuiface.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmuiface.vhd"
-xfile add "../../lib/gaisler/leon3/libmmu.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/libmmu.vhd"
-xfile add "../../lib/gaisler/leon3/libiu.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/libiu.vhd"
-xfile add "../../lib/gaisler/leon3/libcache.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/libcache.vhd"
-xfile add "../../lib/gaisler/leon3/libproc3.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/libproc3.vhd"
-xfile add "../../lib/gaisler/leon3/cachemem.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/cachemem.vhd"
-xfile add "../../lib/gaisler/leon3/mmu_icache.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmu_icache.vhd"
-xfile add "../../lib/gaisler/leon3/mmu_dcache.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmu_dcache.vhd"
-xfile add "../../lib/gaisler/leon3/mmu_acache.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmu_acache.vhd"
-xfile add "../../lib/gaisler/leon3/mmutlbcam.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmutlbcam.vhd"
-xfile add "../../lib/gaisler/leon3/mmulrue.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmulrue.vhd"
-xfile add "../../lib/gaisler/leon3/mmulru.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmulru.vhd"
-xfile add "../../lib/gaisler/leon3/mmutlb.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmutlb.vhd"
-xfile add "../../lib/gaisler/leon3/mmutw.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmutw.vhd"
-xfile add "../../lib/gaisler/leon3/mmu.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmu.vhd"
-xfile add "../../lib/gaisler/leon3/mmu_cache.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mmu_cache.vhd"
-xfile add "../../lib/gaisler/leon3/cpu_disasx.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/cpu_disasx.vhd"
-xfile add "../../lib/gaisler/leon3/iu3.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/iu3.vhd"
-xfile add "../../lib/gaisler/leon3/grfpwx.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/grfpwx.vhd"
-xfile add "../../lib/gaisler/leon3/mfpwx.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/mfpwx.vhd"
-xfile add "../../lib/gaisler/leon3/grlfpwx.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/grlfpwx.vhd"
-xfile add "../../lib/gaisler/leon3/tbufmem.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/tbufmem.vhd"
-xfile add "../../lib/gaisler/leon3/dsu3x.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/dsu3x.vhd"
-xfile add "../../lib/gaisler/leon3/dsu3.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/dsu3.vhd"
-xfile add "../../lib/gaisler/leon3/proc3.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/proc3.vhd"
-xfile add "../../lib/gaisler/leon3/leon3s.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/leon3s.vhd"
-xfile add "../../lib/gaisler/leon3/leon3cg.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/leon3cg.vhd"
-xfile add "../../lib/gaisler/leon3/irqmp.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/irqmp.vhd"
-xfile add "../../lib/gaisler/leon3/grfpwxsh.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/grfpwxsh.vhd"
-xfile add "../../lib/gaisler/leon3/grfpushwx.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/grfpushwx.vhd"
-xfile add "../../lib/gaisler/leon3/leon3sh.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/leon3/leon3sh.vhd"
-xfile add "../../lib/gaisler/misc/misc.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/misc.vhd"
-xfile add "../../lib/gaisler/misc/rstgen.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/rstgen.vhd"
-xfile add "../../lib/gaisler/misc/gptimer.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/gptimer.vhd"
-xfile add "../../lib/gaisler/misc/ahbram.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbram.vhd"
-xfile add "../../lib/gaisler/misc/ahbdpram.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbdpram.vhd"
-xfile add "../../lib/gaisler/misc/ahbtrace.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbtrace.vhd"
-xfile add "../../lib/gaisler/misc/ahbtrace_mb.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbtrace_mb.vhd"
-xfile add "../../lib/gaisler/misc/ahbmst.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbmst.vhd"
-xfile add "../../lib/gaisler/misc/grgpio.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/grgpio.vhd"
-xfile add "../../lib/gaisler/misc/ahbstat.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbstat.vhd"
-xfile add "../../lib/gaisler/misc/logan.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/logan.vhd"
-xfile add "../../lib/gaisler/misc/apbps2.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/apbps2.vhd"
-xfile add "../../lib/gaisler/misc/charrom_package.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/charrom_package.vhd"
-xfile add "../../lib/gaisler/misc/charrom.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/charrom.vhd"
-xfile add "../../lib/gaisler/misc/apbvga.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/apbvga.vhd"
-xfile add "../../lib/gaisler/misc/svgactrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/svgactrl.vhd"
-xfile add "../../lib/gaisler/misc/i2cmst_gen.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/i2cmst_gen.vhd"
-xfile add "../../lib/gaisler/misc/spictrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/spictrl.vhd"
-xfile add "../../lib/gaisler/misc/i2cslv.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/i2cslv.vhd"
-xfile add "../../lib/gaisler/misc/wild.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/wild.vhd"
-xfile add "../../lib/gaisler/misc/wild2ahb.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/wild2ahb.vhd"
-xfile add "../../lib/gaisler/misc/grsysmon.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/grsysmon.vhd"
-xfile add "../../lib/gaisler/misc/gracectrl.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/gracectrl.vhd"
-xfile add "../../lib/gaisler/misc/grgpreg.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/grgpreg.vhd"
-xfile add "../../lib/gaisler/misc/ahbmst2.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahbmst2.vhd"
-xfile add "../../lib/gaisler/misc/ahb_mst_iface.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/misc/ahb_mst_iface.vhd"
-xfile add "../../lib/gaisler/net/net.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/net/net.vhd"
-xfile add "../../lib/gaisler/uart/uart.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/uart.vhd"
-xfile add "../../lib/gaisler/uart/libdcom.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/libdcom.vhd"
-xfile add "../../lib/gaisler/uart/apbuart.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/apbuart.vhd"
-xfile add "../../lib/gaisler/uart/dcom.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/dcom.vhd"
-xfile add "../../lib/gaisler/uart/dcom_uart.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/dcom_uart.vhd"
-xfile add "../../lib/gaisler/uart/ahbuart.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/uart/ahbuart.vhd"
-xfile add "../../lib/gaisler/jtag/jtag.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/jtag/jtag.vhd"
-xfile add "../../lib/gaisler/jtag/libjtagcom.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/jtag/libjtagcom.vhd"
-xfile add "../../lib/gaisler/jtag/jtagcom.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/jtag/jtagcom.vhd"
-xfile add "../../lib/gaisler/jtag/ahbjtag.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/jtag/ahbjtag.vhd"
-xfile add "../../lib/gaisler/jtag/ahbjtag_bsd.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/jtag/ahbjtag_bsd.vhd"
-xfile add "../../lib/gaisler/greth/ethernet_mac.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/greth/ethernet_mac.vhd"
-xfile add "../../lib/gaisler/greth/greth.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/greth/greth.vhd"
-xfile add "../../lib/gaisler/greth/greth_gbit.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/greth/greth_gbit.vhd"
-xfile add "../../lib/gaisler/greth/grethm.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/greth/grethm.vhd"
-xfile add "../../lib/gaisler/ddr/ddr_phy.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr_phy.vhd"
-xfile add "../../lib/gaisler/ddr/ddrsp16a.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddrsp16a.vhd"
-xfile add "../../lib/gaisler/ddr/ddrsp32a.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddrsp32a.vhd"
-xfile add "../../lib/gaisler/ddr/ddrsp64a.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddrsp64a.vhd"
-xfile add "../../lib/gaisler/ddr/ddrspa.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddrspa.vhd"
-xfile add "../../lib/gaisler/ddr/ddr2spa.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr2spa.vhd"
-xfile add "../../lib/gaisler/ddr/ddr2buf.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr2buf.vhd"
-xfile add "../../lib/gaisler/ddr/ddr2spax.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr2spax.vhd"
-xfile add "../../lib/gaisler/ddr/ddr2spax_ahb.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr2spax_ahb.vhd"
-xfile add "../../lib/gaisler/ddr/ddr2spax_ddr.vhd" -lib_vhdl gaisler
-puts "../../lib/gaisler/ddr/ddr2spax_ddr.vhd"
-lib_vhdl new esa
-xfile add "../../lib/esa/memoryctrl/memoryctrl.vhd" -lib_vhdl esa
-puts "../../lib/esa/memoryctrl/memoryctrl.vhd"
-xfile add "../../lib/esa/memoryctrl/mctrl.vhd" -lib_vhdl esa
-puts "../../lib/esa/memoryctrl/mctrl.vhd"
-lib_vhdl new fmf
-lib_vhdl new spansion
-lib_vhdl new gsi
-lib_vhdl new lpp
-xfile add "../../lib/lpp/./general_purpose/Adder.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/Adder.vhd"
-xfile add "../../lib/lpp/./general_purpose/ADDRcntr.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/ADDRcntr.vhd"
-xfile add "../../lib/lpp/./general_purpose/ALU.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/ALU.vhd"
-xfile add "../../lib/lpp/./general_purpose/Clk_divider.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/Clk_divider.vhd"
-xfile add "../../lib/lpp/./general_purpose/general_purpose.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/general_purpose.vhd"
-xfile add "../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd"
-xfile add "../../lib/lpp/./general_purpose/MAC_MUX2.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MAC_MUX2.vhd"
-xfile add "../../lib/lpp/./general_purpose/MAC_MUX.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MAC_MUX.vhd"
-xfile add "../../lib/lpp/./general_purpose/MAC_REG.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MAC_REG.vhd"
-xfile add "../../lib/lpp/./general_purpose/MAC.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MAC.vhd"
-xfile add "../../lib/lpp/./general_purpose/Multiplier.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/Multiplier.vhd"
-xfile add "../../lib/lpp/./general_purpose/MUX2.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/MUX2.vhd"
-xfile add "../../lib/lpp/./general_purpose/REG.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/REG.vhd"
-xfile add "../../lib/lpp/./general_purpose/Shifter.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./general_purpose/Shifter.vhd"
-xfile add "../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd"
-xfile add "../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd"
-xfile add "../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd"
-xfile add "../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd"
-xfile add "../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/clock.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/clock.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd"
-xfile add "../../lib/lpp/./lpp_CNA_amba/Serialize.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_CNA_amba/Serialize.vhd"
-xfile add "../../lib/lpp/./lpp_uart/APB_UART.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_uart/APB_UART.vhd"
-xfile add "../../lib/lpp/./lpp_uart/BaudGen.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_uart/BaudGen.vhd"
-xfile add "../../lib/lpp/./lpp_uart/lpp_uart.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_uart/lpp_uart.vhd"
-xfile add "../../lib/lpp/./lpp_uart/Shift_REG.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_uart/Shift_REG.vhd"
-xfile add "../../lib/lpp/./lpp_uart/UART.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_uart/UART.vhd"
-xfile add "../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd"
-xfile add "../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd"
-xfile add "../../lib/lpp/./lpp_amba/lpp_amba.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./lpp_amba/lpp_amba.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/FILTER.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/FILTER.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/iir_filter.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/iir_filter.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/RAM.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/RAM.vhd"
-xfile add "../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd"
-xfile add "../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd" -lib_vhdl lpp
-puts "../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd"
-lib_vhdl new work
-xfile add "leon3mp.ucf"
-xfile add "config.vhd" -lib_vhdl work
-puts "config.vhd"
-xfile add "ahbrom.vhd" -lib_vhdl work
-puts "ahbrom.vhd"
-xfile add "leon3mp.vhd" -lib_vhdl work
-puts "leon3mp.vhd"
-project set top "rtl" "leon3mp"
-project set "Bus Delimiter" ()
-project set "FSM Encoding Algorithm" None
-project set "Pack I/O Registers into IOBs" yes
-project set "Verilog Macros" ""
-project set "Other XST Command Line Options" "-uc leon3mp.xcf" -process "Synthesize - XST"
-project set "Allow Unmatched LOC Constraints" true -process "Translate"
-project set "Macro Search Path" "../../netlists/xilinx/Spartan3" -process "Translate"
-project set "Pack I/O Registers/Latches into IOBs" {For Inputs and Outputs}
-project set "Other MAP Command Line Options" "-timing" -process Map
-project set "Drive Done Pin High" true -process "Generate Programming File"
-project set "Create ReadBack Data Files" true -process "Generate Programming File"
-project set "Create Mask File" true -process "Generate Programming File"
-project set "Run Design Rules Checker (DRC)" false -process "Generate Programming File"
-project close
-exit
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.npl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.npl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.npl
+++ /dev/null
@@ -1,20 +0,0 @@
-JDF G
-PROJECT leon3mp
-DESIGN leon3mp
-DEVFAM Spartan3E
-DEVICE xc3s1600e
-DEVSPEED -4
-DEVPKG fg320
-DEVTOPLEVELMODULETYPE EDIF
-DEVSIMULATOR Modelsim
-DEVGENERATEDSIMULATIONMODEL VHDL
-SOURCE synplify/leon3mp.edf
-DEPASSOC leon3mp leon3mp.ucf
-[Normal]
-xilxMapAllowLogicOpt=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
-xilxMapCoverMode=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Speed
-xilxNgdbld_AUL=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
-xilxPAReffortLevel=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Medium
-xilxNgdbldMacro=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1105378344, ../../netlists/xilinx/Spartan3
-[STRATEGY-LIST]
-Normal=True
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.prj b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.prj
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.prj
+++ /dev/null
@@ -1,39 +0,0 @@
-source compile.synp
-add_file -vhdl -lib work config.vhd
-add_file -vhdl -lib work ahbrom.vhd
-add_file -vhdl -lib work leon3mp.vhd
-add_file -edif ../../netlists/xilinx/Spartan3/grfpw_0_unisim.edf
-add_file -edif ../../netlists/xilinx/Spartan3/grfpw4_0_unisim.edf
-add_file -edif ../../netlists/xilinx/Spartan3/grlfpw_0_unisim.edf
-add_file -edif ../../netlists/xilinx/Spartan3/grlfpw4_0_unisim.edf
-add_file -constraint  default.sdc
-
-#implementation: "synplify"
-impl -add synplify
-
-#device options
-set_option -technology Spartan3E
-set_option -part xc3s1600e
-set_option -speed_grade -4
-
-#compilation/mapping options
-set_option -symbolic_fsm_compiler 0
-set_option -resource_sharing 0
-set_option -use_fsm_explorer 0
-set_option -write_vhdl 1
-#set_option -disable_io_insertion 0
-
-#map options
-set_option -frequency 70
-
-set_option -top_module leon3mp
-
-#set result format/file last
-project -result_file "synplify/leon3mp.edf"
-
-#implementation attributes
-set_option -vlog_std v95
-set_option -compiler_compatible 0
-set_option -package fg320
-set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0
-impl -active "synplify"
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qpf b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qpf
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qpf
+++ /dev/null
@@ -1,8 +0,0 @@
-#QUARTUS_VERSION = "4.1"
-#DATE = "17:39:37  December 03, 2004"
-
-
-# Revisions
-
-
-PROJECT_REVISION = leon3mp_synplify
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qsf b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qsf
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify.qsf
+++ /dev/null
@@ -1,12 +0,0 @@
-# Project-Wide Assignments
-# ========================
-#set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
-#set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:13:08 DECEMBER 01, 2004"
-
-# Explicitly disable TimeQuest since the GRLIB flow invokes the classical
-# timing analyzer and USE_TIMEQUEST_TIMING_ANALYZER defaults to "ON"
-# set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER "OFF"
-
-set_global_assignment -name VQM_FILE synplify/leon3mp.edf
-
-set_global_assignment -name TOP_LEVEL_ENTITY "leon3mp"
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify_win32.npl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify_win32.npl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_synplify_win32.npl
+++ /dev/null
@@ -1,18 +0,0 @@
-JDF G
-PROJECT leon3mp
-DESIGN leon3mp
-DEVFAM Spartan3E
-DEVICE xc3s1600e
-DEVSPEED -4
-DEVPKG fg320
-DEVTOPLEVELMODULETYPE EDIF
-DEVSIMULATOR Modelsim
-DEVGENERATEDSIMULATIONMODEL VHDL
-SOURCE synplify\leon3mp.edf
-DEPASSOC leon3mp leon3mp.ucf
-[Normal]
-xilxMapAllowLogicOpt=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
-xilxMapCoverMode=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Speed
-xilxNgdbld_AUL=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, True
-xilxPAReffortLevel=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1102861051, Medium
-xilxNgdbldMacro=edif,  Spartan3E, EDIF.t_placeAndRouteDes, 1105378344, ..\..\netlists\xilinx\Spartan3
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_win32.npl b/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_win32.npl
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp_win32.npl
+++ /dev/null
@@ -1,275 +0,0 @@
-JDF G
-PROJECT leon3mp
-DESIGN leon3mp
-DEVFAM Spartan3E
-DEVICE xc3s1600e
-DEVSPEED -4
-DEVPKG fg320
-DEVTOPLEVELMODULETYPE HDL
-DEVSIMULATOR Modelsim
-DEVGENERATEDSIMULATIONMODEL VHDL
-SOURCE config.vhd
-SOURCE ahbrom.vhd
-SOURCE leon3mp.vhd
-SUBLIB grlib VhdlLibrary vhdl
-LIBFILE ..\..\lib\grlib\stdlib\version.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\stdlib\config.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\stdlib\stdlib.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\sparc\sparc.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\modgen\multlib.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\modgen\leaves.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\amba.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\devices.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\defmst.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\apbctrl.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\ahbctrl.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\dma2ahb_pkg.vhd grlib vhdl
-LIBFILE ..\..\lib\grlib\amba\dma2ahb.vhd grlib vhdl
-SUBLIB unisim VhdlLibrary vhdl
-SUBLIB synplify VhdlLibrary vhdl
-SUBLIB techmap VhdlLibrary vhdl
-LIBFILE ..\..\lib\techmap\gencomp\gencomp.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\gencomp\netcomp.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\inferred\memory_inferred.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\inferred\ddr_inferred.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\inferred\mul_inferred.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\inferred\ddr_phy_inferred.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\memory_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\buffer_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\pads_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\clkgen_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\tap_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\ddr_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\ddr_phy_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\grspwc_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\grspwc2_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\grusbhc_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\ssrctrl_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\sysmon_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\unisim\mul_unisim.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\allclkgen.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\allddr.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\allmem.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\allpads.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\alltap.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\clkgen.vhd techmap vhdl
-LIBFILE ..\..\lib\techmap\maps\clkmux.vhd techmap vhdl
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-[Normal]
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-xilxMapTimingDrivenPacking=xstvhd,  Spartan3E, VHDL.t_placeAndRouteDes, 1102861051, True
-xilxNgdbld_AUL=xstvhd,  Spartan3E, VHDL.t_placeAndRouteDes, 1102861051, True
-xilxNgdbldMacro=xstvhd,  Spartan3E, VHDL.t_ngdbuild, 1105377047, ..\..\netlists\xilinx\Spartan3
-xilxPAReffortLevel=xstvhd,  Spartan3E, VHDL.t_placeAndRouteDes, 1102861051, Medium
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.do b/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.do
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.do
+++ /dev/null
@@ -1,17 +0,0 @@
-vlib modelsim
-vlib modelsim/grlib 
-vlib modelsim/unisim 
-vlib modelsim/dw02 
-vlib modelsim/synplify 
-vlib modelsim/techmap 
-vlib modelsim/eth 
-vlib modelsim/gaisler 
-vlib modelsim/esa 
-vlib modelsim/fmf 
-vlib modelsim/spansion 
-vlib modelsim/gsi 
-vlib modelsim/lpp 
-vlib modelsim/cypress 
-vlib modelsim/hynix 
-vlib modelsim/micron 
-vlib modelsim/work 
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.txt b/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.txt
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/libs.txt
+++ /dev/null
@@ -1,1 +0,0 @@
-grlib unisim dw02 synplify techmap eth gaisler esa fmf spansion gsi lpp cypress hynix micron work 
\ No newline at end of file
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim b/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim
+++ /dev/null
@@ -1,307 +0,0 @@
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/version.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/config.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/stdlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/stdio.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/stdlib/testlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/util/util.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/sparc.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/sparc_disas.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/sparc/cpu_disas.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/modgen/multlib.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/modgen/leaves.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/amba.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/devices.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/defmst.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/apbctrl.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/ahbctrl.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/dma2ahb_tp.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/amba_tp.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_util.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_mst.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_slv.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahbs.vhd
-	acom -quiet  -accept87 -work  grlib ../../../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/simple_simprim.vhd
-	acom -quiet  -accept87 -work  unisim ../../../../lib/tech/unisim/ise/unisim_VITAL.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/dw02/mul_dw_gen.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/unisim/grspwc2_unisim.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/unisim/grfpw_0_unisim.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/maps/grfpw_net.vhd
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-	acom -quiet  -accept87 -work  techmap ../../../../lib/techmap/maps/syncram128.vhd
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-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	acom -quiet  -accept87 -work  lpp ../../../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/components.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/package_utility.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/cy7c1354b.vhd
-	acom -quiet  -accept87 -work  cypress ../../../../lib/cypress/ssram/cy7c1380d.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/HY5PS121621F.vhd
-	acom -quiet  -accept87 -work  hynix ../../../../lib/hynix/ddr2/components.vhd
-	alog -quiet  -work micron ../../../../lib/micron/sdram/mobile_sdr.v
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/sdram/components.vhd
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/sdram/mt48lc16m16a2.vhd
-	alog -quiet  -work micron ../../../../lib/micron/ddr/ddr2.v
-	alog -quiet  -work micron ../../../../lib/micron/ddr/mobile_ddr.v
-	acom -quiet  -accept87 -work  micron ../../../../lib/micron/ddr/mt46v16m16.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/debug.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/grtestmod.vhd
-	acom -quiet  -accept87 -work  work ../../../../lib/work/debug/cpu_disas.vhd
-	acom -quiet  -accept87 -work  work ../../config.vhd
-	acom -quiet  -accept87 -work  work ../../ahbrom.vhd
-	acom -quiet  -accept87 -work  work ../../leon3mp.vhd
-	acom -quiet  -accept87 -work  work ../../testbench.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim-addfile b/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim-addfile
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.asim-addfile
+++ /dev/null
@@ -1,5 +0,0 @@
-
-addfile -vhdl ../../config.vhd
-addfile -vhdl ../../ahbrom.vhd
-addfile -vhdl ../../leon3mp.vhd
-addfile -vhdl ../../testbench.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.ncsim b/designs/leon3-APB_LCD-digilent-xc3s1600e/make.ncsim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.ncsim
+++ /dev/null
@@ -1,326 +0,0 @@
-ncsim:
-	mkdir xncsim
-	mkdir xncsim/grlib
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/version.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/config.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/stdlib.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/stdio.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/stdlib/testlib.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/util/util.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/sparc/sparc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/sparc/sparc_disas.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/sparc/cpu_disas.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/modgen/multlib.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/modgen/leaves.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/amba.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/devices.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/defmst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/apbctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/ahbctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/dma2ahb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/dma2ahb_tp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/amba_tp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_util.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_mst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_slv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahbs.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  grlib ../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	mkdir xncsim/unisim
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/simple_simprim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  unisim ../../lib/tech/unisim/ise/unisim_VITAL.vhd
-	mkdir xncsim/dw02
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  dw02 ../../lib/tech/dw02/comp/DW02_components.vhd
-	mkdir xncsim/synplify
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  synplify ../../lib/synplify/sim/synplify.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  synplify ../../lib/synplify/sim/synattr.vhd
-	mkdir xncsim/techmap
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/gencomp/gencomp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/gencomp/netcomp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/inferred/memory_inferred.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/inferred/mul_inferred.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/memory_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/buffer_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/pads_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/clkgen_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/tap_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/ddr_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/ddr_phy_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grspwc2_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grusbhc_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/sysmon_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/mul_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/unisim/grfpw_0_unisim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allclkgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allmem.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/allpads.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/alltap.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkmux.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkand.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/ddr_ireg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/ddr_oreg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/ddrphy.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram64.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram_2p.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram_dp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncfifo.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/regfile_3p.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/tap.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/techbuf.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/nandtree.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/clkpad_ds.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/inpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/inpad_ds.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iodpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iopad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iopad_ds.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/lvds_combo.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/odpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/outpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/outpad_ds.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/toutpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/skew_outpad.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grspwc_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grspwc2_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grlfpw_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grfpw_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/mul_61x61.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/ringosc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/system_monitor.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/grgates.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/inpad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/outpad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/iopad_ddr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram128bw.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram128.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  techmap ../../lib/techmap/maps/syncram156bw.vhd
-	mkdir xncsim/eth
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/comp/ethcomp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_pkg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/eth_rstgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/eth_ahb_mst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_tx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/greth_rx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/core/grethc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/wrapper/greth_gen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-	mkdir xncsim/gaisler
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/arith.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/mul32.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/arith/div32.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libmmu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libiu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libcache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/libproc3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/cachemem.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmulru.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmutw.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/iu3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/dsu3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/proc3.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3s.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/irqmp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/misc.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/rstgen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/gptimer.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grgpio.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/logan.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/apbps2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/charrom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/apbvga.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/spictrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/wild.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/net/net.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/libdcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/apbuart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/dcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	ncvlog -nowarn DLCPTH -nocopyright  -work gaisler ../../lib/gaisler/sim/i2c_slave_model.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sram.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/ata_device.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/sram16.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/phy.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/usbsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/greth.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/greth/grethm.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	mkdir xncsim/esa
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  esa ../../lib/esa/memoryctrl/mctrl.vhd
-	mkdir xncsim/fmf
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/utilities/conversions.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/utilities/gen_utils.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/flash.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/s25fl064a.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/flash/m25p80.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  fmf ../../lib/fmf/fifo/idt7202.vhd
-	mkdir xncsim/spansion
-	mkdir xncsim/gsi
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/functions.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/core_burst.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	mkdir xncsim/lpp
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_uart/UART.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	mkdir xncsim/cypress
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/components.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/package_utility.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	mkdir xncsim/hynix
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  hynix ../../lib/hynix/ddr2/components.vhd
-	mkdir xncsim/micron
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/sdram/mobile_sdr.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/sdram/components.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/ddr/ddr2.v
-	ncvlog -nowarn DLCPTH -nocopyright  -work micron ../../lib/micron/ddr/mobile_ddr.v
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  micron ../../lib/micron/ddr/mt46v16m16.vhd
-	mkdir xncsim/work
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/debug.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/grtestmod.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ../../lib/work/debug/cpu_disas.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work config.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work ahbrom.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work leon3mp.vhd
-	ncvhdl -nowarn DLCPTH -NOVITALCHECK -linedebug -v93 -nocopyright -work  work testbench.vhd
-	ncelab -timescale 10ps/10ps testbench:behav
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.son b/designs/leon3-APB_LCD-digilent-xc3s1600e/make.son
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.son
+++ /dev/null
@@ -1,304 +0,0 @@
-sonata-compile:
-	vhdlp -s -work  grlib ../../lib/grlib/stdlib/version.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/stdlib/config.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/stdlib/stdlib.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/stdlib/stdio.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/stdlib/testlib.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/util/util.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/sparc/sparc.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/sparc/sparc_disas.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/sparc/cpu_disas.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/modgen/multlib.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/modgen/leaves.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/amba.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/devices.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/defmst.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/apbctrl.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/ahbctrl.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/dma2ahb.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/dma2ahb_tp.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/amba_tp.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_pkg.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_util.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahb_mst.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahb_slv.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahbs.vhd
-	vhdlp -s -work  grlib ../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	vhdlp -s -work  unisim ../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	vhdlp -s -work  unisim ../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	vhdlp -s -work  unisim ../../lib/tech/unisim/ise/simple_simprim.vhd
-	vhdlp -s -work  unisim ../../lib/tech/unisim/ise/unisim_VITAL.vhd
-	vhdlp -s -work  dw02 ../../lib/tech/dw02/comp/DW02_components.vhd
-	vhdlp -s -work  synplify ../../lib/synplify/sim/synplify.vhd
-	vhdlp -s -work  synplify ../../lib/synplify/sim/synattr.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/gencomp/gencomp.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/gencomp/netcomp.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/inferred/memory_inferred.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/inferred/mul_inferred.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/memory_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/buffer_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/pads_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/clkgen_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/tap_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/ddr_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/ddr_phy_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/grspwc2_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/grusbhc_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/sysmon_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/mul_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/unisim/grfpw_0_unisim.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/allclkgen.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/allddr.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/allmem.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/allpads.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/alltap.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/clkgen.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/clkmux.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/clkand.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/ddr_ireg.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/ddr_oreg.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/ddrphy.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram64.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram_2p.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram_dp.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncfifo.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/regfile_3p.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/tap.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/techbuf.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/nandtree.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/clkpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/clkpad_ds.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/inpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/inpad_ds.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/iodpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/iopad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/iopad_ds.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/lvds_combo.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/odpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/outpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/outpad_ds.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/toutpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/skew_outpad.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/grspwc_net.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/grspwc2_net.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/grlfpw_net.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/grfpw_net.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/mul_61x61.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/ringosc.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/system_monitor.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/grgates.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/inpad_ddr.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/outpad_ddr.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/iopad_ddr.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram128bw.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram128.vhd
-	vhdlp -s -work  techmap ../../lib/techmap/maps/syncram156bw.vhd
-	vhdlp -s -work  eth ../../lib/eth/comp/ethcomp.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/greth_pkg.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/eth_rstgen.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/eth_ahb_mst.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/greth_tx.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/greth_rx.vhd
-	vhdlp -s -work  eth ../../lib/eth/core/grethc.vhd
-	vhdlp -s -work  eth ../../lib/eth/wrapper/greth_gen.vhd
-	vhdlp -s -work  eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/arith/arith.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/arith/mul32.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/arith/div32.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/leon3.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/libmmu.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/libiu.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/libcache.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/libproc3.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/cachemem.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmulru.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmutw.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmu.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/iu3.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/dsu3.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/proc3.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/leon3s.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/irqmp.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/misc.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/rstgen.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/gptimer.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbram.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/grgpio.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/logan.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/apbps2.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/charrom.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/apbvga.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/spictrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/wild.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/net/net.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/uart.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/libdcom.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/apbuart.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/dcom.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/sim.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/sram.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/ata_device.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/sram16.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/phy.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/usbsim.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/jtag.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/greth/greth.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/greth/grethm.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	vhdlp -s -work  gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	vhdlp -s -work  esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	vhdlp -s -work  esa ../../lib/esa/memoryctrl/mctrl.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/utilities/conversions.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/utilities/gen_utils.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/flash/flash.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/flash/s25fl064a.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/flash/m25p80.vhd
-	vhdlp -s -work  fmf ../../lib/fmf/fifo/idt7202.vhd
-	vhdlp -s -work  gsi ../../lib/gsi/ssram/functions.vhd
-	vhdlp -s -work  gsi ../../lib/gsi/ssram/core_burst.vhd
-	vhdlp -s -work  gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/REG.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_uart/UART.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	vhdlp -s -work  lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	vhdlp -s -work  cypress ../../lib/cypress/ssram/components.vhd
-	vhdlp -s -work  cypress ../../lib/cypress/ssram/package_utility.vhd
-	vhdlp -s -work  cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	vhdlp -s -work  cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	vhdlp -s -work  hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	vhdlp -s -work  hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	vhdlp -s -work  hynix ../../lib/hynix/ddr2/components.vhd
-	vhdlp -s -work  micron ../../lib/micron/sdram/components.vhd
-	vhdlp -s -work  micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	vhdlp -s -work  micron ../../lib/micron/ddr/mt46v16m16.vhd
-	vhdlp -s -work  sonata ../../lib/work/debug/debug.vhd
-	vhdlp -s -work  sonata ../../lib/work/debug/grtestmod.vhd
-	vhdlp -s -work  sonata ../../lib/work/debug/cpu_disas.vhd
-	vhdlp -s -work  sonata config.vhd
-	vhdlp -s -work  sonata ahbrom.vhd
-	vhdlp -s -work  sonata leon3mp.vhd
-	vhdlp -s -work  sonata testbench.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.vsim b/designs/leon3-APB_LCD-digilent-xc3s1600e/make.vsim
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/make.vsim
+++ /dev/null
@@ -1,308 +0,0 @@
-vsim:
-	vcom -quiet  -93  -work grlib ../../lib/grlib/stdlib/version.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/stdlib/config.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/stdlib/stdlib.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/stdlib/stdio.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/stdlib/testlib.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/util/util.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/sparc/sparc.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/sparc/sparc_disas.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/sparc/cpu_disas.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/modgen/multlib.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/modgen/leaves.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/amba.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/devices.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/defmst.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/apbctrl.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/ahbctrl.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/dma2ahb_pkg.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/dma2ahb.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/dma2ahb_tp.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/amba_tp.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_pkg.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahb_mst_pkg.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahb_slv_pkg.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_util.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahb_mst.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahb_slv.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahbs.vhd
-	vcom -quiet  -93  -work grlib ../../lib/grlib/amba/at/at_ahb_ctrl.vhd
-	vcom -quiet  -93  -work unisim ../../lib/tech/unisim/ise/unisim_VPKG.vhd
-	vcom -quiet  -93  -work unisim ../../lib/tech/unisim/ise/unisim_VCOMP.vhd
-	vcom -quiet  -93  -work unisim ../../lib/tech/unisim/ise/simple_simprim.vhd
-	vcom -quiet  -93  -work unisim ../../lib/tech/unisim/ise/unisim_VITAL.vhd
-	vcom -quiet  -93  -work dw02 ../../lib/tech/dw02/comp/DW02_components.vhd
-	vcom -quiet  -93  -work synplify ../../lib/synplify/sim/synplify.vhd
-	vcom -quiet  -93  -work synplify ../../lib/synplify/sim/synattr.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/gencomp/gencomp.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/gencomp/netcomp.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/inferred/memory_inferred.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/inferred/ddr_inferred.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/inferred/mul_inferred.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/inferred/ddr_phy_inferred.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/dw02/mul_dw_gen.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/memory_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/buffer_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/pads_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/clkgen_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/tap_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/ddr_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/ddr_phy_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/grspwc_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/grspwc2_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/grusbhc_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/ssrctrl_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/sysmon_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/mul_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/unisim/grfpw_0_unisim.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/allclkgen.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/allddr.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/allmem.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/allpads.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/alltap.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/clkgen.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/clkmux.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/clkand.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/ddr_ireg.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/ddr_oreg.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/ddrphy.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram64.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram_2p.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram_dp.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncfifo.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/regfile_3p.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/tap.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/techbuf.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/nandtree.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/clkpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/clkpad_ds.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/inpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/inpad_ds.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/iodpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/iopad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/iopad_ds.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/lvds_combo.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/odpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/outpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/outpad_ds.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/toutpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/skew_outpad.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/grspwc_net.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/grspwc2_net.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/grlfpw_net.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/grfpw_net.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/mul_61x61.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/cpu_disas_net.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/ringosc.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/system_monitor.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/grgates.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/inpad_ddr.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/outpad_ddr.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/iopad_ddr.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram128bw.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram128.vhd
-	vcom -quiet  -93  -work techmap ../../lib/techmap/maps/syncram156bw.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/comp/ethcomp.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/greth_pkg.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/eth_rstgen.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/eth_ahb_mst.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/greth_tx.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/greth_rx.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/core/grethc.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/wrapper/greth_gen.vhd
-	vcom -quiet  -93  -work eth ../../lib/eth/wrapper/greth_gbit_gen.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/arith/arith.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/arith/mul32.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/arith/div32.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/memctrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/sdctrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/sdctrl64.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/sdmctrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/srctrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/memctrl/spimctrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/leon3.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmuconfig.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmuiface.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/libmmu.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/libiu.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/libcache.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/libproc3.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/cachemem.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmu_icache.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmu_dcache.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmu_acache.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmutlbcam.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmulrue.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmulru.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmutlb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmutw.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmu.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mmu_cache.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/cpu_disasx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/iu3.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/grfpwx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/mfpwx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/grlfpwx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/tbufmem.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/dsu3x.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/dsu3.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/proc3.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/leon3s.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/leon3cg.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/irqmp.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/grfpwxsh.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/grfpushwx.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/leon3/leon3sh.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/misc.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/rstgen.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/gptimer.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbdpram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbtrace.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbtrace_mb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbmst.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grgpio.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbstat.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/logan.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/apbps2.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/charrom_package.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/charrom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/apbvga.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/svgactrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/i2cmst_gen.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/spictrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/i2cslv.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/wild.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/wild2ahb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grsysmon.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/gracectrl.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/grgpreg.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahbmst2.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/misc/ahb_mst_iface.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/net/net.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/uart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/libdcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/apbuart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/dcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/dcom_uart.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/uart/ahbuart.vhd
-	vlog -quiet  -work gaisler ../../lib/gaisler/sim/i2c_slave_model.v
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sram.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/ata_device.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/sram16.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/phy.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/ahbrep.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/delay_wire.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/spi_flash.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/pwm_check.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/usbsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/grusbdcsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/sim/grusb_dclsim.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtag.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/libjtagcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtagcom.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/ahbjtag.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/ahbjtag_bsd.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/jtag/jtagtst.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/ethernet_mac.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/greth.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/greth_gbit.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/greth/grethm.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr_phy.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp16a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp32a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrsp64a.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddrspa.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spa.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2buf.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax_ahb.vhd
-	vcom -quiet  -93  -work gaisler ../../lib/gaisler/ddr/ddr2spax_ddr.vhd
-	vcom -quiet  -93  -work esa ../../lib/esa/memoryctrl/memoryctrl.vhd
-	vcom -quiet  -93  -work esa ../../lib/esa/memoryctrl/mctrl.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/utilities/conversions.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/utilities/gen_utils.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/flash.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/s25fl064a.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/flash/m25p80.vhd
-	vcom -quiet  -93  -work fmf ../../lib/fmf/fifo/idt7202.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/functions.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/core_burst.vhd
-	vcom -quiet  -93  -work gsi ../../lib/gsi/ssram/g880e18bt.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Adder.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/ADDRcntr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/ALU.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Clk_divider.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/general_purpose.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_CONTROLER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_MUX2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_MUX.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC_REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MAC.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Multiplier.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/MUX2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./general_purpose/Shifter.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_drvr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/AD7688_spi_if.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/ADS7886_drvr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_ad_Conv/lpp_apb_ad_conv.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/APB_CNA.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/clock.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/CNA_TabloC.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/Convertisseur_config.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/GeneSYNC_flag.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/lpp_CNA_amba.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_CNA_amba/Serialize.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/APB_UART.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/BaudGen.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/lpp_uart.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/Shift_REG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_uart/UART.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/APB_MULTI_DIODE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./lpp_amba/lpp_amba.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/APB_IIR_CEL.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FilterCTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTER_RAM_CTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/FILTER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/IIR_CEL_FILTER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/iir_filter.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM_CTRLR2.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/RAM.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/apb_lcd_ctrlr.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/FRAME_CLK.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_DRVR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd
-	vcom -quiet  -93  -work lpp ../../lib/lpp/./amba_lcd_16x2_ctrlr/Top_LCD.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/components.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/package_utility.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/cy7c1354b.vhd
-	vcom -quiet  -93  -work cypress ../../lib/cypress/ssram/cy7c1380d.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/HY5PS121621F_PACK.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/HY5PS121621F.vhd
-	vcom -quiet  -93  -work hynix ../../lib/hynix/ddr2/components.vhd
-	vlog -quiet  -work micron ../../lib/micron/sdram/mobile_sdr.v
-	vcom -quiet  -93  -work micron ../../lib/micron/sdram/components.vhd
-	vcom -quiet  -93  -work micron ../../lib/micron/sdram/mt48lc16m16a2.vhd
-	vlog -quiet  -work micron ../../lib/micron/ddr/ddr2.v
-	vlog -quiet  -work micron ../../lib/micron/ddr/mobile_ddr.v
-	vcom -quiet  -93  -work micron ../../lib/micron/ddr/mt46v16m16.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/debug.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/grtestmod.vhd
-	vcom -quiet  -93  -work work ../../lib/work/debug/cpu_disas.vhd
-	vcom -quiet  -93  -work work config.vhd
-	vcom -quiet  -93  -work work ahbrom.vhd
-	vcom -quiet  -93  -work work leon3mp.vhd
-	vcom -quiet  -93  -work work testbench.vhd
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini b/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/modelsim.ini
+++ /dev/null
@@ -1,227 +0,0 @@
-[Library]
-grlib = modelsim/grlib
-unisim = modelsim/unisim
-dw02 = modelsim/dw02
-synplify = modelsim/synplify
-techmap = modelsim/techmap
-eth = modelsim/eth
-gaisler = modelsim/gaisler
-esa = modelsim/esa
-fmf = modelsim/fmf
-spansion = modelsim/spansion
-gsi = modelsim/gsi
-lpp = modelsim/lpp
-cypress = modelsim/cypress
-hynix = modelsim/hynix
-micron = modelsim/micron
-work = modelsim/work
-std = $MODEL_TECH/../std
-ieee = $MODEL_TECH/../ieee
-vital2000 = $MODEL_TECH/../vital2000
-verilog = $MODEL_TECH/../verilog
-arithmetic = $MODEL_TECH/../arithmetic
-mgc_portable = $MODEL_TECH/../mgc_portable
-std_developerskit = $MODEL_TECH/../std_developerskit
-synopsys = $MODEL_TECH/../synopsys
-
-[vcom]
-; Turn on VHDL-1993 as the default. Normally is off.
-VHDL93 = 1
-
-; Show source line containing error. Default is off.
-Show_source = 1
-
-; Turn off unbound-component warnings. Default is on.
-Show_Warning1 = 0
-
-; Turn off process-without-a-wait-statement warnings. Default is on.
-; Show_Warning2 = 0
-
-; Turn off null-range warnings. Default is on.
-; Show_Warning3 = 0
-
-; Turn off no-space-in-time-literal warnings. Default is on.
-; Show_Warning4 = 0
-
-; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
-Show_Warning5 = 0
-
-; Turn off optimization for IEEE std_logic_1164 package. Default is on.
-; Optimize_1164 = 0
-
-; Turn on resolving of ambiguous function overloading in favor of the
-; "explicit" function declaration (not the one automatically created by
-; the compiler for each type declaration). Default is off.
-Explicit = 1
-
-; Turn off VITAL compliance checking. Default is checking on.
-; NoVitalCheck = 1
-
-; Ignore VITAL compliance checking errors. Default is to not ignore.
-; IgnoreVitalErrors = 1
-
-; Turn off VITAL compliance checking warnings. Default is to show warnings.
-; Show_VitalChecksWarnings = false
-
-; Turn off acceleration of the VITAL packages. Default is to accelerate.
-; NoVital = 1
-
-; Turn off inclusion of debugging info within design units. Default is to include.
-; NoDebug = 1
-
-; Turn off "loading..." messages. Default is messages on.
-Quiet = 1
-
-; Turn on some limited synthesis rule compliance checking. Checks only:
-;	-- signals used (read) by a process must be in the sensitivity list
-; CheckSynthesis = 1
-
-[vlog]
-
-; Turn off inclusion of debugging info within design units. Default is to include.
-; NoDebug = 1
-
-; Turn off "loading..." messages. Default is messages on.
-Quiet = 1
-
-; Turn on Verilog hazard checking (order-dependent accessing of global vars).
-; Default is off.
-; Hazard = 1
-
-; Turn on converting regular Verilog identifiers to uppercase. Allows case
-; insensitivity for module names. Default is no conversion.
-; UpCase = 1
-
-[vsim]
-
-; vopt flow                                   
-; Set to turn on automatic optimization of a design.
-; Default is off (pre-6.0 flow without vopt).
-VoptFlow = 0
-
-; Simulator resolution
-; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
-Resolution = 1ps
-
-; User time unit for run commands
-; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
-; unit specified for Resolution. For example, if Resolution is 100ps,
-; then UserTimeUnit defaults to ps.
-UserTimeUnit = ns
-
-; Default run length
-RunLength = 100
-
-; Maximum iterations that can be run without advancing simulation time
-IterationLimit = 5000
-
-; Directive to license manager:
-; vhdl          Immediately reserve a VHDL license
-; vlog          Immediately reserve a Verilog license
-; plus          Immediately reserve a VHDL and Verilog license
-; nomgc         Do not look for Mentor Graphics Licenses
-; nomti         Do not look for Model Technology Licenses
-; noqueue       Do not wait in the license queue when a license isn't available
-; License = plus
-
-; Stop the simulator after an assertion message
-; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
-BreakOnAssertion = 3
-
-; Assertion Message Format
-; %S - Severity Level 
-; %R - Report Message
-; %T - Time of assertion
-; %D - Delta
-; %I - Instance or Region pathname (if available)
-; %% - print '%' character
-; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
-
-; Default radix for all windows and commands...
-; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
-DefaultRadix = symbolic
-
-; VSIM Startup command
-; Startup = do startup.do
-
-; File for saving command transcript
-TranscriptFile = transcript
-
-; Specify whether paths in simulator commands should be described 
-; in VHDL or Verilog format. For VHDL, PathSeparator = /
-; for Verilog, PathSeparator = .
-PathSeparator = /
-
-; Disable assertion messages
-; IgnoreNote = 1
-; IgnoreWarning = 1
-; IgnoreError = 1
-; IgnoreFailure = 1
-
-; Default force kind. May be freeze, drive, or deposit 
-; or in other terms, fixed, wired or charged.
-; DefaultForceKind = freeze
-
-; If zero, open files when elaborated
-; else open files on first read or write
-; DelayFileOpen = 0
-
-; Control VHDL files opened for write
-;   0 = Buffered, 1 = Unbuffered
-UnbufferedOutput = 0
-
-; This controls the number of characters of a signal name
-; shown in the waveform window and the postscript plot. 
-; The default value or a value of zero tells VSIM to display 
-; the full name.
-; WaveSignalNameWidth = 10
-
-; Turn off warnings from the std_logic_arith, std_logic_unsigned
-; and std_logic_signed packages.
-; StdArithNoWarnings = 1
-
-; Turn off warnings from the IEEE numeric_std and numeric_bit
-; packages.
-; NumericStdNoWarnings = 1
-
-; Control the format of a generate statement label. Don't quote it.
-; GenerateFormat = %s__%d
-
-; Specify whether checkpoint files should be compressed.
-; The default is to be compressed.
-; CheckpointCompressMode = 0
-
-; List of dynamically loaded objects for Verilog PLI applications
-; Veriuser = veriuser.sl
-
-[lmc]
-; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
-libsm = $MODEL_TECH/libsm.sl
-; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
-; libsm = $MODEL_TECH/libsm.dll
-;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
-; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
-;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
-; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
-;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
-; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
-;  Logic Modeling's SmartModel SWIFT software (Sun4 SunOS)
-;	do setenv LD_LIBRARY_PATH $LMC_HOME/lib/sun4SunOS.lib
-;	and run "vsim.swift".
-;  Logic Modeling's SmartModel SWIFT software (Windows NT)
-; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
-
-; ModelSim's interface to Logic Modeling's hardware modeler SFI software
-libhm = $MODEL_TECH/libhm.sl
-; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
-; libhm = $MODEL_TECH/libhm.dll
-;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
-; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
-;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
-; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
-;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
-; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
-;  Logic Modeling's hardware modeler SFI software (Sun4 SunOS)
-; libsfi = <sfi_dir>/lib/sun4.sunos/libsfi.so
-;  Logic Modeling's hardware modeler SFI software (Window NT)
-; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
diff --git a/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml b/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml
deleted file mode 100644
--- a/designs/leon3-APB_LCD-digilent-xc3s1600e/webtalk_pn.xml
+++ /dev/null
@@ -1,56 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<document>
-<!--The data in this file is primarily intended for consumption by Xilinx tools.
-The structure and the elements are likely to change over the next few releases.
-This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Wed Dec  8 09:10:18 2010">
-<section name="Project Information" visible="false">
-<property name="ProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="project"/>
-<property name="ProjectIteration" value="11" type="project"/>
-<property name="ProjectFile" value="/opt/GRLIB/grlib-gpl-1.1.0-b4104/designs/leon3-APB_LCD-digilent-xc3s1600e/leon3mp.xise" type="project"/>
-<property name="ProjectCreationTimestamp" value="2010-12-02T08:01:13" type="project"/>
-</section>
-<section name="Project Statistics" visible="true">
-<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
-<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
-<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
-<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
-<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
-<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
-<property name="PROP_SelectedInstanceHierarchicalPath" value="/APB_IIR_CEL/filter" type="process"/>
-<property name="PROP_Simulator" value="Modelsim-SE Mixed" type="design"/>
-<property name="PROP_SynthFsmEncode" value="None" type="process"/>
-<property name="PROP_SynthTopFile" value="changed" type="process"/>
-<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
-<property name="PROP_UseSmartGuide" value="false" type="design"/>
-<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
-<property name="PROP_intProjectCreationTimestamp" value="2010-12-02T08:01:13" type="design"/>
-<property name="PROP_intWbtProjectID" value="314B616C181AFB6097A4EDCB224EA28B" type="design"/>
-<property name="PROP_intWbtProjectIteration" value="11" type="process"/>
-<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
-<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
-<property name="PROP_map_otherCmdLineOptions" value="-timing" type="process"/>
-<property name="PROP_selectedSimRootSourceNode_behav" value="lpp.IIR_CEL_FILTER" type="process"/>
-<property name="PROP_xilxBitgCfg_GenOpt_DRC" value="false" type="process"/>
-<property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
-<property name="PROP_xilxBitgStart_Clk_DriveDone" value="true" type="process"/>
-<property name="PROP_xilxMapPackRegInto" value="For Inputs and Outputs" type="process"/>
-<property name="PROP_xilxNgdbldMacro" value="changed" type="process"/>
-<property name="PROP_xilxNgdbld_AUL" value="true" type="process"/>
-<property name="PROP_xstBusDelimiter" value="()" type="process"/>
-<property name="PROP_xstPackIORegister" value="Yes" type="process"/>
-<property name="PROP_xst_otherCmdLineOptions" value="-uc leon3mp.xcf" type="process"/>
-<property name="PROP_AutoTop" value="false" type="design"/>
-<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
-<property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
-<property name="PROP_DevDevice" value="xc3s1600e" type="design"/>
-<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
-<property name="PROP_DevPackage" value="fg320" type="design"/>
-<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
-<property name="PROP_DevSpeed" value="-4" type="design"/>
-<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
-<property name="FILE_UCF" value="1" type="source"/>
-<property name="FILE_VHDL" value="302" type="source"/>
-</section>
-</application>
-</document>
diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd
--- a/lib/lpp/lpp_amba/apb_devices_list.vhd
+++ b/lib/lpp/lpp_amba/apb_devices_list.vhd
@@ -47,4 +47,6 @@ PACKAGE apb_devices_list IS
   CONSTANT LPP_APB_ADVANCED_TRIGGER      : amba_device_type := 16#A3#;
   CONSTANT LPP_APB_ADVANCED_TRIGGER_v    : amba_device_type := 16#A4#;
 
+  CONSTANT LPP_AHB_FTDI_FIFO : amba_device_type := 16#A5#;
+
 END;
diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt
--- a/lib/lpp/lpp_sim/vhdlsim.txt
+++ b/lib/lpp/lpp_sim/vhdlsim.txt
@@ -1,4 +1,5 @@
 lpp_sim_pkg.vhd
 sig_reader.vhd
 sig_recorder.vhd
+lpp_sim_pkg.vhd
 lpp_lfr_sim_pkg.vhd
diff --git a/lib/lpp/lpp_usb/ahb_ftdi_fifo.vhd b/lib/lpp/lpp_usb/ahb_ftdi_fifo.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_usb/ahb_ftdi_fifo.vhd
@@ -0,0 +1,83 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+------------------------------------------------------------------------------
+--                        Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.uart.all;
+library lpp;
+use lpp.lpp_usb.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+
+
+entity ahb_ftdi_fifo is
+generic (
+  oepol : integer := 0;
+  hindex  : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+  ahbi    : in  ahb_mst_in_type;
+  ahbo    : out ahb_mst_out_type;
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end ahb_ftdi_fifo;
+
+architecture beh of ahb_ftdi_fifo is
+
+constant REVISION : integer := 0;
+
+signal dmai : ahb_dma_in_type;
+signal dmao : ahb_dma_out_type;
+signal duarti : dcom_uart_in_type;
+signal duarto : dcom_uart_out_type;
+
+begin
+
+  ahbmst0 : ahbmst
+    generic map (hindex => hindex, venid => VENDOR_LPP, devid => LPP_AHB_FTDI_FIFO)
+    port map (rstn, clk, dmai, dmao, ahbi, ahbo);
+
+  dcom_fifo0 : ftdi_async_fifo generic map (oepol)
+    port map (clk, rstn, duarti, duarto, FTDI_RXF, FTDI_TXE, FTDI_SIWUA,
+       FTDI_WR, FTDI_RD, FTDI_D_in, FTDI_D_out, FTDI_D_drive);
+
+  dcom0 : dcom port map (rstn, clk, dmai, dmao, duarti, duarto, ahbi);
+
+
+end beh;
+
diff --git a/lib/lpp/lpp_usb/ftdi_async_fifo.vhd b/lib/lpp/lpp_usb/ftdi_async_fifo.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_usb/ftdi_async_fifo.vhd
@@ -0,0 +1,142 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+------------------------------------------------------------------------------
+--                        Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.uart.all;
+library lpp;
+use lpp.lpp_usb.all;
+
+
+entity ftdi_async_fifo is
+generic (
+  oepol : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+  dcom_in     : in  dcom_uart_in_type;
+  dcom_out    : out dcom_uart_out_type;
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end ftdi_async_fifo;
+
+architecture beh of ftdi_async_fifo is
+
+type fifo_fsm_st is (idle,waitForTXE,preWrite,Write,postWrite,preRead,Read,postRead);
+signal state : fifo_fsm_st:=idle;
+signal output_en : std_logic;
+signal dready : std_logic;
+
+begin
+
+acthi: if oepol = 1 generate
+  output_en <= '1';
+end generate;
+actlow: if oepol = 0 generate
+  output_en <= '0';
+end generate;
+
+dcom_out.dready <= dready;
+FTDI_SIWUA <= '1';
+
+process(rstn,clk)
+begin
+if rstn = '0' then
+  FTDI_RD    <= '1';
+  FTDI_WR    <= '1';
+  FTDI_D_drive  <= not output_en;
+  dready  <= '0';
+  dcom_out.tsempty <= '0';
+  dcom_out.thempty <= '1';
+  dcom_out.lock    <= '1';
+  dcom_out.data    <= (others => '0');
+elsif clk'event and clk='1' then
+  case state is
+    when idle =>
+      if dcom_in.read = '1' then
+        dready <= '0';
+      end if;
+      FTDI_D_drive  <= not output_en;
+      FTDI_WR       <= '1';
+      dcom_out.thempty <= '1';
+      if dcom_in.write = '1' then
+        dcom_out.thempty <= '0';
+        state <= waitForTXE;
+      elsif FTDI_RXF = '0' and dready = '0' then
+        state   <= preRead;
+        FTDI_RD <= '0';
+      end if;
+    when waitForTXE =>
+      if FTDI_TXE = '0' then
+        state   <= preWrite;
+        FTDI_D_drive  <= output_en;
+        FTDI_D_out    <= dcom_in.data;
+      end if;
+    when preWrite =>
+        FTDI_WR <= '0';
+        state   <= Write;
+    when Write =>
+        FTDI_D_drive  <= not output_en;
+        state   <= idle;
+    when preRead =>
+      state <= Read;
+      dcom_out.data <= FTDI_D_in;
+    when Read =>
+      FTDI_RD  <= '1';
+      dready <= '1';
+      state    <= idle;
+    when others => NULL;
+  end case;
+end if;
+end process;
+
+end beh;
+
+-- type dcom_uart_in_type is record
+--   read    	: std_ulogic;
+--   write   	: std_ulogic;
+--   data		: std_logic_vector(7 downto 0);
+-- end record;
+
+-- type dcom_uart_out_type is record
+--   dready 	: std_ulogic;   -> data from ftdi to DCOM
+--   tsempty	: std_ulogic;   -> not used by decom -> set to 0
+--   thempty	: std_ulogic;   -> tels dcom that ready to write to ftdi
+--   lock    	: std_ulogic;   -> set to 1
+--   enable 	: std_ulogic;   -> unused
+--   data		: std_logic_vector(7 downto 0);
+-- end record;
+
diff --git a/lib/lpp/lpp_usb/ftdi_async_fifo_loopback.vhd b/lib/lpp/lpp_usb/ftdi_async_fifo_loopback.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_usb/ftdi_async_fifo_loopback.vhd
@@ -0,0 +1,132 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+------------------------------------------------------------------------------
+--                        Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library gaisler;
+use gaisler.libdcom.all;
+use gaisler.uart.all;
+library lpp;
+use lpp.lpp_usb.all;
+
+
+entity ftdi_async_fifo_loopback is
+generic (
+  oepol : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end ftdi_async_fifo_loopback;
+
+architecture beh of ftdi_async_fifo_loopback is
+
+type fifo_fsm_st is (idle,waitTXE,preWrite,Write,postWrite,preRead,Read,postRead);
+signal state : fifo_fsm_st:=idle;
+signal output_en : std_logic;
+signal dready : std_logic;
+signal fifo_flush_cntr : integer := 31;
+signal fifo_siwu_pulse : std_logic_vector(3 downto 0):= (others => '1');
+
+begin
+
+acthi: if oepol = 1 generate
+  output_en <= '1';
+end generate;
+actlow: if oepol = 0 generate
+  output_en <= '0';
+end generate;
+
+FTDI_SIWUA <= '1';--fifo_siwu_pulse(0);
+
+process(rstn,clk)
+begin
+if rstn = '0' then
+  FTDI_RD    <= '1';
+  FTDI_WR    <= '1';
+  FTDI_D_drive  <= not output_en;
+elsif clk'event and clk='1' then
+  if fifo_flush_cntr = 1 then
+    fifo_siwu_pulse <= (others => '0');
+  else
+    fifo_siwu_pulse  <=  '1' & fifo_siwu_pulse(3 downto 1);
+  end if;
+  case state is
+    when idle =>
+      if FTDI_RXF = '0' then
+        state   <= preRead;
+        FTDI_RD <= '0';
+      end if;
+      FTDI_WR <= '1';
+    when preWrite =>
+        FTDI_WR <= '0';
+        state   <= Write;
+    when Write =>
+        FTDI_D_drive  <= not output_en;
+        state   <= idle;
+        fifo_flush_cntr <= 31;
+    when preRead =>
+      state <= Read;
+    when Read =>
+      FTDI_D_out <= FTDI_D_in;
+      FTDI_RD  <= '1';
+      state    <= waitTXE;
+    when waitTXE =>
+      if FTDI_TXE = '0' then
+        state   <= preWrite;
+        FTDI_D_drive  <= output_en;
+      end if;
+    when others => NULL;
+  end case;
+end if;
+end process;
+
+end beh;
+
+-- type dcom_uart_in_type is record
+--   read    	: std_ulogic;
+--   write   	: std_ulogic;
+--   data		: std_logic_vector(7 downto 0);
+-- end record;
+
+-- type dcom_uart_out_type is record
+--   dready 	: std_ulogic;   -> data from ftdi to DCOM
+--   tsempty	: std_ulogic;   -> not used by decom -> set to 0
+--   thempty	: std_ulogic;   -> tels dcom that ready to write to ftdi
+--   lock    	: std_ulogic;   -> set to 1
+--   enable 	: std_ulogic;   -> unused
+--   data		: std_logic_vector(7 downto 0);
+-- end record;
+
diff --git a/lib/lpp/lpp_usb/lpp_usb.vhd b/lib/lpp/lpp_usb/lpp_usb.vhd
--- a/lib/lpp/lpp_usb/lpp_usb.vhd
+++ b/lib/lpp/lpp_usb/lpp_usb.vhd
@@ -24,6 +24,8 @@ use ieee.std_logic_1164.all;
 library grlib;
 use grlib.amba.all;
 use std.textio.all;
+library gaisler;
+use gaisler.libdcom.all;
 library lpp;
 use lpp.lpp_amba.all;
 
@@ -31,6 +33,71 @@ use lpp.lpp_amba.all;
 
 package lpp_usb is
 
+component ahb_ftdi_fifo is
+generic (
+  oepol : integer := 0;
+  hindex  : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+  ahbi    : in  ahb_mst_in_type;
+  ahbo    : out ahb_mst_out_type;
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end component;
+
+component ftdi_async_fifo is
+generic (
+  oepol : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+  dcom_in     : in  dcom_uart_in_type;
+  dcom_out    : out dcom_uart_out_type;
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end component;
+
+component ftdi_async_fifo_loopback is
+generic (
+  oepol : integer := 0
+);
+port (
+  clk         : in  std_logic;
+  rstn        : in  std_logic;
+
+
+  FTDI_RXF     : in  std_logic;
+  FTDI_TXE     : in  std_logic;
+  FTDI_SIWUA   : out std_logic;
+  FTDI_WR      : out std_logic;
+  FTDI_RD      : out std_logic;
+  FTDI_D_in    : in  std_logic_vector(7 downto 0);
+  FTDI_D_out   : out std_logic_vector(7 downto 0);
+  FTDI_D_drive : out std_logic
+);
+end component;
+
 component FX2_Driver is
 port(
         clk         : in STD_LOGIC;
@@ -120,4 +187,4 @@ end component;
       ); 
   end component;
 
-end package;
\ No newline at end of file
+end package;
diff --git a/lib/opencores/spw_light/spwahbmst.vhd b/lib/opencores/spw_light/spwahbmst.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwahbmst.vhd
@@ -0,0 +1,739 @@
+--
+--  AHB master for AMBA interface.
+--
+--  This is a helper entity for the SpaceWire AMBA interface.
+--  It implements the AHB master which transfers data from/to main memory.
+--
+--  Descriptor flag bits on input:
+--    bit 15:0      (RX) max nr of bytes to receive (must be a multiple of 4)
+--                  (TX) nr of bytes to transmit
+--    bit 16        EN: '1' = descriptor enabled
+--    bit 17        WR: wrap to beginning of descriptor table
+--    bit 18        IE: interrupt at end of descriptor
+--    bit 19        '0'
+--    bit 20        (TX only) send EOP after end of data
+--    bit 21        (TX only) send EEP after end of data
+--
+--  Descriptor flag bits after completion of frame:
+--    bit 15:0      (RX only) LEN: nr of bytes received
+--                  (TX) undefined
+--    bit 16        '0'
+--    bit 18:17     undefined
+--    bit 19        '1' to indicate descriptor completed       
+---   bit 20        (RX only) received EOP after end of data
+--    bit 21        (RX only) received EEP after end of data
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use work.spwambapkg.all;
+
+
+entity spwahbmst is
+
+    generic (
+        -- AHB master index.
+        hindex:         integer;
+
+        -- AHB plug&play information.
+        hconfig:        ahb_config_type;
+
+        -- Maximum burst length as the 2-logarithm of the number of words.
+        maxburst:       integer range 1 to 8
+    );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Synchronous reset (active-low).
+        rstn:       in  std_logic;
+
+        -- Inputs from SpaceWire core.
+        msti:       in  spw_ahbmst_in_type;
+
+        -- Outputs to SpaceWire core.
+        msto:       out spw_ahbmst_out_type;
+
+        -- AHB master input signals.
+        ahbi:       in  ahb_mst_in_type;
+
+        -- AHB master output signals.
+        ahbo:       out ahb_mst_out_type
+    );
+
+end entity spwahbmst;
+
+architecture spwahbmst_arch of spwahbmst is
+
+    --
+    -- Registers.
+    --
+
+    type state_type is (
+        st_idle,
+        st_rxgetdesc, st_rxgetptr, st_rxtransfer, st_rxfinal, st_rxputdesc,
+        st_txgetdesc, st_txgetptr, st_txtransfer, st_txfinal, st_txputdesc, st_txskip );
+
+    type burst_state_type is ( bs_idle, bs_setup, bs_active, bs_end );
+
+    type regs_type is record
+        -- dma state
+        rxdma_act:      std_ulogic;
+        txdma_act:      std_ulogic;
+        ahberror:       std_ulogic;
+        -- main state machine
+        mstate:         state_type;
+        firstword:      std_ulogic;
+        prefertx:       std_ulogic;
+        -- rx descriptor state
+        rxdes_en:       std_ulogic;
+        rxdes_wr:       std_ulogic;
+        rxdes_ie:       std_ulogic;
+        rxdes_eop:      std_ulogic;
+        rxdes_eep:      std_ulogic;
+        rxdes_len:      std_logic_vector(13 downto 0);  -- in 32-bit words
+        rxdes_pos:      std_logic_vector(15 downto 0);  -- in bytes
+        rxaddr:         std_logic_vector(31 downto 2);
+        rxdesc_next:    std_ulogic;
+        -- tx descriptor state
+        txdes_en:       std_ulogic;
+        txdes_wr:       std_ulogic;
+        txdes_ie:       std_ulogic;
+        txdes_eop:      std_ulogic;
+        txdes_eep:      std_ulogic;
+        txdes_len:      std_logic_vector(15 downto 0);  -- in bytes
+        txaddr:         std_logic_vector(31 downto 2);
+        txdesc_next:    std_ulogic;
+        -- interrupts
+        int_rxdesc:     std_ulogic;
+        int_txdesc:     std_ulogic;
+        int_rxpacket:   std_ulogic;
+        -- burst state
+        burststat:      burst_state_type;
+        hbusreq:        std_ulogic;
+        hwrite:         std_ulogic;
+        haddr:          std_logic_vector(31 downto 2);
+        hwdata:         std_logic_vector(31 downto 0);
+    end record;
+
+    constant regs_reset: regs_type := (
+        rxdma_act       => '0',
+        txdma_act       => '0',
+        ahberror        => '0',
+        mstate          => st_idle,
+        firstword       => '0',
+        prefertx        => '0',
+        rxdes_en        => '0',
+        rxdes_wr        => '0',
+        rxdes_ie        => '0',
+        rxdes_eop       => '0',
+        rxdes_eep       => '0',
+        rxdes_len       => (others => '0'),
+        rxdes_pos       => (others => '0'),
+        rxaddr          => (others => '0'),
+        rxdesc_next     => '0',
+        txdes_en        => '0',
+        txdes_wr        => '0',
+        txdes_ie        => '0',
+        txdes_eop       => '0',
+        txdes_eep       => '0',
+        txdes_len       => (others => '0'),
+        txaddr          => (others => '0'),
+        txdesc_next     => '0',
+        int_rxdesc      => '0',
+        int_txdesc      => '0',
+        int_rxpacket    => '0',
+        burststat       => bs_idle,
+        hbusreq         => '0',
+        hwrite          => '0',
+        haddr           => (others => '0'),
+        hwdata          => (others => '0') );
+
+    signal r: regs_type := regs_reset;
+    signal rin: regs_type;
+
+begin
+
+    --
+    -- Combinatorial process
+    --
+    process (r, rstn, msti, ahbi)  is
+        variable v:             regs_type;
+        variable v_hrdata:      std_logic_vector(31 downto 0);
+        variable v_burstreq:    std_logic;
+        variable v_burstack:    std_logic;
+        variable v_rxfifo_read: std_logic;
+        variable v_txfifo_write: std_logic;
+        variable v_txfifo_wdata: std_logic_vector(35 downto 0);
+    begin
+        v           := r;
+
+        -- Decode AHB data bus (64-bit AHB compatibility).
+        v_hrdata    := ahbreadword(ahbi.hrdata);
+
+        -- Assume no burst request.
+        v_burstreq  := '0';
+
+        -- Detect request from burst state machine for next data word.
+        v_burstack  := ahbi.hready and
+                       conv_std_logic(r.burststat = bs_active or r.burststat = bs_end);
+
+        -- Assume no fifo activity; take data for TX fifo from AHB bus.
+        v_rxfifo_read   := '0';
+        v_txfifo_write  := '0';
+        v_txfifo_wdata(35 downto 32) := (others => '0');
+        v_txfifo_wdata(31 downto 0)  := v_hrdata;
+
+        -- Reset registers for interrupts and descriptor updates.
+        v.int_rxdesc    := '0';
+        v.int_txdesc    := '0';
+        v.int_rxpacket  := '0';
+        v.rxdesc_next   := '0';
+        v.txdesc_next   := '0';
+
+        -- Start DMA on external request.
+        if msti.rxdma_start = '1' then v.rxdma_act := '1'; end if;
+        if msti.txdma_start = '1' then v.txdma_act := '1'; end if;
+
+        --
+        -- Main state machine.
+        --
+        case r.mstate is
+
+            when st_idle =>
+                -- Waiting for something to do.
+                v.prefertx  := '0';
+                v.firstword := '1';
+                if msti.txdma_cancel = '1' then
+                    v.txdma_act := '0';
+                    v.txdes_en  := '0';
+                end if;
+                if r.rxdma_act = '1' and msti.rxfifo_empty = '0' and
+                   (r.prefertx = '0' or r.txdma_act = '0' or msti.txfifo_highw = '1') then
+                    -- Start RX transfer.
+                    if r.rxdes_en = '1' then
+                        -- Transfer RX data to current descriptor.
+                        v_burstreq  := '1';
+                        v.hwrite    := '1';
+                        v.haddr     := r.rxaddr;
+                        v.mstate    := st_rxtransfer;
+                    else
+                        -- Must fetch new RX descriptor.
+                        v_burstreq  := '1';
+                        v.hwrite    := '0';
+                        v.haddr     := msti.rxdesc_ptr & "0";
+                        v.mstate    := st_rxgetdesc;
+                    end if;
+                elsif r.txdma_act = '1' and msti.txdma_cancel = '0' and msti.txfifo_highw = '0' then
+                    -- Start TX transfer.
+                    if r.txdes_en = '1' then
+                        -- Transfer TX data from current descriptor.
+                        if unsigned(r.txdes_len) = 0 then
+                            -- Only send EOP/EEP and write back descriptor.
+                            v_burstreq  := '1';
+                            v.hwrite    := '1';
+                            v.haddr     := msti.txdesc_ptr & "0";
+                            v.txdesc_next := '1';
+                            v.mstate    := st_txputdesc;
+                        else
+                            -- Start burst transfer.
+                            v_burstreq  := '1';
+                            v.hwrite    := '0';
+                            v.haddr     := r.txaddr;
+                            if unsigned(r.txdes_len) <= 4 then
+                                -- Transfer only one word.
+                                v.mstate    := st_txfinal;
+                            else
+                                v.mstate    := st_txtransfer;
+                            end if;
+                        end if;
+                    else
+                        -- Must fetch new TX descriptor.
+                        v_burstreq  := '1';
+                        v.hwrite    := '0';
+                        v.haddr     := msti.txdesc_ptr & "0";
+                        v.mstate    := st_txgetdesc;
+                    end if;
+                end if;
+
+            when st_rxgetdesc =>
+                -- Read RX descriptor flags from memory.
+                v_burstreq  := '1';
+                v.hwrite    := '0';
+                v.rxdes_len := v_hrdata(15 downto 2);
+                v.rxdes_en  := v_hrdata(16);
+                v.rxdes_wr  := v_hrdata(17);
+                v.rxdes_ie  := v_hrdata(18);
+                v.rxdes_eop := '0';
+                v.rxdes_eep := '0';
+                v.rxdes_pos := (others => '0');
+                if v_burstack = '1' then
+                    -- Got descriptor flags.
+                    v_burstreq  := '0';
+                    v.mstate    := st_rxgetptr;
+                end if;
+
+            when st_rxgetptr =>
+                -- Read RX data pointer from memory.
+                v.rxaddr    := v_hrdata(31 downto 2);
+                v.haddr     := v_hrdata(31 downto 2);
+                v.firstword := '1';
+                if v_burstack = '1' then
+                    -- Got data pointer.
+                    if r.rxdes_en = '1' then
+                        -- Start transfer.
+                        v_burstreq  := '1';
+                        v.hwrite    := '1';
+                        v.mstate    := st_rxtransfer;
+                    else
+                        -- Reached end of valid descriptors; stop.
+                        v.rxdma_act := '0';
+                        v.mstate    := st_idle;
+                    end if;
+                end if;
+
+            when st_rxtransfer =>
+                -- Continue an RX transfer.
+                v_burstreq  := '1';
+                v.hwrite    := '1';
+                v.firstword := '0';
+                if v_burstack = '1' or r.firstword = '1' then
+                    -- Setup first/next data word.
+                    v.hwdata    := msti.rxfifo_rdata(31 downto 0);
+                    v_rxfifo_read := '1';
+                    -- Update pointers.
+                    v.rxdes_len := std_logic_vector(unsigned(r.rxdes_len) - 1);
+                    v.rxdes_pos := std_logic_vector(unsigned(r.rxdes_pos) + 4);
+                    v.rxaddr    := std_logic_vector(unsigned(r.rxaddr) + 1);
+                    -- Detect EOP/EEP.
+                    v.rxdes_eop :=
+                        (msti.rxfifo_rdata(35) and not msti.rxfifo_rdata(24)) or
+                        (msti.rxfifo_rdata(34) and not msti.rxfifo_rdata(16)) or
+                        (msti.rxfifo_rdata(33) and not msti.rxfifo_rdata(8)) or
+                        (msti.rxfifo_rdata(32) and not msti.rxfifo_rdata(0));
+                    v.rxdes_eep :=
+                        (msti.rxfifo_rdata(35) and msti.rxfifo_rdata(24)) or
+                        (msti.rxfifo_rdata(34) and msti.rxfifo_rdata(16)) or
+                        (msti.rxfifo_rdata(33) and msti.rxfifo_rdata(8)) or
+                        (msti.rxfifo_rdata(32) and msti.rxfifo_rdata(0));
+                    -- Adjust frame length in case of EOP/EEP.
+                    if msti.rxfifo_rdata(35) = '1' then
+                        v.rxdes_pos := r.rxdes_pos(r.rxdes_pos'high downto 2) & "00";
+                    elsif msti.rxfifo_rdata(34) = '1' then
+                        v.rxdes_pos := r.rxdes_pos(r.rxdes_pos'high downto 2) & "01";
+                    elsif msti.rxfifo_rdata(33) = '1' then
+                        v.rxdes_pos := r.rxdes_pos(r.rxdes_pos'high downto 2) & "10";
+                    elsif msti.rxfifo_rdata(32) = '1' then
+                        v.rxdes_pos := r.rxdes_pos(r.rxdes_pos'high downto 2) & "11";
+                    end if;
+                    -- Stop at end of requested length or end of packet or fifo empty.
+                    if msti.rxfifo_nxempty = '1' or
+                       orv(msti.rxfifo_rdata(35 downto 32)) = '1' or
+                       unsigned(r.rxdes_len) = 1 then
+                        v_burstreq  := '0';
+                        v.mstate    := st_rxfinal;
+                    end if;
+                    -- Stop at max burst length boundary.
+                    if (andv(r.rxaddr(maxburst+1 downto 2)) = '1') then
+                        v_burstreq  := '0';
+                        v.mstate    := st_rxfinal;
+                    end if;
+                end if;
+
+            when st_rxfinal =>
+                -- Last data cycle of an RX transfer.
+                if v_burstack = '1' then
+                    if unsigned(r.rxdes_len) = 0 or
+                       r.rxdes_eop = '1' or r.rxdes_eep = '1' then
+                        -- End of frame; write back descriptor.
+                        v_burstreq  := '1';
+                        v.hwrite    := '1';
+                        v.haddr     := msti.rxdesc_ptr & "0";
+                        v.rxdesc_next := '1';
+                        v.mstate    := st_rxputdesc;
+                    else
+                        -- Go through st_idle to pick up more work.
+                        v.mstate    := st_idle;
+                    end if;
+                end if;
+                -- Give preference to TX work since we just did some RX work.
+                v.prefertx  := '1';
+
+            when st_rxputdesc =>
+                -- Write back RX descriptor.
+                v.hwdata(15 downto 0) := r.rxdes_pos;
+                v.hwdata(16)  := '0';
+                v.hwdata(17)  := r.rxdes_wr;
+                v.hwdata(18)  := r.rxdes_ie;
+                v.hwdata(19)  := '1';
+                v.hwdata(20)  := r.rxdes_eop;
+                v.hwdata(21)  := r.rxdes_eep;
+                v.hwdata(31 downto 22) := (others => '0');
+                if v_burstack = '1' then
+                    -- Frame done.
+                    v.rxdes_en      := '0';
+                    v.int_rxdesc    := r.rxdes_ie;
+                    v.int_rxpacket  := r.rxdes_eop or r.rxdes_eep;
+                    -- Go to st_idle.
+                    v.mstate    := st_idle;
+                end if;
+
+            when st_txgetdesc =>
+                -- Read TX descriptor flags from memory.
+                v_burstreq  := '1';
+                v.hwrite    := '0';
+                v.txdes_len := v_hrdata(15 downto 0);
+                v.txdes_en  := v_hrdata(16);
+                v.txdes_wr  := v_hrdata(17);
+                v.txdes_ie  := v_hrdata(18);
+                v.txdes_eop := v_hrdata(20);
+                v.txdes_eep := v_hrdata(21);
+                if v_burstack = '1' then
+                    -- Got descriptor flags.
+                    v_burstreq  := '0';
+                    v.mstate    := st_txgetptr;
+                end if;
+
+            when st_txgetptr =>
+                -- Read TX data pointer from memory.
+                v.txaddr    := v_hrdata(31 downto 2);
+                if v_burstack = '1' then
+                    -- Got data pointer.
+                    if r.txdes_en = '1' then
+                        -- Start transfer.
+                        if unsigned(r.txdes_len) = 0 then
+                            -- Only send EOP/EEP and write back descriptor.
+                            v_burstreq  := '1';
+                            v.hwrite    := '1';
+                            v.haddr     := msti.txdesc_ptr & "0";
+                            v.txdesc_next := '1';
+                            v.mstate    := st_txputdesc;
+                        else
+                            v_burstreq  := '1';
+                            v.hwrite    := '0';
+                            v.haddr     := v_hrdata(31 downto 2);
+                            if unsigned(r.txdes_len) <= 4 then
+                                -- Transfer only one word.
+                                v.mstate    := st_txfinal;
+                            else
+                                v.mstate    := st_txtransfer;
+                            end if;
+                        end if;
+                    else
+                        -- Reached end of valid descriptors; stop.
+                        v.txdma_act := '0';
+                        v.mstate    := st_idle;
+                    end if;
+                end if;
+
+            when st_txtransfer =>
+                -- Continue an TX transfer.
+                v_burstreq  := '1';
+                v.hwrite    := '0';
+                if v_burstack = '1' then
+                    -- Got next data word from memory.
+                    v_txfifo_write  := '1';
+                    -- Update pointers.
+                    v.txdes_len := std_logic_vector(unsigned(r.txdes_len) - 4);
+                    v.txaddr    := std_logic_vector(unsigned(r.txaddr) + 1);
+                    -- Handle end of burst/transfer.
+                    if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
+                        -- This was the last data cycle before the max burst boundary.
+                        -- Go through st_idle to pick up more work.
+                        v_burstreq  := '0';
+                        v.mstate    := st_idle;
+                    elsif msti.txfifo_nxfull = '1' then
+                        -- Fifo full; stop transfer, ignore final data cycle.
+                        v_burstreq  := '0';
+                        v.mstate    := st_txskip;
+                    elsif unsigned(r.txdes_len) <= 8 then
+                        -- Stop at end of requested length (one more data cycle).
+                        v_burstreq  := '0';
+                        v.mstate    := st_txfinal;
+                    elsif andv(r.txaddr(maxburst+1 downto 3)) = '1' then
+                        -- Stop at max burst length boundary (one more data cycle).
+                        v_burstreq  := '0';
+                    end if;
+                else
+                    if andv(r.txaddr(maxburst+1 downto 2)) = '1' then
+                        -- Stop at max burst length boundary (just one more data cycle).
+                        v_burstreq  := '0';
+                    end if;
+                end if;
+
+            when st_txfinal =>
+                -- Last data cycle of a TX descriptor (1 <= txdes_len <= 4).
+                if v_burstack = '1' then
+                    -- Got last data word from memory.
+                    v_txfifo_write  := '1';
+                    v.txdes_len := std_logic_vector(unsigned(r.txdes_len) - 4);
+                    -- Insert EOP in last word if needed.
+                    -- (Or set bit 7 in the flag byte to indicate that the
+                    --  frame ends while the packet continues.)
+                    case r.txdes_len(1 downto 0) is
+                        when "01" =>
+                            v_txfifo_wdata(34)  := '1';
+                            v_txfifo_wdata(23)  := not (r.txdes_eop or r.txdes_eep);
+                            v_txfifo_wdata(22 downto 17) := "000000";
+                            v_txfifo_wdata(16)  := r.txdes_eep;
+                        when "10" =>
+                            v_txfifo_wdata(33)  := '1';
+                            v_txfifo_wdata(15)  := not (r.txdes_eop or r.txdes_eep);
+                            v_txfifo_wdata(14 downto 9) := "000000";
+                            v_txfifo_wdata(8)   := r.txdes_eep;
+                        when "11" =>
+                            v_txfifo_wdata(32)  := '1';
+                            v_txfifo_wdata(7)   := not (r.txdes_eop or r.txdes_eep);
+                            v_txfifo_wdata(6 downto 1) := "000000";
+                            v_txfifo_wdata(0)   := r.txdes_eep;
+                        when others =>
+                            -- txdes_len = 4
+                            -- Store 4 data bytes now; store EOP in st_txputdesc (if needed).
+                    end case;
+                    if msti.txfifo_nxfull = '1' and r.txdes_len(1 downto 0) = "00" then
+                        -- Fifo full so no room to store EOP.
+                        v.mstate    := st_idle;
+                        v.haddr     := msti.txdesc_ptr & "0";
+                    else
+                        -- Prepare to write back descriptor.
+                        v_burstreq  := '1';
+                        v.hwrite    := '1';
+                        v.haddr     := msti.txdesc_ptr & "0";
+                        v.txdesc_next := '1';
+                        v.mstate    := st_txputdesc;
+                    end if;
+                end if;
+
+            when st_txputdesc =>
+                -- Write back TX descriptor.
+                v.hwdata(15 downto 0) := (others => '0');
+                v.hwdata(16)  := '0';
+                v.hwdata(17)  := r.txdes_wr;
+                v.hwdata(18)  := r.txdes_ie;
+                v.hwdata(19)  := '1';
+                v.hwdata(20)  := r.txdes_eop;
+                v.hwdata(21)  := r.txdes_eep;
+                v.hwdata(31 downto 22) := (others => '0');
+                if v_burstack = '1' then
+                    if r.txdes_len(1 downto 0) = "00" and
+                       (r.txdes_eop = '1' or r.txdes_eep = '1') then
+                        -- Store EOP in TX fifo.
+                        v_txfifo_write  := '1';
+                        v_txfifo_wdata(35)  := '1';
+                        v_txfifo_wdata(31 downto 25) := "0000000";
+                        v_txfifo_wdata(24)  := r.txdes_eep;
+                    end if;
+                    -- Frame done.
+                    v.txdes_en  := '0';
+                    v.int_txdesc  := r.txdes_ie;
+                    -- Go to st_idle and give preference to RX work.
+                    v.mstate    := st_idle;
+                end if;
+
+            when st_txskip =>
+                -- Ignore last data cycle of burst because TX fifo is full.
+                if v_burstack = '1' then
+                    v.mstate    := st_idle;
+                end if;
+
+        end case;
+
+        -- Abort DMA when an AHB error occurs.
+        if r.ahberror = '1' then
+            v.rxdma_act := '0';
+            v.txdma_act := '0';
+            v.mstate    := st_idle;
+        end if;
+
+
+        --
+        -- Burst state machine.
+        --
+        -- A transfer starts when the main state machine combinatorially pulls
+        -- v_burstreq high and assigns v.haddr and v.hwrite (i.e. r.haddr and
+        -- r.hwrite must be valid in the first clock cycle AFTER rising v_burstreq).
+        -- In case of a write transfer, r.hwdata must be valid in the second
+        -- clock cycle after rising v_burstreq.
+        --
+        -- During the transfer, the burst state machine announces each word
+        -- with a v_burstack pulse. During a read transfer, ahbi.hrdata is
+        -- valid when v_burstack is high. During a write transfer, a next
+        -- word must be assigned to v.hwdata on the v_burstack pulse.
+        --
+        -- For a single-word transfer, v_burstreq should be high for only one
+        -- clock cycle. For a multi-word transfer, v_burstreq should be high
+        -- until the last-but-one v_burstack pulse. I.e. after v_burstreq is
+        -- released combinatorially on a v_burstack pulse, one last v_burstack
+        -- pulse will follow.
+        --
+        -- The burst state machine transparently handles bus arbitration and
+        -- retrying of transfers. In case of a non-retryable error, r.ahberror
+        -- is set high and further transfers are blocked. The main state
+        -- machine is responsible for ensuring that bursts do not cross a
+        -- forbidden address boundary.
+        --
+        case r.burststat is
+
+            when bs_idle =>
+                -- Wait for request and bus grant.
+                -- (htrans = HTRANS_IDLE)
+                v.hbusreq   := r.hbusreq or v_burstreq;
+                if (r.hbusreq = '1' or v_burstreq = '1') and
+                   ahbi.hready = '1' and
+                   ahbi.hgrant(hindex) = '1' then
+                    -- Start burst.
+                    v.burststat := bs_setup;
+                end if;
+                -- Block new bursts after an error occurred.
+                if r.ahberror = '1' then
+                    v.hbusreq   := '0';
+                    v.burststat := bs_idle;
+                end if;
+
+            when bs_setup =>
+                -- First address cycle.
+                -- (htrans = HTRANS_NONSEQ)
+                v.hbusreq   := '1';
+                if ahbi.hready = '1' then
+                    -- Increment address and continue burst in bs_active.
+                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
+                    v.burststat := bs_active;
+                    -- Stop burst when application ends the transfer.
+                    v.hbusreq   := v_burstreq;
+                    if v_burstreq = '0' then
+                        v.burststat := bs_end;
+                    end if;
+                    -- Stop burst when we are kicked off the bus.
+                    if ahbi.hgrant(hindex) = '0' then
+                        v.burststat := bs_end;
+                    end if;
+                end if;
+
+            when bs_active =>
+                -- Continue burst.
+                -- (htrans = HTRANS_SEQ)
+                v.hbusreq   := '1';
+                if ahbi.hresp /= HRESP_OKAY then
+                    -- Error response from slave.
+                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
+                    if ahbi.hresp = HRESP_ERROR then
+                        -- Permanent error.
+                        v.ahberror  := '1';
+                        v.hbusreq   := '0';
+                    else
+                        -- Must retry request.
+                        v.hbusreq   := '1';
+                    end if;
+                    v.burststat := bs_idle;
+                elsif ahbi.hready = '1' then
+                    -- Increment address.
+                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) + 1);
+                    -- Stop burst when application ends the transfer.
+                    v.hbusreq   := v_burstreq;
+                    if v_burstreq = '0' then
+                        v.burststat := bs_end;
+                    end if;
+                    -- Stop burst when we are kicked off the bus.
+                    if ahbi.hgrant(hindex) = '0' then
+                        v.burststat := bs_end;
+                    end if;
+                end if;
+
+            when bs_end =>
+                -- Last data cycle of burst.
+                -- (htrans = HTRANS_IDLE)
+                v.hbusreq   := r.hbusreq or v_burstreq;
+                if ahbi.hresp /= HRESP_OKAY then
+                    -- Error response from slave.
+                    v.haddr(maxburst+1 downto 2) := std_logic_vector(unsigned(r.haddr(maxburst+1 downto 2)) - 1);
+                    if ahbi.hresp = HRESP_ERROR then
+                        -- Permanent error.
+                        v.ahberror  := '1';
+                        v.hbusreq   := '0';
+                    else
+                        -- Must retry request.
+                        v.hbusreq   := '1';
+                    end if;
+                    v.burststat := bs_idle;
+                elsif ahbi.hready = '1' then
+                    -- Burst complete.
+                    if (r.hbusreq = '1' or v_burstreq = '1') and
+                       ahbi.hgrant(hindex) = '1' then
+                        -- Immediately start next burst.
+                        v.burststat := bs_setup;
+                    else
+                        v.burststat := bs_idle;
+                    end if;
+                end if;
+
+        end case;
+
+
+        --
+        -- Drive output signals.
+        --
+        ahbo.hbusreq    <= r.hbusreq;
+        if r.burststat = bs_setup then
+            ahbo.htrans     <= HTRANS_NONSEQ;
+        elsif r.burststat = bs_active then
+            ahbo.htrans     <= HTRANS_SEQ;
+        else
+            ahbo.htrans     <= HTRANS_IDLE;
+        end if;
+        ahbo.haddr      <= r.haddr & "00";
+        ahbo.hwrite     <= r.hwrite;
+        ahbo.hwdata     <= ahbdrivedata(r.hwdata);
+        ahbo.hlock      <= '0';             -- never lock the bus
+        ahbo.hsize      <= HSIZE_WORD;      -- always 32-bit words
+        ahbo.hburst     <= HBURST_INCR;     -- undetermined incremental burst
+        ahbo.hprot      <= "0011";          -- not cacheable, privileged, data
+        ahbo.hirq       <= (others => '0'); -- no interrupts via AHB bus
+        ahbo.hconfig    <= hconfig;         -- AHB plug&play data
+        ahbo.hindex     <= hindex;          -- index feedback
+
+        msto.rxdma_act      <= r.rxdma_act;
+        msto.txdma_act      <= r.txdma_act;
+        msto.ahberror       <= r.ahberror;
+        msto.int_rxdesc     <= r.int_rxdesc;
+        msto.int_txdesc     <= r.int_txdesc;
+        msto.int_rxpacket   <= r.int_rxpacket;
+        msto.rxdesc_next    <= r.rxdesc_next;
+        msto.rxdesc_wrap    <= r.rxdesc_next and r.rxdes_wr;
+        msto.txdesc_next    <= r.txdesc_next;
+        msto.txdesc_wrap    <= r.txdesc_next and r.txdes_wr;
+        msto.rxfifo_read    <= v_rxfifo_read;
+        msto.txfifo_write   <= v_txfifo_write;
+        msto.txfifo_wdata   <= v_txfifo_wdata;
+
+
+        --
+        -- Reset.
+        --
+        if rstn = '0' then
+            v   := regs_reset;
+        end if;
+
+
+        --
+        -- Update registers.
+        --
+        rin <= v;
+    end process;
+
+
+    --
+    -- Synchronous process: update registers.
+    --
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwahbmst_arch;
diff --git a/lib/opencores/spw_light/spwamba.vhd b/lib/opencores/spw_light/spwamba.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwamba.vhd
@@ -0,0 +1,886 @@
+--
+--  SpaceWire core with AMBA interface.
+--
+--  APB registers:
+--
+--      Address 0x00: Control Register
+--          bit 0     Reset spwamba core (auto-clear)
+--          bit 1     Reset DMA engines (auto-clear)
+--          bit 2     Link start
+--          bit 3     Link autostart
+--          bit 4     Link disable
+--          bit 5     Enable timecode transmission through tick_in signal
+--          bit 6     Start RX DMA (auto-clear)
+--          bit 7     Start TX DMA (auto-clear)
+--          bit 8     Cancel TX DMA and discard TX data queue (auto-clear)
+--          bit 9     Enable interrupt on link up/down
+--          bit 10    Enable interrupt on time code received
+--          bit 11    Enable interrupt on RX descriptor
+--          bit 12    Enable interrupt on TX descriptor
+--          bit 13    Enable interrupt on RX packet
+--          bit 27:24 desctablesize (read-only)
+--
+--      Address 0x04: Status Register
+--          bit 1:0   Link status: 0=off, 1=started, 2=connecting, 3=run
+--          bit 2     Got disconnect error (sticky)
+--          bit 3     Got parity error (sticky)
+--          bit 4     Got escape error (sticky)
+--          bit 5     Got credit error (sticky)
+--          bit 6     RX DMA enabled
+--          bit 7     TX DMA enabled
+--          bit 8     AHB error occurred (reset DMA engine to clear)
+--          bit 9     Reserved
+--          bit 10    Received timecode (sticky)
+--          bit 11    Finished RX descriptor with IE='1' (sticky)
+--          bit 12    Finished TX descriptor with IE='1' (sticky)
+--          bit 13    Received packet (sticky)
+--          bit 14    RX buffer empty after packet
+--
+--          Sticky bits are reset by writing a '1' bit to the corresponding
+--          bit position(s).
+--
+--      Address 0x08: Transmission Clock Scaler
+--          bit 7:0   txclk division factor minus 1
+--
+--      Address 0x0c: Timecode Register
+--          bit 5:0   Last received timecode value (read-only)
+--          bit 7:6   Control bits received with last timecode (read-only)
+--          bit 13:8  Timecode value to send on next tick_in (auto-increment)
+--          bit 15:14 Reserved (write as zero)
+--          bit 16    Write '1' to send a timecode (auto-clear)
+--
+--      Address 0x10: Descriptor pointer for RX DMA
+--          bit 2:0                 Reserved, write as zero
+--          bit desctablesize+2:3   Descriptor index (auto-increment)
+--          bit 31:desctablesize+3  Fixed address bits of descriptor table
+--
+--          For example, if desctablesize = 10, a 8192-byte area is
+--          determined by bits 31:13. This area has room for 1024 descriptors
+--          of 8 bytes each. Bits 12:3 point to the current descriptor within
+--          the table.
+--      
+--      Address 0x14: Descriptor pointer for TX DMA
+--          bit 2:0                 Reserved, write as zero
+--          bit desctablesize+2:3   Descriptor index (auto-increment)
+--          bit 31:desctablesize+3  Fixed address bits of descriptor table
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.amba.all;
+use grlib.devices.all;
+use grlib.stdlib.all;
+use work.spwpkg.all;
+use work.spwambapkg.all;
+
+entity spwamba is
+
+    generic (
+        -- Technology selection for FIFO memories.
+        tech:           integer range 0 to NTECH := DEFFABTECH;
+
+        -- AHB master index.
+        hindex:         integer;
+
+        -- APB slave index.
+        pindex:         integer;
+
+        -- Bits 19 to 8 of the APB address range.
+        paddr:          integer;
+
+        -- Mask for APB address bits 19 to 8.
+        pmask:          integer := 16#fff#;
+
+        -- Index of the interrupt request line.
+        pirq:           integer;
+
+        -- System clock frequency in Hz.
+        -- This must be set to the frequency of "clk". It is used to setup
+        -- counters for reset timing, disconnect timeout and to transmit
+        -- at 10 Mbit/s during the link handshake.
+        sysfreq:        real;
+
+        -- Transmit clock frequency in Hz (only if tximpl = impl_fast).
+        -- This must be set to the frequency of "txclk". It is used to
+        -- transmit at 10 Mbit/s during the link handshake.
+        txclkfreq:      real := 0.0;
+
+        -- Selection of a receiver front-end implementation.
+        rximpl:         spw_implementation_type := impl_generic;
+
+        -- Maximum number of bits received per system clock
+        -- (must be 1 in case of impl_generic).
+        rxchunk:        integer range 1 to 4 := 1;
+
+        -- Selection of a transmitter implementation.
+        tximpl:         spw_implementation_type := impl_generic;
+
+        -- Enable capability to generate time-codes.
+        timecodegen:    boolean := true;
+
+        -- Size of the receive FIFO as the 2-logarithm of the number of words.
+        -- Must be at least 6 (64 words = 256 bytes).
+        rxfifosize:     integer range 6 to 12 := 8;
+
+        -- Size of the transmit FIFO as the 2-logarithm of the number of words.
+        txfifosize:     integer range 2 to 12 := 8;
+
+        -- Size of the DMA descriptor tables as the 2-logarithm of the number
+        -- of descriptors.
+        desctablesize:  integer range 4 to 14 := 10;
+
+        -- Maximum burst length as the 2-logarithm of the number of words (default 8 words).
+        maxburst:       integer range 1 to 8 := 3
+    );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Receiver sample clock (only for impl_fast)
+        rxclk:      in  std_logic;
+
+        -- Transmit clock (only for impl_fast)
+        txclk:      in  std_logic;
+
+        -- Synchronous reset (active-low).
+        rstn:       in  std_logic;
+
+        -- APB slave input signals.
+        apbi:       in  apb_slv_in_type;
+
+        -- APB slave output signals.
+        apbo:       out apb_slv_out_type;
+
+        -- AHB master input signals.
+        ahbi:       in  ahb_mst_in_type;
+
+        -- AHB master output signals.
+        ahbo:       out ahb_mst_out_type;
+
+        -- Pulse for TimeCode generation.
+        tick_in:    in  std_logic;
+
+        -- High for one clock cycle if a TimeCode was just received.
+        tick_out:   out std_logic;
+
+        -- Data In signal from SpaceWire bus.
+        spw_di:     in  std_logic;
+
+        -- Strobe In signal from SpaceWire bus.
+        spw_si:     in  std_logic;
+
+        -- Data Out signal to SpaceWire bus.
+        spw_do:     out std_logic;
+
+        -- Strobe Out signal to SpaceWire bus.
+        spw_so:     out std_logic
+    );
+
+end entity spwamba;
+
+architecture spwamba_arch of spwamba is
+
+    -- Reset time (6.4 us) in system clocks
+    constant reset_time:        integer := integer(sysfreq * 6.4e-6);
+
+    -- Disconnect time (850 ns) in system clocks
+    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
+
+    -- Initial tx clock scaler (10 Mbit).
+    type impl_to_real_type is array(spw_implementation_type) of real;
+    constant tximpl_to_txclk_freq: impl_to_real_type :=
+        (impl_generic => sysfreq, impl_fast => txclkfreq);
+    constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
+    constant default_divcnt:    std_logic_vector(7 downto 0) :=
+        std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
+
+    -- Registers.
+    type regs_type is record
+        -- packet state
+        rxpacket:       std_logic;      -- '1' when receiving a packet
+        rxeep:          std_logic;      -- '1' when rx EEP character pending
+        txpacket:       std_logic;      -- '1' when transmitting a packet
+        txdiscard:      std_logic;      -- '1' when discarding a tx packet
+        -- RX fifo state
+        rxfifo_raddr:   std_logic_vector(rxfifosize-1 downto 0);
+        rxfifo_waddr:   std_logic_vector(rxfifosize-1 downto 0);
+        rxfifo_wdata:   std_logic_vector(35 downto 0);
+        rxfifo_write:   std_ulogic;
+        rxfifo_empty:   std_ulogic;
+        rxfifo_bytemsk: std_logic_vector(2 downto 0);
+        rxroom:         std_logic_vector(5 downto 0);
+        -- TX fifo state
+        txfifo_raddr:   std_logic_vector(txfifosize-1 downto 0);
+        txfifo_waddr:   std_logic_vector(txfifosize-1 downto 0);
+        txfifo_empty:   std_ulogic;
+        txfifo_nxfull:  std_ulogic;
+        txfifo_highw:   std_ulogic;
+        txfifo_bytepos: std_logic_vector(1 downto 0);
+        -- APB registers
+        ctl_reset:      std_ulogic;
+        ctl_resetdma:   std_ulogic;
+        ctl_linkstart:  std_ulogic;
+        ctl_autostart:  std_ulogic;
+        ctl_linkdis:    std_ulogic;
+        ctl_ticken:     std_ulogic;
+        ctl_rxstart:    std_ulogic;
+        ctl_txstart:    std_ulogic;
+        ctl_txcancel:   std_ulogic;
+        ctl_ielink:     std_ulogic;
+        ctl_ietick:     std_ulogic;
+        ctl_ierxdesc:   std_ulogic;
+        ctl_ietxdesc:   std_ulogic;
+        ctl_ierxpacket: std_ulogic;
+        sta_link:       std_logic_vector(1 downto 0);
+        sta_errdisc:    std_ulogic;
+        sta_errpar:     std_ulogic;
+        sta_erresc:     std_ulogic;
+        sta_errcred:    std_ulogic;
+        sta_gottick:    std_ulogic;
+        sta_rxdesc:     std_ulogic;
+        sta_txdesc:     std_ulogic;
+        sta_rxpacket:   std_ulogic;
+        sta_rxempty:    std_ulogic;
+        txdivcnt:       std_logic_vector(7 downto 0);
+        time_in:        std_logic_vector(5 downto 0);
+        tick_in:        std_ulogic;
+        rxdesc_ptr:     std_logic_vector(31 downto 3);
+        txdesc_ptr:     std_logic_vector(31 downto 3);
+        -- APB interrupt request
+        irq:            std_ulogic;
+    end record;
+
+    constant regs_reset: regs_type := (
+        rxpacket        => '0',
+        rxeep           => '0',
+        txpacket        => '0',
+        txdiscard       => '0',
+        rxfifo_raddr    => (others => '0'),
+        rxfifo_waddr    => (others => '0'),
+        rxfifo_wdata    => (others => '0'),
+        rxfifo_write    => '0',
+        rxfifo_empty    => '1',
+        rxfifo_bytemsk  => "111",
+        rxroom          => (others => '1'),
+        txfifo_raddr    => (others => '0'),
+        txfifo_waddr    => (others => '0'),
+        txfifo_empty    => '1',
+        txfifo_nxfull   => '0',
+        txfifo_highw    => '0',
+        txfifo_bytepos  => "00",
+        ctl_reset       => '0',
+        ctl_resetdma    => '0',
+        ctl_linkstart   => '0',
+        ctl_autostart   => '0',
+        ctl_linkdis     => '0',
+        ctl_ticken      => '0',
+        ctl_rxstart     => '0',
+        ctl_txstart     => '0',
+        ctl_txcancel    => '0',
+        ctl_ielink      => '0',
+        ctl_ietick      => '0',
+        ctl_ierxdesc    => '0',
+        ctl_ietxdesc    => '0',
+        ctl_ierxpacket  => '0',
+        sta_link        => "00",
+        sta_errdisc     => '0',
+        sta_errpar      => '0',
+        sta_erresc      => '0',
+        sta_errcred     => '0',
+        sta_gottick     => '0',
+        sta_rxdesc      => '0',
+        sta_txdesc      => '0',
+        sta_rxpacket    => '0',
+        sta_rxempty     => '1',
+        txdivcnt        => default_divcnt,
+        time_in         => (others => '0'),
+        tick_in         => '0',
+        rxdesc_ptr      => (others => '0'),
+        txdesc_ptr      => (others => '0'),
+        irq             => '0' );
+
+    signal r: regs_type := regs_reset;
+    signal rin: regs_type;
+
+    -- Component interface signals.
+    signal recv_rxen:       std_logic;
+    signal recvo:           spw_recv_out_type;
+    signal recv_inact:      std_logic;
+    signal recv_inbvalid:   std_logic;
+    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
+    signal xmit_rst:        std_logic;
+    signal xmiti:           spw_xmit_in_type;
+    signal xmito:           spw_xmit_out_type;
+    signal xmit_divcnt:     std_logic_vector(7 downto 0);
+    signal link_rst:        std_logic;
+    signal linki:           spw_link_in_type;
+    signal linko:           spw_link_out_type;
+    signal msti:            spw_ahbmst_in_type;
+    signal msto:            spw_ahbmst_out_type;
+    signal ahbmst_rstn:     std_logic;
+
+    -- Memory interface signals.
+    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize-1 downto 0);
+    signal s_rxfifo_rdata:  std_logic_vector(35 downto 0);
+    signal s_rxfifo_wen:    std_logic;
+    signal s_rxfifo_waddr:  std_logic_vector(rxfifosize-1 downto 0);
+    signal s_rxfifo_wdata:  std_logic_vector(35 downto 0);
+    signal s_txfifo_raddr:  std_logic_vector(txfifosize-1 downto 0);
+    signal s_txfifo_rdata:  std_logic_vector(35 downto 0);
+    signal s_txfifo_wen:    std_logic;
+    signal s_txfifo_waddr:  std_logic_vector(txfifosize-1 downto 0);
+    signal s_txfifo_wdata:  std_logic_vector(35 downto 0);
+
+
+    -- APB slave plug&play configuration
+    constant REVISION:      integer := 0;
+    constant pconfig:       apb_config_type := (
+        0 => ahb_device_reg(VENDOR_OPENCORES, DEVICE_SPACEWIRELIGHT, 0, REVISION, pirq),
+        1 => apb_iobar(paddr, pmask) );
+
+    -- AHB master plug&play configuration
+    constant hconfig:       ahb_config_type := (
+        0 => ahb_device_reg(VENDOR_OPENCORES, DEVICE_SPACEWIRELIGHT, 0, REVISION, 0),
+        others => zero32 );
+
+begin
+
+    -- Instantiate link controller.
+    link_inst: spwlink
+        generic map (
+            reset_time  => reset_time )
+        port map (
+            clk         => clk,
+            rst         => link_rst,
+            linki       => linki,
+            linko       => linko,
+            rxen        => recv_rxen,
+            recvo       => recvo,
+            xmiti       => xmiti,
+            xmito       => xmito );
+
+    -- Instantiate receiver.
+    recv_inst: spwrecv
+        generic map(
+            disconnect_time => disconnect_time,
+            rxchunk     => rxchunk )
+        port map (
+            clk         => clk,
+            rxen        => recv_rxen,
+            recvo       => recvo,
+            inact       => recv_inact,
+            inbvalid    => recv_inbvalid,
+            inbits      => recv_inbits );
+
+    -- Instantiate receiver front-end.
+    recvfront_sel0: if rximpl = impl_generic generate
+        recvfront_generic_inst: spwrecvfront_generic
+            port map (
+                clk         => clk,
+                rxen        => recv_rxen,
+                inact       => recv_inact,
+                inbvalid    => recv_inbvalid,
+                inbits      => recv_inbits,
+                spw_di      => spw_di,
+                spw_si      => spw_si );
+    end generate;
+    recvfront_sel1: if rximpl = impl_fast generate
+        recvfront_fast_inst: spwrecvfront_fast
+            generic map (
+                rxchunk     => rxchunk )
+            port map (
+                clk         => clk,
+                rxclk       => rxclk,
+                rxen        => recv_rxen,
+                inact       => recv_inact,
+                inbvalid    => recv_inbvalid,
+                inbits      => recv_inbits,
+                spw_di      => spw_di,
+                spw_si      => spw_si );
+    end generate;
+
+    -- Instantiate transmitter.
+    xmit_sel0: if tximpl = impl_generic generate
+        xmit_inst: spwxmit
+            port map (
+                clk     => clk,
+                rst     => xmit_rst,
+                divcnt  => xmit_divcnt,
+                xmiti   => xmiti,
+                xmito   => xmito,
+                spw_do  => spw_do,
+                spw_so  => spw_so );
+    end generate;
+    xmit_sel1: if tximpl = impl_fast generate
+        xmit_fast_inst: spwxmit_fast
+            port map (
+                clk     => clk,
+                txclk   => txclk,
+                rst     => xmit_rst,
+                divcnt  => xmit_divcnt,
+                xmiti   => xmiti,
+                xmito   => xmito,
+                spw_do  => spw_do,
+                spw_so  => spw_so );
+    end generate;
+
+    -- Instantiate RX FIFO.
+    rxfifo: syncram_2p
+        generic map (
+            tech        => tech,
+            abits       => rxfifosize,
+            dbits       => 36,
+            sepclk      => 0 )
+        port map (
+            rclk        => clk,
+            renable     => '1',
+            raddress    => s_rxfifo_raddr,
+            dataout     => s_rxfifo_rdata,
+            wclk        => clk,
+            write       => s_rxfifo_wen,
+            waddress    => s_rxfifo_waddr,
+            datain      => s_rxfifo_wdata );
+
+    -- Instantiate TX FIFO.
+    txfifo: syncram_2p
+        generic map (
+            tech        => tech,
+            abits       => txfifosize,
+            dbits       => 36,
+            sepclk      => 0 )
+        port map (
+            rclk        => clk,
+            renable     => '1',
+            raddress    => s_txfifo_raddr,
+            dataout     => s_txfifo_rdata,
+            wclk        => clk,
+            write       => s_txfifo_wen,
+            waddress    => s_txfifo_waddr,
+            datain      => s_txfifo_wdata );
+
+    -- Instantiate AHB master.
+    ahbmst: spwahbmst
+        generic map (
+            hindex      => hindex,
+            hconfig     => hconfig,
+            maxburst    => maxburst )
+        port map (
+            clk         => clk,
+            rstn        => ahbmst_rstn,
+            msti        => msti,
+            msto        => msto,
+            ahbi        => ahbi,
+            ahbo        => ahbo );
+
+
+    --
+    -- Combinatorial process
+    --
+    process (r, linko, msto, s_rxfifo_rdata, s_txfifo_rdata, rstn, apbi, tick_in)  is
+        variable v:             regs_type;
+        variable v_tmprxroom:   unsigned(rxfifosize-1 downto 0);
+        variable v_prdata:      std_logic_vector(31 downto 0);
+        variable v_irq:         std_logic_vector(NAHBIRQ-1 downto 0);
+        variable v_txfifo_bytepos: integer range 0 to 3;
+    begin
+        v           := r;
+        v_tmprxroom := to_unsigned(0, rxfifosize);
+        v_prdata    := (others => '0');
+        v_irq           := (others => '0');
+        v_irq(pirq)     := r.irq;
+
+        -- Convert RX/TX byte index to integer.
+        v_txfifo_bytepos := to_integer(unsigned(r.txfifo_bytepos));
+
+        -- Reset auto-clearing registers.
+        v.ctl_reset     := '0';
+        v.ctl_resetdma  := '0';
+        v.ctl_rxstart   := '0';
+        v.ctl_txstart   := '0';
+
+        -- Register external timecode trigger (if enabled).
+        if timecodegen and r.ctl_ticken = '1' then
+            v.tick_in   := tick_in;
+        else
+            v.tick_in   := '0';
+        end if;
+
+        -- Auto-increment timecode counter.
+        if r.tick_in = '1' then
+            v.time_in   := std_logic_vector(unsigned(r.time_in) + 1);
+        end if;
+
+        -- Keep track of whether we are sending and/or receiving a packet.
+        if linko.rxchar = '1' then
+            -- got character
+            v.rxpacket  := not linko.rxflag;
+        end if;
+        if linko.txack = '1' then
+            -- send character
+            v.txpacket  := not s_txfifo_rdata(35-v_txfifo_bytepos);
+        end if;
+
+        -- Accumulate a word to write to the RX fifo.
+        -- Note: If the EOP/EEP marker falls in the middle of a word,
+        -- subsequent bytes must be a copy of the marker, otherwise
+        -- the AHB master may not work correctly.
+        v.rxfifo_write  := '0';
+        for i in 3 downto 0 loop
+            if (i = 0) or (r.rxfifo_bytemsk(i-1) = '1') then
+                if r.rxeep = '1' then
+                    v.rxfifo_wdata(32+i)             := '1';
+                    v.rxfifo_wdata(7+8*i downto 8*i) := "00000001";
+                else
+                    v.rxfifo_wdata(32+i)             := linko.rxflag;
+                    v.rxfifo_wdata(7+8*i downto 8*i) := linko.rxdata;
+                end if;
+            end if;
+        end loop;
+        if linko.rxchar = '1' or (r.rxeep = '1' and unsigned(r.rxroom) /= 0) then
+            v.rxeep     := '0';
+            if r.rxfifo_bytemsk(0) = '0' or linko.rxflag = '1' or r.rxeep = '1' then
+                -- Flush the current word to the FIFO.
+                v.rxfifo_write   := '1';
+                v.rxfifo_bytemsk := "111";
+            else
+                -- Store one byte.
+                v.rxfifo_bytemsk := '0' & r.rxfifo_bytemsk(2 downto 1);
+            end if;
+        end if;
+
+        -- Read from TX fifo.
+        if (r.txfifo_empty = '0') and (linko.txack = '1' or r.txdiscard = '1') then
+            -- Update byte pointer.
+            if r.txfifo_bytepos = "11" or
+               s_txfifo_rdata(35-v_txfifo_bytepos) = '1' or
+               (v_txfifo_bytepos < 3 and
+                s_txfifo_rdata(34-v_txfifo_bytepos) = '1' and
+                s_txfifo_rdata(23-8*v_txfifo_bytepos) = '1') then
+                -- This is the last byte in the current word;
+                -- OR the current byte is an EOP/EEP marker;
+                -- OR the next byte in the current word is a non-EOP end-of-frame marker.
+                v.txfifo_bytepos := "00";
+                v.txfifo_raddr  := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
+            else
+                -- Move to next byte.
+                v.txfifo_bytepos := std_logic_vector(unsigned(r.txfifo_bytepos) + 1);
+            end if;
+            -- Clear discard flag when past EOP.
+            if s_txfifo_rdata(35-v_txfifo_bytepos) = '1' then
+                v.txdiscard := '0';
+            end if;
+        end if;
+
+        -- Update RX fifo pointers.
+        if msto.rxfifo_read = '1' then
+            -- Read one word.
+            v.rxfifo_raddr  := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
+        end if;
+        if r.rxfifo_write = '1' then
+            -- Write one word.
+            v.rxfifo_waddr  := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
+        end if;
+
+        -- Detect RX fifo empty (using new value of rxfifo_raddr).
+        -- Note: The FIFO is empty if head and tail pointer are equal.
+        v.rxfifo_empty  := conv_std_logic(v.rxfifo_raddr = r.rxfifo_waddr);
+
+        -- Indicate RX fifo room for SpaceWire flow control.
+        -- The flow control window is normally expressed as a number of bytes,
+        -- but we don't know how many bytes we can fit in each word because
+        -- some words are only partially used. So we report FIFO room as if
+        -- each FIFO word can hold only one byte, which is an overly
+        -- pessimistic estimate.
+        -- (Use the new value of rxfifo_waddr.)
+        v_tmprxroom     := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
+        if v_tmprxroom > 63 then
+            -- at least 64 bytes room.
+            v.rxroom    := "111111";
+        else
+            -- less than 64 bytes room.
+            -- If linko.rxchar = '1', decrease rxroom by one to account for
+            -- the pipeline delay through r.rxfifo_write.
+            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0) - 
+                             to_unsigned(conv_integer(linko.rxchar), 6));
+        end if;
+
+        -- Update TX fifo write pointer.
+        if msto.txfifo_write = '1' then
+            -- write one word.
+            v.txfifo_waddr  := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
+        end if;
+
+        -- Detect TX fifo empty.
+        -- Note: The FIFO may be either full or empty if head and tail pointer
+        -- are equal, hence the additional test for txfifo_nxfull.
+        v.txfifo_empty  := conv_std_logic(v.txfifo_raddr = r.txfifo_waddr) and not r.txfifo_nxfull;
+
+        -- Detect TX fifo full after one more write.
+        if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2, txfifosize) then
+            -- currently exactly 2 words left.
+            v.txfifo_nxfull := msto.txfifo_write;
+        end if;
+
+        -- Detect TX fifo high water mark.
+        if txfifosize > maxburst then
+            -- Indicate high water when there is no room for a maximum burst.
+            if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**maxburst + 1, txfifosize) then
+                -- currently room for exactly one maximum burst.
+                v.txfifo_highw  := msto.txfifo_write;
+            end if;
+        else
+            -- Indicate high water when more than half full.
+            if unsigned(r.txfifo_raddr) - unsigned(r.txfifo_waddr) = to_unsigned(2**(txfifosize-1), txfifosize) then
+                -- currently exactly half full.
+                v.txfifo_highw  := msto.txfifo_write;
+            end if;
+        end if;
+
+        -- Update descriptor pointers.
+        if msto.rxdesc_next = '1' then
+            if msto.rxdesc_wrap = '1' then
+                v.rxdesc_ptr(desctablesize+2 downto 3) := (others => '0');
+            else
+                v.rxdesc_ptr(desctablesize+2 downto 3) :=
+                    std_logic_vector(unsigned(r.rxdesc_ptr(desctablesize+2 downto 3)) + 1);
+            end if;
+        end if;
+        if msto.txdesc_next = '1' then
+            if msto.txdesc_wrap = '1' then
+                v.txdesc_ptr(desctablesize+2 downto 3) := (others => '0');
+            else
+                v.txdesc_ptr(desctablesize+2 downto 3) :=
+                    std_logic_vector(unsigned(r.txdesc_ptr(desctablesize+2 downto 3)) + 1);
+            end if;
+        end if;
+
+        -- If the link is lost, set a flag to discard the current packet.
+        if linko.running = '0' then
+            v.rxeep     := v.rxeep or v.rxpacket;       -- use new value of rxpacket
+            v.txdiscard := v.txdiscard or v.txpacket;   -- use new value of txpacket
+            v.rxpacket  := '0';
+            v.txpacket  := '0';
+        end if;
+
+        -- Clear the discard flag when the link is explicitly disabled.
+        if r.ctl_linkdis = '1' then
+            v.txdiscard := '0';
+        end if;
+
+        -- Extend TX cancel command until TX DMA has stopped.
+        if msto.txdma_act = '0' then
+            v.ctl_txcancel  := '0';
+        end if;
+
+        -- Update status registers.
+        v.sta_link(0)   := linko.running or linko.started;
+        v.sta_link(1)   := linko.running or linko.connecting;
+        if linko.errdisc  = '1' then v.sta_errdisc := '1'; end if;
+        if linko.errpar   = '1' then v.sta_errpar  := '1'; end if;
+        if linko.erresc   = '1' then v.sta_erresc  := '1'; end if;
+        if linko.errcred  = '1' then v.sta_errcred := '1'; end if;
+        if linko.tick_out = '1' then v.sta_gottick := '1'; end if;
+        if msto.int_rxdesc   = '1' then v.sta_rxdesc   := '1'; end if;
+        if msto.int_txdesc   = '1' then v.sta_txdesc   := '1'; end if;
+        if msto.int_rxpacket = '1' then v.sta_rxpacket := '1'; end if;
+        if msto.int_rxpacket = '1' and r.rxfifo_empty = '1' then
+            v.sta_rxempty   := '1';
+        elsif r.rxfifo_empty = '0' then
+            v.sta_rxempty   := '0';
+        end if;
+
+        -- Generate interrupt requests.
+        v.irq       :=
+            (r.ctl_ielink     and (linko.running xor (r.sta_link(0) and r.sta_link(1)))) or
+            (r.ctl_ietick     and linko.tick_out) or
+            (r.ctl_ierxdesc   and msto.int_rxdesc) or
+            (r.ctl_ietxdesc   and msto.int_txdesc) or
+            (r.ctl_ierxpacket and msto.int_rxpacket);
+
+        -- APB read access.
+        if apbi.psel(pindex) = '1' then
+            case apbi.paddr(4 downto 2) is
+                when "000" =>   -- read control register
+                    v_prdata(0)     := '0';
+                    v_prdata(1)     := '0';
+                    v_prdata(2)     := r.ctl_linkstart;
+                    v_prdata(3)     := r.ctl_autostart;
+                    v_prdata(4)     := r.ctl_linkdis;
+                    v_prdata(5)     := r.ctl_ticken;
+                    v_prdata(6)     := '0';
+                    v_prdata(7)     := '0';
+                    v_prdata(8)     := r.ctl_txcancel;
+                    v_prdata(9)     := r.ctl_ielink;
+                    v_prdata(10)    := r.ctl_ietick;
+                    v_prdata(11)    := r.ctl_ierxdesc;
+                    v_prdata(12)    := r.ctl_ietxdesc;
+                    v_prdata(13)    := r.ctl_ierxpacket;
+                    v_prdata(27 downto 24) := std_logic_vector(to_unsigned(desctablesize, 4));
+                when "001" =>   -- read status register
+                    v_prdata(1 downto 0)    := r.sta_link;
+                    v_prdata(2)     := r.sta_errdisc;
+                    v_prdata(3)     := r.sta_errpar;
+                    v_prdata(4)     := r.sta_erresc;
+                    v_prdata(5)     := r.sta_errcred;
+                    v_prdata(6)     := msto.rxdma_act;
+                    v_prdata(7)     := msto.txdma_act;
+                    v_prdata(8)     := msto.ahberror;
+                    v_prdata(10)    := r.sta_gottick;
+                    v_prdata(11)    := r.sta_rxdesc;
+                    v_prdata(12)    := r.sta_txdesc;
+                    v_prdata(13)    := r.sta_rxpacket;
+                    v_prdata(14)    := r.sta_rxempty;
+                when "010" =>   -- read transmission clock scaler
+                    v_prdata(7 downto 0)    := r.txdivcnt;
+                when "011" =>   -- read timecode register
+                    v_prdata(5 downto 0)    := linko.time_out;
+                    v_prdata(7 downto 6)    := linko.ctrl_out;
+                    v_prdata(13 downto 8)   := r.time_in;
+                    v_prdata(16 downto 14)  := "000";
+                when "100" =>   -- read rx descriptor pointer
+                    v_prdata(2 downto 0)    := (others => '0');
+                    v_prdata(31 downto 3)   := r.rxdesc_ptr;
+                when "101" =>   -- read tx descriptor pointer
+                    v_prdata(2 downto 0)    := (others => '0');
+                    v_prdata(31 downto 3)   := r.txdesc_ptr;
+                when others =>
+                    null;
+            end case;
+        end if;
+
+        -- APB write access.
+        if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
+            case apbi.paddr(4 downto 2) is
+                when "000" =>   -- write control register
+                    v.ctl_reset     := apbi.pwdata(0);
+                    v.ctl_resetdma  := apbi.pwdata(1);
+                    v.ctl_linkstart := apbi.pwdata(2);
+                    v.ctl_autostart := apbi.pwdata(3);
+                    v.ctl_linkdis   := apbi.pwdata(4);
+                    v.ctl_ticken    := apbi.pwdata(5);
+                    v.ctl_rxstart   := apbi.pwdata(6);
+                    v.ctl_txstart   := apbi.pwdata(7);
+                    if apbi.pwdata(8) = '1' then v.ctl_txcancel := '1'; end if;
+                    v.ctl_ielink    := apbi.pwdata(9);
+                    v.ctl_ietick    := apbi.pwdata(10);
+                    v.ctl_ierxdesc  := apbi.pwdata(11);
+                    v.ctl_ietxdesc  := apbi.pwdata(12);
+                    v.ctl_ierxpacket := apbi.pwdata(13);
+                when "001" =>   -- write status register
+                    if apbi.pwdata(2) = '1' then v.sta_errdisc := '0'; end if;
+                    if apbi.pwdata(3) = '1' then v.sta_errpar  := '0'; end if;
+                    if apbi.pwdata(4) = '1' then v.sta_erresc  := '0'; end if;
+                    if apbi.pwdata(5) = '1' then v.sta_errcred := '0'; end if;
+                    if apbi.pwdata(10) = '1' then v.sta_gottick := '0'; end if;
+                    if apbi.pwdata(11) = '1' then v.sta_rxdesc := '0'; end if;
+                    if apbi.pwdata(12) = '1' then v.sta_txdesc := '0'; end if;
+                    if apbi.pwdata(13) = '1' then v.sta_rxpacket := '0'; end if;
+                when "010" =>   -- write transmission clock scaler
+                    v.txdivcnt      := apbi.pwdata(7 downto 0);
+                when "011" =>   -- write timecode register
+                    v.time_in       := apbi.pwdata(13 downto 8);
+                    if apbi.pwdata(16) = '1' then v.tick_in := '1'; end if;
+                when "100" =>   -- write rx descriptor pointer
+                    v.rxdesc_ptr    := apbi.pwdata(31 downto 3);
+                when "101" =>   -- write tx descriptor pointer
+                    v.txdesc_ptr    := apbi.pwdata(31 downto 3);
+                when others =>
+                    null;
+            end case;
+        end if;
+
+        -- Drive control signals to RX fifo.
+        s_rxfifo_raddr  <= v.rxfifo_raddr;      -- new value of rxfifo_raddr
+        s_rxfifo_wen    <= r.rxfifo_write;
+        s_rxfifo_waddr  <= r.rxfifo_waddr;
+        s_rxfifo_wdata  <= r.rxfifo_wdata;
+
+        -- Drive control signals to TX fifo.
+        s_txfifo_raddr  <= v.txfifo_raddr;      -- new value of txfifo_raddr
+        s_txfifo_wen    <= msto.txfifo_write;
+        s_txfifo_waddr  <= r.txfifo_waddr;
+        s_txfifo_wdata  <= msto.txfifo_wdata;
+
+        -- Drive inputs to spwlink.
+        linki.autostart <= r.ctl_autostart;
+        linki.linkstart <= r.ctl_linkstart;
+        linki.linkdis   <= r.ctl_linkdis;
+        linki.rxroom    <= r.rxroom;
+        linki.tick_in   <= r.tick_in;
+        linki.ctrl_in   <= "00";
+        linki.time_in   <= r.time_in;
+        linki.txwrite   <= (not r.txfifo_empty) and (not r.txdiscard);
+        linki.txflag    <= s_txfifo_rdata(35-v_txfifo_bytepos);
+        linki.txdata    <= s_txfifo_rdata(31-8*v_txfifo_bytepos downto 24-8*v_txfifo_bytepos);
+
+        -- Drive divcnt input to spwxmit.
+        if linko.running = '1' then
+            xmit_divcnt <= r.txdivcnt;
+        else
+            xmit_divcnt <= default_divcnt;
+        end if;
+
+        -- Drive inputs to AHB master.
+        msti.rxdma_start    <= r.ctl_rxstart;
+        msti.txdma_start    <= r.ctl_txstart;
+        msti.txdma_cancel   <= r.ctl_txcancel;
+        msti.rxdesc_ptr     <= r.rxdesc_ptr;
+        msti.txdesc_ptr     <= r.txdesc_ptr;
+        msti.rxfifo_rdata   <= s_rxfifo_rdata;
+        msti.rxfifo_empty   <= r.rxfifo_empty;
+        msti.rxfifo_nxempty <= v.rxfifo_empty;  -- new value of rxfifo_empty
+        msti.txfifo_nxfull  <= r.txfifo_nxfull;
+        msti.txfifo_highw   <= r.txfifo_highw;
+
+        -- Pass tick_out signal to output port.
+        tick_out        <= linko.tick_out;
+
+        -- Drive APB output signals.
+        apbo.prdata     <= v_prdata;
+        apbo.pirq       <= v_irq;
+        apbo.pconfig    <= pconfig;
+        apbo.pindex     <= pindex;
+
+        -- Reset components.
+        ahbmst_rstn     <= rstn and (not r.ctl_reset) and (not r.ctl_resetdma);
+        link_rst        <= (not rstn) or r.ctl_reset;
+        xmit_rst        <= not rstn;
+
+        -- Clear TX fifo on cancel request.
+        if r.ctl_txcancel = '1' then
+            v.txfifo_raddr  := (others => '0');
+            v.txfifo_waddr  := (others => '0');
+            v.txfifo_empty  := '1';
+            v.txfifo_nxfull := '0';
+            v.txfifo_highw  := '0';
+            v.txfifo_bytepos := "00";
+            v.txpacket      := '0';
+            v.txdiscard     := '0';
+        end if;
+
+        -- Reset registers.
+        if rstn = '0' or r.ctl_reset = '1' then
+            v   := regs_reset;
+        end if;
+
+        -- Update registers.
+        rin <= v;
+    end process;
+
+
+    --
+    -- Update registers.
+    --
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwamba_arch;
diff --git a/lib/opencores/spw_light/spwambapkg.vhd b/lib/opencores/spw_light/spwambapkg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwambapkg.vhd
@@ -0,0 +1,159 @@
+--
+--  VHDL package for SpaceWire AMBA interface.
+--
+--  This package depends on Gaisler GRLIB.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+library techmap;
+use techmap.gencomp.all;
+use work.spwpkg.all;
+
+package spwambapkg is
+
+
+    -- AMBA plug&play device id
+    constant DEVICE_SPACEWIRELIGHT: amba_device_type := 16#131#;
+
+
+    -- Signals from SpaceWire core to AHB master.
+    type spw_ahbmst_in_type is record
+
+        -- Pulse high to start the RX DMA engine.
+        rxdma_start:    std_ulogic;
+
+        -- Pulse high to start the TX DMA engine.
+        txdma_start:    std_ulogic;
+
+        -- Stop TX DMA engine (at end of current burst).
+        txdma_cancel:   std_ulogic;
+
+        -- Address of current RX descriptor (8-byte aligned).
+        rxdesc_ptr:     std_logic_vector(31 downto 3);
+
+        -- Address of current TX descriptor (8-byte aligned).
+        txdesc_ptr:     std_logic_vector(31 downto 3);
+
+        -- Read port of RX FIFO.
+        rxfifo_rdata:   std_logic_vector(35 downto 0);
+
+        -- High if RX FIFO is empty.
+        rxfifo_empty:   std_ulogic;
+
+        -- High if RX FIFO will be empty after one read.
+        -- May combinatorially depend on spw_ahbmst_out_type.rxfifo_read.
+        rxfifo_nxempty: std_ulogic;
+
+        -- High if TX FIFO is full or has room for at most one word.
+        txfifo_nxfull:  std_ulogic;
+
+        -- High if TX FIFO is close to full (blocks refill).
+        txfifo_highw:   std_ulogic;
+    end record;
+
+    -- Signals from AHB master to SpaceWire core.
+    type spw_ahbmst_out_type is record
+
+        -- High if the RX DMA engine is enabled.
+        rxdma_act:      std_ulogic;
+
+        -- High if the TX DMA engine is enabled.
+        txdma_act:      std_ulogic;
+
+        -- High if an error occurred on the AHB bus.
+        ahberror:       std_ulogic;
+
+        -- Pulsed high to trigger an RX descriptor interrupt.
+        int_rxdesc:     std_ulogic;
+
+        -- Pulsed high to trigger a TX descriptor interrupt.
+        int_txdesc:     std_ulogic;
+
+        -- Pulsed high when a complete packet has been received.
+        int_rxpacket:   std_ulogic;
+
+        -- Pulsed high to request the next RX descriptor address.
+        -- (rxdesc_ptr must be updated in the next clock cycle).
+        rxdesc_next:    std_ulogic;
+
+        -- Pulsed high together with rxdesc_next to wrap the RX descriptor pointer.
+        rxdesc_wrap:    std_ulogic;
+
+        -- Pulsed high to request the next TX descriptor address.
+        -- (txdesc_ptr must be updated in the next clock cycle).
+        txdesc_next:    std_ulogic;
+
+        -- Pulsed high together with txdesc_next to wrap the TX descriptor pointer.
+        txdesc_wrap:    std_ulogic;
+
+        -- Read strobe to RX fifo.
+        rxfifo_read:    std_ulogic;
+
+        -- Write enable to TX fifo.
+        txfifo_write:   std_ulogic;
+
+        -- Input port of TX fifo.
+        txfifo_wdata:   std_logic_vector(35 downto 0);
+    end record;
+
+
+    -- SpaceWire core with AMBA interface.
+    component spwamba is
+        generic (
+            tech:           integer range 0 to NTECH := DEFFABTECH;
+            hindex:         integer;                -- AHB master index
+            pindex:         integer;                -- APB slave index
+            paddr:          integer;                -- APB address range
+            pmask:          integer := 16#fff#;     -- APB address mask
+            pirq:           integer;                -- interrupt number
+            sysfreq:        real;                   -- system clock frequency in Hz
+            txclkfreq:      real := 0.0;            -- txclk frequency in Hz
+            rximpl:         spw_implementation_type := impl_generic;
+            rxchunk:        integer range 1 to 4 := 1;
+            tximpl:         spw_implementation_type := impl_generic;
+            timecodegen:    boolean := true;        -- support timecode generation
+            rxfifosize:     integer range 6 to 12 := 8; -- size of receive FIFO (2-log of words)
+            txfifosize:     integer range 2 to 12 := 8; -- size of transmit FIFO (2-log of words)
+            desctablesize:  integer range 4 to 14 := 10; -- size of the DMA descriptor tables (2-log of descriptors)
+            maxburst:       integer range 1 to 8 := 3   -- max burst length (2-log of words)
+        );
+        port (
+            clk:        in  std_logic;              -- system clock.
+            rxclk:      in  std_logic;              -- receiver sample clock
+            txclk:      in  std_logic;              -- transmit clock
+            rstn:       in  std_logic;              -- synchronous reset (active-low)
+            apbi:       in  apb_slv_in_type;        -- APB slave input signals
+            apbo:       out apb_slv_out_type;       -- APB slave output signals
+            ahbi:       in  ahb_mst_in_type;        -- AHB master input signals
+            ahbo:       out ahb_mst_out_type;       -- AHB master output signals
+            tick_in:    in  std_logic;              -- pulse for timecode generation
+            tick_out:   out std_logic;              -- timecode received
+            spw_di:     in  std_logic;              -- Data In signal from SpaceWire bus
+            spw_si:     in  std_logic;              -- Strobe In signal from SpaceWire bus
+            spw_do:     out std_logic;              -- Data Out signal to SpaceWire bus
+            spw_so:     out std_logic               -- Strobe Out signal to SpaceWire bus
+        );
+    end component spwamba;
+
+
+    -- AHB master for AMBA interface.
+    component spwahbmst is
+        generic (
+            hindex:         integer;                -- AHB master index
+            hconfig:        ahb_config_type;        -- AHB plug&play information
+            maxburst:       integer range 1 to 8    -- 2log of max burst length
+        );
+        port (
+            clk:        in  std_logic;              -- system clock
+            rstn:       in  std_logic;              -- synchronous reset (active-low)
+            msti:       in  spw_ahbmst_in_type;     -- inputs from SpaceWire core
+            msto:       out spw_ahbmst_out_type;    -- outputs to SpaceWire core
+            ahbi:       in  ahb_mst_in_type;        -- AHB master input signals
+            ahbo:       out ahb_mst_out_type        -- AHB master output signals
+        );
+    end component spwahbmst;
+
+end package;
diff --git a/lib/opencores/spw_light/spwlink.vhd b/lib/opencores/spw_light/spwlink.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwlink.vhd
@@ -0,0 +1,286 @@
+--
+--  SpaceWire Exchange Level Controller.
+--
+--  This entity implements exchange level aspects of the SpaceWire protocol.
+--  It handles connection setup, error detection and flow control.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwlink is
+
+    generic (
+        -- Reset time expressed in system clock cycles.
+        -- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard.
+        reset_time:      integer
+    );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Synchronous reset (active-high).
+        -- Disconnects, resets error conditions, puts the link state machine
+        -- in state ErrorReset.
+        rst:        in  std_logic;
+
+        -- Link level inputs.
+        linki:      in  spw_link_in_type;
+
+        -- Link level outputs.
+        linko:      out spw_link_out_type;
+
+        -- Receiver enable signal to spwrecv.
+        rxen:       out std_logic;
+
+        -- Output signals from spwrecv.
+        recvo:      in  spw_recv_out_type;
+
+        -- Input signals for spwxmit.
+        xmiti:      out spw_xmit_in_type;
+
+        -- Output signals from spwxmit.
+        xmito:      in  spw_xmit_out_type
+    );
+
+end entity spwlink;
+
+architecture spwlink_arch of spwlink is
+
+    -- Convert boolean to std_logic.
+    type bool_to_logic_type is array(boolean) of std_ulogic;
+    constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
+
+    -- State machine.
+    type state_type is (
+      S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run );
+
+    -- Registers
+    type regs_type is record
+        -- state machine
+        state:          state_type;
+        -- credit accounting
+        tx_credit:  unsigned(5 downto 0);
+        rx_credit:  unsigned(5 downto 0);
+        errcred:    std_ulogic;
+        -- reset timer
+        timercnt:   unsigned(10 downto 0);
+        timerdone:  std_ulogic;
+        -- signal to transmitter
+        xmit_fct_in: std_ulogic;
+    end record;
+
+    -- Initial state
+    constant regs_reset: regs_type := (
+        state       => S_ErrorReset,
+        tx_credit   => "000000",
+        rx_credit   => "000000",
+        errcred     => '0',
+        timercnt    => to_unsigned(reset_time, 11),
+        timerdone   => '0',
+        xmit_fct_in => '0' );
+
+    signal r:       regs_type := regs_reset;
+    signal rin:     regs_type;
+
+begin
+
+    -- Combinatorial process
+    process (r, rst, linki, recvo, xmito) is
+        variable v: regs_type;
+        variable v_timerrst: std_logic;
+    begin
+        v := r;
+        v_timerrst := '0';
+
+        -- State machine.
+        case r.state is
+
+            when S_ErrorReset =>
+                -- Wait for timer.
+                if r.timercnt = 0 then
+                    v.state     := S_ErrorWait;
+                    v_timerrst  := '1';
+                end if;
+                v.errcred   := '0';
+                v.xmit_fct_in := '0';
+
+            when S_ErrorWait =>
+                -- Wait for 2 timer periods.
+                if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
+                   ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
+                    -- Note: spwrecv will never issue errpar, erresc, gotfct,
+                    -- tick_out or rxchar before the first NULL has been seen.
+                    -- Therefore it's ok here to bail on those conditions
+                    -- without explicitly testing got_null.
+                    v.state     := S_ErrorReset;    -- error, go back to reset
+                    v_timerrst  := '1';
+                elsif r.timercnt = 0 then
+                    if r.timerdone = '1' then
+                        v.state     := S_Ready;
+                        v_timerrst  := '1';
+                    end if;
+                end if;
+
+            when S_Ready =>
+                -- Wait for link start.
+                if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
+                   ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then
+                    v.state     := S_ErrorReset;    -- error, go back to reset
+                    v_timerrst  := '1';
+                elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and
+                      ((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then
+                    v.state     := S_Started;       -- link enabled; start sending NULL
+                    v_timerrst  := '1';
+                end if;
+
+            when S_Started =>
+                -- Wait for NULL.
+                if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
+                   ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or
+                   ((r.timercnt = 0) and r.timerdone = '1') then
+                    v.state     := S_ErrorReset;    -- error, go back to reset
+                    v_timerrst  := '1';
+                elsif recvo.gotnull = '1' then
+                    v.state     := S_Connecting;    -- received null, continue
+                    v_timerrst  := '1';
+                end if;
+
+            when S_Connecting =>
+                -- Wait for FCT.
+                if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
+                   ((recvo.tick_out or recvo.rxchar) = '1') or
+                   ((r.timercnt = 0) and r.timerdone = '1') then
+                    v.state     := S_ErrorReset;    -- error, go back to reset
+                    v_timerrst  := '1';
+                elsif recvo.gotfct = '1' then
+                    v.state     := S_Run;           -- got FCT, init completed
+                end if;
+
+            when S_Run =>
+                -- All is well.
+                if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or
+                   (r.errcred = '1') or
+                   (linki.linkdis = '1') then
+                    v.state     := S_ErrorReset;    -- error, go back to reset
+                    v_timerrst  := '1';
+                end if;
+
+            when others =>
+                v.state     := S_ErrorReset;        -- recover from invalid state
+                v_timerrst  := '1';
+
+        end case;
+
+        -- Update credit counters.
+        if r.state = S_ErrorReset then
+
+            -- reset credit
+            v.tx_credit := to_unsigned(0, v.tx_credit'length);
+            v.rx_credit := to_unsigned(0, v.rx_credit'length);
+
+        else
+
+            -- update TX credit
+            if recvo.gotfct = '1' then
+                -- just received a FCT token
+                v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length);
+                if r.tx_credit > 48 then
+                    -- received too many FCT tokens
+                    v.errcred   := '1';
+                end if;
+            end if;
+            if xmito.txack = '1' then
+                -- just sent one byte
+                v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length);
+            end if;
+
+            -- update RX credit after sending FCT
+            if xmito.fctack = '1' then
+               -- just sent a FCT token
+                v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length);
+            end if;
+
+            -- decide about sending FCT tokens
+            v.xmit_fct_in := bool_to_logic( (v.rx_credit <= 48) and
+                                            (v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom)) );
+
+            -- update RX credit after receiving character
+            if recvo.rxchar = '1' then
+                -- just received a character
+                v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length);
+                if r.rx_credit = 0 then
+                    -- remote transmitter violated its credit
+                    v.errcred   := '1';
+                end if;
+            end if;
+
+        end if;
+
+        -- Update the initializaton reset timer.
+        if v_timerrst = '1' then
+            v.timercnt  := to_unsigned(reset_time, v.timercnt'length);
+            v.timerdone := '0';
+        else
+            if r.timercnt = 0 then
+                v.timercnt  := to_unsigned(reset_time, v.timercnt'length);
+                v.timerdone := '1';
+            else
+                v.timercnt  := r.timercnt - 1;
+            end if;
+        end if;
+
+        -- Reset
+        if rst = '1' then
+            v := regs_reset;
+        end if;
+
+        -- Drive link level outputs.
+        linko.started   <= bool_to_logic(r.state = S_Started);
+        linko.connecting <= bool_to_logic(r.state = S_Connecting);
+        linko.running   <= bool_to_logic(r.state = S_Run);
+        linko.errdisc   <= recvo.errdisc and bool_to_logic(r.state = S_Run);
+        linko.errpar    <= recvo.errpar  and bool_to_logic(r.state = S_Run);
+        linko.erresc    <= recvo.erresc  and bool_to_logic(r.state = S_Run);
+        linko.errcred   <= r.errcred;
+        linko.txack     <= xmito.txack;
+        linko.tick_out  <= recvo.tick_out and bool_to_logic(r.state = S_Run);
+        linko.ctrl_out  <= recvo.ctrl_out;
+        linko.time_out  <= recvo.time_out;
+        linko.rxchar    <= recvo.rxchar  and bool_to_logic(r.state = S_Run);
+        linko.rxflag    <= recvo.rxflag;
+        linko.rxdata    <= recvo.rxdata;
+
+        -- Drive receiver inputs.
+        rxen            <= bool_to_logic(r.state /= S_ErrorReset);
+
+        -- Drive transmitter input signals.
+        xmiti.txen      <= bool_to_logic(r.state = S_Started or
+                                         r.state = S_Connecting or
+                                         r.state = S_Run);
+        xmiti.stnull    <= bool_to_logic(r.state = S_Started);
+        xmiti.stfct     <= bool_to_logic(r.state = S_Connecting);
+        xmiti.fct_in    <= r.xmit_fct_in;
+        xmiti.tick_in   <= linki.tick_in and bool_to_logic(r.state = S_Run);
+        xmiti.ctrl_in   <= linki.ctrl_in;
+        xmiti.time_in   <= linki.time_in;
+        xmiti.txwrite   <= linki.txwrite and bool_to_logic(r.tx_credit /= 0);
+        xmiti.txflag    <= linki.txflag;
+        xmiti.txdata    <= linki.txdata;
+
+        -- Update registers.
+        rin <= v;
+    end process;
+
+    -- Update registers.
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwlink_arch;
diff --git a/lib/opencores/spw_light/spwpkg.vhd b/lib/opencores/spw_light/spwpkg.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwpkg.vhd
@@ -0,0 +1,403 @@
+--
+--  SpaceWire VHDL package
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package spwpkg is
+
+
+    -- Indicates a platform-specific implementation.
+    type spw_implementation_type is ( impl_generic, impl_fast );
+
+
+    -- Input signals to spwlink.
+    type spw_link_in_type is record
+
+        -- Enables automatic link start on receipt of a NULL character.
+        autostart:  std_logic;
+
+        -- Enables link start once the Ready state is reached.
+        -- Without either "autostart" or "linkstart", the link remains in
+        -- state Ready.
+        linkstart:  std_logic;
+
+        -- Do not start link (overrides "linkstart" and "autostart") and/or
+        -- disconnect the currently running link.
+        linkdis:    std_logic;
+
+        -- Number of bytes available in the receive buffer. Used to for
+        -- flow-control operation. At least 8 bytes must be available
+        -- initially, otherwise the link can not start. Values larger than 63
+        -- are irrelevant and may be presented as 63. The available room may
+        -- decrease by one byte due to the reception of an N-Char; in that case
+        -- the "rxroom" signal must be updated on the clock following the clock
+        -- on which "rxchar" is high. Under no other circumstances may "rxroom"
+        -- be decreased.
+        rxroom:     std_logic_vector(5 downto 0);
+
+        -- High for one clock cycle to request transmission of a TimeCode.
+        -- The request is registered inside spwxmit until it can be processed.
+        tick_in:    std_logic;
+
+        -- Control bits of the TimeCode to be sent.
+        -- Must be valid while tick_in is high.
+        ctrl_in:    std_logic_vector(1 downto 0);
+
+        -- Counter value of the TimeCode to be sent.
+        -- Must be valid while tick_in is high.
+        time_in:    std_logic_vector(5 downto 0);
+
+        -- Requests transmission of an N-Char.
+        -- Keep this signal high until confirmed by "txack".
+        txwrite:    std_logic;
+
+        -- Control flag to be sent with the next N-Char.
+        -- Must be valid while "txwrite" is high.
+        txflag:     std_logic;
+
+        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
+        -- Must be valid while "txwrite" is high.
+        txdata:     std_logic_vector(7 downto 0);
+    end record;
+
+
+    -- Output signals from spwlink.
+    type spw_link_out_type is record
+
+        -- High if the link state machine is currently in state Started.
+        started:    std_logic;
+
+        -- High if the link state machine is currently in state Connecting.
+        connecting: std_logic;
+
+        -- High if the link state machine is currently in state Run.
+        running:    std_logic;
+
+        -- Disconnect detected in state Run. Triggers a reset and reconnect.
+        -- This indication is auto-clearing.
+        errdisc:    std_logic;
+
+        -- Parity error detected in state Run. Triggers a reset and reconnect.
+        -- This indication is auto-clearing.
+        errpar:     std_logic;
+
+        -- Invalid escape sequence detected in state Run.
+        -- Triggers a reset and reconnect; auto-clearing.
+        erresc:     std_logic;
+
+        -- Credit error detected. Triggers a reset and reconnect.
+        -- This indication is auto-clearing.
+        errcred:    std_logic;
+
+        -- High to confirm the transmission of an N-Char.
+        -- This is a Wishbone-style handshake signal. It has a combinatorial
+        -- dependency on "txwrite".
+        txack:      std_logic;
+
+        -- High for one clock cycle if a TimeCode was just received.
+        -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50
+        -- is not implemented; all received timecodes are reported.
+        tick_out:   std_logic;
+
+        -- Control bits of last received TimeCode.
+        ctrl_out:   std_logic_vector(1 downto 0);
+
+        -- Counter value of last received TimeCode.
+        time_out:   std_logic_vector(5 downto 0);
+
+        -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was
+        -- just received. The data bits must be accepted immediately from
+        -- "rxflag" and "rxdata".
+        rxchar:     std_logic;
+
+        -- High if the received character is EOP or EEP, low if it is a data
+        -- byte. Valid when "rxchar" is high.
+        rxflag:     std_logic;
+
+        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
+        -- Valid when "rxchar" is high.
+        rxdata:     std_logic_vector(7 downto 0);
+    end record;
+
+
+    -- Output signals from spwrecv to spwlink.
+    type spw_recv_out_type is record
+
+        -- High if at least one signal change was seen since enable.
+        -- Resets to low when rxen is low.
+        gotbit:     std_logic;
+
+        -- High if at least one valid NULL pattern was detected since enable.
+        -- Resets to low when rxen is low.
+        gotnull:    std_logic;
+
+        -- High for one clock cycle if an FCT token was just received.
+        gotfct:     std_logic;
+
+        -- High for one clock cycle if a TimeCode was just received.
+        tick_out:   std_logic;
+
+        -- Control bits of last received TimeCode.
+        ctrl_out:   std_logic_vector(1 downto 0);
+
+        -- Counter value of last received TimeCode.
+        time_out:   std_logic_vector(5 downto 0);
+
+        -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received.
+        rxchar:     std_logic;
+
+        -- High if rxchar is high and the received character is EOP or EEP.
+        -- Low if rxchar is high and the received character is a data byte.
+        rxflag:     std_logic;
+
+        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
+        -- Valid when "rxchar" is high.
+        rxdata:     std_logic_vector(7 downto 0);
+
+        -- Disconnect detected (after a signal change was seen).
+        -- Resets to low when rxen is low or when a signal change is seen.
+        errdisc:    std_logic;
+
+        -- Parity error detected (after a valid NULL pattern was seen).
+        -- Sticky; resets to low when rxen is low.
+        errpar:     std_logic;
+
+        -- Escape sequence error detected (after a valid NULL pattern was seen).
+        -- Sticky; resets to low when rxen is low.
+        erresc:     std_logic;
+    end record;
+
+
+    -- Input signals to spwxmit from spwlink.
+    type spw_xmit_in_type is record
+
+        -- High to enable transmitter; low to disable and reset transmitter.
+        txen:       std_logic;
+
+        -- Indicates that only NULL characters may be transmitted.
+        stnull:     std_logic;
+
+        -- Indicates that only NULL and/or FCT characters may be transmitted.
+        stfct:      std_logic;
+
+        -- Requests transmission of an FCT character.
+        -- Keep this signal high until confirmed by "fctack".
+        fct_in:     std_logic;
+
+        -- High for one clock cycle to request transmission of a TimeCode.
+        -- The request is registered inside spwxmit until it can be processed.
+        tick_in:    std_logic;
+
+        -- Control bits of the TimeCode to be sent.
+        -- Must be valid while "tick_in" is high.
+        ctrl_in:    std_logic_vector(1 downto 0);
+
+        -- Counter value of the TimeCode to be sent.
+        -- Must be valid while "tick_in" is high.
+        time_in:    std_logic_vector(5 downto 0);
+
+        -- Request transmission of an N-Char.
+        -- Keep this signal high until confirmed by "txack".
+        txwrite:    std_logic;
+
+        -- Control flag to be sent with the next N-Char.
+        -- Must be valid while "txwrite" is high.
+        txflag:     std_logic;
+
+        -- Byte to send, or "00000000" for EOP or "00000001" for EEP.
+        -- Must be valid while "txwrite" is high.
+        txdata:     std_logic_vector(7 downto 0);
+    end record;
+
+
+    -- Output signals from spwxmit to spwlink.
+    type spw_xmit_out_type is record
+
+        -- High to confirm transmission on an FCT character.
+        -- This is a Wishbone-style handshaking signal; it is combinatorially
+        -- dependent on "fct_in".
+        fctack:     std_logic;
+
+        -- High to confirm transmission of an N-Char.
+        -- This is a Wishbone-style handshaking signal; it is combinatorially
+        -- dependent on both "fct_in" and "txwrite".
+        txack:      std_logic;
+    end record;
+
+
+    -- Character-stream interface
+    component spwstream is
+        generic (
+            sysfreq:        real;                           -- clk freq in Hz
+            txclkfreq:      real := 0.0;                    -- txclk freq in Hz
+            rximpl:         spw_implementation_type := impl_generic;
+            rxchunk:        integer range 1 to 4 := 1;      -- max bits per clk
+            tximpl:         spw_implementation_type := impl_generic;
+            rxfifosize_bits: integer range 6 to 14 := 11;   -- rx fifo size
+            txfifosize_bits: integer range 2 to 14 := 11    -- tx fifo size
+        );
+        port (
+            clk:        in  std_logic;          -- system clock
+            rxclk:      in  std_logic;          -- receiver sample clock
+            txclk:      in  std_logic;          -- transmit clock
+            rst:        in  std_logic;          -- synchronous reset
+            autostart:  in  std_logic;          -- automatic link start
+            linkstart:  in  std_logic;          -- forced link start
+            linkdis:    in  std_logic;          -- stop link
+            txdivcnt:   in  std_logic_vector(7 downto 0);   -- tx scale factor
+            tick_in:    in  std_logic;          -- request timecode xmit
+            ctrl_in:    in  std_logic_vector(1 downto 0);   
+            time_in:    in  std_logic_vector(5 downto 0);
+            txwrite:    in  std_logic;          -- request character xmit
+            txflag:     in  std_logic;          -- control flag of tx char
+            txdata:     in  std_logic_vector(7 downto 0);
+            txrdy:      out std_logic;          -- room in tx fifo
+            txhalff:    out std_logic;          -- tx fifo half full
+            tick_out:   out std_logic;          -- timecode received
+            ctrl_out:   out std_logic_vector(1 downto 0);
+            time_out:   out std_logic_vector(5 downto 0);
+            rxvalid:    out std_logic;          -- rx fifo not empty
+            rxhalff:    out std_logic;          -- rx fifo half full
+            rxflag:     out std_logic;          -- control flag of rx char
+            rxdata:     out std_logic_vector(7 downto 0);
+            rxread:     in  std_logic;          -- accept rx character
+            started:    out std_logic;          -- link in Started state
+            connecting: out std_logic;          -- link in Connecting state
+            running:    out std_logic;          -- link in Run state
+            errdisc:    out std_logic;          -- disconnect error
+            errpar:     out std_logic;          -- parity error
+            erresc:     out std_logic;          -- escape error
+            errcred:    out std_logic;          -- credit error
+            spw_di:     in  std_logic;
+            spw_si:     in  std_logic;
+            spw_do:     out std_logic;
+            spw_so:     out std_logic
+        );
+    end component spwstream;
+
+
+    -- Link Level Interface
+    component spwlink is
+        generic (
+            reset_time:      integer        -- reset time in clocks (6.4 us)
+        );
+        port (
+            clk:        in  std_logic;      -- system clock
+            rst:        in  std_logic;      -- synchronous reset (active-high)
+            linki:      in  spw_link_in_type;
+            linko:      out spw_link_out_type;
+            rxen:       out std_logic;
+            recvo:      in  spw_recv_out_type;
+            xmiti:      out spw_xmit_in_type;
+            xmito:      in  spw_xmit_out_type
+        );
+    end component spwlink;
+
+
+    -- Receiver
+    component spwrecv is
+        generic (
+            disconnect_time: integer range 1 to 255;    -- disconnect period in system clock cycles
+            rxchunk:        integer range 1 to 4        -- nr of bits per system clock
+        );
+        port (
+            clk:        in  std_logic;      -- system clock
+            rxen:       in  std_logic;      -- receiver enabled
+            recvo:      out spw_recv_out_type;
+            inact:      in  std_logic;
+            inbvalid:   in  std_logic;
+            inbits:     in  std_logic_vector(rxchunk-1 downto 0)
+        );
+    end component spwrecv;
+
+
+    -- Transmitter (generic implementation)
+    component spwxmit is
+        port (
+            clk:        in  std_logic;      -- system clock
+            rst:        in  std_logic;      -- synchronous reset (active-high)
+            divcnt:     in  std_logic_vector(7 downto 0);
+            xmiti:      in  spw_xmit_in_type;
+            xmito:      out spw_xmit_out_type;
+            spw_do:     out std_logic;      -- tx data to SPW bus
+            spw_so:     out std_logic       -- tx strobe to SPW bus
+        );
+    end component spwxmit;
+
+
+    -- Transmitter (separate tx clock domain)
+    component spwxmit_fast is
+        port (
+            clk:        in  std_logic;      -- system clock
+            txclk:      in  std_logic;      -- transmit clock
+            rst:        in  std_logic;      -- synchronous reset (active-high)
+            divcnt:     in  std_logic_vector(7 downto 0);
+            xmiti:      in  spw_xmit_in_type;
+            xmito:      out spw_xmit_out_type;
+            spw_do:     out std_logic;      -- tx data to SPW bus
+            spw_so:     out std_logic       -- tx strobe to SPW bus
+        );
+    end component spwxmit_fast;
+
+
+    -- Front-end for SpaceWire Receiver (generic implementation)
+    component spwrecvfront_generic is
+        port (
+            clk:        in  std_logic;      -- system clock
+            rxen:       in  std_logic;      -- high to enable receiver
+            inact:      out std_logic;      -- high if activity on input
+            inbvalid:   out std_logic;      -- high if inbits contains a valid received bit
+            inbits:     out std_logic_vector(0 downto 0);   -- received bit
+            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
+            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
+        );
+    end component spwrecvfront_generic;
+
+
+    -- Front-end for SpaceWire Receiver (separate rx clock domain)
+    component spwrecvfront_fast is
+        generic (
+            rxchunk:        integer range 1 to 4    -- max number of bits per system clock
+        );
+        port (
+            clk:        in  std_logic;      -- system clock
+            rxclk:      in  std_logic;      -- sample clock (DDR)
+            rxen:       in  std_logic;      -- high to enable receiver
+            inact:      out std_logic;      -- high if activity on input
+            inbvalid:   out std_logic;      -- high if inbits contains a valid group of received bits
+            inbits:     out std_logic_vector(rxchunk-1 downto 0);    -- received bits
+            spw_di:     in  std_logic;      -- Data In signal from SpaceWire bus
+            spw_si:     in  std_logic       -- Strobe In signal from SpaceWire bus
+        );
+    end component spwrecvfront_fast;
+
+
+    -- Synchronous two-port memory.
+    component spwram is
+        generic (
+            abits:      integer;
+            dbits:      integer );
+        port (
+            rclk:       in  std_logic;
+            wclk:       in  std_logic;
+            ren:        in  std_logic;
+            raddr:      in  std_logic_vector(abits-1 downto 0);
+            rdata:      out std_logic_vector(dbits-1 downto 0);
+            wen:        in  std_logic;
+            waddr:      in  std_logic_vector(abits-1 downto 0);
+            wdata:      in  std_logic_vector(dbits-1 downto 0) );
+    end component spwram;
+
+
+    --  Double flip-flop synchronizer.
+    component syncdff is
+        port (
+            clk:        in  std_logic;          -- clock (destination domain)
+            rst:        in  std_logic;          -- asynchronous reset, active-high
+            di:         in  std_logic;          -- input data
+            do:         out std_logic );        -- output data
+    end component syncdff;
+
+end package;
diff --git a/lib/opencores/spw_light/spwram.vhd b/lib/opencores/spw_light/spwram.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwram.vhd
@@ -0,0 +1,58 @@
+--
+--  Synchronous two-port RAM with separate clocks for read and write ports.
+--  The synthesizer for Xilinx Spartan-3 will infer Block RAM for this entity.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity spwram is
+
+    generic (
+        abits:      integer;
+        dbits:      integer );
+
+    port (
+        rclk:       in  std_logic;
+        wclk:       in  std_logic;
+        ren:        in  std_logic;
+        raddr:      in  std_logic_vector(abits-1 downto 0);
+        rdata:      out std_logic_vector(dbits-1 downto 0);
+        wen:        in  std_logic;
+        waddr:      in  std_logic_vector(abits-1 downto 0);
+        wdata:      in  std_logic_vector(dbits-1 downto 0) );
+
+end entity spwram;
+
+architecture spwram_arch of spwram is
+
+    type mem_type is array(0 to (2**abits - 1)) of
+                     std_logic_vector(dbits-1 downto 0);
+
+    signal s_mem:   mem_type;
+
+begin
+
+    -- read process
+    process (rclk) is
+    begin
+        if rising_edge(rclk) then
+            if ren = '1' then
+                rdata <= s_mem(to_integer(unsigned(raddr)));
+            end if;
+        end if;
+    end process;
+
+    -- write process
+    process (wclk) is
+    begin
+        if rising_edge(wclk) then
+            if wen = '1' then
+                s_mem(to_integer(unsigned(waddr))) <= wdata;
+            end if;
+        end if;
+    end process;
+
+end architecture;
+
diff --git a/lib/opencores/spw_light/spwrecv.vhd b/lib/opencores/spw_light/spwrecv.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwrecv.vhd
@@ -0,0 +1,267 @@
+--
+--  SpaceWire Receiver
+--
+--  This entity decodes the sequence of incoming data bits into tokens.
+--  Data bits are passed to this entity from the Receiver Front-end
+--  in groups of rxchunk bits at a time.
+--
+--  The bitrate of the incoming SpaceWire signal must be strictly less
+--  than rxchunk times the system clock frequency. 
+--
+
+library ieee;
+use ieee.std_logic_1164.all, ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwrecv is
+
+    generic (
+        -- Disconnect timeout, expressed in system clock cycles.
+        -- Should be 850 ns (727 ns .. 1000 ns) according to the standard.
+        disconnect_time: integer range 1 to 255;
+
+        -- Nr of bits sampled per system clock.
+        rxchunk:        integer range 1 to 4
+    );
+
+    port (
+        -- System clock.
+	clk:        in  std_logic;
+
+        -- High to enable receiver; low to disable and reset receiver.
+        rxen:       in  std_logic;
+
+        -- Output signals to spwlink.
+        recvo:      out spw_recv_out_type;
+
+        -- High if there has been recent activity on the input lines.
+        inact:      in  std_logic;
+
+        -- High if inbits contains a valid group of received bits.
+        inbvalid:   in  std_logic;
+
+        -- Received bits from receiver front-end.
+        inbits:     in  std_logic_vector(rxchunk-1 downto 0)
+    );
+
+end entity spwrecv;
+
+architecture spwrecv_arch of spwrecv is
+
+    -- registers
+    type regs_type is record
+        -- receiver state
+        bit_seen:   std_ulogic;         -- got a bit transition
+        null_seen:  std_ulogic;         -- got a NULL token
+        -- input shift register
+        bitshift:   std_logic_vector(8 downto 0);
+        bitcnt:     std_logic_vector(9 downto 0);   -- one-hot counter
+        -- parity flag
+        parity:     std_ulogic;
+        -- decoding
+        control:    std_ulogic;         -- next code is control code
+        escaped:    std_ulogic;         -- last code was ESC
+        -- output registers
+        gotfct:     std_ulogic;
+        tick_out:   std_ulogic;
+        rxchar:     std_ulogic;
+        rxflag:     std_ulogic;
+        timereg:    std_logic_vector(7 downto 0);
+        datareg:    std_logic_vector(7 downto 0);
+        -- disconnect timer
+        disccnt:    unsigned(7 downto 0);
+        -- error flags
+        errpar:     std_ulogic;
+        erresc:     std_ulogic;
+    end record;
+
+    -- Initial state
+    constant regs_reset: regs_type := (
+        bit_seen    => '0',
+        null_seen   => '0',
+        bitshift    => (others => '1'),
+        bitcnt      => (others => '0'),
+        parity      => '0',
+        control     => '0',
+        escaped     => '0',
+        gotfct      => '0',
+        tick_out    => '0',
+        rxchar      => '0',
+        rxflag      => '0',
+        timereg     => (others => '0'),
+        datareg     => (others => '0'),
+        disccnt     => "00000000",
+        errpar      => '0',
+        erresc      => '0' );
+
+    -- registers
+    signal r:       regs_type := regs_reset;
+    signal rin:     regs_type;
+
+begin
+
+    -- combinatorial process
+    process  (r, rxen, inact, inbvalid, inbits)
+        variable v:         regs_type;
+        variable v_inbit:   std_ulogic;
+    begin
+        v           := r;
+        v_inbit     := '0';
+
+        -- disconnect timer
+        if inact = '1' then
+            -- activity on input; reset timer
+            v.disccnt   := to_unsigned(disconnect_time, v.disccnt'length);
+        elsif r.disccnt /= 0 then
+            -- count down
+            v.disccnt   := r.disccnt - 1;
+        end if;
+
+        -- assume no new token
+        v.gotfct    := '0';
+        v.tick_out  := '0';
+        v.rxchar    := '0';
+
+        if inbvalid = '1' then
+
+            -- process incoming bits
+            for i in 0 to rxchunk-1 loop
+                v_inbit     := inbits(i);
+
+                -- got a bit transition
+                v.bit_seen  := '1';
+
+                if v.bitcnt(0) = '1' then
+                    -- received new token
+                    -- note that this will not happen before null_seen='1'
+                    if (v.parity xor v_inbit) = '0' then
+                        -- Parity check failed.
+                        v.errpar    := '1';
+                    else
+                        if v.control = '1' then
+                            -- received control code
+                            case v.bitshift(7 downto 6) is
+                                when "00" => -- FCT or NULL
+                                    v.gotfct    := not r.escaped;
+                                    v.escaped   := '0';
+                                when "10" => -- EOP
+                                    if r.escaped = '1' then
+                                        v.erresc    := '1';
+                                    end if;
+                                    v.escaped   := '0';
+                                    v.rxchar    := not r.escaped;
+                                    v.rxflag    := '1';
+                                    v.datareg   := "00000000";
+                                when "01" => -- EEP
+                                    if r.escaped = '1' then
+                                        v.erresc    := '1';
+                                    end if;
+                                    v.escaped   := '0';
+                                    v.rxchar    := not r.escaped;
+                                    v.rxflag    := '1';
+                                    v.datareg   := "00000001";
+                                when others => -- ESC
+                                    if r.escaped = '1' then
+                                        v.erresc    := '1';
+                                    end if;
+                                    v.escaped   := '1';
+                            end case;
+                        else
+                            -- received 8-bit character
+                            if r.escaped = '1' then
+                                -- received Time-Code
+                                v.tick_out  := '1';
+                                v.timereg   := v.bitshift(7 downto 0);
+                            else
+                                -- received data character
+                                v.rxflag    := '0';
+                                v.rxchar    := '1';
+                                v.datareg   := v.bitshift(7 downto 0);
+                            end if;
+                            v.escaped   := '0';
+                        end if;
+                    end if;
+                    -- prepare for next code
+                    v.parity    := '0';
+                    v.control   := v_inbit;
+                    if v_inbit = '1' then
+                        -- next word will be control code.
+                        v.bitcnt    := (3 => '1', others => '0');
+                    else
+                        -- next word will be a data byte.
+                        v.bitcnt    := (9 => '1', others => '0');
+                    end if;
+                else
+                    -- wait until next code is completely received;
+                    -- accumulate parity
+                    v.bitcnt    := '0' & v.bitcnt(9 downto 1);
+                    v.parity    := v.parity xor v_inbit;
+                end if;
+
+                -- detect first NULL
+                if v.null_seen = '0' then
+                    if v.bitshift = "000101110" then
+                        -- got first NULL pattern
+                        v.null_seen := '1';
+                        v.control   := v_inbit; -- should always be '1'
+                        v.parity    := '0';
+                        v.bitcnt    := (3 => '1', others => '0');
+                    end if;
+                end if;
+
+                -- shift new bit into register.
+                v.bitshift  := v_inbit & v.bitshift(v.bitshift'high downto 1);
+
+            end loop;
+        end if;
+
+        -- synchronous reset
+        if rxen = '0' then
+            v.bit_seen  := '0';
+            v.null_seen := '0';
+            v.bitshift  := "111111111";
+            v.bitcnt    := (others => '0');
+            v.gotfct    := '0';
+            v.tick_out  := '0';
+            v.rxchar    := '0';
+            v.rxflag    := '0';
+            v.escaped   := '0';
+            v.timereg   := "00000000";
+            v.datareg   := "00000000";
+            v.disccnt   := to_unsigned(0, v.disccnt'length);
+            v.errpar    := '0';
+            v.erresc    := '0';
+        end if;
+
+        -- drive outputs
+        recvo.gotbit    <= r.bit_seen;
+        recvo.gotnull   <= r.null_seen;
+        recvo.gotfct    <= r.gotfct;
+        recvo.tick_out  <= r.tick_out;
+        recvo.ctrl_out  <= r.timereg(7 downto 6);
+        recvo.time_out  <= r.timereg(5 downto 0);
+        recvo.rxchar    <= r.rxchar;
+        recvo.rxflag    <= r.rxflag;
+        recvo.rxdata    <= r.datareg;
+        if r.bit_seen = '1' and r.disccnt = 0 then
+            recvo.errdisc   <= '1';
+        else
+            recvo.errdisc   <= '0';
+        end if;
+        recvo.errpar    <= r.errpar;
+        recvo.erresc    <= r.erresc;
+
+        -- update registers
+        rin         <= v;
+
+    end process;
+
+    -- update registers on rising edge of system clock
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwrecv_arch;
diff --git a/lib/opencores/spw_light/spwrecvfront_fast.vhd b/lib/opencores/spw_light/spwrecvfront_fast.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwrecvfront_fast.vhd
@@ -0,0 +1,424 @@
+--
+--  Front-end for SpaceWire Receiver
+--
+--  This entity samples the input signals DataIn and StrobeIn to detect
+--  valid bit transitions. Received bits are handed to the application
+--  in groups of "rxchunk" bits at a time, synchronous to the system clock.
+--
+--  This receiver is based on synchronous oversampling of the input signals.
+--  Inputs are sampled on the rising and falling edges of an externally
+--  supplied sample clock "rxclk". Therefore the maximum bitrate of the
+--  incoming signal must be significantly lower than two times the "rxclk"
+--  clock frequency. The maximum incoming bitrate must also be strictly
+--  lower than rxchunk times the system clock frequency.
+--
+--  This code is tuned for implementation on Xilinx Spartan-3.
+--
+--  Details
+--  -------
+--
+--  Stage A: The inputs "spw_di" and "spw_si" are handled as DDR signals,
+--  synchronously sampled on both edges of "rxclk".
+--
+--  Stage B: The input signals are re-registered on the rising edge of "rxclk"
+--  for further processing. This implies that every rising edge of "rxclk"
+--  produces two new samples of "spw_di" and two new samples of "spw_si".
+--
+--  Stage C: Transitions in input signals are detected by comparing the XOR
+--  of data and strobe to the XOR of the previous data and strobe samples.
+--  If there is a difference, we know that either data or strobe has changed
+--  and the new value of data is a valid new bit. Every rising edge of "rxclk"
+--  thus produces either zero, or one or two new data bits.
+--
+--  Stage D: Received bits are collected in groups of "rxchunk" bits
+--  (unless rxchunk=1, in which case groups of 2 bits are used). Complete
+--  groups are pushed into an 8-deep cyclic buffer. A 3-bit counter "headptr"
+--  indicates the current position in the cyclic buffer.
+--
+--  The system clock domain reads bit groups from the cyclic buffer. A tail
+--  pointer indicates the next location to read from the buffer. A comparison
+--  between the "tailptr" and a re-synchronized copy of the "headptr" determines
+--  whether valid bits are available in the buffer.
+--
+--  Activity detection is based on a 3-bit counter "bitcnt". This counter is
+--  incremented whenever the rxclk domain receives 1 or 2 new bits. The system
+--  clock domain monitors a re-synchronized copy of the activity counter to
+--  determine whether it has been updated since the previous system clock cycle.
+--
+--  Implementation guidelines 
+--  -------------------------
+--
+--  IOB flip-flops must be used to sample spw_di and spw_si.
+--  Clock skew between the IOBs for spw_di and spw_si must be minimized.
+--
+--  "rxclk" must be at least as fast as the system clock;
+--  "rxclk" does not need to be phase-related to the system clock;
+--  it is allowed for "rxclk" to be equal to the system clock.
+--
+--  The following timing constraints are needed:
+--   * PERIOD constraint on the system clock;
+--   * PERIOD constraint on "rxclk";
+--   * FROM-TO constraint from "rxclk" to system clock, equal to one "rxclk" period;
+--   * FROM-TO constraint from system clock to "rxclk", equal to one "rxclk" period.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwrecvfront_fast is
+
+    generic (
+        -- Number of bits to pass to the application per system clock.
+        rxchunk:        integer range 1 to 4 );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Sample clock.
+        rxclk:      in  std_logic;
+
+        -- High to enable receiver; low to disable and reset receiver.
+        rxen:       in  std_logic;
+
+        -- High if there has been recent activity on the input lines.
+        inact:      out std_logic;
+
+        -- High if inbits contains a valid group of received bits.
+        -- If inbvalid='1', the application must sample inbits on
+        -- the rising edge of clk.
+        inbvalid:   out std_logic;
+
+        -- Received bits (bit 0 is the earliest received bit).
+        inbits:     out std_logic_vector(rxchunk-1 downto 0);
+
+        -- Data In signal from SpaceWire bus.
+        spw_di:     in  std_logic;
+
+        -- Strobe In signal from SpaceWire bus.
+        spw_si:     in  std_logic );
+
+    -- Turn off FSM extraction.
+    -- Without this, XST will happily apply one-hot encoding to rrx.headptr.
+    attribute FSM_EXTRACT: string;
+    attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO";
+
+end entity spwrecvfront_fast;
+
+architecture spwrecvfront_arch of spwrecvfront_fast is
+
+    -- width of bit groups in cyclic buffer;
+    -- typically equal to rxchunk, except when rxchunk = 1
+    type memwidth_array_type is array(1 to 4) of integer;
+    constant chunk_to_memwidth: memwidth_array_type := ( 2, 2, 3, 4 );
+    constant memwidth: integer := chunk_to_memwidth(rxchunk);
+
+    -- registers in rxclk domain
+    type rxregs_type is record
+        -- stage B: re-register input samples
+        b_di0:      std_ulogic;
+        b_si0:      std_ulogic;
+        b_di1:      std_ulogic;
+        b_si1:      std_ulogic;
+        -- stage C: data/strobe decoding
+        c_bit:      std_logic_vector(1 downto 0);
+        c_val:      std_logic_vector(1 downto 0);
+        c_xor1:     std_ulogic;
+        -- stage D: collect groups of memwidth bits
+        d_shift:    std_logic_vector(memwidth-1 downto 0);
+        d_count:    std_logic_vector(memwidth-1 downto 0);
+        -- cyclic buffer access
+        bufdata:    std_logic_vector(memwidth-1 downto 0);
+        bufwrite:   std_ulogic;
+        headptr:    std_logic_vector(2 downto 0);
+        -- activity detection
+        bitcnt:     std_logic_vector(2 downto 0);
+    end record;
+
+    -- registers in system clock domain
+    type regs_type is record
+        -- data path from buffer to output
+        tailptr:    std_logic_vector(2 downto 0);
+        inbvalid:   std_ulogic;
+        -- split 2-bit groups if rxchunk=1
+        splitbit:   std_ulogic;
+        splitinx:   std_ulogic;
+        splitvalid: std_ulogic;
+        -- activity detection
+        bitcntp:    std_logic_vector(2 downto 0);
+        inact:      std_ulogic;
+        -- reset signal towards rxclk domain
+        rxdis:      std_ulogic;
+    end record;
+
+    constant regs_reset: regs_type := (
+        tailptr     => "000",
+        inbvalid    => '0',
+        splitbit    => '0',
+        splitinx    => '0',
+        splitvalid  => '0',
+        bitcntp     => "000",
+        inact       => '0',
+        rxdis       => '1' );
+
+    -- Signals that are re-synchronized from rxclk to system clock domain.
+    type syncsys_type is record
+        headptr:    std_logic_vector(2 downto 0);   -- pointer in cyclic buffer
+        bitcnt:     std_logic_vector(2 downto 0);   -- activity detection
+    end record;
+
+    -- Registers.
+    signal r:           regs_type := regs_reset;
+    signal rin:         regs_type;
+    signal rrx, rrxin:  rxregs_type;
+
+    -- Synchronized signals after crossing clock domains.
+    signal syncrx_rstn: std_logic;
+    signal syncsys:     syncsys_type;
+
+    -- Output data from cyclic buffer.
+    signal s_bufdout:   std_logic_vector(memwidth-1 downto 0);
+
+    -- stage A: input flip-flops for rising/falling rxclk
+    signal s_a_di0:     std_logic;
+    signal s_a_si0:     std_logic;
+    signal s_a_di1:     std_logic;
+    signal s_a_si1:     std_logic;
+    signal s_a_di2:     std_logic;
+    signal s_a_si2:     std_logic;
+
+    -- force use of IOB flip-flops
+    attribute IOB: string;
+    attribute IOB of s_a_di1: signal is "TRUE";
+    attribute IOB of s_a_si1: signal is "TRUE";
+    attribute IOB of s_a_di2: signal is "TRUE";
+    attribute IOB of s_a_si2: signal is "TRUE";
+
+begin
+
+    -- Cyclic data buffer.
+    bufmem: spwram
+        generic map (
+            abits   => 3,
+            dbits   => memwidth )
+        port map (
+            rclk    => clk,
+            wclk    => rxclk,
+            ren     => '1',
+            raddr   => r.tailptr,
+            rdata   => s_bufdout,
+            wen     => rrx.bufwrite,
+            waddr   => rrx.headptr,
+            wdata   => rrx.bufdata );
+
+    -- Synchronize reset signal for rxclk domain.
+    syncrx_reset: syncdff
+        port map ( clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn );
+
+    -- Synchronize signals from rxclk domain to system clock domain.
+    syncsys_headptr0: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0) );
+    syncsys_headptr1: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1) );
+    syncsys_headptr2: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2) );
+    syncsys_bitcnt0: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0) );
+    syncsys_bitcnt1: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1) );
+    syncsys_bitcnt2: syncdff
+        port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2) );
+
+    -- sample inputs on rising edge of rxclk
+    process (rxclk) is
+    begin
+        if rising_edge(rxclk) then
+            s_a_di1     <= spw_di;
+            s_a_si1     <= spw_si;
+        end if;
+    end process;
+
+    -- sample inputs on falling edge of rxclk
+    process (rxclk) is
+    begin
+        if falling_edge(rxclk) then
+            s_a_di2     <= spw_di;
+            s_a_si2     <= spw_si;
+            -- reregister inputs in fabric flip-flops
+            s_a_di0     <= s_a_di2;
+            s_a_si0     <= s_a_si2;
+        end if;
+    end process;
+
+    -- combinatorial process
+    process  (r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1)
+        variable v:     regs_type;
+        variable vrx:   rxregs_type;
+    begin
+        v       := r;
+        vrx     := rrx;
+
+        -- ---- SAMPLE CLOCK DOMAIN ----
+
+        -- stage B: re-register input samples
+        vrx.b_di0   := s_a_di0;
+        vrx.b_si0   := s_a_si0;
+        vrx.b_di1   := s_a_di1;
+        vrx.b_si1   := s_a_si1;
+
+        -- stage C: decode data/strobe and detect valid bits
+        if (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) = '1' then
+            vrx.c_bit(0) := rrx.b_di0;
+        else
+            vrx.c_bit(0) := rrx.b_di1;
+        end if;
+        vrx.c_bit(1) := rrx.b_di1;
+        vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or
+                        (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
+        vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and
+                        (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1);
+        vrx.c_xor1   := rrx.b_di1 xor rrx.b_si1;
+
+        -- Note:
+        -- c_val = "00" if no new bits are received
+        -- c_val = "01" if one new bit is received; the new bit is in c_bit(0)
+        -- c_val = "11" if two new bits are received
+
+        -- stage D: collect groups of memwidth bits
+        if rrx.c_val(0) = '1' then
+
+            -- shift incoming bits into register
+            if rrx.c_val(1) = '1' then
+                vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
+            else
+                vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
+            end if;
+
+            -- prepare to store a group of memwidth bits
+            if rrx.d_count(0) = '1' then
+                -- only one more bit needed
+                vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1);
+            else
+                vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2);
+            end if;
+
+            -- countdown nr of needed bits (one-hot counter)
+            if rrx.c_val(1) = '1' then
+                vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth-1 downto 2);
+            else
+                vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth-1 downto 1);
+            end if;
+
+        end if;
+
+        -- stage D: store groups of memwidth bits
+        vrx.bufwrite := rrx.c_val(0) and (rrx.d_count(0) or (rrx.c_val(1) and rrx.d_count(1)));
+
+        -- Increment head pointer.
+        if rrx.bufwrite = '1' then
+            vrx.headptr := std_logic_vector(unsigned(rrx.headptr) + 1);
+        end if;
+
+        -- Activity detection.
+        if rrx.c_val(0) = '1' then
+            vrx.bitcnt  := std_logic_vector(unsigned(rrx.bitcnt) + 1);
+        end if;
+
+        -- Synchronous reset of rxclk domain.
+        if syncrx_rstn = '0' then
+            vrx.c_val   := "00";
+            vrx.c_xor1  := '0';
+            vrx.d_count := (others => '0');
+            vrx.d_count(memwidth-1) := '1';
+            vrx.bufwrite := '0';
+            vrx.headptr := "000";
+            vrx.bitcnt  := "000";
+        end if;
+
+        -- ---- SYSTEM CLOCK DOMAIN ----
+
+        -- Compare tailptr to headptr to decide whether there is new data.
+        -- If the values are equal, we are about to read a location which has
+        -- not yet been written by the rxclk domain.
+        if r.tailptr = syncsys.headptr then
+            -- No more data in cyclic buffer.
+            v.inbvalid  := '0';
+        else
+            -- Reading valid data from cyclic buffer.
+            v.inbvalid  := '1';
+            -- Increment tail pointer.
+            if rxchunk /= 1 then
+                v.tailptr   := std_logic_vector(unsigned(r.tailptr) + 1);
+            end if;
+        end if;
+
+        -- If rxchunk=1, split 2-bit groups into separate bits.
+        if rxchunk = 1 then
+            -- Select one of the two bits.
+            if r.splitinx = '0' then
+                v.splitbit  := s_bufdout(0);
+            else
+                v.splitbit  := s_bufdout(1);
+            end if;
+            -- Indicate valid bit.
+            v.splitvalid := r.inbvalid;
+            -- Increment tail pointer.
+            if r.inbvalid = '1' then
+                v.splitinx   := not r.splitinx;
+                if r.splitinx = '0' then
+                    v.tailptr   := std_logic_vector(unsigned(r.tailptr) + 1);
+                end if;
+            end if;
+        end if;
+
+        -- Activity detection.
+        v.bitcntp   := syncsys.bitcnt;
+        if r.bitcntp = syncsys.bitcnt then
+            v.inact     := '0';
+        else
+            v.inact     := '1';
+        end if;
+
+        -- Synchronous reset of system clock domain.
+        if rxen = '0' then
+            v   := regs_reset;
+        end if;
+
+        -- Register rxen to ensure glitch-free signal to rxclk domain
+        v.rxdis     := not rxen;
+
+        -- drive outputs
+        inact       <= r.inact;
+        if rxchunk = 1 then
+            inbvalid    <= r.splitvalid;
+            inbits(0)   <= r.splitbit;
+        else
+            inbvalid    <= r.inbvalid;
+            inbits      <= s_bufdout;
+        end if;
+
+        -- update registers
+        rrxin       <= vrx;
+        rin         <= v;
+
+    end process;
+
+    -- update registers on rising edge of rxclk
+    process (rxclk) is
+    begin
+        if rising_edge(rxclk) then
+            rrx <= rrxin;
+        end if;
+    end process;
+
+    -- update registers on rising edge of system clock
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwrecvfront_arch;
diff --git a/lib/opencores/spw_light/spwrecvfront_generic.vhd b/lib/opencores/spw_light/spwrecvfront_generic.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwrecvfront_generic.vhd
@@ -0,0 +1,96 @@
+--
+--  Front-end for SpaceWire Receiver
+--
+--  This entity samples the input signals DataIn and StrobeIn to detect
+--  valid bit transitions. Received bits are handed to the application.
+--
+--  Inputs are sampled on the rising edge of the system clock, therefore
+--  the maximum bitrate of the incoming signal must be significantly lower
+--  than system clock frequency.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity spwrecvfront_generic is
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- High to enable receiver; low to disable and reset receiver.
+        rxen:       in  std_logic;
+
+        -- High if there has been recent activity on the input lines.
+        inact:      out std_logic;
+
+        -- High if inbits contains a valid received bit.
+        -- If inbvalid='1', the application must sample inbits on
+        -- the rising edge of clk.
+        inbvalid:   out std_logic;
+
+        -- Received bit
+        inbits:     out std_logic_vector(0 downto 0);
+
+        -- Data In signal from SpaceWire bus.
+        spw_di:     in  std_logic;
+
+        -- Strobe In signal from SpaceWire bus.
+        spw_si:     in  std_logic );
+
+end entity spwrecvfront_generic;
+
+architecture spwrecvfront_arch of spwrecvfront_generic is
+
+    -- input flip-flops
+    signal s_spwdi1:    std_ulogic;
+    signal s_spwsi1:    std_ulogic;
+    signal s_spwdi2:    std_ulogic;
+    signal s_spwsi2:    std_ulogic;
+
+    -- data/strobe decoding
+    signal s_spwsi3:    std_ulogic;
+
+    -- output registers
+    signal s_inbvalid:  std_ulogic;
+    signal s_inbit:     std_ulogic;
+
+begin
+
+    -- drive outputs
+    inact       <= s_inbvalid;
+    inbvalid    <= s_inbvalid;
+    inbits(0)   <= s_inbit;
+
+    -- synchronous process
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+
+            -- sample input signal
+            s_spwdi1    <= spw_di;
+            s_spwsi1    <= spw_si;
+
+            -- more flip-flops for safe synchronization
+            s_spwdi2    <= s_spwdi1;
+            s_spwsi2    <= s_spwsi1;
+
+            -- keep strobe signal for data/strobe decoding
+            s_spwsi3    <= s_spwsi2;
+
+            -- keep data bit for data/strobe decoding
+            s_inbit     <= s_spwdi2;
+
+            if rxen = '1' then
+                -- data/strobe decoding
+                s_inbvalid  <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3;
+            else
+                -- reset receiver
+                s_inbvalid  <= '0';
+            end if;
+
+        end if;
+    end process;
+
+end architecture spwrecvfront_arch;
diff --git a/lib/opencores/spw_light/spwstream.vhd b/lib/opencores/spw_light/spwstream.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwstream.vhd
@@ -0,0 +1,547 @@
+--
+--  SpaceWire core with character-stream interface.
+--
+--  This entity provides a SpaceWire core with a character-stream interface.
+--  The interface provides means for connection initiation, sending and
+--  receiving of N-Chars and TimeCodes, and error reporting.
+--
+--  This entity instantiates spwlink, spwrecv, spwxmit and one of the
+--  spwrecvfront implementations. It also implements a receive FIFO and
+--  a transmit FIFO.
+--
+--  The SpaceWire standard requires that each transceiver use an initial
+--  signalling rate of 10 Mbit/s. This implies that the system clock frequency
+--  must be a multiple of 10 MHz. See the manual for further details on
+--  bitrates and clocking.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwstream is
+
+    generic (
+        -- System clock frequency in Hz.
+        -- This must be set to the frequency of "clk". It is used to setup
+        -- counters for reset timing, disconnect timeout and to transmit
+        -- at 10 Mbit/s during the link handshake.
+        sysfreq:        real;
+
+        -- Transmit clock frequency in Hz (only if tximpl = impl_fast).
+        -- This must be set to the frequency of "txclk". It is used to
+        -- transmit at 10 Mbit/s during the link handshake.
+        txclkfreq:      real := 0.0;
+
+        -- Selection of a receiver front-end implementation.
+        rximpl:         spw_implementation_type := impl_generic;
+
+        -- Maximum number of bits received per system clock
+        -- (must be 1 in case of impl_generic).
+        rxchunk:        integer range 1 to 4 := 1;
+
+        -- Selection of a transmitter implementation.
+        tximpl:         spw_implementation_type := impl_generic;
+
+        -- Size of the receive FIFO as the 2-logarithm of the number of bytes.
+        -- Must be at least 6 (64 bytes).
+        rxfifosize_bits: integer range 6 to 14 := 11;
+
+        -- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
+        txfifosize_bits: integer range 2 to 14 := 11
+    );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Receiver sample clock (only for impl_fast)
+        rxclk:      in  std_logic;
+
+        -- Transmit clock (only for impl_fast)
+        txclk:      in  std_logic;
+
+        -- Synchronous reset (active-high).
+        rst:        in  std_logic;
+
+        -- Enables automatic link start on receipt of a NULL character.
+        autostart:  in  std_logic;
+
+        -- Enables link start once the Ready state is reached.
+        -- Without autostart or linkstart, the link remains in state Ready.
+        linkstart:  in  std_logic;
+
+        -- Do not start link (overrides linkstart and autostart) and/or
+        -- disconnect a running link.
+        linkdis:    in  std_logic;
+
+        -- Scaling factor minus 1, used to scale the transmit base clock into
+        -- the transmission bit rate. The system clock (for impl_generic) or
+        -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
+        -- Changing this signal will immediately change the transmission rate.
+        -- During link setup, the transmission rate is always 10 Mbit/s.
+        txdivcnt:   in  std_logic_vector(7 downto 0);
+
+        -- High for one clock cycle to request transmission of a TimeCode.
+        -- The request is registered inside the entity until it can be processed.
+        tick_in:    in  std_logic;
+
+        -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
+        ctrl_in:    in  std_logic_vector(1 downto 0);
+
+        -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
+        time_in:    in  std_logic_vector(5 downto 0);
+
+        -- Pulled high by the application to write an N-Char to the transmit
+        -- queue. If "txwrite" and "txrdy" are both high on the rising edge
+        -- of "clk", a character is added to the transmit queue.
+        -- This signal has no effect if "txrdy" is low.
+        txwrite:    in  std_logic;
+
+        -- Control flag to be sent with the next N_Char.
+        -- Must be valid while txwrite is high.
+        txflag:     in  std_logic;
+
+        -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
+        -- Must be valid while txwrite is high.
+        txdata:     in  std_logic_vector(7 downto 0);
+
+        -- High if the entity is ready to accept an N-Char for transmission.
+        txrdy:      out std_logic;
+
+        -- High if the transmission queue is at least half full.
+        txhalff:    out std_logic;
+
+        -- High for one clock cycle if a TimeCode was just received.
+        tick_out:   out std_logic;
+
+        -- Control bits of the last received TimeCode.
+        ctrl_out:   out std_logic_vector(1 downto 0);
+
+        -- Counter value of the last received TimeCode.
+        time_out:   out std_logic_vector(5 downto 0);
+
+        -- High if "rxflag" and "rxdata" contain valid data.
+        -- This signal is high unless the receive FIFO is empty.
+        rxvalid:    out std_logic;
+
+        -- High if the receive FIFO is at least half full.
+        rxhalff:    out std_logic;
+
+        -- High if the received character is EOP or EEP; low if the received
+        -- character is a data byte. Valid if "rxvalid" is high.
+        rxflag:     out std_logic;
+
+        -- Received byte, or "00000000" for EOP or "00000001" for EEP.
+        -- Valid if "rxvalid" is high.
+        rxdata:     out std_logic_vector(7 downto 0);
+
+        -- Pulled high by the application to accept a received character.
+        -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
+        -- a character is removed from the receive FIFO and "rxvalid", "rxflag"
+        -- and "rxdata" are updated.
+        -- This signal has no effect if "rxvalid" is low.
+        rxread:     in  std_logic;
+
+        -- High if the link state machine is currently in the Started state.
+        started:    out std_logic;
+
+        -- High if the link state machine is currently in the Connecting state.
+        connecting: out std_logic;
+
+        -- High if the link state machine is currently in the Run state, indicating
+        -- that the link is fully operational. If none of started, connecting or running
+        -- is high, the link is in an initial state and the transmitter is not yet enabled.
+        running:    out std_logic;
+
+        -- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
+        -- This indication is auto-clearing.
+        errdisc:    out std_logic;
+
+        -- Parity error detected in state Run. Triggers a reset and reconnect of the link.
+        -- This indication is auto-clearing.
+        errpar:     out std_logic;
+
+        -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
+        -- the link. This indication is auto-clearing.
+        erresc:     out std_logic;
+
+        -- Credit error detected. Triggers a reset and reconnect of the link.
+        -- This indication is auto-clearing.
+        errcred:    out std_logic;
+
+        -- Data In signal from SpaceWire bus.
+        spw_di:     in  std_logic;
+
+        -- Strobe In signal from SpaceWire bus.
+        spw_si:     in  std_logic;
+
+        -- Data Out signal to SpaceWire bus.
+        spw_do:     out std_logic;
+
+        -- Strobe Out signal to SpaceWire bus.
+        spw_so:     out std_logic
+    );
+
+end entity spwstream;
+
+architecture spwstream_arch of spwstream is
+
+    -- Convert boolean to std_logic.
+    type bool_to_logic_type is array(boolean) of std_ulogic;
+    constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
+
+    -- Reset time (6.4 us) in system clocks
+    constant reset_time:        integer := integer(sysfreq * 6.4e-6);
+
+    -- Disconnect time (850 ns) in system clocks
+    constant disconnect_time:   integer := integer(sysfreq * 850.0e-9);
+
+    -- Initial tx clock scaler (10 Mbit).
+    type impl_to_real_type is array(spw_implementation_type) of real;
+    constant tximpl_to_txclk_freq: impl_to_real_type :=
+        (impl_generic => sysfreq, impl_fast => txclkfreq);
+    constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
+    constant default_divcnt:    std_logic_vector(7 downto 0) :=
+        std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
+
+    -- Registers.
+    type regs_type is record
+        -- packet state
+        rxpacket:       std_logic;      -- '1' when receiving a packet
+        rxeep:          std_logic;      -- '1' when rx EEP character pending
+        txpacket:       std_logic;      -- '1' when transmitting a packet
+        txdiscard:      std_logic;      -- '1' when discarding a tx packet
+        -- FIFO pointers
+        rxfifo_raddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
+        rxfifo_waddr:   std_logic_vector(rxfifosize_bits-1 downto 0);
+        txfifo_raddr:   std_logic_vector(txfifosize_bits-1 downto 0);
+        txfifo_waddr:   std_logic_vector(txfifosize_bits-1 downto 0);
+        -- FIFO state
+        rxfifo_rvalid:  std_logic;      -- '1' if s_rxfifo_rdata is valid
+        txfifo_rvalid:  std_logic;      -- '1' if s_txfifo_rdata is valid
+        rxfull:         std_logic;      -- '1' if RX fifo is full
+        rxhalff:        std_logic;      -- '1' if RX fifo is at least half full
+        txfull:         std_logic;      -- '1' if TX fifo is full
+        txhalff:        std_logic;      -- '1' if TX fifo is at least half full
+        rxroom:         std_logic_vector(5 downto 0);
+    end record;
+
+    constant regs_reset: regs_type := (
+        rxpacket        => '0',
+        rxeep           => '0',
+        txpacket        => '0',
+        txdiscard       => '0',
+        rxfifo_raddr    => (others => '0'),
+        rxfifo_waddr    => (others => '0'),
+        txfifo_raddr    => (others => '0'),
+        txfifo_waddr    => (others => '0'),
+        rxfifo_rvalid   => '0',
+        txfifo_rvalid   => '0',
+        rxfull          => '0',
+        rxhalff         => '0',
+        txfull          => '0',
+        txhalff         => '0',
+        rxroom          => (others => '0') );
+
+    signal r: regs_type := regs_reset;
+    signal rin: regs_type;
+
+    -- Interface signals to components.
+    signal recv_rxen:       std_logic;
+    signal recvo:           spw_recv_out_type;
+    signal recv_inact:      std_logic;
+    signal recv_inbvalid:   std_logic;
+    signal recv_inbits:     std_logic_vector(rxchunk-1 downto 0);
+    signal xmiti:           spw_xmit_in_type;
+    signal xmito:           spw_xmit_out_type;
+    signal xmit_divcnt:     std_logic_vector(7 downto 0);
+    signal linki:           spw_link_in_type;
+    signal linko:           spw_link_out_type;
+
+    -- Memory interface signals.
+    signal s_rxfifo_raddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
+    signal s_rxfifo_rdata:  std_logic_vector(8 downto 0);
+    signal s_rxfifo_wen:    std_logic;
+    signal s_rxfifo_waddr:  std_logic_vector(rxfifosize_bits-1 downto 0);
+    signal s_rxfifo_wdata:  std_logic_vector(8 downto 0);
+    signal s_txfifo_raddr:  std_logic_vector(txfifosize_bits-1 downto 0);
+    signal s_txfifo_rdata:  std_logic_vector(8 downto 0);
+    signal s_txfifo_wen:    std_logic;
+    signal s_txfifo_waddr:  std_logic_vector(txfifosize_bits-1 downto 0);
+    signal s_txfifo_wdata:  std_logic_vector(8 downto 0);
+
+begin
+
+    -- Instantiate link controller.
+    link_inst: spwlink
+        generic map (
+            reset_time  => reset_time )
+        port map (
+            clk         => clk,
+            rst         => rst,
+            linki       => linki,
+            linko       => linko,
+            rxen        => recv_rxen,
+            recvo       => recvo,
+            xmiti       => xmiti,
+            xmito       => xmito );
+
+    -- Instantiate receiver.
+    recv_inst: spwrecv
+        generic map(
+            disconnect_time => disconnect_time,
+            rxchunk     => rxchunk )
+        port map (
+            clk         => clk,
+            rxen        => recv_rxen,
+            recvo       => recvo,
+            inact       => recv_inact,
+            inbvalid    => recv_inbvalid,
+            inbits      => recv_inbits );
+
+    -- Instantiate transmitter.
+    xmit_sel0: if tximpl = impl_generic generate
+        xmit_inst: spwxmit
+            port map (
+                clk     => clk,
+                rst     => rst,
+                divcnt  => xmit_divcnt,
+                xmiti   => xmiti,
+                xmito   => xmito,
+                spw_do  => spw_do,
+                spw_so  => spw_so );
+    end generate;
+    xmit_sel1: if tximpl = impl_fast generate
+        xmit_fast_inst: spwxmit_fast
+            port map (
+                clk     => clk,
+                txclk   => txclk,
+                rst     => rst,
+                divcnt  => xmit_divcnt,
+                xmiti   => xmiti,
+                xmito   => xmito,
+                spw_do  => spw_do,
+                spw_so  => spw_so );
+    end generate;
+
+    -- Instantiate receiver front-end.
+    recvfront_sel0: if rximpl = impl_generic generate
+        recvfront_generic_inst: spwrecvfront_generic
+            port map (
+                clk         => clk,
+                rxen        => recv_rxen,
+                inact       => recv_inact,
+                inbvalid    => recv_inbvalid,
+                inbits      => recv_inbits,
+                spw_di      => spw_di,
+                spw_si      => spw_si );
+    end generate;
+    recvfront_sel1: if rximpl = impl_fast generate
+        recvfront_fast_inst: spwrecvfront_fast
+            generic map (
+                rxchunk     => rxchunk )
+            port map (
+                clk         => clk,
+                rxclk       => rxclk,
+                rxen        => recv_rxen,
+                inact       => recv_inact,
+                inbvalid    => recv_inbvalid,
+                inbits      => recv_inbits,
+                spw_di      => spw_di,
+                spw_si      => spw_si );
+    end generate;
+
+    -- Instantiate RX memory.
+    rxmem: spwram
+        generic map (
+            abits       => rxfifosize_bits,
+            dbits       => 9 )
+        port map (
+            rclk        => clk,
+            wclk        => clk,
+            ren         => '1',
+            raddr       => s_rxfifo_raddr,
+            rdata       => s_rxfifo_rdata,
+            wen         => s_rxfifo_wen,
+            waddr       => s_rxfifo_waddr,
+            wdata       => s_rxfifo_wdata );
+
+    -- Instantiate TX memory.
+    txmem: spwram
+        generic map (
+            abits       => txfifosize_bits,
+            dbits       => 9 )
+        port map (
+            rclk        => clk,
+            wclk        => clk,
+            ren         => '1',
+            raddr       => s_txfifo_raddr,
+            rdata       => s_txfifo_rdata,
+            wen         => s_txfifo_wen,
+            waddr       => s_txfifo_waddr,
+            wdata       => s_txfifo_wdata );
+
+    -- Combinatorial process
+    process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread)  is
+        variable v:             regs_type;
+        variable v_tmprxroom:   unsigned(rxfifosize_bits-1 downto 0);
+        variable v_tmptxroom:   unsigned(txfifosize_bits-1 downto 0);
+    begin
+        v           := r;
+        v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
+        v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
+
+        -- Keep track of whether we are sending and/or receiving a packet.
+        if linko.rxchar = '1' then
+            -- got character
+            v.rxpacket  := not linko.rxflag;
+        end if;
+        if linko.txack = '1' then
+            -- send character
+            v.txpacket  := not s_txfifo_rdata(8);
+        end if;
+
+        -- Update RX fifo pointers.
+        if (rxread = '1') and (r.rxfifo_rvalid = '1') then
+            -- read from fifo
+            v.rxfifo_raddr  := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
+        end if;
+        if r.rxfull = '0' then
+            if (linko.rxchar = '1') or (r.rxeep = '1') then
+                -- write to fifo (received char or pending EEP)
+                v.rxfifo_waddr  := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
+            end if;
+            v.rxeep         := '0';
+        end if;
+
+        -- Keep track of whether the RX fifo contains valid data.
+        -- (use new value of rxfifo_raddr)
+        v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
+
+        -- Update room in RX fifo (use new value of rxfifo_waddr).
+        v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
+        v.rxfull    := bool_to_logic(v_tmprxroom = 0);
+        v.rxhalff   := not v_tmprxroom(v_tmprxroom'high);
+        if v_tmprxroom > 63 then
+            v.rxroom    := (others => '1');
+        else
+            v.rxroom    := std_logic_vector(v_tmprxroom(5 downto 0));
+        end if;
+
+        -- Update TX fifo pointers.
+        if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
+            -- read from fifo
+            v.txfifo_raddr  := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
+            if s_txfifo_rdata(8) = '1' then
+                v.txdiscard := '0';     -- got EOP/EEP, stop discarding data
+            end if;
+        end if;
+        if (r.txfull = '0') and (txwrite = '1') then
+            -- write to fifo
+            v.txfifo_waddr  := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
+        end if;
+
+        -- Keep track of whether the TX fifo contains valid data.
+        -- (use new value of txfifo_raddr)
+        v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
+
+        -- Update room in TX fifo (use new value of txfifo_waddr).
+        v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
+        v.txfull    := bool_to_logic(v_tmptxroom = 0);
+        v.txhalff   := not v_tmptxroom(v_tmptxroom'high);
+ 
+        -- If the link is lost, set a flag to discard the current packet.
+        if linko.running = '0' then
+            v.rxeep     := v.rxeep or v.rxpacket;       -- use new value of rxpacket
+            v.txdiscard := v.txdiscard or v.txpacket;   -- use new value of txpacket
+            v.rxpacket  := '0';
+            v.txpacket  := '0';
+        end if;
+
+        -- Clear the discard flag when the link is explicitly disabled.
+        if linkdis = '1' then
+            v.txdiscard := '0';
+        end if;
+
+        -- Drive control signals to RX fifo.
+        s_rxfifo_raddr  <= v.rxfifo_raddr;  -- using new value of rxfifo_raddr
+        s_rxfifo_wen    <= (not r.rxfull) and (linko.rxchar or r.rxeep);
+        s_rxfifo_waddr  <= r.rxfifo_waddr;
+        if r.rxeep = '1' then
+            s_rxfifo_wdata  <= "100000001";
+        else
+            s_rxfifo_wdata  <= linko.rxflag & linko.rxdata;
+        end if;
+
+        -- Drive control signals to TX fifo.
+        s_txfifo_raddr  <= v.txfifo_raddr;  -- using new value of txfifo_raddr
+        s_txfifo_wen    <= (not r.txfull) and txwrite;
+        s_txfifo_waddr  <= r.txfifo_waddr;
+        s_txfifo_wdata  <= txflag & txdata;
+
+        -- Drive inputs to spwlink.
+        linki.autostart <= autostart;
+        linki.linkstart <= linkstart;
+        linki.linkdis   <= linkdis;
+        linki.rxroom    <= r.rxroom;
+        linki.tick_in   <= tick_in;
+        linki.ctrl_in   <= ctrl_in;
+        linki.time_in   <= time_in;
+        linki.txwrite   <= r.txfifo_rvalid and not r.txdiscard;
+        linki.txflag    <= s_txfifo_rdata(8);
+        linki.txdata    <= s_txfifo_rdata(7 downto 0);
+
+        -- Drive divcnt input to spwxmit.
+        if linko.running = '1' then
+            xmit_divcnt <= txdivcnt;
+        else
+            xmit_divcnt <= default_divcnt;
+        end if;
+
+        -- Drive outputs.
+        txrdy       <= not r.txfull;
+        txhalff     <= r.txhalff;
+        tick_out    <= linko.tick_out;
+        ctrl_out    <= linko.ctrl_out;
+        time_out    <= linko.time_out;
+        rxvalid     <= r.rxfifo_rvalid;
+        rxhalff     <= r.rxhalff;
+        rxflag      <= s_rxfifo_rdata(8);
+        rxdata      <= s_rxfifo_rdata(7 downto 0);
+        started     <= linko.started;
+        connecting  <= linko.connecting;
+        running     <= linko.running;
+        errdisc     <= linko.errdisc;
+        errpar      <= linko.errpar;
+        erresc      <= linko.erresc;
+        errcred     <= linko.errcred;
+
+        -- Reset.
+        if rst = '1' then
+            v.rxpacket      := '0';
+            v.rxeep         := '0';
+            v.txpacket      := '0';
+            v.txdiscard     := '0';
+            v.rxfifo_raddr  := (others => '0');
+            v.rxfifo_waddr  := (others => '0');
+            v.txfifo_raddr  := (others => '0');
+            v.txfifo_waddr  := (others => '0');
+            v.rxfifo_rvalid := '0';
+            v.txfifo_rvalid := '0';
+        end if;
+
+        -- Update registers.
+        rin <= v;
+    end process;
+
+    -- Update registers.
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwstream_arch;
diff --git a/lib/opencores/spw_light/spwxmit.vhd b/lib/opencores/spw_light/spwxmit.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwxmit.vhd
@@ -0,0 +1,249 @@
+--
+--  SpaceWire Transmitter
+--
+--  This entity translates outgoing characters and tokens into
+--  data-strobe signalling.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwxmit is
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Synchronous reset (active-high).
+        rst:        in  std_logic;
+
+        -- Scaling factor minus 1, used to scale the system clock into the
+        -- transmission bit rate. The system clock is divided by
+        -- (unsigned(divcnt) + 1). Changing this signal will immediately
+        -- change the transmission rate.
+        divcnt:     in  std_logic_vector(7 downto 0);
+
+        -- Input signals from spwlink.
+        xmiti:      in  spw_xmit_in_type;
+
+        -- Output signals to spwlink.
+        xmito:      out spw_xmit_out_type;
+
+        -- Data Out signal to SpaceWire bus.
+        spw_do:     out std_logic;
+
+        -- Strobe Out signal to SpaceWire bus.
+        spw_so:     out std_logic
+    );
+
+end entity spwxmit;
+
+architecture spwxmit_arch of spwxmit is
+
+    -- Registers
+    type regs_type is record
+        -- tx clock
+        txclken:    std_ulogic;         -- high if a bit must be transmitted
+        txclkcnt:   unsigned(7 downto 0);
+        -- output shift register
+        bitshift:   std_logic_vector(12 downto 0);
+        bitcnt:     unsigned(3 downto 0);
+        -- output signals
+        out_data:   std_ulogic;
+        out_strobe: std_ulogic;
+        -- parity flag
+        parity:     std_ulogic;
+        -- pending time tick
+        pend_tick:  std_ulogic;
+        pend_time:  std_logic_vector(7 downto 0);
+        -- transmitter mode
+        allow_fct:  std_ulogic;         -- allowed to send FCTs
+        allow_char: std_ulogic;         -- allowed to send data and time
+        sent_null:  std_ulogic;         -- sent at least one NULL token
+        sent_fct:   std_ulogic;         -- sent at least one FCT token
+    end record;
+
+    -- Initial state
+    constant regs_reset: regs_type := (
+        txclken     => '0',
+        txclkcnt    => "00000000",
+        bitshift    => (others => '0'),
+        bitcnt      => "0000",
+        out_data    => '0',
+        out_strobe  => '0',
+        parity      => '0',
+        pend_tick   => '0',
+        pend_time   => (others => '0'),
+        allow_fct   => '0',
+        allow_char  => '0',
+        sent_null   => '0',
+        sent_fct    => '0' );
+
+    -- Registers
+    signal r:       regs_type := regs_reset;
+    signal rin:     regs_type;
+
+begin
+
+    -- Combinatorial process
+    process (r, rst, divcnt, xmiti) is
+        variable v: regs_type;
+    begin
+        v := r;
+
+        -- Generate TX clock.
+        if r.txclkcnt = 0 then
+            v.txclkcnt  := unsigned(divcnt);
+            v.txclken   := '1';
+        else
+            v.txclkcnt  := r.txclkcnt - 1;
+            v.txclken   := '0';
+        end if;
+
+        if xmiti.txen = '0' then
+
+            -- Transmitter disabled; reset state.
+            v.bitcnt     := "0000";
+            v.parity     := '0';
+            v.pend_tick  := '0';
+            v.allow_fct  := '0';
+            v.allow_char := '0';
+            v.sent_null  := '0';
+            v.sent_fct   := '0';
+
+            -- Gentle reset of spacewire bus signals
+            if r.txclken = '1' then
+                v.out_data   := r.out_data and r.out_strobe;
+                v.out_strobe := '0';
+            end if;
+
+        else
+            -- Transmitter enabled.
+
+            v.allow_fct  := (not xmiti.stnull) and r.sent_null;
+            v.allow_char := (not xmiti.stnull) and r.sent_null and
+                            (not xmiti.stfct) and r.sent_fct;
+
+            -- On tick of transmission clock, put next bit on the output.
+            if r.txclken = '1' then
+
+                if r.bitcnt = 0 then
+
+                    -- Need to start a new character.
+                    if (r.allow_char = '1') and (r.pend_tick = '1') then
+                        -- Send Time-Code.
+                        v.out_data  := r.parity;
+                        v.bitshift(12 downto 5) := r.pend_time;
+                        v.bitshift(4 downto 0)  := "01111";
+                        v.bitcnt    := to_unsigned(13, v.bitcnt'length);
+                        v.parity    := '0';
+                        v.pend_tick := '0';
+                    elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then
+                        -- Send FCT.
+                        v.out_data  := r.parity;
+                        v.bitshift(2 downto 0)  := "001";
+                        v.bitcnt    := to_unsigned(3, v.bitcnt'length);
+                        v.parity    := '1';
+                        v.sent_fct  := '1';
+                    elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then
+                        -- Send N-Char.
+                        v.bitshift(0) := xmiti.txflag;
+                        v.parity    := xmiti.txflag;
+                        if xmiti.txflag = '0' then
+                            -- Data byte
+                            v.out_data  := not r.parity;
+                            v.bitshift(8 downto 1) := xmiti.txdata;
+                            v.bitcnt    := to_unsigned(9, v.bitcnt'length);
+                        else
+                            -- EOP or EEP
+                            v.out_data  := r.parity;
+                            v.bitshift(1) := xmiti.txdata(0);
+                            v.bitshift(2) := not xmiti.txdata(0);
+                            v.bitcnt    := to_unsigned(3, v.bitcnt'length);
+                        end if;
+                    else
+                        -- Send NULL.
+                        v.out_data  := r.parity;
+                        v.bitshift(6 downto 0) := "0010111";
+                        v.bitcnt    := to_unsigned(7, v.bitcnt'length);
+                        v.parity    := '0';
+                        v.sent_null := '1';
+                    end if;
+
+                else
+
+                    -- Shift next bit to the output.
+                    v.out_data  := r.bitshift(0);
+                    v.parity    := r.parity xor r.bitshift(0);
+                    v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1);
+                    v.bitcnt    := r.bitcnt - 1;
+
+                end if;
+
+                -- Data-Strobe encoding.
+                v.out_strobe := not (r.out_strobe xor r.out_data xor v.out_data);
+
+            end if;
+
+            -- Store requests for time tick transmission.
+            if xmiti.tick_in = '1' then
+                v.pend_tick := '1';
+                v.pend_time := xmiti.ctrl_in & xmiti.time_in;
+            end if;
+
+        end if;
+
+        -- Synchronous reset
+        if rst = '1' then
+            v := regs_reset;
+        end if;
+
+        -- Drive outputs.
+        -- Note: the outputs are combinatorially dependent on certain inputs.
+
+        -- Set fctack high if (transmitter enabled) AND
+        -- (ready for token) AND (FCTs allowed) AND
+        -- ((characters not allowed) OR (no timecode pending)) AND
+        -- (FCT requested)
+        if (xmiti.txen = '1') and
+           (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and
+           ((r.allow_char = '0') or (r.pend_tick = '0')) then
+            xmito.fctack  <= xmiti.fct_in;
+        else
+            xmito.fctack  <= '0';
+        end if;
+
+        -- Set txrdy high if (transmitter enabled) AND
+        -- (ready for token) AND (characters enabled) AND
+        -- (no timecode pending) AND (no FCT requested) AND
+        -- (character requested)
+        if (xmiti.txen = '1') and
+           (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and
+           (r.pend_tick = '0') and (xmiti.fct_in = '0') then
+            xmito.txack   <= xmiti.txwrite;
+        else
+            xmito.txack   <= '0';
+        end if;
+
+        -- Update registers
+        rin <= v;
+    end process;
+
+    -- Synchronous process
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+
+            -- Update registers
+            r <= rin;
+
+            -- Drive spacewire output signals
+            spw_do  <= r.out_data;
+            spw_so  <= r.out_strobe;
+
+        end if;
+    end process;
+
+end architecture spwxmit_arch;
diff --git a/lib/opencores/spw_light/spwxmit_fast.vhd b/lib/opencores/spw_light/spwxmit_fast.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/spwxmit_fast.vhd
@@ -0,0 +1,721 @@
+--
+--  SpaceWire Transmitter
+--
+--  This entity translates outgoing characters and tokens into
+--  data-strobe signalling.
+--
+--  The output stage is driven by a separate transmission clock "txclk" which
+--  will typically be faster than the system clock. The actual transmission
+--  rate is determined by dividing the transmission clock by an integer factor.
+--
+--  The code is tuned for implementation on Xilinx Spartan-3.
+--
+--  Concept
+--  -------
+--
+--  Logic in the system clock domain generates a stream of tokens to be
+--  transmitted. These tokens are encoded as instances of the token_type
+--  record. Tokens are queued in a two-slot FIFO buffer (r.token0 and r.token1)
+--  with a 1-bit pointer (r.tokmux) pointing to the head of the queue.
+--  When a token is pushed into the buffer, a flag register is flipped
+--  (r.sysflip0 and r.sysflip1) to indicate to the txclk domain that the
+--  buffer slot has been refilled.
+--
+--  The txclk domain pulls tokens from the FIFO buffer, flipping flag
+--  registers (rtx.txflip0 and rtx.txflip1) to indicate to the system clock
+--  domain that a token has been pulled. When the system clock domain detects
+--  that a token has been consumed, it refills the buffer slot with a new
+--  token (assuming that there are tokens waiting to be transmitted).
+--  Whenever the FIFO buffer is empty, the txclk domain sends NULLs instead.
+--  This can happen either when there are no tokens to send, or when the
+--  system clock domain is late to refill the buffer.
+--
+--  Details
+--  -------
+--
+--  Logic in the system clock domain accepts transmission requests through
+--  the external interface of the entity. Pending requests are translated
+--  into a stream of tokens. The tokens are pushed to the txclk domain through
+--  the FIFO buffer as described above.
+--
+--  The data path through the txclk domain is divided into stages B through F
+--  in a half-hearted attempt to keep things simple.
+--
+--  Stage B takes a token from the FIFO buffer and updates a buffer status
+--  flag to indicate that the buffer slot needs to be refilled. If the FIFO
+--  is empty, a NULL is inserted. Stage B is triggered one clock after
+--  stage E switches to a new token. If the previous token was ESC, stage B
+--  skips a turn because stage C will already know what to do.
+--
+--  Stage C takes a token from stage B and translates it into a bit pattern.
+--  Time codes and NULL tokens are broken into two separate tokens starting
+--  with ESC. Stage C is triggered one clock after the shift buffer in
+--  stage E drops to 3 tokens.
+--
+--  Stage D completes the task of translating tokens to bit patterns and
+--  distinguishes between 10-bit and 4-bit tokens. It is not explicitly
+--  triggered but simply follows stage C.
+--
+--  Stage E is the bit shift register. It shifts when "txclken" is high.
+--  A one-hot counter keeps track of the number of bits remaining in
+--  the register. When the register falls empty, it loads a new 10-bit or
+--  4-bit pattern as prepared by stage D. Stage E also computes parity.
+--
+--  Stage F performs data strobe encoding. When the transmitter is disabled,
+--  the outputs of stage F fall to zero in a controlled way.
+-- 
+--  To generate the transmission bit clock, the txclk is divided by an
+--  integer factor (divcnt+1) using an 8-bit down counter. The implementation
+--  of this counter has become quite complicated in order to meet timing goals.
+--  The counter consists of 4 blocks of two bits each (txclkcnt), with a
+--  carry-save concept used between blocks (txclkcy). Detection of terminal
+--  count (txclkdone) has a pipeline delay of two cycles. Therefore a separate
+--  concept is used if the initial count is less than 2 (txdivnorm). This is
+--  all glued together in the final assignment to txclken.
+--
+--  The initial count for txclk division (divcnt) comes from the system clock
+--  domain and thus needs to be synchronized for use in the txclk domain.
+--  To facilitate this, the system clock domain latches the value of divcnt
+--  once every 6 sysclk cycles and sets a flag to indicate when the latched
+--  value can safely be used by the txclk domain.
+--
+--  A tricky aspect of the design is the initial state of the txclk logic.
+--  When the transmitter is enabled (txen goes high), the txclk logic starts
+--  with the first ESC pattern already set up in stage D, and stage C ready
+--  to produce the FCT part of the first NULL.
+--
+--  The following guidelines are used to get good timing for the txclk domain:
+--   * The new value of a register depends on at most 4 inputs (single LUT),
+--     or in a few cases on 5 inputs (two LUTs and F5MUX).
+--   * Synchronous resets may be used, but only if the reset signal comes
+--     directly from a register (no logic in set/reset path);
+--   * Clock enables may be used, but only if the enable signal comes directly
+--     from a register (no logic in clock enable path).
+--
+--  Synchronization issues
+--  ----------------------
+--
+--  There is a two-slot FIFO buffer between the system and txclk domains.
+--  After the txclk domain pulls a token from the buffer, the system clock
+--  domain should ideally refill the buffer before the txclk domain again
+--  tries to pull from the same buffer slot. If the refill occurs late,
+--  the txclk domain needs to insert a NULL token which is inefficient
+--  use of bandwidth.
+--
+--  Assuming the transmission consists of a stream of data characters,
+--  10 bits per character, there are exactly 2*10 bit periods between
+--  successive reads from the same buffer slot by the txclk logic.
+--
+--  The time needed for the system clock logic to refill a buffer slot =
+--     1 txclk period   (update of rtx.txflipN)
+--   + 1 txclk period   (routing delay between domains)
+--   + 2 sysclk periods (synchronizer for txflipN)
+--   + 1 sysclk period  (refill buffer slot and update r.sysflipN)
+--   + 1 txclk period   (routing delay between domains)
+--   + 2 txclk periods  (synchronizer for sysflipN)
+--   = 5 txclk periods + 3 sysclk periods
+--
+--  If for example txclk is 4 times as fast as sysclk, this amounts to
+--   5 txclk + 3 sysclk = 5 + 3*4 txclk = 17 txclk
+--  is less than 20 bit periods even at maximum transmission rate, so
+--  no problem there.
+--
+--  This is different when the data stream includes 4-bit tokens.
+--  See the manual for further comments.
+--
+--  Implementation guidelines
+--  -------------------------
+--
+--  To minimize clock skew, IOB flip-flops should be used to drive
+--  spw_do and spw_so.
+--
+--  "txclk" must be at least as fast as the system clock;
+--  "txclk" does not need to be phase-related to the system clock;
+--  it is allowed for "txclk" to be equal to "clk".
+--
+--  The following timing constraints are needed:
+--   * PERIOD constraint on the system clock;
+--   * PERIOD constraint on "txclk";
+--   * FROM-TO constraint from "txclk" to the system clock, equal to
+--     one "txclk" period;
+--   * FROM-TO constraint from the system clock to "txclk", equal to
+--     one "txclk" period.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity spwxmit_fast is
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Transmit clock.
+        txclk:      in  std_logic;
+
+        -- Synchronous reset (active-high)
+        -- Used asynchronously by fast clock domain (must be glitch-free).
+        rst:        in  std_logic;
+
+        -- Scaling factor minus 1, used to scale the system clock into the
+        -- transmission bit rate. The system clock is divided by
+        -- (unsigned(divcnt) + 1). Changing this signal will immediately
+        -- change the transmission rate.
+        divcnt:     in  std_logic_vector(7 downto 0);
+
+        -- Input signals from spwlink.
+        xmiti:      in  spw_xmit_in_type;
+
+        -- Output signals to spwlink.
+        xmito:      out spw_xmit_out_type;
+
+        -- Data Out signal to SpaceWire bus.
+        spw_do:     out std_logic;
+
+        -- Strobe Out signal to SpaceWire bus.
+        spw_so:     out std_logic
+    );
+
+    -- Turn off FSM extraction to avoid synchronization problems.
+    attribute FSM_EXTRACT: string;
+    attribute FSM_EXTRACT of spwxmit_fast: entity is "NO";
+
+end entity spwxmit_fast;
+
+architecture spwxmit_fast_arch of spwxmit_fast is
+
+    -- Convert boolean to std_logic.
+    type bool_to_logic_type is array(boolean) of std_ulogic;
+    constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
+
+    -- Data records passed between clock domains.
+    type token_type is record
+        tick:       std_ulogic;                     -- send time code
+        fct:        std_ulogic;                     -- send FCT
+        fctpiggy:   std_ulogic;                     -- send FCT and N-char
+        flag:       std_ulogic;                     -- send EOP or EEP
+        char:       std_logic_vector(7 downto 0);   -- character or time code
+    end record;
+
+    -- Registers in txclk domain
+    type txregs_type is record
+        -- sync to system clock domain
+        txflip0:    std_ulogic;
+        txflip1:    std_ulogic;
+        -- stage B
+        b_update:   std_ulogic;
+        b_mux:      std_ulogic;
+        b_txflip:   std_ulogic;
+        b_valid:    std_ulogic;
+        b_token:    token_type;
+        -- stage C
+        c_update:   std_ulogic;
+        c_busy:     std_ulogic;
+        c_esc:      std_ulogic;
+        c_fct:      std_ulogic;
+        c_bits:     std_logic_vector(8 downto 0);
+        -- stage D
+        d_bits:     std_logic_vector(8 downto 0);
+        d_cnt4:     std_ulogic;
+        d_cnt10:    std_ulogic;
+        -- stage E
+        e_valid:    std_ulogic;
+        e_shift:    std_logic_vector(9 downto 0);
+        e_count:    std_logic_vector(9 downto 0);
+        e_parity:   std_ulogic;
+        -- stage F
+        f_spwdo:    std_ulogic;
+        f_spwso:    std_ulogic;
+        -- tx clock enable logic
+        txclken:    std_ulogic;
+        txclkpre:   std_ulogic;
+        txclkcnt:   std_logic_vector(7 downto 0);
+        txclkcy:    std_logic_vector(2 downto 0);
+        txclkdone:  std_logic_vector(1 downto 0);
+        txclkdiv:   std_logic_vector(7 downto 0);
+        txdivnorm:  std_ulogic;
+    end record;
+
+    -- Registers in system clock domain
+    type regs_type is record
+        -- sync status to txclk domain
+        txenreg:    std_ulogic;
+        txdivreg:   std_logic_vector(7 downto 0);
+        txdivnorm:  std_ulogic;
+        txdivtmp:   std_logic_vector(1 downto 0);
+        txdivsafe:  std_ulogic;
+        -- data stream to txclk domain
+        sysflip0:   std_ulogic;
+        sysflip1:   std_ulogic;
+        token0:     token_type;
+        token1:     token_type;
+        tokmux:     std_ulogic;
+        -- transmitter management
+        pend_fct:   std_ulogic;                     -- '1' if an outgoing FCT is pending
+        pend_char:  std_ulogic;                     -- '1' if an outgoing N-Char is pending
+        pend_data:  std_logic_vector(8 downto 0);   -- control flag and data bits of pending char
+        pend_tick:  std_ulogic;                     -- '1' if an outgoing time tick is pending
+        pend_time:  std_logic_vector(7 downto 0);   -- data bits of pending time tick
+        allow_fct:  std_ulogic;                     -- '1' when allowed to send FCTs
+        allow_char: std_ulogic;                     -- '1' when allowed to send data and time
+        sent_fct:   std_ulogic;                     -- '1' when at least one FCT token was sent
+    end record;
+
+    -- Initial state of system clock domain
+    constant token_reset: token_type := (
+        tick        => '0',
+        fct         => '0',
+        fctpiggy    => '0',
+        flag        => '0',
+        char        => (others => '0') );
+    constant regs_reset: regs_type := (
+        txenreg     => '0',
+        txdivreg    => (others => '0'),
+        txdivnorm   => '0',
+        txdivtmp    => "00",
+        txdivsafe   => '0',
+        sysflip0    => '0',
+        sysflip1    => '0',
+        token0      => token_reset,
+        token1      => token_reset,
+        tokmux      => '0',
+        pend_fct    => '0',
+        pend_char   => '0',
+        pend_data   => (others => '0'),
+        pend_tick   => '0',
+        pend_time   => (others => '0'),
+        allow_fct   => '0',
+        allow_char  => '0',
+        sent_fct    => '0' );
+
+    -- Signals that are re-synchronized from system clock to txclk domain.
+    type synctx_type is record
+        rstn:       std_ulogic;
+        sysflip0:   std_ulogic;
+        sysflip1:   std_ulogic;
+        txen:       std_ulogic;
+        txdivsafe:  std_ulogic;
+    end record;
+
+    -- Signals that are re-synchronized from txclk to system clock domain.
+    type syncsys_type is record
+        txflip0:    std_ulogic;
+        txflip1:    std_ulogic;
+    end record;
+
+    -- Registers
+    signal rtx:     txregs_type;
+    signal rtxin:   txregs_type;
+    signal r:       regs_type := regs_reset;
+    signal rin:     regs_type;
+
+    -- Synchronized signals after crossing clock domains.
+    signal synctx:  synctx_type;
+    signal syncsys: syncsys_type;
+
+    -- Output flip-flops
+    signal s_spwdo: std_logic;
+    signal s_spwso: std_logic;
+
+    -- Force use of IOB flip-flops
+    attribute IOB: string;
+    attribute IOB of s_spwdo: signal is "TRUE";
+    attribute IOB of s_spwso: signal is "TRUE";
+
+begin
+
+    -- Reset synchronizer for txclk domain.
+    synctx_rst: syncdff
+        port map ( clk => txclk, rst => rst, di => '1',         do => synctx.rstn );
+
+    -- Synchronize signals from system clock domain to txclk domain.
+    synctx_sysflip0: syncdff
+        port map ( clk => txclk, rst => rst, di => r.sysflip0,  do => synctx.sysflip0 );
+    synctx_sysflip1: syncdff
+        port map ( clk => txclk, rst => rst, di => r.sysflip1,  do => synctx.sysflip1 );
+    synctx_txen: syncdff
+        port map ( clk => txclk, rst => rst, di => r.txenreg,   do => synctx.txen );
+    synctx_txdivsafe: syncdff
+        port map ( clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe );
+
+    -- Synchronize signals from txclk domain to system clock domain.
+    syncsys_txflip0: syncdff
+        port map ( clk => clk,   rst => rst, di => rtx.txflip0, do => syncsys.txflip0 );
+    syncsys_txflip1: syncdff
+        port map ( clk => clk,   rst => rst, di => rtx.txflip1, do => syncsys.txflip1 );
+
+    -- Drive SpaceWire output signals
+    spw_do      <= s_spwdo;
+    spw_so      <= s_spwso;
+
+    -- Combinatorial process
+    process (r, rtx, rst, divcnt, xmiti, synctx, syncsys) is
+        variable v:         regs_type;
+        variable vtx:       txregs_type;
+        variable v_needtoken: std_ulogic;
+        variable v_havetoken: std_ulogic;
+        variable v_token:     token_type;
+    begin
+        v           := r;
+        vtx         := rtx;
+        v_needtoken := '0';
+        v_havetoken := '0';
+        v_token     := token_reset;
+
+        -- ---- FAST CLOCK DOMAIN ----
+
+        -- Stage B: Multiplex tokens from system clock domain.
+        -- Update stage B three bit periods after updating stage C
+        -- (i.e. in time for the next update of stage C).
+        -- Do not update stage B if stage C is indicating that it needs to
+        -- send a second token to complete its task.
+        vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_busy);
+        if rtx.b_mux = '0' then
+            vtx.b_txflip := rtx.txflip0;
+        else
+            vtx.b_txflip := rtx.txflip1;
+        end if;
+        if rtx.b_update = '1' then
+            if rtx.b_mux = '0' then
+                -- get token from slot 0
+                vtx.b_valid := synctx.sysflip0 xor rtx.b_txflip;
+                vtx.b_token := r.token0;
+                -- update mux flag if we got a valid token
+                vtx.b_mux   := synctx.sysflip0 xor rtx.b_txflip;
+                vtx.txflip0 := synctx.sysflip0;
+                vtx.txflip1 := rtx.txflip1;
+            else
+                -- get token from slot 1
+                vtx.b_valid := synctx.sysflip1 xor rtx.b_txflip;
+                vtx.b_token := r.token1;
+                -- update mux flag if we got a valid token
+                vtx.b_mux   := not (synctx.sysflip1 xor rtx.b_txflip);
+                vtx.txflip0 := rtx.txflip0;
+                vtx.txflip1 := synctx.sysflip1;
+            end if;
+        end if;
+
+        -- Stage C: Prepare to transmit EOP, EEP or a data character.
+        vtx.c_update := rtx.txclken and rtx.e_count(3);
+        if rtx.c_update = '1' then
+
+            -- NULL is broken into two tokens: ESC + FCT.
+            -- Time-codes are broken into two tokens: ESC + char.
+
+            -- Enable c_esc on the first pass of a NULL or a time-code.
+            vtx.c_esc   := (rtx.b_token.tick or (not rtx.b_valid)) and
+                           (not rtx.c_esc);
+
+            -- Enable c_fct on the first pass of an FCT and on
+            -- the second pass of a NULL (also the first pass, but c_esc
+            -- is stronger than c_fct).
+            vtx.c_fct   := (rtx.b_token.fct and (not rtx.c_busy)) or
+                           (not rtx.b_valid);
+
+            -- Enable c_busy on the first pass of a NULL or a time-code
+            -- or a piggy-backed FCT. This will tell stage B that we are
+            -- not done yet.
+            vtx.c_busy  := (rtx.b_token.tick or (not rtx.b_valid) or
+                            rtx.b_token.fctpiggy) and (not rtx.c_busy);
+
+            if rtx.b_token.flag = '1' then
+                if rtx.b_token.char(0) = '0' then
+                    -- prepare to send EOP
+                    vtx.c_bits  := "000000101"; -- EOP = P101
+                else
+                    -- prepare to send EEP
+                    vtx.c_bits  := "000000011"; -- EEP = P110
+                end if;
+            else
+                -- prepare to send data char
+                vtx.c_bits  := rtx.b_token.char & '0';
+            end if;
+        end if;
+
+        -- Stage D: Prepare to transmit FCT, ESC, or the stuff from stage C.
+        if rtx.c_esc = '1' then
+            -- prepare to send ESC
+            vtx.d_bits  := "000000111";     -- ESC = P111
+            vtx.d_cnt4  := '1';             -- 3 bits + implicit parity bit
+            vtx.d_cnt10 := '0';
+        elsif rtx.c_fct = '1' then
+            -- prepare to send FCT
+            vtx.d_bits  := "000000001";     -- FCT = P100
+            vtx.d_cnt4  := '1';             -- 3 bits + implicit parity bit
+            vtx.d_cnt10 := '0';
+        else
+            -- send the stuff from stage C.
+            vtx.d_bits  := rtx.c_bits;
+            vtx.d_cnt4  := rtx.c_bits(0);
+            vtx.d_cnt10 := not rtx.c_bits(0);
+        end if;
+
+        -- Stage E: Shift register.
+        if rtx.txclken = '1' then
+            if rtx.e_count(0) = '1' then
+                -- reload shift register; output parity bit
+                vtx.e_valid  := '1';
+                vtx.e_shift(vtx.e_shift'high downto 1) := rtx.d_bits;
+                vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0));
+                vtx.e_count  := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000";
+                vtx.e_parity := rtx.d_bits(0);
+            else
+                -- shift bits to output; update parity bit
+                vtx.e_shift  := '0' & rtx.e_shift(rtx.e_shift'high downto 1);
+                vtx.e_count  := '0' & rtx.e_count(rtx.e_count'high downto 1);
+                vtx.e_parity := rtx.e_parity xor rtx.e_shift(1);
+            end if;
+        end if;
+
+        -- Stage F: Data/strobe encoding.
+        if rtx.txclken = '1' then
+            if rtx.e_valid = '1' then
+                -- output next data/strobe bits
+                vtx.f_spwdo := rtx.e_shift(0);
+                vtx.f_spwso := not (rtx.e_shift(0) xor rtx.f_spwdo xor rtx.f_spwso);
+            else
+                -- gentle reset of spacewire signals
+                vtx.f_spwdo := rtx.f_spwdo and rtx.f_spwso;
+                vtx.f_spwso := '0';
+            end if;
+        end if;
+
+        -- Generate tx clock enable
+        -- An 8-bit counter decrements on every clock. A txclken pulse is
+        -- produced 2 cycles after the counter reaches value 2. Counter reload
+        -- values of 0 and 1 are handled as special cases.
+        -- count down in blocks of two bits
+        vtx.txclkcnt(1 downto 0) := std_logic_vector(unsigned(rtx.txclkcnt(1 downto 0)) - 1);
+        vtx.txclkcnt(3 downto 2) := std_logic_vector(unsigned(rtx.txclkcnt(3 downto 2)) - unsigned(rtx.txclkcy(0 downto 0)));
+        vtx.txclkcnt(5 downto 4) := std_logic_vector(unsigned(rtx.txclkcnt(5 downto 4)) - unsigned(rtx.txclkcy(1 downto 1)));
+        vtx.txclkcnt(7 downto 6) := std_logic_vector(unsigned(rtx.txclkcnt(7 downto 6)) - unsigned(rtx.txclkcy(2 downto 2)));
+        -- propagate carry in blocks of two bits
+        vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00");
+        vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00");
+        vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00");
+        -- detect value 2 in counter
+        vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010");
+        vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000");
+        -- trigger txclken
+        vtx.txclken  := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre;
+        vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0)));
+        -- reload counter
+        if rtx.txclken = '1' then
+            vtx.txclkcnt  := rtx.txclkdiv;
+            vtx.txclkcy   := "000";
+            vtx.txclkdone := "00";
+        end if;
+
+        -- Synchronize txclkdiv
+        if synctx.txdivsafe = '1' then
+            vtx.txclkdiv  := r.txdivreg;
+            vtx.txdivnorm := r.txdivnorm;
+        end if;
+
+        -- Transmitter disabled.
+        if synctx.txen = '0' then
+            vtx.txflip0   := '0';
+            vtx.txflip1   := '0';
+            vtx.b_update  := '0';
+            vtx.b_mux     := '0';
+            vtx.b_valid   := '0';
+            vtx.c_update  := '0';
+            vtx.c_busy    := '1';
+            vtx.c_esc     := '1';           -- need to send 2nd part of NULL
+            vtx.c_fct     := '1';
+            vtx.d_bits    := "000000111";   -- ESC = P111
+            vtx.d_cnt4    := '1';           -- 3 bits + implicit parity bit
+            vtx.d_cnt10   := '0';
+            vtx.e_valid   := '0';
+            vtx.e_parity  := '0';
+            vtx.e_count   := (0 => '1', others => '0');
+        end if;
+
+        -- Reset.
+        if synctx.rstn = '0' then
+            vtx.f_spwdo   := '0';
+            vtx.f_spwso   := '0';
+            vtx.txclken   := '0';
+            vtx.txclkpre  := '1';
+            vtx.txclkcnt  := (others => '0');
+            vtx.txclkdiv  := (others => '0');
+            vtx.txdivnorm := '0';
+        end if;
+
+        -- ---- SYSTEM CLOCK DOMAIN ----
+
+        -- Hold divcnt and txen for use by txclk domain.
+        v.txdivtmp  := std_logic_vector(unsigned(r.txdivtmp) - 1);
+        if r.txdivtmp = "00" then
+            if r.txdivsafe = '0' then
+                -- Latch the current value of divcnt and txen.
+                v.txdivsafe := '1';
+                v.txdivtmp  := "01";
+                v.txdivreg  := divcnt;
+                if unsigned(divcnt(divcnt'high downto 1)) = 0 then
+                    v.txdivnorm := '0';
+                else
+                    v.txdivnorm := '1';
+                end if;
+                v.txenreg   := xmiti.txen;
+            else
+                -- Drop the txdivsafe flag but keep latched values.
+                v.txdivsafe := '0';
+            end if;
+        end if;
+
+        -- Pass falling edge of txen signal as soon as possible.
+        if xmiti.txen = '0' then
+            v.txenreg   := '0';
+        end if;
+
+        -- Store requests for FCT transmission.
+        if xmiti.fct_in = '1' and r.allow_fct = '1' then
+            v.pend_fct  := '1';
+        end if;
+
+        if xmiti.txen = '0' then
+
+            -- Transmitter disabled; reset state.
+            v.sysflip0    := '0';
+            v.sysflip1    := '0';
+            v.tokmux      := '0';
+            v.pend_fct    := '0';
+            v.pend_char   := '0';
+            v.pend_tick   := '0';
+            v.allow_fct   := '0';
+            v.allow_char  := '0';
+            v.sent_fct    := '0';
+
+        else
+
+            -- Determine if a new token is needed.
+            if r.tokmux = '0' then
+                if r.sysflip0 = syncsys.txflip0 then
+                    v_needtoken := '1';
+                end if;
+            else
+                if r.sysflip1 = syncsys.txflip1 then
+                    v_needtoken := '1';
+                end if;
+            end if;
+
+            -- Prepare new token.
+            if r.allow_char = '1' and r.pend_tick = '1' then
+                -- prepare to send time code
+                v_token.tick  := '1';
+                v_token.fct   := '0';
+                v_token.fctpiggy := '0';
+                v_token.flag  := '0';
+                v_token.char  := r.pend_time;
+                v_havetoken   := '1';
+                if v_needtoken = '1' then
+                    v.pend_tick := '0';
+                end if;
+            else
+                if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then
+                    -- prepare to send FCT
+                    v_token.fct   := '1';
+                    v_havetoken   := '1';
+                    if v_needtoken = '1' then
+                        v.pend_fct  := '0';
+                        v.sent_fct  := '1';
+                    end if;
+                end if;
+                if r.allow_char = '1' and r.pend_char = '1' then
+                    -- prepare to send N-Char
+                    -- Note: it is possible to send an FCT and an N-Char
+                    -- together by enabling the fctpiggy flag.
+                    v_token.fctpiggy := v_token.fct;
+                    v_token.flag  := r.pend_data(8);
+                    v_token.char  := r.pend_data(7 downto 0);
+                    v_havetoken   := '1';
+                    if v_needtoken = '1' then
+                        v.pend_char := '0';
+                    end if;
+                end if;
+            end if;
+
+            -- Put new token in slot.
+            if v_havetoken = '1' then
+                if r.tokmux = '0' then
+                    if r.sysflip0 = syncsys.txflip0 then
+                        v.sysflip0  := not r.sysflip0;
+                        v.token0    := v_token;
+                        v.tokmux    := '1';
+                    end if;
+                else
+                    if r.sysflip1 = syncsys.txflip1 then
+                        v.sysflip1  := not r.sysflip1;
+                        v.token1    := v_token;
+                        v.tokmux    := '0';
+                    end if;
+                end if;
+            end if;
+
+            -- Determine whether we are allowed to send FCTs and characters
+            v.allow_fct  := not xmiti.stnull;
+            v.allow_char := (not xmiti.stnull) and (not xmiti.stfct) and r.sent_fct;
+
+            -- Store request for data transmission.
+            if xmiti.txwrite = '1' and r.allow_char = '1' and r.pend_char = '0' then
+                v.pend_char  := '1';
+                v.pend_data  := xmiti.txflag & xmiti.txdata;
+            end if;
+
+            -- Store requests for time tick transmission.
+            if xmiti.tick_in = '1' then
+                v.pend_tick := '1';
+                v.pend_time := xmiti.ctrl_in & xmiti.time_in;
+            end if;
+
+        end if;
+
+        -- Synchronous reset of system clock domain.
+        if rst = '1' then
+            v := regs_reset;
+        end if;
+
+        -- Drive outputs.
+        -- Note: the outputs are combinatorially dependent on certain inputs.
+
+        -- Set fctack high if (FCT requested) and (FCTs allowed) AND
+        -- (no FCT pending)
+        xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and
+                        (not r.pend_fct);
+
+        -- Set txrdy high if (character requested) AND (characters allowed) AND
+        -- (no character pending)
+        xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and
+                       (not r.pend_char);
+
+        -- Update registers.
+        rin     <= v;
+        rtxin   <= vtx;
+    end process;
+
+    -- Synchronous process in txclk domain
+    process (txclk) is
+    begin
+        if rising_edge(txclk) then
+            -- drive spacewire output signals
+            s_spwdo <= rtx.f_spwdo;
+            s_spwso <= rtx.f_spwso;
+            -- update registers
+            rtx <= rtxin;
+        end if;
+    end process;
+
+    -- Synchronous process in system clock domain
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            -- update registers
+            r <= rin;
+        end if;
+    end process;
+
+end architecture spwxmit_fast_arch;
diff --git a/lib/opencores/spw_light/streamtest.vhd b/lib/opencores/spw_light/streamtest.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/streamtest.vhd
@@ -0,0 +1,446 @@
+--
+--  Test application for spwstream.
+--
+--  This entity implements one spwstream instance with SpaceWire signals
+--  routed to external ports. The SpaceWire port is assumed to be looped back
+--  to itself externally, either directly (tx pins wired to rx pins) or
+--  through a remote SpaceWire device which is programmed to echo anything
+--  it receives.
+--
+--  This entity submits a series of test patterns to the transmit side of
+--  spwstream. At the same time it monitors the receive side of spwstream
+--  and verifies that received data matches the transmitted data pattern.
+--
+--  Link mode and tx bit rate may be programmed through digital inputs
+--  (presumably connected to switches or buttons). Link state and progress of
+--  the test are reported through digital outputs (presumably connected to
+--  LEDs).
+--
+--  Note: there is no check on the integrity of the first packet received
+--  after the link goes up.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.spwpkg.all;
+
+entity streamtest is
+
+    generic (
+        -- System clock frequency in Hz.
+        sysfreq:    real;
+
+        -- txclk frequency in Hz (if tximpl = impl_fast).
+        txclkfreq:  real;
+
+        -- 2-log of division factor from system clock freq to timecode freq.
+        tickdiv:    integer range 12 to 24 := 20;
+
+        -- Receiver front-end implementation.
+        rximpl:     spw_implementation_type := impl_generic;
+
+        -- Maximum number of bits received per system clock (impl_fast only).
+        rxchunk:    integer range 1 to 4 := 1;
+
+        -- Transmitter implementation.
+        tximpl:     spw_implementation_type := impl_generic;
+
+        -- Size of receive FIFO.
+        rxfifosize_bits: integer range 6 to 14 := 11;
+
+        -- Size of transmit FIFO.
+        txfifosize_bits: integer range 2 to 14 := 11 );
+
+    port (
+        -- System clock.
+        clk:        in  std_logic;
+
+        -- Receiver sample clock (only for impl_fast).
+        rxclk:      in  std_logic;
+
+        -- Transmit clock (only for impl_fast).
+        txclk:      in  std_logic;
+
+        -- Synchronous reset (active-high).
+        rst:        in  std_logic;
+
+        -- Enables spontaneous link start.
+        linkstart:  in  std_logic;
+
+        -- Enables automatic link start on receipt of a NULL token.
+        autostart:  in  std_logic;
+
+        -- Do not start link and/or disconnect current link.
+        linkdisable: in std_logic;
+
+        -- Enable sending test patterns to spwstream.
+        senddata:   in  std_logic;
+
+        -- Enable sending time codes to spwstream.
+        sendtick:   in  std_logic;
+
+        -- Scaling factor minus 1 for TX bitrate.
+        txdivcnt:   in  std_logic_vector(7 downto 0);
+
+        -- Link in state Started.
+        linkstarted: out std_logic;
+
+        -- Link in state Connecting.
+        linkconnecting: out std_logic;
+
+        -- Link in state Run.
+        linkrun:    out std_logic;
+
+        -- Link error (one cycle pulse, not directly suitable for LED)
+        linkerror:  out std_logic;
+
+        -- High when taking a byte from the receive FIFO.
+        gotdata:    out std_logic;
+
+        -- Incorrect or unexpected data received (sticky).
+        dataerror:  out std_logic;
+
+        -- Incorrect or unexpected time code received (sticky).
+        tickerror:  out std_logic;
+
+        -- SpaceWire signals.
+        spw_di:     in  std_logic;
+        spw_si:     in  std_logic;
+        spw_do:     out std_logic;
+        spw_so:     out std_logic );
+
+end entity streamtest;
+
+architecture streamtest_arch of streamtest is
+
+    -- Update 16-bit maximum length LFSR by 8 steps
+    function lfsr16(x: in std_logic_vector) return std_logic_vector is
+        variable y: std_logic_vector(15 downto 0);
+    begin
+        -- poly = x^16 + x^14 + x^13 + x^11 + 1
+        -- tap positions = x(0), x(2), x(3), x(5)
+        y(7 downto 0)  := x(15 downto 8);
+        y(15 downto 8) := x(7 downto 0) xor x(9 downto 2) xor x(10 downto 3) xor x(12 downto 5);
+        return y;
+    end function;
+
+    -- Sending side state.
+    type tx_state_type is ( txst_idle, txst_prepare, txst_data );
+
+    -- Receiving side state.
+    type rx_state_type is ( rxst_idle, rxst_data );
+
+    -- Registers.
+    type regs_type is record
+        tx_state:       tx_state_type;
+        tx_timecnt:     std_logic_vector((tickdiv-1) downto 0);
+        tx_quietcnt:    std_logic_vector(15 downto 0);
+        tx_pktlen:      std_logic_vector(15 downto 0);
+        tx_lfsr:        std_logic_vector(15 downto 0);
+        tx_enabledata:  std_ulogic;
+        rx_state:       rx_state_type;
+        rx_quietcnt:    std_logic_vector(15 downto 0);
+        rx_enabledata:  std_ulogic;
+        rx_gottick:     std_ulogic;
+        rx_expecttick:  std_ulogic;
+        rx_expectglitch: unsigned(5 downto 0);
+        rx_badpacket:   std_ulogic;
+        rx_pktlen:      std_logic_vector(15 downto 0);
+        rx_prev:        std_logic_vector(15 downto 0);
+        rx_lfsr:        std_logic_vector(15 downto 0);
+        running:        std_ulogic;
+        tick_in:        std_ulogic;
+        time_in:        std_logic_vector(5 downto 0);
+        txwrite:        std_ulogic;
+        txflag:         std_ulogic;
+        txdata:         std_logic_vector(7 downto 0);
+        rxread:         std_ulogic;
+        gotdata:        std_ulogic;
+        dataerror:      std_ulogic;
+        tickerror:      std_ulogic;
+    end record;
+
+    -- Reset state.
+    constant regs_reset: regs_type := (
+        tx_state        => txst_idle,
+        tx_timecnt      => (others => '0'),
+        tx_quietcnt     => (others => '0'),
+        tx_pktlen       => (others => '0'),
+        tx_lfsr         => (1 => '1', others => '0'),
+        tx_enabledata   => '0',
+        rx_state        => rxst_idle,
+        rx_quietcnt     => (others => '0'),
+        rx_enabledata   => '0',
+        rx_gottick      => '0',
+        rx_expecttick   => '0',
+        rx_expectglitch => "000001",
+        rx_badpacket    => '0',
+        rx_pktlen       => (others => '0'),
+        rx_prev         => (others => '0'),
+        rx_lfsr         => (others => '0'),
+        running         => '0',
+        tick_in         => '0',
+        time_in         => (others => '0'),
+        txwrite         => '0',
+        txflag          => '0',
+        txdata          => (others => '0'),
+        rxread          => '0',
+        gotdata         => '0',
+        dataerror       => '0',
+        tickerror       => '0' );
+
+    signal r:   regs_type := regs_reset;
+    signal rin: regs_type;
+
+    -- Interface signals.
+    signal s_txrdy:     std_logic;
+    signal s_tickout:   std_logic;
+    signal s_timeout:   std_logic_vector(5 downto 0);
+    signal s_rxvalid:   std_logic;
+    signal s_rxflag:    std_logic;
+    signal s_rxdata:    std_logic_vector(7 downto 0);
+    signal s_running:   std_logic;
+    signal s_errdisc:   std_logic;
+    signal s_errpar:    std_logic;
+    signal s_erresc:    std_logic;
+    signal s_errcred:   std_logic;
+
+begin
+
+    -- spwstream instance
+    spwstream_inst: spwstream
+        generic map (
+            sysfreq         => sysfreq,
+            txclkfreq       => txclkfreq,
+            rximpl          => rximpl,
+            rxchunk         => rxchunk,
+            tximpl          => tximpl,
+            rxfifosize_bits => rxfifosize_bits,
+            txfifosize_bits => txfifosize_bits )
+        port map (
+            clk         => clk,
+            rxclk       => rxclk,
+            txclk       => txclk,
+            rst         => rst,
+            autostart   => autostart,
+            linkstart   => linkstart,
+            linkdis     => linkdisable,
+            txdivcnt    => txdivcnt,
+            tick_in     => r.tick_in,
+            ctrl_in     => (others => '0'),
+            time_in     => r.time_in,
+            txwrite     => r.txwrite,
+            txflag      => r.txflag,
+            txdata      => r.txdata,
+            txrdy       => s_txrdy,
+            txhalff     => open,
+            tick_out    => s_tickout,
+            ctrl_out    => open,
+            time_out    => s_timeout,
+            rxvalid     => s_rxvalid,
+            rxhalff     => open,
+            rxflag      => s_rxflag,
+            rxdata      => s_rxdata,
+            rxread      => r.rxread,
+            started     => linkstarted,
+            connecting  => linkconnecting,
+            running     => s_running,
+            errdisc     => s_errdisc,
+            errpar      => s_errpar,
+            erresc      => s_erresc,
+            errcred     => s_errcred,
+            spw_di      => spw_di,
+            spw_si      => spw_si,
+            spw_do      => spw_do,
+            spw_so      => spw_so );
+
+    -- Drive status indications.
+    linkrun     <= s_running;
+    linkerror   <= s_errdisc or s_errpar or s_erresc or s_errcred;
+    gotdata     <= r.gotdata;
+    dataerror   <= r.dataerror;
+    tickerror   <= r.tickerror;
+
+    process (r, rst, senddata, sendtick, s_txrdy, s_tickout, s_timeout, s_rxvalid, s_rxflag, s_rxdata, s_running) is
+        variable v: regs_type;
+    begin
+        v           := r;
+
+        -- Initiate timecode transmissions.
+        v.tx_timecnt := std_logic_vector(unsigned(r.tx_timecnt) + 1);
+        if unsigned(v.tx_timecnt) = 0 then
+            v.tick_in   := sendtick;
+        else
+            v.tick_in   := '0';
+        end if;
+        if r.tick_in = '1' then
+            v.time_in   := std_logic_vector(unsigned(r.time_in) + 1);
+            v.rx_expecttick := '1';
+            v.rx_gottick    := '0';
+        end if;
+
+        -- Turn data generator on/off at regular intervals.
+        v.tx_quietcnt := std_logic_vector(unsigned(r.tx_quietcnt) + 1);
+        if unsigned(r.tx_quietcnt) = 61000 then
+            v.tx_quietcnt := (others => '0');
+        end if;
+        v.tx_enabledata := senddata and (not r.tx_quietcnt(15));
+
+        -- Generate data packets.
+        case r.tx_state is
+            when txst_idle =>
+                -- generate packet length
+                v.tx_state  := txst_prepare;
+                v.tx_pktlen := r.tx_lfsr;
+                v.txwrite   := '0';
+                v.tx_lfsr   := lfsr16(r.tx_lfsr);
+            when txst_prepare =>
+                -- generate first byte of packet
+                v.tx_state  := txst_data;
+                v.txwrite   := r.tx_enabledata;
+                v.txflag    := '0';
+                v.txdata    := r.tx_lfsr(15 downto 8);
+                v.tx_lfsr   := lfsr16(r.tx_lfsr);
+            when txst_data =>
+                -- generate data bytes and EOP
+                v.txwrite   := r.tx_enabledata;
+                if r.txwrite = '1' and s_txrdy = '1' then
+                    -- just sent one byte
+                    v.tx_pktlen := std_logic_vector(unsigned(r.tx_pktlen) - 1);
+                    if unsigned(r.tx_pktlen) = 0 then
+                        -- done with packet
+                        v.tx_state  := txst_idle;
+                        v.txwrite   := '0';
+                    elsif unsigned(r.tx_pktlen) = 1 then
+                        -- generate EOP
+                        v.txwrite   := r.tx_enabledata;
+                        v.txflag    := '1';
+                        v.txdata    := (others => '0');
+                        v.tx_lfsr   := lfsr16(r.tx_lfsr);
+                    else
+                        -- generate next data byte
+                        v.txwrite   := r.tx_enabledata;
+                        v.txflag    := '0';
+                        v.txdata    := r.tx_lfsr(15 downto 8);
+                        v.tx_lfsr   := lfsr16(r.tx_lfsr);
+                    end if;
+                end if;
+        end case;
+
+        -- Blink light when receiving data.
+        v.gotdata   := s_rxvalid and r.rxread;
+
+        -- Detect missing timecodes.
+        if r.tick_in = '1' and r.rx_expecttick = '1' then
+            -- This is bad; a new timecode is being generated while
+            -- we have not even received the previous one yet.
+            v.tickerror := '1';
+        end if;
+
+        -- Receive and check incoming timecodes.
+        if s_tickout = '1' then
+            if unsigned(s_timeout) + 1 /= unsigned(r.time_in) then
+                -- Received time code does not match last transmitted code.
+                v.tickerror := '1';
+            end if;
+            if r.rx_gottick = '1' then
+                -- Already received the last transmitted time code.
+                v.tickerror := '1';
+            end if;
+            v.rx_expecttick := '0';
+            v.rx_gottick    := '1';
+        end if;
+
+        -- Turn data receiving on/off at regular intervals
+        v.rx_quietcnt := std_logic_vector(unsigned(r.rx_quietcnt) + 1);
+        if unsigned(r.rx_quietcnt) = 55000 then
+            v.rx_quietcnt := (others => '0');
+        end if;
+        v.rx_enabledata := not r.rx_quietcnt(15);
+
+        case r.rx_state is
+            when rxst_idle =>
+                -- get expected packet length
+                v.rx_state  := rxst_data;
+                v.rx_pktlen := r.rx_lfsr;
+                v.rx_lfsr   := lfsr16(r.rx_lfsr);
+                v.rx_prev   := (others => '0');
+            when rxst_data =>
+                v.rxread    := r.rx_enabledata;
+                if r.rxread = '1' and s_rxvalid = '1' then
+                    -- got next byte
+                    v.rx_pktlen := std_logic_vector(unsigned(r.rx_pktlen) - 1);
+                    v.rx_prev   := s_rxdata & r.rx_prev(15 downto 8);
+                    if s_rxflag = '1' then
+                        -- got EOP or EEP
+                        v.rxread    := '0';
+                        v.rx_state  := rxst_idle;
+                        if s_rxdata = "00000000" then
+                            -- got EOP
+                            if unsigned(r.rx_pktlen) /= 0 then
+                                -- unexpected EOP
+                                v.rx_badpacket := '1';
+                            end if;
+                            -- count errors against expected glitches
+                            if v.rx_badpacket = '1' then
+                                -- got glitch
+                                if r.rx_expectglitch = 0 then
+                                    v.dataerror := '1';
+                                else
+                                    v.rx_expectglitch := r.rx_expectglitch - 1;
+                                end if;
+                            end if;
+                            -- resynchronize LFSR
+                            v.rx_lfsr   := lfsr16(lfsr16(r.rx_prev));
+                        else
+                            -- got EEP
+                            v.rx_badpacket := '1';
+                        end if;
+                        v.rx_badpacket := '0';
+                    else
+                        -- got next byte
+                        v.rx_lfsr   := lfsr16(r.rx_lfsr);
+                        if unsigned(r.rx_pktlen) = 0 then
+                            -- missing EOP
+                            v.rx_badpacket := '1';
+                        end if;
+                        if s_rxdata /= r.rx_lfsr(15 downto 8) then
+                            -- bad data
+                            v.rx_badpacket := '1';
+                        end if;
+                    end if;
+                end if;
+        end case;
+
+        -- If the link goes away, we should expect inconsistency on the receiving side.
+        v.running := s_running;
+        if r.running = '1' and s_running = '0' then
+            if r.rx_expectglitch /= "111111" then
+                v.rx_expectglitch := r.rx_expectglitch + 1;
+            end if;
+        end if;
+
+        -- If there is no link, we should not expect to receive time codes.
+        if s_running = '0' then
+            v.rx_expecttick := '0';
+        end if;
+
+        -- Synchronous reset.
+        if rst = '1' then
+            v := regs_reset;
+        end if;
+
+        -- Update registers.
+        rin <= v;
+    end process;
+
+    -- Update registers.
+    process (clk) is
+    begin
+        if rising_edge(clk) then
+            r <= rin;
+        end if;
+    end process;
+
+end architecture streamtest_arch;
diff --git a/lib/opencores/spw_light/syncdff.vhd b/lib/opencores/spw_light/syncdff.vhd
new file mode 100644
--- /dev/null
+++ b/lib/opencores/spw_light/syncdff.vhd
@@ -0,0 +1,70 @@
+--
+--  Double flip-flop synchronizer.
+--
+--  This entity is used to safely capture asynchronous signals.
+--
+--  An implementation may assign additional constraints to this entity
+--  in order to reduce the probability of meta-stability issues.
+--  For example, an extra tight timing constraint could be placed on
+--  the data path from syncdff_ff1 to syncdff_ff2 to ensure that
+--  meta-stability of ff1 is resolved before ff2 captures the signal.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity syncdff is
+
+    port (
+        clk:        in  std_logic;          -- clock (destination domain)
+        rst:        in  std_logic;          -- asynchronous reset, active-high
+        di:         in  std_logic;          -- input data
+        do:         out std_logic           -- output data
+    );
+
+    -- Turn off register replication in XST.
+    attribute REGISTER_DUPLICATION: string;
+    attribute REGISTER_DUPLICATION of syncdff: entity is "NO";
+
+end entity syncdff;
+
+architecture syncdff_arch of syncdff is
+
+    -- flip-flops
+    signal syncdff_ff1: std_ulogic := '0';
+    signal syncdff_ff2: std_ulogic := '0';
+
+    -- Turn of shift-register extraction in XST.
+    attribute SHIFT_EXTRACT: string;
+    attribute SHIFT_EXTRACT of syncdff_ff1: signal is "NO";
+    attribute SHIFT_EXTRACT of syncdff_ff2: signal is "NO";
+
+    -- Tell XST to place both flip-flops in the same slice.
+    attribute RLOC: string;
+    attribute RLOC of syncdff_ff1: signal is "X0Y0";
+    attribute RLOC of syncdff_ff2: signal is "X0Y0";
+
+    -- Tell XST to keep the flip-flop net names to be used in timing constraints.
+    attribute KEEP: string;
+    attribute KEEP of syncdff_ff1: signal is "SOFT";
+    attribute KEEP of syncdff_ff2: signal is "SOFT";
+
+begin
+
+    -- second flip-flop drives the output signal
+    do <= syncdff_ff2;
+
+    process (clk, rst) is
+    begin
+        if rst = '1' then
+            -- asynchronous reset
+            syncdff_ff1 <= '0';
+            syncdff_ff2 <= '0';
+        elsif rising_edge(clk) then
+            -- data synchronization
+            syncdff_ff1 <= di;
+            syncdff_ff2 <= syncdff_ff1;
+        end if;
+    end process;
+
+end architecture syncdff_arch;
diff --git a/scripts/linklibs.sh b/scripts/linklibs.sh
--- a/scripts/linklibs.sh
+++ b/scripts/linklibs.sh
@@ -39,10 +39,15 @@ if [ -d "$GRLIBPATH" ]; then
 
 				echo "Patch $1/lib/libs.txt..."
 				if(grep -q $LPP_PATCHPATH/lib/lpp $1/lib/libs.txt); then
-					echo "No need to Patch $1/lib/libs.txt..."
+					echo "No need to add lpp in $1/lib/libs.txt..."
 				else
 					echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
 				fi
+				if(grep -q $LPP_PATCHPATH/lib/opencores $1/lib/libs.txt); then
+					echo "No need to add opencores in $1/lib/libs.txt..."
+				else
+					echo $LPP_PATCHPATH/lib/opencores >>$1/lib/libs.txt
+				fi
 				echo
 				echo
 				echo
diff --git a/tests/Validation_LFR/Makefile b/tests/Validation_LFR/Makefile
new file mode 100644
--- /dev/null
+++ b/tests/Validation_LFR/Makefile
@@ -0,0 +1,84 @@
+VHDLIB=../..
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=testbench
+BOARD=LFR-EQM
+include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=
+QSF=
+EFFORT=high
+XSTOPT=
+SYNPOPT=
+VHDLSYNFILES=
+VHDLSIMFILES= tb.vhd $(VHDLIB)/boards/designs/LFR-EQM-RTAX/LFR-EQM.vhd
+SIMTOP=testbench
+CLEAN=soft-clean
+
+TECHLIBS = axcelerator
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann micron usbhc  opencores fmf ftlib gsi
+
+DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
+	grlfpc \
+	./dsp/lpp_fft_rtax \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lfr_management \
+	./lpp_sim/CY7C1061DV33 \
+	./lpp_cna \
+	./lpp_uart \
+	./lpp_usb \
+	./dsp/lpp_fft \
+	./lpp_leon3_soc \
+	./lpp_debug_lfr
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd \
+	lpp_lfr_ms_FFT.vhd \
+	lpp_lfr_apbreg.vhd \
+	CoreFFT.vhd \
+	lpp_lfr_ms.vhd \
+	lpp_lfr_sim_pkg.vhd \
+	mtie_maps.vhd \
+	ftsrctrlc.vhd \
+	ftsdctrl.vhd \
+	ftsrctrl8.vhd \
+	ftmctrl.vhd \
+	ftsdctrl64.vhd \
+	ftahbram.vhd \
+	ftahbram2.vhd \
+	sramft.vhd \
+	nandfctrlx.vhd
+
+include $(GRLIB)/bin/Makefile
+include $(GRLIB)/software/leon3/Makefile
+
+##################  project specific targets ##########################
+distclean:myclean
+vsim:cp_for_vsim
+
+myclean:
+	rm -f input.txt output_fx.txt *.log
+	rm -rf ./2016*
+
+generate :
+	python ./generate.py
+
+cp_for_vsim: generate
+	cp ./input.txt simulation/
+
+archivate:
+	xonsh ./archivate.xsh
+
+test: | generate ghdl ghdl-run archivate
+
+
diff --git a/tests/Validation_LFR/tb.vhd b/tests/Validation_LFR/tb.vhd
new file mode 100644
--- /dev/null
+++ b/tests/Validation_LFR/tb.vhd
@@ -0,0 +1,254 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE IEEE.std_logic_signed.ALL;
+USE IEEE.MATH_real.ALL;
+
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+
+LIBRARY std;
+USE std.textio.ALL;
+
+LIBRARY lpp;
+USE lpp.iir_filter.ALL;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.FILTERcfg.ALL;
+USE lpp.lpp_lfr_filter_coeff.ALL;
+USE lpp.general_purpose.ALL;
+USE lpp.data_type_pkg.ALL;
+USE lpp.lpp_lfr_pkg.ALL;
+USE lpp.general_purpose.ALL;
+USE lpp.lpp_sim_pkg.ALL;
+USE lpp.lpp_waveform_pkg.ALL;
+
+ENTITY testbench IS
+GENERIC(
+    tech          : INTEGER := 0; --axcel,0
+    Mem_use       : INTEGER := use_CEL --use_RAM,use_CEL
+);
+END;
+
+ARCHITECTURE behav OF testbench IS
+
+
+COMPONENT LFR_EQM IS
+  GENERIC (
+    Mem_use                : INTEGER := use_RAM;
+    USE_BOOTLOADER         : INTEGER := 0;
+    USE_ADCDRIVER          : INTEGER := 1;
+    tech                   : INTEGER := inferred;
+    tech_leon              : INTEGER := inferred;
+    DEBUG_FORCE_DATA_DMA   : INTEGER := 0;
+    USE_DEBUG_VECTOR       : INTEGER := 0
+    );
+
+  PORT (
+    clk50MHz    : IN STD_ULOGIC;
+    clk49_152MHz : IN STD_ULOGIC;
+    reset        : IN STD_ULOGIC;
+
+    TAG          : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
+
+    address        : OUT   STD_LOGIC_VECTOR(18 DOWNTO 0);
+    data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+    nSRAM_MBE      : INOUT   STD_LOGIC;   -- new
+    nSRAM_E1       : OUT   STD_LOGIC;   -- new
+    nSRAM_E2       : OUT   STD_LOGIC;   -- new
+--    nSRAM_SCRUB    : OUT   STD_LOGIC;   -- new
+    nSRAM_W        : OUT   STD_LOGIC;   -- new
+    nSRAM_G        : OUT   STD_LOGIC;   -- new
+    nSRAM_BUSY     : IN   STD_LOGIC;   -- new
+    -- SPW --------------------------------------------------------------------
+    spw1_en        : OUT   STD_LOGIC;   -- new
+    spw1_din       : IN    STD_LOGIC;
+    spw1_sin       : IN    STD_LOGIC;
+    spw1_dout      : OUT   STD_LOGIC;
+    spw1_sout      : OUT   STD_LOGIC;
+    spw2_en        : OUT   STD_LOGIC;   -- new
+    spw2_din       : IN    STD_LOGIC;
+    spw2_sin       : IN    STD_LOGIC;
+    spw2_dout      : OUT   STD_LOGIC;
+    spw2_sout      : OUT   STD_LOGIC;
+    -- ADC --------------------------------------------------------------------
+    bias_fail_sw   : OUT   STD_LOGIC;
+    ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
+    ADC_smpclk     : OUT   STD_LOGIC;
+    ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
+    -- DAC --------------------------------------------------------------------
+    DAC_SDO    : OUT STD_LOGIC;
+    DAC_SCK    : OUT STD_LOGIC;
+    DAC_SYNC   : OUT STD_LOGIC;
+    DAC_CAL_EN : OUT STD_LOGIC;
+    -- HK ---------------------------------------------------------------------
+    HK_smpclk      : OUT   STD_LOGIC;
+    ADC_OEB_bar_HK : OUT   STD_LOGIC;
+    HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0)
+    );
+
+END LFR_EQM;
+
+
+  SIGNAL TSTAMP    : INTEGER   := 0;
+  SIGNAL clk       : STD_LOGIC := '0';
+  SIGNAL clk_24576Hz   : STD_LOGIC := '0';
+  SIGNAL clk_24576Hz_r : STD_LOGIC := '0';
+  SIGNAL rstn      : STD_LOGIC;
+
+  SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
+  SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
+  SIGNAL signal_rec : sample_vector(0 to ChanelCount-1,15 downto 0);
+
+  SIGNAL end_of_simu : STD_LOGIC := '0';
+
+  CONSTANT half_samplig_period : time := 20345052 ps; --INTEGER( REAL(1000**4) / REAL(2.0*24576.0)) * 1 ps;
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- CLOCK and RESET
+  -----------------------------------------------------------------------------
+  PROCESS
+  BEGIN  -- PROCESS
+    WAIT UNTIL clk = '1';
+    rstn <= '0';
+    WAIT UNTIL clk = '1';
+    WAIT UNTIL clk = '1';
+    WAIT UNTIL clk = '1';
+    rstn <= '1';
+    WAIT UNTIL end_of_simu = '1';
+    WAIT FOR 10 ps;
+    assert false report "end of test" severity note;
+    --  Wait forever; this will finish the simulation.
+    wait;
+  END PROCESS;
+  -----------------------------------------------------------------------------
+
+
+  clk_24576Hz_gen:PROCESS
+  BEGIN
+    IF end_of_simu /= '1' THEN
+      clk_24576Hz <= NOT clk_24576Hz;
+      WAIT FOR half_samplig_period;
+    ELSE
+      WAIT FOR 10 ps;
+      assert false report "end of test" severity note;
+      WAIT;
+    END IF;
+  END PROCESS;
+
+  clk_25M_gen:PROCESS
+  BEGIN
+    IF end_of_simu /= '1' THEN
+      clk <= NOT clk;
+      TSTAMP <= TSTAMP+20;
+      WAIT FOR 20 ns;
+    ELSE
+      WAIT FOR 10 ps;
+      assert false report "end of test" severity note;
+      WAIT;
+    END IF;
+  END PROCESS;
+
+
+  -----------------------------------------------------------------------------
+  -- LPP_LFR_FILTER f1
+  -----------------------------------------------------------------------------
+
+    IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
+    GENERIC MAP (
+      tech         => tech,
+      Mem_use      => Mem_use,          -- use_RAM
+      Sample_SZ    => 18,
+      Coef_SZ      => f0_to_f1_COEFFICIENT_SIZE,
+      Coef_Nb      => f0_to_f1_CEL_NUMBER*5,
+      Coef_sel_SZ  => 5,
+      Cels_count   => f0_to_f1_CEL_NUMBER,
+      ChanelsCount => ChanelCount,
+      FILENAME     => ""
+      )
+    PORT MAP (
+      rstn           => rstn,
+      clk            => clk,
+      virg_pos       => f0_to_f1_POINT_POSITION,
+      coefs          => coefs_iir_cel_f0_to_f1,
+
+      sample_in_val  => sample_val,
+      sample_in      => sample,
+      sample_out_val => sample_fx_val,
+      sample_out     => sample_fx);
+
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- SAMPLE GENERATION
+  -----------------------------------------------------------------------------
+
+
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      sample_val <= '0';
+      clk_24576Hz_r  <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+      clk_24576Hz_r <= clk_24576Hz;
+      IF clk_24576Hz = '1' AND clk_24576Hz_r = '0' THEN
+        sample_val <= '1';
+      ELSE
+        sample_val <= '0';
+      END IF;
+    END IF;
+  END PROCESS;
+  -----------------------------------------------------------------------------
+
+  ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
+    SampleLoop : FOR j IN 0 TO 15 GENERATE
+      sample_fx_wdata(i)(j) <= sample_fx(i,j);
+      signal_rec(i,j) <= sample_fx_wdata(i)(j);
+      sample(i,j) <= signal_gen(i,j);
+    END GENERATE;
+      sample(i,16) <= signal_gen(i,16);
+      sample(i,17) <= signal_gen(i,17);
+  END GENERATE;
+
+
+
+  -----------------------------------------------------------------------------
+  --  READ INPUT SIGNALS
+  -----------------------------------------------------------------------------
+
+  gen: sig_reader
+  GENERIC MAP(
+        FNAME       => "input.txt",
+        WIDTH       => ChanelCount,
+        RESOLUTION  => 18,
+        GAIN        => 1.0
+    )
+    PORT MAP(
+        clk             => sample_val,
+        end_of_simu     => end_of_simu,
+        out_signal      => signal_gen
+    );
+
+
+  -----------------------------------------------------------------------------
+  --  RECORD OUTPUT SIGNALS
+  -----------------------------------------------------------------------------
+
+  rec : sig_recorder
+  GENERIC MAP(
+      FNAME       => "output_fx.txt",
+      WIDTH       => ChanelCount,
+      RESOLUTION  => 16
+  )
+  PORT MAP(
+      clk             => sample_fx_val,
+      end_of_simu     => end_of_simu,
+      timestamp       => TSTAMP,
+      input_signal    => signal_rec
+  );
+
+END;