diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -32,7 +32,7 @@ USE gaisler.memctrl.ALL; USE gaisler.leon3.ALL; USE gaisler.uart.ALL; USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE +USE gaisler.spacewire.ALL; LIBRARY esa; USE esa.memoryctrl.ALL; LIBRARY lpp; @@ -61,15 +61,15 @@ ENTITY MINI_LFR_top IS --UARTs TXD1 : IN STD_LOGIC; RXD1 : OUT STD_LOGIC; - nCTS1 : OUT STD_LOGIC; - nRTS1 : IN STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; TXD2 : IN STD_LOGIC; RXD2 : OUT STD_LOGIC; - nCTS2 : OUT STD_LOGIC; - nDTR2 : IN STD_LOGIC; - nRTS2 : IN STD_LOGIC; - nDCD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; --EXT CONNECTOR IO0 : INOUT STD_LOGIC; @@ -86,19 +86,19 @@ ENTITY MINI_LFR_top IS IO11 : INOUT STD_LOGIC; --SPACE WIRE - SPW_EN : OUT STD_LOGIC; -- 0 => off - SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK SPW_NOM_SIN : IN STD_LOGIC; SPW_NOM_DOUT : OUT STD_LOGIC; SPW_NOM_SOUT : OUT STD_LOGIC; - SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK SPW_RED_SIN : IN STD_LOGIC; SPW_RED_DOUT : OUT STD_LOGIC; SPW_RED_SOUT : OUT STD_LOGIC; -- MINI LFR ADC INPUTS ADC_nCS : OUT STD_LOGIC; ADC_CLK : OUT STD_LOGIC; - ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- SRAM SRAM_nWE : OUT STD_LOGIC; @@ -113,36 +113,58 @@ END MINI_LFR_top; ARCHITECTURE beh OF MINI_LFR_top IS - SIGNAL clk_50_s : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; + SIGNAL clk_50_s : STD_LOGIC := '0'; + SIGNAL clk_25 : STD_LOGIC := '0'; ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); -- - SIGNAL errorn : STD_LOGIC; + SIGNAL errorn : STD_LOGIC; -- UART AHB --------------------------------------------------------------- - SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data - SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data + SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data + SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data -- UART APB --------------------------------------------------------------- - SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data - SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data - -- - SIGNAL I00_s : STD_LOGIC; + SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data + SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data + -- + SIGNAL I00_s : STD_LOGIC; -- - CONSTANT NB_APB_SLAVE : INTEGER := 1; + CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 1; - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); - -- - SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0); - + CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account + + SIGNAL apbi_ext : apb_slv_in_type; + SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); + SIGNAL ahbi_s_ext : ahb_slv_in_type; + SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); + SIGNAL ahbi_m_ext : AHB_Mst_In_Type; + SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; + SIGNAL swno : grspw_out_type; +-- SIGNAL clkmn : STD_ULOGIC; +-- SIGNAL txclk : STD_ULOGIC; + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + -- ADC -------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL ADC_smpclk_sig : STD_LOGIC; + SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0); + + SIGNAL bias_fail_sw_sig : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL sample_val_s : STD_LOGIC; + SIGNAL sample_val_s2 : STD_LOGIC; BEGIN -- beh ----------------------------------------------------------------------------- @@ -155,7 +177,7 @@ BEGIN -- beh clk_50_s <= NOT clk_50_s; END IF; END PROCESS; - + PROCESS(clk_50_s) BEGIN IF clk_50_s'EVENT AND clk_50_s = '1' THEN @@ -164,15 +186,16 @@ BEGIN -- beh END PROCESS; ----------------------------------------------------------------------------- - + PROCESS (clk_25, reset) BEGIN -- PROCESS IF reset = '0' THEN -- asynchronous reset (active low) LED0 <= '0'; LED1 <= '0'; LED2 <= '0'; - IO1 <= '0'; - IO2 <= '1'; + IO0 <= '0'; + --IO1 <= '0'; + IO2 <= '1'; IO3 <= '0'; IO4 <= '0'; IO5 <= '0'; @@ -182,75 +205,49 @@ BEGIN -- beh IO9 <= '0'; IO10 <= '0'; IO11 <= '0'; - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge LED0 <= '0'; LED1 <= '1'; LED2 <= BP0; - IO1 <= '1'; - IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; - IO3 <= ADC_SDO(0) OR ADC_SDO(1); - IO4 <= ADC_SDO(2) OR ADC_SDO(1); - IO5 <= ADC_SDO(3) OR ADC_SDO(4); - IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); - IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; - IO8 <= IO_s(8); - IO9 <= IO_s(9); - IO10 <= IO_s(10); - IO11 <= IO_s(11); + IO0 <= '1'; + --IO1 <= '1'; + IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; + IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); + IO4 <= sample_val; + IO5 <= ahbi_m_ext.HREADY; + IO6 <= ahbi_m_ext.HRESP(0); + IO7 <= ahbi_m_ext.HRESP(1); + IO8 <= ahbi_m_ext.HGRANT(2); + IO9 <= ahbo_m_ext(2).HLOCK; + IO10 <= ahbo_m_ext(2).HBUSREQ; + IO11 <= sample_val_s2; END IF; END PROCESS; - - PROCESS (clk_49, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - I00_s <= '0'; - ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge - I00_s <= NOT I00_s; - END IF; - END PROCESS; - IO0 <= I00_s; + + --PROCESS (clk_49, reset) + --BEGIN -- PROCESS + -- IF reset = '0' THEN -- asynchronous reset (active low) + -- I00_s <= '0'; + -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge + -- I00_s <= NOT I00_s; + -- END IF; + --END PROCESS; + --IO0 <= I00_s; --UARTs - nCTS1 <= '1'; - nCTS2 <= '1'; - nDCD2 <= '1'; + nCTS1 <= '1'; + nCTS2 <= '1'; + nDCD2 <= '1'; + + --EXT CONNECTOR --SPACE WIRE - SPW_EN <= '0'; -- 0 => off - - SPW_NOM_DOUT <= '0'; - SPW_NOM_SOUT <= '0'; - SPW_RED_DOUT <= '0'; - SPW_RED_SOUT <= '0'; - - ADC_nCS <= '0'; - ADC_CLK <= '0'; - - ----------------------------------------------------------------------------- - lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst - GENERIC MAP ( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pmask => 16#fff#) - PORT MAP ( - HCLK => clk_25, - HRESETn => reset , - ahbmi => ahbi_m_ext , - ahbmo => ahbo_m_ext(1), - apbi => apbi_ext, - apbo => apbo_ext(5), - out_ren => IO_s(11), - out_send => IO_s(10), - out_done => IO_s(9), - out_dmaout_okay => IO_s(8) - ); - - ----------------------------------------------------------------------------- + ADC_nCS <= '0'; + ADC_CLK <= '0'; - leon3_soc_1: leon3_soc + + leon3_soc_1 : leon3_soc GENERIC MAP ( fabtech => apa3e, memtech => apa3e, @@ -270,30 +267,213 @@ BEGIN -- beh ENABLE_GPT => 1, NB_AHB_MASTER => NB_AHB_MASTER, NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE) + NB_APB_SLAVE => NB_APB_SLAVE) PORT MAP ( - clk => clk_25, - reset => reset, - errorn => errorn, - ahbrxd => TXD1, - ahbtxd => RXD1, - urxd1 => TXD2, - utxd1 => RXD2, - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - + clk => clk_25, + reset => reset, + errorn => errorn, + ahbrxd => TXD1, + ahbtxd => RXD1, + urxd1 => TXD2, + utxd1 => RXD2, + address => SRAM_A, + data => SRAM_DQ, + nSRAM_BE0 => SRAM_nBE(0), + nSRAM_BE1 => SRAM_nBE(1), + nSRAM_BE2 => SRAM_nBE(2), + nSRAM_BE3 => SRAM_nBE(3), + nSRAM_WE => SRAM_nWE, + nSRAM_CE => SRAM_CE, + nSRAM_OE => SRAM_nOE, + apbi_ext => apbi_ext, apbo_ext => apbo_ext, ahbi_s_ext => ahbi_s_ext, ahbo_s_ext => ahbo_s_ext, ahbi_m_ext => ahbi_m_ext, ahbo_m_ext => ahbo_m_ext); + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1 : apb_lfr_time_management + GENERIC MAP ( + pindex => 7, + paddr => 7, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clk_25, + clk49_152MHz => clk_49, + resetn => reset, + grspw_tick => swno.tickout, + apbi => apbi_ext, + apbo => apbo_ext(7), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + SPW_EN <= '1'; + + spw_clk <= clk_50_s; + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DIN, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SIN, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_DOUT, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_NOM_SOUT, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_SIN, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ + PORT MAP (SPW_RED_DIN, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_DOUT, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => inferred) + PORT MAP (SPW_RED_SOUT, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => apa3e, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(reset, clk_25, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR ------------------------------------------------------------------------ +------------------------------------------------------------------------------- + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"00000009") + PORT MAP ( + clk => clk_25, + rstn => reset, + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi_ext, + apbo => apbo_ext(6), + ahbi => ahbi_m_ext, + ahbo => ahbo_m_ext(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw_sig); + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk_49, + cnv_rstn => reset, + cnv => ADC_smpclk_sig, + clk => clk_25, + rstn => reset, + ADC_data => ADC_data_sig, + ADC_nOE => ADC_OEB_bar_CH_sig, + sample => OPEN, + sample_val => sample_val);--OPEN );-- + + ADC_data_sig <= (OTHERS => '1'); + + lpp_debug_lfr_1 : lpp_debug_lfr + GENERIC MAP ( + pindex => 8, + paddr => 8, + pmask => 16#fff#) + PORT MAP ( + HCLK => clk_25, + HRESETn => reset, + apbi => apbi_ext, + apbo => apbo_ext(8), + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3)); + + PROCESS (clk_25, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + sample_val_s2 <= '0'; + sample_val_s <= '0'; + --sample_val <= '0'; + ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge + sample_val_s <= IO1; + sample_val_s2 <= sample_val_s; + --sample_val <= (NOT sample_val_s2) AND sample_val_s; + END IF; + END PROCESS; + + END beh; diff --git a/designs/MINI-LFR_waveformPicker/Makefile b/designs/MINI-LFR_waveformPicker/Makefile --- a/designs/MINI-LFR_waveformPicker/Makefile +++ b/designs/MINI-LFR_waveformPicker/Makefile @@ -19,7 +19,7 @@ CLEAN=soft-clean TECHLIBS = proasic3e LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc + tmtc openchip hynix ihp gleichmann micron usbhc DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ @@ -35,6 +35,7 @@ DIRSKIP = b1553 pcif leon2 leon2ft crypt ./lpp_uart \ ./lpp_usb \ ./lpp_Header \ + ./lpp_sim/CY7C1061DV33 \ FILESKIP =lpp_lfr_ms.vhd \ i2cmst.vhd \ diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -23,3 +23,4 @@ ./lpp_Header ./lpp_leon3_soc ./lpp_debug_lfr +./lpp_sim/CY7C1061DV33 diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd @@ -30,14 +30,12 @@ PACKAGE lpp_lfr_time_management IS -- APB_LFR_TIME_MANAGEMENT COMPONENT apb_lfr_time_management IS - GENERIC( pindex : INTEGER := 0; --! APB slave index paddr : INTEGER := 0; --! ADDR field of the APB BAR pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR pirq : INTEGER := 0 ); - PORT ( clk25MHz : IN STD_LOGIC; --! Clock clk49_152MHz : IN STD_LOGIC; --! secondary clock @@ -48,7 +46,6 @@ PACKAGE lpp_lfr_time_management IS coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time ); - END COMPONENT; COMPONENT lfr_time_management diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd --- a/lib/lpp/lpp_amba/apb_devices_list.vhd +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -39,5 +39,6 @@ PACKAGE apb_devices_list IS CONSTANT LPP_LFR : amba_device_type := 16#19#; CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; + CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; END; diff --git a/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd b/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd --- a/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd +++ b/lib/lpp/lpp_debug_lfr/lpp_debug_lfr_pkg.vhd @@ -1,51 +1,71 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com ----------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; - -PACKAGE lpp_debug_lfr_pkg IS - - COMPONENT lpp_debug_dma_singleOrBurst - GENERIC ( - tech : INTEGER; - hindex : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - ahbmi : IN AHB_Mst_In_Type; - ahbmo : OUT AHB_Mst_Out_Type; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - out_ren : OUT STD_LOGIC; - out_send : OUT STD_LOGIC; - out_done : OUT STD_LOGIC; - out_dmaout_okay : OUT STD_LOGIC - ); - END COMPONENT; - -END; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +LIBRARY lpp; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_ad_conv.ALL; + +PACKAGE lpp_debug_lfr_pkg IS + + COMPONENT lpp_debug_dma_singleOrBurst + GENERIC ( + tech : INTEGER; + hindex : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + ahbmi : IN AHB_Mst_In_Type; + ahbmo : OUT AHB_Mst_Out_Type; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + out_ren : OUT STD_LOGIC; + out_send : OUT STD_LOGIC; + out_done : OUT STD_LOGIC; + out_dmaout_okay : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT lpp_debug_lfr + GENERIC ( + tech : INTEGER; + hindex : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + sample_B : OUT Samples14v(2 DOWNTO 0); + sample_E : OUT Samples14v(4 DOWNTO 0)); + END COMPONENT; + + +END; \ No newline at end of file diff --git a/lib/lpp/lpp_debug_lfr/vhdlsyn.txt b/lib/lpp/lpp_debug_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_debug_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_debug_lfr/vhdlsyn.txt @@ -1,2 +1,3 @@ lpp_debug_lfr_pkg.vhd lpp_debug_dma_singleOrBurst.vhd +lpp_debug_lfr.vhd diff --git a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd @@ -167,9 +167,14 @@ BEGIN -- beh END PROCESS; DMAIn.Data <= data; + + ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE + '1'; - ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE - '1'; + -- \/ JC - 20/01/2014 \/ + --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE + -- '1'; + -- /\ JC - 20/01/2014 /\ -- \/ JC - 11/12/2013 \/ --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE diff --git a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd --- a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd @@ -140,8 +140,14 @@ BEGIN -- NOT single_send_ok; --ren <= burst_ren AND single_ren; - ren <= '0' WHEN DMAOut.OKAY = '1' ELSE - '1'; + -- \/ JC - 20/01/2014 \/ + ren <= burst_ren WHEN valid_burst = '1' ELSE + single_ren; + + + --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE + -- '1'; + -- /\ JC - 20/01/2014 /\ ----------------------------------------------------------------------------- -- SEND 1 word by DMA diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -413,7 +413,7 @@ BEGIN END GENERATE all_ahbs; -- AHB_Master ------------------------------------------------------------- ahbi_m_ext <= ahbmi; - all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE + all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); END GENERATE max_16_ahbm; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -69,7 +69,37 @@ ENTITY lpp_lfr IS debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); debug_f2_data_valid : OUT STD_LOGIC; debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC + debug_f3_data_valid : OUT STD_LOGIC; + + -- debug FIFO_IN + debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_in_valid : OUT STD_LOGIC; + + --debug FIFO OUT + debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_out_valid : OUT STD_LOGIC; + debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_out_valid : OUT STD_LOGIC; + debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_out_valid : OUT STD_LOGIC; + debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_out_valid : OUT STD_LOGIC; + + --debug DMA IN + debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_dma_in_valid : OUT STD_LOGIC; + debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_dma_in_valid : OUT STD_LOGIC; + debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_dma_in_valid : OUT STD_LOGIC; + debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_dma_in_valid : OUT STD_LOGIC ); END lpp_lfr; @@ -405,19 +435,19 @@ BEGIN --f0 addr_data_f0 => addr_data_f0, data_f0_in_valid => sample_f0_val, - data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug + data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug --f1 addr_data_f1 => addr_data_f1, data_f1_in_valid => sample_f1_val, - data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, + data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, --f2 addr_data_f2 => addr_data_f2, data_f2_in_valid => sample_f2_val, - data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, + data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, --f3 addr_data_f3 => addr_data_f3, data_f3_in_valid => sample_f3_val, - data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, + data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, -- OUTPUT -- DMA interface --f0 data_f0_addr_out => data_f0_addr_out_s, @@ -444,7 +474,7 @@ BEGIN data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, data_f3_data_out_ren => data_f3_data_out_ren, - --debug + -- debug SNAPSHOT_OUT debug_f0_data => debug_f0_data, debug_f0_data_valid => debug_f0_data_valid , debug_f1_data => debug_f1_data , @@ -452,12 +482,35 @@ BEGIN debug_f2_data => debug_f2_data , debug_f2_data_valid => debug_f2_data_valid , debug_f3_data => debug_f3_data , - debug_f3_data_valid => debug_f3_data_valid + debug_f3_data_valid => debug_f3_data_valid, + + -- debug FIFO_IN + debug_f0_data_fifo_in => debug_f0_data_fifo_in , + debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, + debug_f1_data_fifo_in => debug_f1_data_fifo_in , + debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, + debug_f2_data_fifo_in => debug_f2_data_fifo_in , + debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, + debug_f3_data_fifo_in => debug_f3_data_fifo_in , + debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid ); ----------------------------------------------------------------------------- + -- DEBUG -- WFP OUT + debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; + debug_f0_data_fifo_out <= data_f0_data_out; + debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; + debug_f1_data_fifo_out <= data_f1_data_out; + debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; + debug_f2_data_fifo_out <= data_f2_data_out; + debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; + debug_f3_data_fifo_out <= data_f3_data_out; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- -- TEMP ----------------------------------------------------------------------------- @@ -557,71 +610,31 @@ BEGIN data_f1_data_out WHEN dma_sel(1) = '1' ELSE data_f2_data_out WHEN dma_sel(2) = '1' ELSE data_f3_data_out; - - --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE - -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE - -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE - -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE - -- '0'; - - --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE - -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE - -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE - -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE - -- '0'; - - -- TODO - --dma_send <= dma_sel_valid OR dma_valid_burst; - - --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1'; - --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1'; - --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1'; - --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1'; data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; + dma_data_2 <= dma_data; - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- ongoing_reg <= '0'; - -- dma_sel_reg <= (OTHERS => '0'); - -- dma_send_reg <= '0'; - -- dma_valid_burst_reg <= '0'; - -- dma_address_reg <= (OTHERS => '0'); - -- dma_data_reg <= (OTHERS => '0'); - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN - -- ongoing_reg <= '1'; - -- dma_valid_burst_reg <= dma_valid_burst; - -- dma_sel_reg <= dma_sel; - -- ELSE - -- IF dma_done = '1' THEN - -- ongoing_reg <= '0'; - -- END IF; - -- END IF; - -- dma_send_reg <= dma_send; - -- dma_address_reg <= dma_address; - -- dma_data_reg <= dma_data; - -- END IF; - --END PROCESS; - dma_data_2 <= dma_data; - --PROCESS (clk, rstn) - --BEGIN -- PROCESS - -- IF rstn = '0' THEN -- asynchronous reset (active low) - -- dma_data_2 <= (OTHERS => '0'); - -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge - -- dma_data_2 <= dma_data; - - -- END IF; - --END PROCESS; + ----------------------------------------------------------------------------- + -- DEBUG -- DMA IN + debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; + debug_f0_data_dma_in <= dma_data; + debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; + debug_f1_data_dma_in <= dma_data; + debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; + debug_f2_data_dma_in <= dma_data; + debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; + debug_f3_data_dma_in <= dma_data; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst @@ -635,12 +648,12 @@ BEGIN AHB_Master_In => ahbi, AHB_Master_Out => ahbo, - send => dma_send, --_reg, - valid_burst => dma_valid_burst, --_reg, + send => dma_send, + valid_burst => dma_valid_burst, done => dma_done, ren => dma_ren, - address => dma_address, --_reg, - data => dma_data_2); --_reg); + address => dma_address, + data => dma_data_2); ----------------------------------------------------------------------------- -- Matrix Spectral - TODO diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -142,7 +142,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS CONSTANT REVISION : INTEGER := 1; CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp), + 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), 1 => apb_iobar(paddr, pmask)); TYPE lpp_SpectralMatrix_regs IS RECORD diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -32,7 +32,7 @@ PACKAGE lpp_lfr_pkg IS ready_matrix_f0_1 : OUT STD_LOGIC; ready_matrix_f1 : OUT STD_LOGIC; ready_matrix_f2 : OUT STD_LOGIC; - error_anticipating_empty_fifo : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; error_bad_component_error : OUT STD_LOGIC; debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); status_ready_matrix_f0_0 : IN STD_LOGIC; @@ -101,15 +101,46 @@ PACKAGE lpp_lfr_pkg IS fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); data_shaping_BW : OUT STD_LOGIC; - --debug - debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f0_data_valid : OUT STD_LOGIC; - debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f1_data_valid : OUT STD_LOGIC; - debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f2_data_valid : OUT STD_LOGIC; - debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC ); + --debug + debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f0_data_valid : OUT STD_LOGIC; + debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f1_data_valid : OUT STD_LOGIC; + debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f2_data_valid : OUT STD_LOGIC; + debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + debug_f3_data_valid : OUT STD_LOGIC; + + -- debug FIFO_IN + debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_in_valid : OUT STD_LOGIC; + + --debug FIFO OUT + debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_out_valid : OUT STD_LOGIC; + debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_out_valid : OUT STD_LOGIC; + debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_out_valid : OUT STD_LOGIC; + debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_out_valid : OUT STD_LOGIC; + + --debug DMA IN + debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_dma_in_valid : OUT STD_LOGIC; + debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_dma_in_valid : OUT STD_LOGIC; + debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_dma_in_valid : OUT STD_LOGIC; + debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_dma_in_valid : OUT STD_LOGIC + ); END COMPONENT; COMPONENT lpp_lfr_apbreg @@ -180,16 +211,16 @@ PACKAGE lpp_lfr_pkg IS addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); --------------------------------------------------------------------------- - debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; - + COMPONENT lpp_top_ms GENERIC ( Mem_use : INTEGER; diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -129,7 +129,7 @@ ENTITY lpp_waveform IS data_f3_data_out_valid_burst : OUT STD_LOGIC; data_f3_data_out_ren : IN STD_LOGIC; - --debug + --debug SNAPSHOT OUT debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); debug_f0_data_valid : OUT STD_LOGIC; debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); @@ -137,7 +137,18 @@ ENTITY lpp_waveform IS debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); debug_f2_data_valid : OUT STD_LOGIC; debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC + debug_f3_data_valid : OUT STD_LOGIC; + + --debug FIFO IN + debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_in_valid : OUT STD_LOGIC + ); END lpp_waveform; @@ -285,7 +296,7 @@ BEGIN -- beh data_out_valid => data_f3_out_valid); ----------------------------------------------------------------------------- - -- DEBUG + -- DEBUG -- SNAPSHOT OUT debug_f0_data_valid <= data_f0_out_valid; debug_f0_data <= data_f0_out; debug_f1_data_valid <= data_f1_out_valid; @@ -332,9 +343,9 @@ BEGIN -- beh ----------------------------------------------------------------------------- -- TODO : debug ----------------------------------------------------------------------------- - all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE - all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE - time_out_2(J,I) <= time_out(J)(I); + all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + time_out_2(J, I) <= time_out(J)(I); END GENERATE all_sample_of_time_out; END GENERATE all_bit_of_time_out; @@ -350,7 +361,7 @@ BEGIN -- beh -- END GENERATE all_sample_of_time_out; --END GENERATE all_bit_of_time_out; -- DEBUG -- - + lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter GENERIC MAP (tech => tech, nb_data_by_buffer_size => nb_data_by_buffer_size) @@ -369,6 +380,18 @@ BEGIN -- beh full_almost => full_almost, full => full); + ----------------------------------------------------------------------------- + -- DEBUG -- SNAPSHOT IN + debug_f0_data_fifo_in_valid <= NOT data_wen(0); + debug_f0_data_fifo_in <= wdata; + debug_f1_data_fifo_in_valid <= NOT data_wen(1); + debug_f1_data_fifo_in <= wdata; + debug_f2_data_fifo_in_valid <= NOT data_wen(2); + debug_f2_data_fifo_in <= wdata; + debug_f3_data_fifo_in_valid <= NOT data_wen(3); + debug_f3_data_fifo_in <= wdata; + ----------------------------------------------------------------------------- + lpp_waveform_fifo_1 : lpp_waveform_fifo GENERIC MAP (tech => tech) PORT MAP ( diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -30,7 +30,7 @@ USE lpp.general_purpose.ALL; ENTITY lpp_waveform_fifo_arbiter IS GENERIC( tech : INTEGER := 0; - nb_data_by_buffer_size : INTEGER + nb_data_by_buffer_size : INTEGER := 11 ); PORT( clk : IN STD_LOGIC; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd @@ -54,8 +54,8 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); - SIGNAL reg_sel : INTEGER; - SIGNAL reg_sel_s : INTEGER; + SIGNAL reg_sel : INTEGER := 0; + SIGNAL reg_sel_s : INTEGER := 0; BEGIN diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -176,7 +176,18 @@ PACKAGE lpp_waveform_pkg IS debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); debug_f2_data_valid : OUT STD_LOGIC; debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC); + debug_f3_data_valid : OUT STD_LOGIC; + + --debug FIFO IN + debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_f3_data_fifo_in_valid : OUT STD_LOGIC + ); END COMPONENT; COMPONENT lpp_waveform_dma_genvalid