diff --git a/designs/MINI-LFR_WFP_MS/run.do b/designs/MINI-LFR_WFP_MS/run.do new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_WFP_MS/run.do @@ -0,0 +1,10 @@ +vcom -quiet -93 -work work MINI_LFR_top.vhd +vcom -quiet -93 -work work testbench.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run 250 us diff --git a/designs/MINI-LFR_WFP_MS/testbench.vhd b/designs/MINI-LFR_WFP_MS/testbench.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_WFP_MS/testbench.vhd @@ -0,0 +1,258 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +use IEEE.std_logic_textio.all; +LIBRARY STD; +use std.textio.all; + +LIBRARY grlib; +USE grlib.stdlib.ALL; +LIBRARY gaisler; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.lpp_sim_pkg.ALL; +USE lpp.lpp_lfr_apbreg_pkg.ALL; +USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + COMPONENT MINI_LFR_top + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + SPW_EN : OUT STD_LOGIC; + SPW_NOM_DIN : IN STD_LOGIC; + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + SIGNAL clk_50 : STD_LOGIC := '0'; + SIGNAL clk_49 : STD_LOGIC := '0'; + SIGNAL reset : STD_LOGIC; + SIGNAL BP0 : STD_LOGIC; + SIGNAL BP1 : STD_LOGIC; + SIGNAL LED0 : STD_LOGIC; + SIGNAL LED1 : STD_LOGIC; + SIGNAL LED2 : STD_LOGIC; + SIGNAL TXD1 : STD_LOGIC; + SIGNAL RXD1 : STD_LOGIC; + SIGNAL nCTS1 : STD_LOGIC; + SIGNAL nRTS1 : STD_LOGIC; + SIGNAL TXD2 : STD_LOGIC; + SIGNAL RXD2 : STD_LOGIC; + SIGNAL nCTS2 : STD_LOGIC; + SIGNAL nDTR2 : STD_LOGIC; + SIGNAL nRTS2 : STD_LOGIC; + SIGNAL nDCD2 : STD_LOGIC; + SIGNAL IO0 : STD_LOGIC; + SIGNAL IO1 : STD_LOGIC; + SIGNAL IO2 : STD_LOGIC; + SIGNAL IO3 : STD_LOGIC; + SIGNAL IO4 : STD_LOGIC; + SIGNAL IO5 : STD_LOGIC; + SIGNAL IO6 : STD_LOGIC; + SIGNAL IO7 : STD_LOGIC; + SIGNAL IO8 : STD_LOGIC; + SIGNAL IO9 : STD_LOGIC; + SIGNAL IO10 : STD_LOGIC; + SIGNAL IO11 : STD_LOGIC; + SIGNAL SPW_EN : STD_LOGIC; + SIGNAL SPW_NOM_DIN : STD_LOGIC; + SIGNAL SPW_NOM_SIN : STD_LOGIC; + SIGNAL SPW_NOM_DOUT : STD_LOGIC; + SIGNAL SPW_NOM_SOUT : STD_LOGIC; + SIGNAL SPW_RED_DIN : STD_LOGIC; + SIGNAL SPW_RED_SIN : STD_LOGIC; + SIGNAL SPW_RED_DOUT : STD_LOGIC; + SIGNAL SPW_RED_SOUT : STD_LOGIC; + SIGNAL ADC_nCS : STD_LOGIC; + SIGNAL ADC_CLK : STD_LOGIC; + SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL SRAM_nWE : STD_LOGIC; + SIGNAL SRAM_CE : STD_LOGIC; + SIGNAL SRAM_nOE : STD_LOGIC; + SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + + CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; + CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; + CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; + + + SIGNAL message_simu : STRING(1 TO 15) := "---------------"; + +BEGIN + + ----------------------------------------------------------------------------- + -- TB + ----------------------------------------------------------------------------- + PROCESS + CONSTANT txp : TIME := 320 ns; + BEGIN -- PROCESS + TXD1 <= '1'; + reset <= '0'; + WAIT FOR 500 ns; + reset <= '1'; + WAIT FOR 10000 ns; + message_simu <= "0 - UART init "; + UART_INIT(TXD1,txp); + + message_simu <= "1 - UART test "; + UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); + UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); + UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); + + -- UNSET the LFR reset + message_simu <= "2 - LFR UNRESET"; + UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); + UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); + -- + message_simu <= "3 - LFR CONFIG "; + UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); + + WAIT; + END PROCESS; + + ----------------------------------------------------------------------------- + -- CLOCK + ----------------------------------------------------------------------------- + clk_50 <= NOT clk_50 AFTER 5 ns; + clk_49 <= NOT clk_49 AFTER 10172 ps; + + ----------------------------------------------------------------------------- + -- DON'T CARE + ----------------------------------------------------------------------------- + BP0 <= '0'; + BP1 <= '0'; + nRTS1 <= '0' ; + + TXD2 <= '1'; + nRTS2 <= '1'; + nDTR2 <= '1'; + + SPW_NOM_DIN <= '1'; + SPW_NOM_SIN <= '1'; + SPW_RED_DIN <= '1'; + SPW_RED_SIN <= '1'; + + ADC_SDO <= x"AA"; + + SRAM_DQ <= (OTHERS => 'Z'); + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + MINI_LFR_top_1: MINI_LFR_top + PORT MAP ( + clk_50 => clk_50, + clk_49 => clk_49, + reset => reset, + + BP0 => BP0, + BP1 => BP1, + + LED0 => LED0, + LED1 => LED1, + LED2 => LED2, + + TXD1 => TXD1, + RXD1 => RXD1, + nCTS1 => nCTS1, + nRTS1 => nRTS1, + + TXD2 => TXD2, + RXD2 => RXD2, + nCTS2 => nCTS2, + nDTR2 => nDTR2, + nRTS2 => nRTS2, + nDCD2 => nDCD2, + + IO0 => IO0, + IO1 => IO1, + IO2 => IO2, + IO3 => IO3, + IO4 => IO4, + IO5 => IO5, + IO6 => IO6, + IO7 => IO7, + IO8 => IO8, + IO9 => IO9, + IO10 => IO10, + IO11 => IO11, + + SPW_EN => SPW_EN, + SPW_NOM_DIN => SPW_NOM_DIN, + SPW_NOM_SIN => SPW_NOM_SIN, + SPW_NOM_DOUT => SPW_NOM_DOUT, + SPW_NOM_SOUT => SPW_NOM_SOUT, + SPW_RED_DIN => SPW_RED_DIN, + SPW_RED_SIN => SPW_RED_SIN, + SPW_RED_DOUT => SPW_RED_DOUT, + SPW_RED_SOUT => SPW_RED_SOUT, + + ADC_nCS => ADC_nCS, + ADC_CLK => ADC_CLK, + ADC_SDO => ADC_SDO, + + SRAM_nWE => SRAM_nWE, + SRAM_CE => SRAM_CE, + SRAM_nOE => SRAM_nOE,ddr_buffer_f + SRAM_nBE => SRAM_nBE, + SRAM_A => SRAM_A, + SRAM_DQ => SRAM_DQ); + + +END; diff --git a/designs/MINI-LFR_WFP_MS/wave.do b/designs/MINI-LFR_WFP_MS/wave.do new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_WFP_MS/wave.do @@ -0,0 +1,24 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/message_simu +add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp +add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp +add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {11527482482 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 539 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {61313789250 ps} diff --git a/lib/lpp/dsp/cic/cic_lfr_add_sub.vhd b/lib/lpp/dsp/cic/cic_lfr_add_sub.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/cic/cic_lfr_add_sub.vhd @@ -0,0 +1,94 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.all; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; + +ENTITY cic_lfr_add_sub IS + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + OP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- 00 A + B + -- 01 A - B + -- 10 A + B + Carry + -- 11 A - B - Carry + + data_in_A : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_in_B : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_in_Carry : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + data_out_Carry : OUT STD_LOGIC + ); +END cic_lfr_add_sub; + +ARCHITECTURE beh OF cic_lfr_add_sub IS + + SIGNAL data_carry : STD_LOGIC; + SIGNAL STD_LOGIC_VECTOR_ZERO : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_add : STD_LOGIC_VECTOR(16 DOWNTO 0); + SIGNAL data_sub : STD_LOGIC_VECTOR(16 DOWNTO 0); + + SIGNAL data : STD_LOGIC_VECTOR(16 DOWNTO 0); + +BEGIN + + STD_LOGIC_VECTOR_ZERO <= (OTHERS => '0'); + data_carry <= '0' WHEN OP(1) = '0' ELSE data_in_Carry; + + data_add <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A) + + SIGNED('0' & data_in_B) + + SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry)); + + data_sub <= STD_LOGIC_VECTOR( SIGNED('0' & data_in_A) + - SIGNED('0' & data_in_B) + - SIGNED(STD_LOGIC_VECTOR_ZERO & data_carry)); + + data <= data_add WHEN OP(0) = '0' ELSE data_sub; + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN + data_out_Carry <= '0'; + data_out <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN + IF run = '0' THEN + data_out_Carry <= '0'; + data_out <= (OTHERS => '0'); + ELSE + data_out_Carry <= data(16); + data_out <= data(15 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + +END beh; + diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd @@ -0,0 +1,12 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +PACKAGE lpp_lfr_time_management_apbreg_pkg IS + + CONSTANT ADDR_LFR_TM_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000"; + CONSTANT ADDR_LFR_TM_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001"; + CONSTANT ADDR_LFR_TM_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010"; + CONSTANT ADDR_LFR_TM_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011"; + +END lpp_lfr_time_management_apbreg_pkg; diff --git a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.stdlib.ALL; +LIBRARY gaisler; +USE gaisler.libdcom.ALL; +USE gaisler.sim.ALL; +USE gaisler.jtagtst.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_sim_pkg IS + + PROCEDURE UART_INIT ( + SIGNAL TX : OUT STD_LOGIC; + CONSTANT tx_period : IN TIME + ); + PROCEDURE UART_WRITE_ADDR32 ( + SIGNAL TX : OUT STD_LOGIC; + CONSTANT tx_period : IN TIME; + CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PROCEDURE UART_WRITE ( + SIGNAL TX : OUT STD_LOGIC; + CONSTANT tx_period : IN TIME; + CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2); + CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END lpp_sim_pkg; + +PACKAGE BODY lpp_sim_pkg IS + + PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS + BEGIN + txc(TX, 16#55#, tx_period); + END; + + PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME; + CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS + BEGIN + txc(TX, 16#c0#, tx_period); + txa(TX, + to_integer(UNSIGNED(ADDR(31 DOWNTO 24))), + to_integer(UNSIGNED(ADDR(23 DOWNTO 16))), + to_integer(UNSIGNED(ADDR(15 DOWNTO 8))), + to_integer(UNSIGNED(ADDR(7 DOWNTO 0))), + tx_period); + txa(TX, + to_integer(UNSIGNED(DATA(31 DOWNTO 24))), + to_integer(UNSIGNED(DATA(23 DOWNTO 16))), + to_integer(UNSIGNED(DATA(15 DOWNTO 8))), + to_integer(UNSIGNED(DATA(7 DOWNTO 0))), + tx_period); + END; + + PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME; + CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2); + CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS + + CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00"; + + BEGIN + txc(TX, 16#c0#, tx_period); + txa(TX, + to_integer(UNSIGNED(ADDR(31 DOWNTO 24))), + to_integer(UNSIGNED(ADDR(23 DOWNTO 16))), + to_integer(UNSIGNED(ADDR(15 DOWNTO 8))), + to_integer(UNSIGNED(ADDR_last)), + tx_period); + txa(TX, + to_integer(UNSIGNED(DATA(31 DOWNTO 24))), + to_integer(UNSIGNED(DATA(23 DOWNTO 16))), + to_integer(UNSIGNED(DATA(15 DOWNTO 8))), + to_integer(UNSIGNED(DATA(7 DOWNTO 0))), + tx_period); + END; + +END lpp_sim_pkg; diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -0,0 +1,2 @@ +lpp_sim_pkg.vhd + diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd @@ -0,0 +1,90 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +PACKAGE lpp_lfr_apbreg_pkg IS + + ----------------------------------------------------------------------------- + -- SPECTRAL_MATRIX + ----------------------------------------------------------------------------- + CONSTANT ADDR_LFR_SM_CONFIG : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000"; + CONSTANT ADDR_LFR_SM_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001"; + CONSTANT ADDR_LFR_SM_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010"; + CONSTANT ADDR_LFR_SM_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011"; + + CONSTANT ADDR_LFR_SM_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100"; + CONSTANT ADDR_LFR_SM_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101"; + CONSTANT ADDR_LFR_SM_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110"; + CONSTANT ADDR_LFR_SM_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000111"; + + CONSTANT ADDR_LFR_SM_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001000"; + CONSTANT ADDR_LFR_SM_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001001"; + CONSTANT ADDR_LFR_SM_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001010"; + CONSTANT ADDR_LFR_SM_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001011"; + + CONSTANT ADDR_LFR_SM_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001100"; + CONSTANT ADDR_LFR_SM_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001101"; + CONSTANT ADDR_LFR_SM_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001110"; + CONSTANT ADDR_LFR_SM_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "001111"; + + CONSTANT ADDR_LFR_SM_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010000"; + CONSTANT ADDR_LFR_SM_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010001"; + CONSTANT ADDR_LFR_SM_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010010"; + CONSTANT ADDR_LFR_SM_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010011"; + + CONSTANT ADDR_LFR_SM_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010100"; + ----------------------------------------------------------------------------- + -- WAVEFORM PICKER + ----------------------------------------------------------------------------- + CONSTANT ADDR_LFR_WP_DATASHAPING : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010101"; + CONSTANT ADDR_LFR_WP_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010110"; + CONSTANT ADDR_LFR_WP_F0_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "010111"; + + CONSTANT ADDR_LFR_WP_F0_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011000"; + CONSTANT ADDR_LFR_WP_F1_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011001"; + CONSTANT ADDR_LFR_WP_F1_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011010"; + CONSTANT ADDR_LFR_WP_F2_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011011"; + + CONSTANT ADDR_LFR_WP_F2_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011100"; + CONSTANT ADDR_LFR_WP_F3_0_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011101"; + CONSTANT ADDR_LFR_WP_F3_1_ADDR : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011110"; + CONSTANT ADDR_LFR_WP_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 2) := "011111"; + + CONSTANT ADDR_LFR_WP_DELTASNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100000"; + CONSTANT ADDR_LFR_WP_DELTA_F0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100001"; + CONSTANT ADDR_LFR_WP_DELTA_F0_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100010"; + CONSTANT ADDR_LFR_WP_DELTA_F1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100011"; + + CONSTANT ADDR_LFR_WP_DELTA_F2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100100"; + CONSTANT ADDR_LFR_WP_DATA_IN_BUFFER : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100101"; + CONSTANT ADDR_LFR_WP_NBSNAPSHOT : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100110"; + CONSTANT ADDR_LFR_WP_START_DATE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "100111"; + + CONSTANT ADDR_LFR_WP_F0_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101000"; + CONSTANT ADDR_LFR_WP_F0_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101001"; + CONSTANT ADDR_LFR_WP_F0_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101010"; + CONSTANT ADDR_LFR_WP_F0_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101011"; + + CONSTANT ADDR_LFR_WP_F1_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101100"; + CONSTANT ADDR_LFR_WP_F1_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101101"; + CONSTANT ADDR_LFR_WP_F1_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101110"; + CONSTANT ADDR_LFR_WP_F1_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "101111"; + + CONSTANT ADDR_LFR_WP_F2_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110000"; + CONSTANT ADDR_LFR_WP_F2_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110001"; + CONSTANT ADDR_LFR_WP_F2_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110010"; + CONSTANT ADDR_LFR_WP_F2_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110011"; + + CONSTANT ADDR_LFR_WP_F3_0_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110100"; + CONSTANT ADDR_LFR_WP_F3_0_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110101"; + CONSTANT ADDR_LFR_WP_F3_1_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110110"; + CONSTANT ADDR_LFR_WP_F3_1_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "110111"; + + CONSTANT ADDR_LFR_WP_LENGTH : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111000"; + ----------------------------------------------------------------------------- + -- LFR + ----------------------------------------------------------------------------- + CONSTANT ADDR_LFR_VERSION : STD_LOGIC_VECTOR(7 DOWNTO 2) := "111100"; + + +END lpp_lfr_apbreg_pkg; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fsmdma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fsmdma.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fsmdma.vhd @@ -0,0 +1,136 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_waveform_fsmdma IS + PORT ( + -- AMBA AHB system signals + clk : IN STD_ULOGIC; + rstn : IN STD_ULOGIC; + run : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- FIFO - IN + fifo_buffer_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_empty_threshold : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + + --------------------------------------------------------------------------- + -- DMA - OUT + dma_fifo_valid_burst : OUT STD_LOGIC; + dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_fifo_ren : IN STD_LOGIC; + + dma_buffer_new : OUT STD_LOGIC; + dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); + dma_buffer_full : IN STD_LOGIC; + dma_buffer_full_err : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- Reg In + status_buffer_ready : IN STD_LOGIC; + addr_buffer : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); + -- Reg Out + ready_buffer : OUT STD_LOGIC; + buffer_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error_buffer_full : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_fsmdma IS + + TYPE FSM_DMA_STATE IS (IDLE, ONGOING); + SIGNAL state : FSM_DMA_STATE; + SIGNAL burst_valid_s : STD_LOGIC; + +BEGIN + burst_valid_s <= NOT fifo_empty_threshold; + + error_buffer_full <= dma_buffer_full_err; + + fifo_ren <= dma_fifo_ren WHEN state = ONGOING ELSE '1'; + dma_fifo_data <= fifo_data; + dma_fifo_valid_burst <= burst_valid_s WHEN state = ONGOING ELSE '0'; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + buffer_time <= (OTHERS => '0'); + dma_buffer_addr <= (OTHERS => '0'); + dma_buffer_length <= (OTHERS => '0'); + dma_buffer_new <= '0'; + ready_buffer <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + ready_buffer <= '0'; + dma_buffer_new <= '0'; + IF run = '1' THEN + CASE state IS + WHEN IDLE => + IF fifo_empty = '0' THEN + IF status_buffer_ready = '0' THEN + state <= ONGOING; + buffer_time <= fifo_buffer_time; + dma_buffer_addr <= addr_buffer; + dma_buffer_length <= length_buffer; + dma_buffer_new <= '1'; + END IF; + END IF; + WHEN ONGOING => + IF dma_buffer_full = '1' THEN + ready_buffer <= '1'; + state <= IDLE; + END IF; + WHEN OTHERS => NULL; + END CASE; + ELSE + state <= IDLE; + buffer_time <= (OTHERS => '0'); + dma_buffer_addr <= (OTHERS => '0'); + dma_buffer_length <= (OTHERS => '0'); + dma_buffer_new <= '0'; + END IF; + END IF; + END PROCESS; + +END Behavioral;