diff --git a/boards/GSE_ICI/GSE_ICI.pdc b/boards/GSE_ICI/GSE_ICI.pdc
--- a/boards/GSE_ICI/GSE_ICI.pdc
+++ b/boards/GSE_ICI/GSE_ICI.pdc
@@ -13,6 +13,7 @@ set_iobank Bank0 -vcci 3.30 -fixed no
 
 set_io Clock -iostd LVTTL -REGISTER No -RES_PULL None -pinname 151 -fixed yes
 set_io DataRTX -iostd LVTTL -REGISTER No -RES_PULL None -pinname 190 -fixed yes
+set_io DataRTX_echo -iostd LVTTL -REGISTER No -RES_PULL None -pinname 42 -fixed yes
 set_io Gate -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 189 -fixed yes
 set_io Major_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 185 -fixed yes
 set_io Minor_Frame -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 183 -fixed yes
@@ -36,4 +37,11 @@ set_io reset -iostd LVTTL -REGISTER No -
 #set_io sclkbis -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 180 -fixed yes
 set_io sloe -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 153 -fixed yes
 set_io slrd -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 167 -fixed yes
-set_io slwr -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 166 -fixed yes
\ No newline at end of file
+set_io slwr -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 166 -fixed yes
+set_io BUS0   -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 48 -fixed yes
+set_io BUS12  -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 9 -fixed yes
+set_io BUS13  -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 7 -fixed yes
+set_io BUS14  -iostd LVTTL -REGISTER No -OUT_DRIVE 12 -SLEW High -RES_PULL None -SKEW Off -OUT_LOAD 35 -pinname 5 -fixed yes
+
+
+
diff --git a/boards/GSE_ICI/Makefile.inc b/boards/GSE_ICI/Makefile.inc
--- a/boards/GSE_ICI/Makefile.inc
+++ b/boards/GSE_ICI/Makefile.inc
@@ -4,15 +4,15 @@ SPEED=Std
 SYNFREQ=50
 
 PART=A3PE1500
-DESIGNER_PACKAGE=PQFP
+DESIGNER_PACKAGE=PQFF
 DESIGNER_PINS=208
 DESIGNER_VOLTAGE=COM
 DESIGNER_TEMP=COM
 
 MANUFACTURER=Actel
 MGCPART=$(PART)
-MGCTECHNOLOGY=PROASIC3
-MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
-LIBERO_DIE=IT14X14M4LDP
-LIBERO_PACKAGE=fg$(DESIGNER_PINS)
+MGCTECHNOLOGY=ProASIC3E
+MGCPACKAGE= {$(DESIGNER_PINS)$(DESIGNER_PACKAGE)}
+LIBERO_DIE=IT10X10M3
+LIBERO_PACKAGE=pq$(DESIGNER_PINS)
 
diff --git a/boards/GSE_ICI/default.sdc b/boards/GSE_ICI/default.sdc
--- a/boards/GSE_ICI/default.sdc
+++ b/boards/GSE_ICI/default.sdc
@@ -10,7 +10,9 @@
 #
 # Clocks
 #
-define_clock  {clk} -name {clk}  -freq 60 -clockgroup default_clkgroup -route 5
+define_clock  {clk} -name {clk}  -freq 48 -clockgroup default_clkgroup -route 5
+
+define_clock  {SCLKint} -name {SCLKint}  -freq 3.3 -clockgroup default_clkgroup -route 5
 
 #
 # Clock to Clock
diff --git a/designs/EGSE_ICI/DC_GATE_GEN.vhd b/designs/EGSE_ICI/DC_GATE_GEN.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/DC_GATE_GEN.vhd
@@ -0,0 +1,53 @@
+-- DC_GATE_GEN.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+
+
+
+
+
+entity DC_GATE_GEN is
+generic(WordCnt   :   integer := 144);
+port
+(
+    clk     :   in  std_logic;
+    Wcount  :   in  integer range 0 to WordCnt-1;
+    Gate    :   out std_logic
+);
+end entity;
+
+
+
+
+architecture ar_DC_GATE_GEN of DC_GATE_GEN is
+begin
+process(clk)
+    begin
+        if clk'event and clk ='0' then
+                case Wcount is
+                    when 48 =>
+                        gate <= '1';
+                    when 49 =>
+                        gate <= '1';
+
+                    when 50 =>
+                        gate <= '1';
+                    when 51 =>
+                        gate <= '1';
+
+                    when 52 =>
+                        gate <= '1';
+                    when 53 =>
+                        gate <= '1';
+
+                    
+                    when others =>
+                        gate <= '0';
+                end case;
+        end if;
+end process;
+end architecture;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/EGSE_ICI.vhd b/designs/EGSE_ICI/EGSE_ICI.vhd
--- a/designs/EGSE_ICI/EGSE_ICI.vhd
+++ b/designs/EGSE_ICI/EGSE_ICI.vhd
@@ -1,158 +1,282 @@
--- TOP_GSE.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
+-- TOP_GSE.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 library lpp;
 use lpp.lpp_usb.all;
+use lpp.Rocket_PCM_Encoder.all;
+use lpp.iir_filter.all;
+use lpp.general_purpose.all;
 library techmap;
-use techmap.gencomp.all;
-
-entity TOP_EGSE2 is 
-generic(WordSize : integer := 8; WordCnt    :   integer := 144;MinFCount   :   integer := 64;Simu : integer :=0);
-port(
-    Clock        : in  std_logic;
-    reset        : in  std_logic;
-    DataRTX      : in  std_logic;
-    DataRTX_echo : out std_logic;
-    SCLK         : out std_logic;
-    Gate         : out std_logic;
-    Major_Frame  : out std_logic;
-    Minor_Frame  : out std_logic;
-    if_clk       : out STD_LOGIC;
-    flagb        : in  STD_LOGIC; 
-    slwr         : out STD_LOGIC;
-    slrd         : out std_logic;
-    pktend       : out STD_LOGIC;
-    sloe         : out STD_LOGIC;
-    fdbusw       : out std_logic_vector (7 downto 0);
-    fifoadr      : out std_logic_vector (1 downto 0)
-);
-end TOP_EGSE2;
-
-
-
-architecture ar_TOP_EGSE2 of TOP_EGSE2 is
-
-  component CLKINT
-    port( A : in    std_logic := 'U';
-          Y : out   std_logic
-        );
-  end component;
-
-signal  clk         :   std_logic;
-signal  sclkint     :   std_logic;
-signal  RaZ         :   std_logic;
-signal  rstn        :   std_logic;
-signal  WordCount   :   integer range 0 to WordCnt-1;
-signal  WordClk     :   std_logic;
-signal  MinFCnt     :   integer range 0 to MinFCount-1;
-signal  MinF        :   std_logic;
-signal  MinFclk     :   std_logic;
-signal  MajF        :   std_logic;
-signal  GateLF      :   std_logic;
-signal  GateHF      :   std_logic;
-signal  GateDC      :   std_logic;
-signal  Gateint     :   std_logic;
-signal  GateR       :   std_logic;
-signal  NwDat       :   std_logic;
-signal  DATA        :   std_logic_vector(WordSize-1 downto 0);
-
-Signal  FIFODATin   :   std_logic_vector(7 downto 0);
-Signal  FIFODATout  :   std_logic_vector(7 downto 0);
-
-Signal  USB_DATA  :   std_logic_vector(7 downto 0);
-Signal  FIFOwe,FIFOre,FIFOfull      :   std_logic; 
-Signal  USBwe,USBfull,USBempty      :   std_logic; 
-
-Signal  clk80       :   std_logic;
-
-
-
-begin
+use techmap.gencomp.all;
+use work.config.all;
+
+
+entity TOP_EGSE2 is 
+generic(WordSize : integer := 8; WordCnt    :   integer := 144;MinFCount   :   integer := 64;Simu : integer :=0);
+port(
+    Clock        : in  std_logic;
+    reset        : in  std_logic;
+    DataRTX      : in  std_logic;
+    DataRTX_echo : out std_logic;
+    SCLK         : out std_logic;
+    Gate         : out std_logic;
+    Major_Frame  : out std_logic;
+    Minor_Frame  : out std_logic;
+    if_clk       : out STD_LOGIC;
+    flagb        : in  STD_LOGIC; 
+    slwr         : out STD_LOGIC;
+    slrd         : out std_logic;
+    pktend       : out STD_LOGIC;
+    sloe         : out STD_LOGIC;
+    fdbusw       : out std_logic_vector (7 downto 0);
+    fifoadr      : out std_logic_vector (1 downto 0);
+    BUS0         : out std_logic;
+    BUS12        : out std_logic;
+    BUS13        : out std_logic;
+    BUS14        : out std_logic
+);
+end TOP_EGSE2;
+
+
+
+architecture ar_TOP_EGSE2 of TOP_EGSE2 is
+
+  component CLKINT
+    port( A : in    std_logic := 'U';
+          Y : out   std_logic
+        );
+  end component;
+
+signal  clk         :   std_logic;
+signal  clk_48      :   std_logic;
+signal  sclkint     :   std_logic;
+signal  RaZ         :   std_logic;
+signal  rstn        :   std_logic;
+signal  WordCount   :   integer range 0 to WordCnt-1;
+signal  WordClk     :   std_logic;
+signal  MinFCnt     :   integer range 0 to MinFCount-1;
+signal  MinF        :   std_logic;
+signal  MinFclk     :   std_logic;
+signal  MajF        :   std_logic;
+signal  GateLF      :   std_logic;
+signal  GateHF      :   std_logic;
+signal  GateDC      :   std_logic;
+signal  GateR       :   std_logic;
+signal  Gateint     :   std_logic;
+signal  NwDat       :   std_logic;
+signal  NwDatR      :   std_logic;
+signal  DATA        :   std_logic_vector(WordSize-1 downto 0);
+signal  MinFVector  :   std_logic_vector(WordSize-1 downto 0);
+
+Signal  PROTO_WEN          :   std_logic;
+Signal  PROTO_DATAIN       :   std_logic_vector (WordSize-1 downto 0);
+Signal  PROTO_FULL         :   std_logic;
+Signal  PROTO_WR           :   std_logic;
+Signal  PROTO_DATAOUT      :   std_logic_vector (WordSize-1 downto 0);
+
+Signal  clk80       :   std_logic;
+
+
+
+begin
+
+
+DataRTX_echo    <= DataRTX; --P48
+
+
+ck_int0 :  CLKINT
+        port map(Clock,clk_48);
+
+DEFPLL: IF simu = 0 generate
+    PLL : entity work.PLL0
+        port map(
+            POWERDOWN => '1',
+            CLKA => clk_48,
+            LOCK => RaZ,
+            GLA  => clk80,
+            GLB  => clk         --33.3MHz
+        );
+end generate;
+
+
+SIMPLL: IF simu = 1 generate
+    PLL : entity work.PLL0Sim
+        port map(
+            POWERDOWN => '1',
+            CLKA => clk_48,
+            LOCK => RaZ,
+            GLA  => clk80,
+            GLB  => clk
+        );
+end generate;
+
+
+    gene3_3M : entity Clk_Divider2 
+    generic map(N => 10)
+    port map(
+        clk_in  => clk,
+        clk_out => sclkint
+    );
+
+    Wcounter : entity Word_Cntr
+        generic map(WordSize  => WordSize ,N  => WordCnt)
+        port map(
+            Sclk    => Sclkint,
+            reset   => rstn,
+            WordClk => WordClk,
+            Cnt_out => WordCount
+        );
 
-
-DataRTX_echo    <= DataRTX; --P48
-
-    ck_int0 :  CLKINT
-        port map(Clock,clk);
-
-DEFPLL: IF simu = 0 generate
-    PLL : entity work.PLL0
-        port map(
-            POWERDOWN => '1',
-            CLKA => clk,
-            LOCK => RaZ,
-            GLA  => SCLKint,
-            GLB  => clk80
-        );
-end generate;
-
-
-SIMPLL: IF simu = 1 generate
-    PLL : entity work.PLL0Sim
-        port map(
-            POWERDOWN => '1',
-            CLKA => clk,
-            LOCK => RaZ,
-            GLA  => SCLKint,
-            GLB  => clk80
-        );
-end generate;
-
-
-USB2: entity work.FX2_WithFIFO
-generic map(apa3)
-port map(
-        clk         => clk,
-        if_clk      => if_clk,
-        reset       => rstn,
-        flagb       => flagb,
-        slwr        => slwr,
-        slrd        => slrd,
-        pktend      => pktend,
-        sloe        => sloe,
-        fdbusw      => fdbusw,
-        fifoadr     => fifoadr,
-        FULL        => USBfull,
-        Write       => USBwe,
-        Data        => USB_DATA
-
-    );
-
-
-rstn    <=  reset and RaZ;
+    MFGEN0 : entity work.MinF_Gen  
+        generic map(WordCnt => WordCnt)
+        port map(
+            clk         => Sclkint,
+            reset       => rstn,
+            WordCnt_in  => WordCount,
+            WordClk     => WordClk,
+            MinF_Clk    => MinF
+        );
+
+    MinFcounter : entity Word_Cntr
+        generic map(WordSize  => WordCnt ,N  => MinFCount)
+        port map(
+            Sclk    => WordClk,
+            reset   => rstn,
+            WordClk => MinFclk,
+            Cnt_out => MinFCnt
+        );
+
+    MFGEN1 : entity work.MajF_Gen  
+        generic map(WordCnt => WordCnt,MinFCount => MinFCount)
+        port map(
+            clk         => Sclkint,
+            reset       => rstn,
+            WordCnt_in  => WordCount,
+            MinfCnt_in  => MinFCnt,
+            WordClk     => WordClk,
+            MajF_Clk    => MajF
+        );
+
+    LFGATEGEN0 : entity work.LF_GATE_GEN
+        generic map(WordCnt  => WordCnt)
+        port map(
+            clk     => Sclkint,
+            Wcount  => WordCount,
+            Gate    => GateLF
+        );
+
+    DCGATEGEN0 : entity work.DC_GATE_GEN
+        generic map(WordCnt  => WordCnt)
+        port map(
+            clk     => Sclkint,
+            Wcount  => WordCount,
+            Gate    => GateDC
+        );
+
+--GateDC  <= '0';
+--GateLF  <= '0';
+
+HFGATEGEN0 :
+        GateHF <= '1' when WordCount = 120 else 
+                  '1' when WordCount = 121 else '0';
+
+
+
+SD0 : entity Serial_driver2 
+generic map(Sz  => WordSize)
+port map(
+    Sclk    =>  Sclkint,
+    rstn    =>  rstn,
+    Sdata   =>  DataRTX,
+    Gate    =>  GateR,
+    NwDat   =>  NwDat,
+    Data    =>  DATA
+);
+
+
+
+proto: entity work.ICI_EGSE_PROTOCOL
+generic map(WordSize  => WordSize,WordCnt  => WordCnt,MinFCount => MinFCount,Simu => 0)
+port map(
+    clk        => clk,
+--    reset      => not MinF,
+    reset      => rstn,
+    WEN        => PROTO_WEN,
+    MinfCnt_in => MinfCnt,
+    WordCnt_in => WordCount,
+    DATAIN     => PROTO_DATAIN,
+    FULL       => PROTO_FULL,
+    WR         => PROTO_WR,
+    DATAOUT    => PROTO_DATAOUT
+);
+
+
+
+USB2: entity work.FX2_WithFIFO
+generic map(CFG_MEMTECH,use_RAM)
+port map(
+        clk         => clk,
+        if_clk      => if_clk,
+        reset       => rstn,
+        flagb       => flagb,
+        slwr        => slwr,
+        slrd        => slrd,
+        pktend      => pktend,
+        sloe        => sloe,
+        fdbusw      => fdbusw,
+        fifoadr     => fifoadr,
+        FULL        => PROTO_FULL,
+        wen         => PROTO_WR,
+        Data        => PROTO_DATAOUT
+);
+
+
+rstn    <=  reset and RaZ;
+SCLK    <=  Sclkint;
+
+Major_Frame <=  MajF;
+--Minor_Frame <=  MinF;
+Minor_Frame <=  MinFclk;
+gateint <=  GateDC or GateLF or GateHF;
+Gate    <=  gateint;
+
+process(Sclkint,rstn)
+begin
+    if rstn = '0' then 
+        GateR <=    '0';
+    elsif Sclkint'event and Sclkint = '0' then
+        GateR   <=   Gateint;
+    end if;
+end process;
+
+BUS0  <= WordClk;
+BUS12 <= MinFVector(0);
+BUS13 <= MinFclk;
+BUS14 <= '1' when WordCount = 0 else '0';
+
+MinFVector    <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
+
 
 process(clk,rstn)
 begin
-    if rstn = '0' then  
-        USB_DATA    <= (others => '0');
-        USBwe       <= '0';
+    if rstn = '0' then
+        PROTO_DATAIN    <= (others => '0');
+        PROTO_WEN       <= '1';
     elsif clk'event and clk = '1' then
-        if USBfull = '0' then
-            USB_DATA    <=  std_logic_vector(unsigned(USB_DATA) + 1 );
-            USBwe       <= '1';
+        NwDatR   <= NwDat;
+        if NwDat = '1' and NwDatR = '0'  then
+            PROTO_DATAIN  <=  std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
+            PROTO_WEN       <= '0';
         else
-            USBwe       <= '0';
+            PROTO_WEN       <= '1';
         end if;
     end if;
-end process;
-
-end ar_TOP_EGSE2;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+end process;
+
+end ar_TOP_EGSE2;
+
+
+
+
+
diff --git a/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL.vhd
@@ -0,0 +1,98 @@
+-- ICI_EGSE_PROTOCOL.vhd
+-- ICI_EGSE_PROTOCOL.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ICI_EGSE_PROTOCOL is 
+generic(WordSize : integer := 8;WordCnt : integer :=144;MinFCount   :   integer := 64;Simu : integer :=0);
+port(
+    clk          : in  std_logic;
+    reset        : in  std_logic;
+    WEN          : in  std_logic;
+    WordCnt_in   : in  integer range 0 to WordCnt-1;
+    MinfCnt_in   : in  integer range 0 to MinFCount-1;
+    DATAIN       : in  std_logic_vector (WordSize-1 downto 0);
+    FULL         : in  std_logic;
+    WR           : out std_logic;
+    DATAOUT      : out std_logic_vector (WordSize-1 downto 0)
+);
+end ICI_EGSE_PROTOCOL;
+
+
+architecture ar_ICI_EGSE_PROTOCOL of ICI_EGSE_PROTOCOL is
+
+type   DATA_pipe_t is  array(NATURAL RANGE <>) of  std_logic_vector (WordSize-1 downto 0);
+
+signal DATA_pipe    : DATA_pipe_t(10 downto 0);
+signal WR_pipe      : std_logic_vector(10 downto 0);
+signal headerSended : std_logic := '0';
+
+
+begin
+
+WR          <= WR_pipe(0);
+
+DATAOUT     <= DATA_pipe(0);
+
+
+process(reset,clk)
+begin
+    if reset = '0' then
+        WR_pipe(10 downto 0)         <= (others => '1');
+rstloop: for i in 0 to 10 loop
+            DATA_pipe(i)    <= X"00";
+        end loop;
+        headerSended    <=  '0';
+    elsif clk'event and clk ='1' then
+        if WordCnt_in = 1 and headerSended = '0' then
+            WR_pipe(4 downto 1)         <= (others => '0');
+            WR_pipe(1)      <=  '0';
+            WR_pipe(3)      <=  '0';
+            WR_pipe(5)      <=  '0';
+            WR_pipe(7)      <=  '0';
+            WR_pipe(9)      <=  '0';
+            DATA_pipe(1)    <= X"0F";
+            DATA_pipe(3)    <= X"5a";
+            DATA_pipe(5)    <= X"a5";
+            DATA_pipe(7)    <= X"F0";           
+            DATA_pipe(9)    <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
+            WR_pipe(0)      <=  '1';
+            WR_pipe(2)      <=  '1';
+            WR_pipe(4)      <=  '1';
+            WR_pipe(6)      <=  '1';
+            WR_pipe(8)      <=  '1';
+            WR_pipe(10)     <=  '1';
+            DATA_pipe(0)    <= X"00";
+            DATA_pipe(2)    <= X"00";
+            DATA_pipe(4)    <= X"00";
+            DATA_pipe(6)    <= X"00";
+            DATA_pipe(10)   <= X"00";
+            headerSended    <= '1';
+        elsif (FULL = '0') then
+            if WordCnt_in /= 1 then
+                headerSended    <= '0';
+            end if;
+            DATA_pipe(0)    <= DATA_pipe(1);
+            DATA_pipe(1)    <= DATA_pipe(2);
+            DATA_pipe(2)    <= DATA_pipe(3);
+            DATA_pipe(3)    <= DATA_pipe(4);
+            DATA_pipe(4)    <= DATA_pipe(5);
+            DATA_pipe(5)    <= DATA_pipe(6);
+            DATA_pipe(6)    <= DATA_pipe(7);
+            DATA_pipe(7)    <= DATA_pipe(8);
+            DATA_pipe(8)    <= DATA_pipe(9);
+            DATA_pipe(9)    <= DATA_pipe(10);
+            DATA_pipe(10)   <= DATAIN;
+            WR_pipe(10 downto 0)         <=  WEN & WR_pipe(10 downto 1);
+        else
+            WR_pipe(0)      <= '1';
+            if WordCnt_in /= 1 then
+                headerSended    <= '0';
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end ar_ICI_EGSE_PROTOCOL;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/ICI_EGSE_PROTOCOL2.vhd b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL2.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/ICI_EGSE_PROTOCOL2.vhd
@@ -0,0 +1,87 @@
+-- ICI_EGSE_PROTOCOL.vhd
+-- ICI_EGSE_PROTOCOL.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ICI_EGSE_PROTOCOL2 is
+generic(WordSize : integer := 8;Simu : integer :=0);
+port(
+    clk          : in  std_logic;
+    reset        : in  std_logic;
+    WEN          : in  std_logic;
+    MinF         : in  std_logic;
+    DATAIN       : in  std_logic_vector (WordSize-1 downto 0);
+    FULL         : in  std_logic;
+    WR           : out std_logic;
+    DATAOUT      : out std_logic_vector (WordSize-1 downto 0)
+);
+end ICI_EGSE_PROTOCOL2;
+
+
+architecture ar_ICI_EGSE_PROTOCOL2 of ICI_EGSE_PROTOCOL2 is
+
+type   state_t is (idle,forward,header1,header2,header3,header4);
+signal MinFReg      : std_logic;
+signal state        : state_t;
+
+begin
+
+process(reset,clk)
+begin
+    if reset = '0' then
+        MinFReg         <= '1';
+        state   <=  idle;
+        DATAOUT <=  X"00";
+        WR      <=  '1';
+    elsif clk'event and clk ='1' then
+        MinFReg         <= MinF;
+        case state is
+            when idle =>
+                DATAOUT <=  X"00";
+                WR      <=  '1';
+                state   <= forward;
+            when forward =>
+                DATAOUT <=  DATAIN;
+                WR      <=  WEN;
+                if MinFReg = '0' and MinF = '1' then
+                    state   <= header1;
+                end if;
+            when header1 =>
+                if FULL = '0' then
+                    WR       <= '0';
+                    DATAOUT  <= X"5a";
+                    state    <= header2;
+                else
+                    WR  <= '1';
+                end if;
+            when header2 =>
+                if FULL = '0' then
+                    WR       <= '0';
+                    DATAOUT  <= X"F0";
+                    state    <= header3;
+                else
+                    WR  <= '1';
+                end if;
+            when header3 =>
+                if FULL = '0' then
+                    WR       <= '0';
+                    DATAOUT  <= X"0F";
+                    state    <= header4;
+                else
+                    WR  <= '1';
+                end if;
+            when header4 =>
+                if FULL = '0' then
+                    WR       <= '0';
+                    DATAOUT  <= X"a5";
+                    state    <= forward;
+                else
+                    WR  <= '1';
+                end if;
+        end case;
+    end if;
+end process;
+
+
+end ar_ICI_EGSE_PROTOCOL2;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/LF_GATE_GEN.vhd b/designs/EGSE_ICI/LF_GATE_GEN.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/LF_GATE_GEN.vhd
@@ -0,0 +1,116 @@
+-- LF_GATE_GEN.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+
+
+
+
+
+entity LF_GATE_GEN is
+generic(WordCnt   :   integer := 144);
+port
+(
+    clk     :   in  std_logic;
+    Wcount  :   in  integer range 0 to WordCnt-1;
+    Gate    :   out std_logic
+);
+end entity;
+
+
+
+
+architecture ar_LF_GATE_GEN of LF_GATE_GEN is
+begin
+process(clk)
+    begin
+        if clk'event and clk ='0' then
+                case Wcount is
+                    when 6 =>
+                        gate <= '1';
+                    when 7 =>
+                        gate <= '1';
+                    when 8 =>
+                        gate <= '1';
+                    when 9 =>
+                        gate <= '1';
+                    when 10 =>
+                        gate <= '1';
+                    when 11 =>
+                        gate <= '1';
+
+                    when 30 =>
+                        gate <= '1';
+                    when 31 =>
+                        gate <= '1';
+                    when 32 =>
+                        gate <= '1';
+                    when 33 =>
+                        gate <= '1';
+                    when 34 =>
+                        gate <= '1';
+                    when 35 =>
+                        gate <= '1';
+
+                    when 54 =>
+                        gate <= '1';
+                    when 55 =>
+                        gate <= '1';
+                    when 56 =>
+                        gate <= '1';
+                    when 57 =>
+                        gate <= '1';
+                    when 58 =>
+                        gate <= '1';
+                    when 59 =>
+                        gate <= '1';
+
+                    when 78 =>
+                        gate <= '1';
+                    when 79 =>
+                        gate <= '1';
+                    when 80 =>
+                        gate <= '1';
+                    when 81 =>
+                        gate <= '1';
+                    when 82 =>
+                        gate <= '1';
+                    when 83 =>
+                        gate <= '1';
+
+                    when 102 =>
+                        gate <= '1';
+                    when 103 =>
+                        gate <= '1';
+                    when 104 =>
+                        gate <= '1';
+                    when 105 =>
+                        gate <= '1';
+                    when 106 =>
+                        gate <= '1';
+                    when 107 =>
+                        gate <= '1';
+
+                    when 126 =>
+                        gate <= '1';
+                    when 127 =>
+                        gate <= '1';
+                    when 128 =>
+                        gate <= '1';
+                    when 129 =>
+                        gate <= '1';
+                    when 130 =>
+                        gate <= '1';
+                    when 131 =>
+                        gate <= '1';
+
+
+                    when others =>
+                        gate <= '0';
+                end case;
+        end if;
+end process;
+end architecture;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/MajF_Gen.vhd b/designs/EGSE_ICI/MajF_Gen.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/MajF_Gen.vhd
@@ -0,0 +1,42 @@
+-- MajF_Gen.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+entity MajF_Gen is 
+generic(WordCnt : integer :=144;MinFCount   :   integer := 64);
+port(
+    clk         :   in  std_logic;
+    reset       :   in  std_logic;
+    WordCnt_in  :   in  integer range 0 to WordCnt-1;
+    MinfCnt_in  :   in  integer range 0 to MinFCount-1;
+    WordClk     :   in  std_logic;
+    MajF_Clk    :   out std_logic
+);
+end entity;
+
+
+
+
+
+
+architecture arMajF_Gen of MajF_Gen is
+
+begin
+
+process(clk)
+begin
+    if reset = '0' then
+        MajF_Clk    <=  '0';
+    elsif clk'event and clk = '0' then
+        if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' then
+            MajF_Clk    <=  '1';
+        else
+            MajF_Clk    <=  '0';
+        end if;
+    end if;
+end process;
+
+end architecture;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/Makefile b/designs/EGSE_ICI/Makefile
--- a/designs/EGSE_ICI/Makefile
+++ b/designs/EGSE_ICI/Makefile
@@ -9,7 +9,7 @@ QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
 EFFORT=high
 XSTOPT=
 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
-VHDLSYNFILES=config.vhd EGSE_ICI.vhd
+VHDLSYNFILES=config.vhd EGSE_ICI.vhd DC_GATE_GEN.vhd LF_GATE_GEN.vhd MajF_Gen.vhd MinF_Gen.vhd Serial_driver.vhd ICI_EGSE_PROTOCOL.vhd 
 VHDLSIMFILES=testbench.vhd
 SIMTOP=testbench
 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
@@ -22,8 +22,8 @@ TECHLIBS = proasic3
 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
 	tmtc openchip hynix ihp gleichmann micron usbhc spw  fmf gsi  eth spansion  esa
 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
-	pci grusbhc haps  slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft sparc can greth net gr1553b lpp_waveform \
-	lpp_dma
+	pci grusbhc haps  slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft can greth net gr1553b ./amba_lcd_16x2_ctrlr ./lpp_waveform \
+	./lpp_dma
 
 FILESKIP = i2cmst.vhd
 
diff --git a/designs/EGSE_ICI/MinF_Gen.vhd b/designs/EGSE_ICI/MinF_Gen.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/MinF_Gen.vhd
@@ -0,0 +1,41 @@
+-- MinF_Gen.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+entity MinF_Gen is 
+generic(WordCnt : integer :=144);
+port(
+    clk         :   in  std_logic;
+    reset       :   in  std_logic;
+    WordCnt_in  :   in  integer range 0 to WordCnt-1;
+    WordClk     :   in  std_logic;
+    MinF_Clk    :   out std_logic
+);
+end entity;
+
+
+
+
+
+
+architecture arMinF_Gen of MinF_Gen is
+
+begin
+
+process(clk)
+begin
+    if reset = '0' then
+        MinF_Clk    <=  '0';
+    elsif clk'event and clk = '0' then
+        if WordCnt_in = 0 and WordClk = '1' then
+            MinF_Clk    <=  '1';
+        else
+            MinF_Clk    <=  '0';
+        end if;
+    end if;
+end process;
+
+end architecture;
\ No newline at end of file
diff --git a/designs/EGSE_ICI/Serial_driver.vhd b/designs/EGSE_ICI/Serial_driver.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/Serial_driver.vhd
@@ -0,0 +1,62 @@
+-- Serial_driver.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+
+
+entity Serial_driver2 is
+generic(Sz  :   integer := 8);
+port(
+    Sclk    :   in std_logic;
+    rstn    :   in  std_logic;
+    Sdata   :   in  std_logic;
+    Gate    :   in  std_logic;
+    NwDat   :   out std_logic;
+    Data    :   out std_logic_vector(Sz-1 downto 0)
+);
+end entity;
+
+
+
+architecture  arSerial_driver2 of Serial_driver2 is
+signal  DataR    :    std_logic_vector(Sz-1 downto 0);
+signal  DataCnt  :    integer range 0 to Sz-1 :=0;
+signal  DataCntR :    integer range 0 to Sz-1 :=0;
+begin
+
+
+process(rstn,Sclk)
+begin
+    if rstn = '0' then
+        DataR   <=  (others=>'0');
+        NwDat   <=  '0';
+    elsif Sclk'event and Sclk ='1' then
+        DataCntR    <=  DataCnt;
+        if DataCntR = Sz-1 then
+            NwDat   <=  '1';
+            Data    <=  DataR;
+        else
+            NwDat   <=  '0';
+        end if;
+        if Gate ='1' then
+            DataR   <=  DataR(Sz-2 downto 0) & Sdata;
+            if DataCnt = Sz-1 then
+                DataCnt <=  0;
+            else
+                DataCnt <=  DataCnt +1;
+            end if;
+        else
+            DataCnt <=  0;
+        end if;
+    end if;
+end process;
+
+
+end architecture;
+
+
+
+
diff --git a/designs/EGSE_ICI/config.vhd b/designs/EGSE_ICI/config.vhd
--- a/designs/EGSE_ICI/config.vhd
+++ b/designs/EGSE_ICI/config.vhd
@@ -36,145 +36,5 @@ package config is
   constant CFG_PCISYSCLK: integer := 0;
   constant CFG_CLK_NOFB : integer := 0;
 
--- LEON3 processor core
-  constant CFG_LEON3 : integer := 1;
-  constant CFG_NCPU : integer := (1);
-  constant CFG_NWIN : integer := (7);
-  constant CFG_V8 : integer := 0;
-  constant CFG_MAC : integer := 0;
-  constant CFG_SVT : integer := 0;
-  constant CFG_RSTADDR : integer := 16#00000#;
-  constant CFG_LDDEL : integer := (1);
-  constant CFG_NWP : integer := (0);
-  constant CFG_PWD : integer := 1*2;
-  constant CFG_FPU : integer := 0 + 16*0;
-  constant CFG_GRFPUSH : integer := 0;
-  constant CFG_ICEN : integer := 1;
-  constant CFG_ISETS : integer := 1;
-  constant CFG_ISETSZ : integer := 4;
-  constant CFG_ILINE : integer := 4;
-  constant CFG_IREPL : integer := 0;
-  constant CFG_ILOCK : integer := 0;
-  constant CFG_ILRAMEN : integer := 0;
-  constant CFG_ILRAMADDR: integer := 16#8E#;
-  constant CFG_ILRAMSZ : integer := 1;
-  constant CFG_DCEN : integer := 1;
-  constant CFG_DSETS : integer := 1;
-  constant CFG_DSETSZ : integer := 4;
-  constant CFG_DLINE : integer := 4;
-  constant CFG_DREPL : integer := 0;
-  constant CFG_DLOCK : integer := 0;
-  constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
-  constant CFG_DFIXED : integer := 16#00F3#;
-  constant CFG_DLRAMEN : integer := 0;
-  constant CFG_DLRAMADDR: integer := 16#8F#;
-  constant CFG_DLRAMSZ : integer := 1;
-  constant CFG_MMUEN : integer := 0;
-  constant CFG_ITLBNUM : integer := 2;
-  constant CFG_DTLBNUM : integer := 2;
-  constant CFG_TLB_TYPE : integer := 1 + 0*2;
-  constant CFG_TLB_REP : integer := 1;
-  constant CFG_DSU : integer := 1;
-  constant CFG_ITBSZ : integer := 0;
-  constant CFG_ATBSZ : integer := 0;
-  constant CFG_LEON3FT_EN : integer := 0;
-  constant CFG_IUFT_EN : integer := 0;
-  constant CFG_FPUFT_EN : integer := 0;
-  constant CFG_RF_ERRINJ : integer := 0;
-  constant CFG_CACHE_FT_EN : integer := 0;
-  constant CFG_CACHE_ERRINJ : integer := 0;
-  constant CFG_LEON3_NETLIST: integer := 0;
-  constant CFG_DISAS : integer := 0 + 0;
-  constant CFG_PCLOW : integer := 2;
-
--- AMBA settings
-  constant CFG_DEFMST : integer := (0);
-  constant CFG_RROBIN : integer := 1;
-  constant CFG_SPLIT : integer := 0;
-  constant CFG_AHBIO : integer := 16#FFF#;
-  constant CFG_APBADDR : integer := 16#800#;
-  constant CFG_AHB_MON : integer := 0;
-  constant CFG_AHB_MONERR : integer := 0;
-  constant CFG_AHB_MONWAR : integer := 0;
-
--- DSU UART
-  constant CFG_AHB_UART : integer := 1;
-
--- JTAG based DSU interface
-  constant CFG_AHB_JTAG : integer := 0;
-
--- Ethernet DSU
-  constant CFG_DSU_ETH : integer := 0 + 0;
-  constant CFG_ETH_BUF : integer := 1;
-  constant CFG_ETH_IPM : integer := 16#C0A8#;
-  constant CFG_ETH_IPL : integer := 16#0033#;
-  constant CFG_ETH_ENM : integer := 16#00007A#;
-  constant CFG_ETH_ENL : integer := 16#CC0001#;
-
--- LEON2 memory controller
-  constant CFG_MCTRL_LEON2 : integer := 1;
-  constant CFG_MCTRL_RAM8BIT : integer := 0;
-  constant CFG_MCTRL_RAM16BIT : integer := 0;
-  constant CFG_MCTRL_5CS : integer := 0;
-  constant CFG_MCTRL_SDEN : integer := 0;
-  constant CFG_MCTRL_SEPBUS : integer := 0;
-  constant CFG_MCTRL_INVCLK : integer := 0;
-  constant CFG_MCTRL_SD64 : integer := 0;
-  constant CFG_MCTRL_PAGE : integer := 0 + 0;
-
--- SSRAM controller
-  constant CFG_SSCTRL : integer := 0;
-  constant CFG_SSCTRLP16 : integer := 0;
-
--- AHB ROM
-  constant CFG_AHBROMEN : integer := 0;
-  constant CFG_AHBROPIP : integer := 0;
-  constant CFG_AHBRODDR : integer := 16#000#;
-  constant CFG_ROMADDR : integer := 16#000#;
-  constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-
--- AHB RAM
-  constant CFG_AHBRAMEN : integer := 0;
-  constant CFG_AHBRSZ : integer := 1;
-  constant CFG_AHBRADDR : integer := 16#A00#;
-
--- Gaisler Ethernet core
-  constant CFG_GRETH : integer := 0;
-  constant CFG_GRETH1G : integer := 0;
-  constant CFG_ETH_FIFO : integer := 8;
-
--- CAN 2.0 interface
-  constant CFG_CAN : integer := 0;
-  constant CFG_CANIO : integer := 16#0#;
-  constant CFG_CANIRQ : integer := 0;
-  constant CFG_CANLOOP : integer := 0;
-  constant CFG_CAN_SYNCRST : integer := 0;
-  constant CFG_CANFT : integer := 0;
-
--- UART 1
-  constant CFG_UART1_ENABLE : integer := 1;
-  constant CFG_UART1_FIFO : integer := 1;
-
--- LEON3 interrupt controller
-  constant CFG_IRQ3_ENABLE : integer := 1;
-
--- Modular timer
-  constant CFG_GPT_ENABLE : integer := 1;
-  constant CFG_GPT_NTIM : integer := (2);
-  constant CFG_GPT_SW : integer := (8);
-  constant CFG_GPT_TW : integer := (32);
-  constant CFG_GPT_IRQ : integer := (8);
-  constant CFG_GPT_SEPIRQ : integer := 1;
-  constant CFG_GPT_WDOGEN : integer := 0;
-  constant CFG_GPT_WDOG : integer := 16#0#;
-
--- GPIO port
-  constant CFG_GRGPIO_ENABLE : integer := 1;
-  constant CFG_GRGPIO_IMASK : integer := 16#0000#;
-  constant CFG_GRGPIO_WIDTH : integer := (7);
-
--- GRLIB debugging
-  constant CFG_DUART : integer := 0;
-
 
 end;
diff --git a/designs/EGSE_ICI/testbench.vhd b/designs/EGSE_ICI/testbench.vhd
new file mode 100644
--- /dev/null
+++ b/designs/EGSE_ICI/testbench.vhd
@@ -0,0 +1,61 @@
+-- LF_GATE_GEN.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+
+
+
+
+
+
+entity testbench is
+port
+(
+);
+end entity;
+
+
+
+
+architecture ar_testbench of testbench is
+signal Clock        :   std_logic;
+signal reset        :   std_logic;
+signal DataRTX      :   std_logic;
+signal DataRTX_echo :   std_logic;
+signal SCLK         :   std_logic;
+signal Gate         :   std_logic;
+signal Major_Frame  :   std_logic;
+signal Minor_Frame  :   std_logic;
+signal if_clk       :   STD_LOGIC;
+signal flagb        :   STD_LOGIC; 
+signal slwr         :   STD_LOGIC;
+signal slrd         :   std_logic;
+signal pktend       :   STD_LOGIC;
+signal sloe         :   STD_LOGIC;
+signal fdbusw       :   std_logic_vector (7 downto 0);
+signal fifoadr      :   std_logic_vector (1 downto 0);
+
+begin
+EGSE: entity TOP_EGSE2 
+generic map(8,144,64,1)
+port map(Clock,
+    reset,
+    DataRTX,
+    DataRTX_echo,
+    SCLK,
+    Gate,
+    Major_Frame,
+    Minor_Frame,
+    if_clk,
+    flagb,
+    slwr,
+    slrd,
+    pktend,
+    sloe,
+    fdbusw,
+    fifoadr
+);
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/Rocket_PCM_Encoder/Word_Cntr.vhd b/lib/lpp/Rocket_PCM_Encoder/Word_Cntr.vhd
--- a/lib/lpp/Rocket_PCM_Encoder/Word_Cntr.vhd
+++ b/lib/lpp/Rocket_PCM_Encoder/Word_Cntr.vhd
@@ -35,7 +35,11 @@ begin
         WordClk <=  '0';
     elsif Sclk'event and Sclk = '1' then
         if Wcnt = WordSize - 1 then
-            Cnt_int <=  Cnt_int + 1;
+            if Cnt_int = N-1 then
+                Cnt_int <= 0;
+            else
+                Cnt_int <=  Cnt_int + 1;
+            end if;
             Wcnt    <=  0;
             WordClk <=  '1';
         else
diff --git a/lib/lpp/lpp_usb/FX2_WithFIFO.vhd b/lib/lpp/lpp_usb/FX2_WithFIFO.vhd
--- a/lib/lpp/lpp_usb/FX2_WithFIFO.vhd
+++ b/lib/lpp/lpp_usb/FX2_WithFIFO.vhd
@@ -29,7 +29,7 @@ port(
         fifoadr     : out std_logic_vector (1 downto 0);
 
         FULL        : out std_logic;
-        Write       : in std_logic;
+        wen         : in std_logic;
         Data        : in std_logic_vector(7 downto 0)
     ); 
 end FX2_WithFIFO;
@@ -40,18 +40,18 @@ architecture Ar_FX2_WithFIFO of FX2_With
 type FX2State is (idle);
 
 Signal  USB_DATA  :   std_logic_vector(7 downto 0);
-Signal  FIFOwe,FIFOre,FIFOfull      :   std_logic; 
-Signal  USBwe,USBfull,USBempty      :   std_logic; 
+Signal  FIFOfull      :   std_logic; 
+Signal  USBwe,USBfull     :   std_logic; 
 
 begin
 
 FULL    <=  FIFOfull;
 
-FIFO: lpp_fifo 
+--FIFO:  lpp_fifo
+FIFO: FIFO_pipeline
 generic map(
     tech          => tech,
     Mem_use       => Mem_use,
-    Enable_ReUse  => '0',
     DataSz        =>  8,
     abits         =>  12
     )
@@ -64,7 +64,7 @@ port map(
     empty   =>   USBwe,
     raddr   =>   open,
     wclk    =>   clk,
-    wen     =>   not Write,
+    wen     =>   wen,
     wdata   =>   Data,
     full    =>   FIFOfull,
     waddr   =>   open
@@ -91,4 +91,3 @@ port map(
 end ar_FX2_WithFIFO; 
 
 
-