diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd
--- a/lib/lpp/lpp_cna/APB_DAC.vhd
+++ b/lib/lpp/lpp_cna/APB_DAC.vhd
@@ -45,7 +45,9 @@ entity APB_DAC is
     rst     : in  std_logic;           --! Reset general du composant
     apbi    : in  apb_slv_in_type;     --! Registre de gestion des entrées du bus
     apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
+    DataIN : in std_logic_vector(15 downto 0);
     Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
+    Readn   : out std_logic;
     SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
     SCLK    : out std_logic;           --! Horloge systeme du convertisseur
     DATA    : out std_logic            --! Donnée numérique sérialisé
@@ -68,7 +70,7 @@ signal Ready : std_logic;
 
 type DAC_ctrlr_Reg is record
      DAC_Cfg  : std_logic_vector(1 downto 0);
-     DAC_Data : std_logic_vector(15 downto 0);
+--     DAC_Data : std_logic_vector(15 downto 0);
 end record;
 
 signal Rec : DAC_ctrlr_Reg;
@@ -81,13 +83,14 @@ Rec.DAC_Cfg(1) <= Ready;
 
     CONV0 : DacDriver
         generic map (cpt_serial)
-        port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
+        port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Ready,Data);
+--        port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
 
 
     process(rst,clk)
     begin
         if(rst='0')then
-            Rec.DAC_Data <=  (others => '0');
+--            Rec.DAC_Data <=  (others => '0');
 
         elsif(clk'event and clk='1')then 
         
@@ -97,8 +100,8 @@ Rec.DAC_Cfg(1) <= Ready;
                 case apbi.paddr(abits-1 downto 2) is
                     when "000000" =>
                         Rec.DAC_Cfg(0) <= apbi.pwdata(0);
-                    when "000001" =>
-                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
+--                    when "000001" =>
+--                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
                     when others =>
                         null;
                 end case;
@@ -110,9 +113,9 @@ Rec.DAC_Cfg(1) <= Ready;
                     when "000000" =>
                         Rdata(31 downto 2) <= X"ABCDEF5" & "00";
                         Rdata(1 downto 0) <= Rec.DAC_Cfg;
-                    when "000001" =>
-                        Rdata(31 downto 16) <= X"FD18";
-                        Rdata(15 downto 0) <= Rec.DAC_Data;
+--                    when "000001" =>
+--                        Rdata(31 downto 16) <= X"FD18";
+--                        Rdata(15 downto 0) <= Rec.DAC_Data;
                     when others =>
                         Rdata <= (others => '0');
                 end case;
diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd
--- a/lib/lpp/lpp_cna/DacDriver.vhd
+++ b/lib/lpp/lpp_cna/DacDriver.vhd
@@ -32,9 +32,10 @@ generic(cpt_serial : integer := 6);  --! Générique contenant le résultat de la division clk/sclk  !!! clk=25Mhz
     clk         : in std_logic;                        --! Horloge du composant
     rst         : in std_logic;                        --! Reset general du composant
     enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-    Data_C      : in std_logic_vector(15 downto 0);    --! Donnée Numérique d'entrée sur 16 bits
+    Data_IN      : in std_logic_vector(15 downto 0);    --! Donnée Numérique d'entrée sur 16 bits
     SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
     SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
+    Readn       : out std_logic;
     Ready     : out std_logic;                       --! Flag, signale la fin de la sérialisation d'une donnée
     Data        : out std_logic                        --! Donnée numérique sérialisé
     );
@@ -46,7 +47,7 @@ end entity;
 architecture ar_DacDriver of DacDriver is
 
 signal s_SCLK      : std_logic;
-signal Sended    : std_logic;
+signal Send    : std_logic;
 
 begin
 
@@ -56,12 +57,14 @@ SystemCLK : Systeme_Clock
 
 
 Signal_sync : Gene_SYNC
-    port map (s_SCLK,rst,enable,Sended,SYNC);
+    port map (s_SCLK,rst,enable,Send,SYNC);
 
 
 Serial : serialize
-    port map (clk,rst,s_SCLK,Data_C,Sended,Ready,Data);
+    port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
 
+RenGEN : ReadFifo_GEN
+    port map (clk,rst,Send,Readn);
 
 SCLK        <= s_SCLK;
 
diff --git a/lib/lpp/lpp_cna/Gene_SYNC.vhd b/lib/lpp/lpp_cna/Gene_SYNC.vhd
--- a/lib/lpp/lpp_cna/Gene_SYNC.vhd
+++ b/lib/lpp/lpp_cna/Gene_SYNC.vhd
@@ -29,7 +29,7 @@ entity Gene_SYNC is
   port(
     SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
     enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-    Sended : out std_logic;   --! Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée
+    Send : out std_logic;   --! Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée
     SYNC : out std_logic         --! Signal de synchronisation du convertisseur généré
     );
 end Gene_SYNC;
@@ -46,7 +46,7 @@ begin
         if(raz='0')then
             SYNC <= '0';
             count <= 14;  
-            Sended <= '0';
+            Send <= '0';
         
         elsif(SCLK' event and SCLK='1')then    
             if(enable='1')then
@@ -57,10 +57,10 @@ begin
                 elsif(count=16)then
                     count <= 0;
                     SYNC <= '0';
-                    Sended <= '1';
+                    Send <= '1';
                 else
                     count <= count+1;
-                    Sended <= '0';
+                    Send <= '0';
                 end if;
 
             end if;
diff --git a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                     Mail : martin.morlot@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+entity ReadFifo_GEN is
+  port(
+    clk,raz : in std_logic;                      --! Horloge et Reset du composant
+    SYNC : in std_logic;
+    Readn : out std_logic
+    );
+end entity;
+
+
+architecture ar_ReadFifo_GEN of ReadFifo_GEN is
+
+type etat is (eX,e0);
+signal ect      : etat;
+
+signal SYNC_reg : std_logic;
+
+begin
+    process(clk,raz)
+        begin
+        if(raz='0')then           
+            ect         <= eX;
+            Readn  <= '1';           
+
+        elsif(clk'event and clk='1')then
+            SYNC_reg <= SYNC;
+          
+            case ect is
+                when eX =>                     
+                    if (SYNC_reg='0' and  SYNC='1') then 
+                        Readn    <= '0';                   
+                        ect     <= e0;
+                    end if;
+
+                when e0 =>
+                    Readn <= '1';                    
+                    ect <= eX;
+
+            end case;
+        end if;
+    end process;
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd
--- a/lib/lpp/lpp_cna/lpp_cna.vhd
+++ b/lib/lpp/lpp_cna/lpp_cna.vhd
@@ -37,15 +37,18 @@ component APB_DAC is
     paddr    : integer := 0;
     pmask    : integer := 16#fff#;
     pirq     : integer := 0;
-    abits    : integer := 8);
+    abits    : integer := 8;
+    cpt_serial : integer := 6);
   port (
     clk     : in  std_logic;
     rst     : in  std_logic;
     apbi    : in  apb_slv_in_type;
     apbo    : out apb_slv_out_type;
-    Cal_EN  : out std_logic;
-    SYNC    : out std_logic;
-    SCLK    : out std_logic;
+    DataIN : in std_logic_vector(15 downto 0);
+    Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
+    Readn   : out std_logic;
+    SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
+    SCLK    : out std_logic;           --! Horloge systeme du convertisseur
     DATA    : out std_logic
     );
 end component;
@@ -57,9 +60,10 @@ generic(cpt_serial : integer := 6);  --! Générique contenant le résultat de la division clk/sclk  !!! clk=25Mhz
         clk       : in std_logic;
         rst         : in std_logic;
         enable      : in std_logic;
-        Data_C      : in std_logic_vector(15 downto 0);
-        SYNC        : out std_logic;
-        SCLK        : out std_logic;
+        Data_IN      : in std_logic_vector(15 downto 0);    --! Donnée Numérique d'entrée sur 16 bits
+        SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
+        SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
+        Readn       : out std_logic;
         Ready     : out std_logic;
         Data        : out std_logic
         );
@@ -78,7 +82,7 @@ component Gene_SYNC is
     port(
     SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
     enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-    Sended : out std_logic;   --! Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée
+    Send : out std_logic;   --! Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée
     SYNC : out std_logic);         --! Signal de synchronisation du convertisseur généré
 end component;
 
@@ -93,4 +97,12 @@ port(
     Data    : out std_logic);
 end component;
 
+component ReadFifo_GEN is
+  port(
+    clk,raz : in std_logic;                      --! Horloge et Reset du composant
+    SYNC : in std_logic;
+    Readn : out std_logic
+    );
+end component;
+
 end;
\ No newline at end of file