diff --git a/.hgignore b/.hgignore --- a/.hgignore +++ b/.hgignore @@ -22,5 +22,6 @@ syntax: glob *vhdlsyn.txt *.orig *.o +*.a *~ diff --git a/LPP_drivers/includes/apb_dac_Driver.h b/LPP_drivers/includes/apb_dac_Driver.h new file mode 100644 --- /dev/null +++ b/LPP_drivers/includes/apb_dac_Driver.h @@ -0,0 +1,35 @@ +#ifndef APB_CNA_DRIVER_H +#define APB_CNA_DRIVER_H + +#define DAC_ready 3 +#define DAC_enable 1 +#define DAC_disable 0 + + +/*=================================================== + T Y P E S D E F +====================================================*/ + +struct DAC_Driver +{ + int configReg; + int dataReg; +}; + +typedef struct DAC_Driver DAC_Device; + +/*=================================================== + F U N C T I O N S +====================================================*/ + +DAC_Device* DacOpen(int count); + +//DAC_Device* DacClose(int count); + +int DacTable(); + +int DacConst(); + + + +#endif diff --git a/LPP_drivers/includes/lpp_apb_functions.h b/LPP_drivers/includes/lpp_apb_functions.h --- a/LPP_drivers/includes/lpp_apb_functions.h +++ b/LPP_drivers/includes/lpp_apb_functions.h @@ -14,7 +14,7 @@ -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------*/ #ifndef LPP_APB_FUNCTIONS_H #define LPP_APB_FUNCTIONS_H @@ -30,6 +30,8 @@ #define LPP_SIMPLE_DIODE 0x003 #define LPP_MULTI_DIODE 0x004 #define LPP_LCD_CTRLR 0x005 +#define LPP_UART_CTRLR 0x006 +#define LPP_DAC_CTRLR 0x007 /** @todo implemente a descriptor structure for any APB device */ diff --git a/LPP_drivers/lib/libapb_lcd_driver.a b/LPP_drivers/lib/libapb_lcd_driver.a deleted file mode 100644 index 50eca0d0964aab16fb6e58951b653f43ccb3fe25..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 GIT binary patch literal 0 Hc$@ ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -signal flag_nw : std_logic; -signal bp : std_logic; -signal Rz : std_logic; -signal flag_sd : std_logic; -signal Rdata : std_logic_vector(31 downto 0); - -type CNA_ctrlr_Reg is record - CNA_Cfg : std_logic_vector(3 downto 0); - CNA_Data : std_logic_vector(15 downto 0); -end record; - -signal Rec : CNA_ctrlr_Reg; ---signal ConfigREG : std_logic_vector(3 downto 0); ---signal DataREG : std_logic_vector(15 downto 0); - -begin - -bp <= Rec.CNA_Cfg(0); -flag_nw <= Rec.CNA_Cfg(1); -Rec.CNA_Cfg(2) <= flag_sd; -Rec.CNA_Cfg(3) <= Rz; - - - - CONVERTER : entity Work.CNA_TabloC - port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); - - - - process(rst,clk) - begin - if(rst='0')then - Rec.CNA_Data <= (others => '0'); - - elsif(clk'event and clk='1')then - - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); - when "000001" => - Rec.CNA_Data <= apbi.pwdata(15 downto 0); - when others => - null; - end case; - end if; - - --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 4) <= X"ABCDEF5"; - Rdata(3 downto 0) <= Rec.CNA_Cfg; - when "000001" => - Rdata(31 downto 16) <= X"FD18"; - Rdata(15 downto 0) <= Rec.CNA_Data; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -end ar_APB_CNA; diff --git a/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd b/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd +++ /dev/null @@ -1,88 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.Convertisseur_config.all; - -entity CNA_TabloC is - port( - clock : in std_logic; - rst : in std_logic; - flag_nw : in std_logic; - bp : in std_logic; - Data_C : in std_logic_vector(15 downto 0); - SYNC : out std_logic; - SCLK : out std_logic; - Rz : out std_logic; - flag_sd : out std_logic; - Data : out std_logic - ); -end CNA_TabloC; - - -architecture ar_CNA_TabloC of CNA_TabloC is - -component CLKINT -port( A : in std_logic := 'U'; - Y : out std_logic); -end component; - -signal clk : std_logic; ---signal reset : std_logic; - -signal raz : std_logic; -signal sys_clk : std_logic; -signal Data_int : std_logic_vector(15 downto 0); -signal OKAI_send : std_logic; - -begin - - -CLKINT_0 : CLKINT - port map(A => clock, Y => clk); - -CLKINT_1 : CLKINT - port map(A => rst, Y => raz); - - -SystemCLK : entity work.Clock_Serie - generic map (nb_serial) - port map (clk,raz,sys_clk); - - -Signal_sync : entity work.GeneSYNC_flag - port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); - - -Serial : entity work.serialize - port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); - - ---raz <= not reset; -Rz <= raz; -SCLK <= not sys_clk; ---Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); ---Data_TOT <= "0001" & Data_Cvec; - -with bp select - Data_int <= X"9555" when '1', - Data_C when others; - -end ar_CNA_TabloC; diff --git a/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd b/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd +++ /dev/null @@ -1,41 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -Package Convertisseur_config is - - ---===========================================================| ---================= Valeurs Sinus 1Khz ======================| ---===========================================================| -type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); -constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); - ---constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); - - ---===========================================================| ---============= Fréquence de sérialisation ==================| ---===========================================================| -constant Freq_serial : integer := 1_000_000; -constant nb_serial : integer := 40_000_000 / Freq_serial; - -end; diff --git a/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd b/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd +++ /dev/null @@ -1,111 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity GeneSYNC_flag is - -port( - clk,raz : in std_logic; - flag_nw : in std_logic; - Sysclk : in std_logic; - OKAI_send : out std_logic; - SYNC : out std_logic -); - -end GeneSYNC_flag; - - -architecture ar_GeneSYNC_flag of GeneSYNC_flag is - -signal Sysclk_reg : std_logic; -signal flag_nw_reg : std_logic; -signal count : integer; - -type etat is (e0,e1,e2,eX); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - SYNC <= '0'; - Sysclk_reg <= '0'; - flag_nw_reg <= '0'; - count <= 14; - OKAI_send <= '0'; - ect <= e0; - - elsif(clk' event and clk='1')then - Sysclk_reg <= Sysclk; - flag_nw_reg <= flag_nw; - - case ect is - when e0 => - if(flag_nw_reg='0' and flag_nw='1')then - ect <= e1; - else - count <= 14; - ect <= e0; - end if; - - - when e1 => - if(Sysclk_reg='1' and Sysclk='0')then - if(count=15)then - SYNC <= '1'; - count <= count+1; - ect <= e2; - elsif(count=16)then - count <= 0; - OKAI_send <= '1'; - ect <= eX; - else - count <= count+1; - OKAI_send <= '0'; - ect <= e1; - end if; - end if; - - - when e2 => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=16)then - SYNC <= '0'; - ect <= e1; - end if; - end if; - - when eX => - if(Sysclk_reg='0' and Sysclk='1')then - if(count=15)then - OKAI_send <= '0'; - ect <= e0; - else - count <= count+1; - ect <= eX; - end if; - end if; - - end case; - end if; - - end process; -end ar_GeneSYNC_flag; diff --git a/lib/lpp/lpp_CNA_amba/Serialize.vhd b/lib/lpp/lpp_CNA_amba/Serialize.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/Serialize.vhd +++ /dev/null @@ -1,103 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - -entity Serialize is - -port( - clk,raz : in std_logic; - sclk : in std_logic; - vectin : in std_logic_vector(15 downto 0); - send : in std_logic; - sended : out std_logic; - Data : out std_logic); - -end Serialize; - - -architecture ar_Serialize of Serialize is - -type etat is (attente,serialize); -signal ect : etat; - -signal vector_int : std_logic_vector(16 downto 0); -signal vectin_reg : std_logic_vector(15 downto 0); -signal load : std_logic; -signal N : integer range 0 to 16; -signal CPT_ended : std_logic:='0'; - -begin - process(clk,raz) - begin - if(raz='0')then - ect <= attente; - vectin_reg <= (others=> '0'); - load <= '0'; - sended <= '1'; - - elsif(clk'event and clk='1')then - vectin_reg <= vectin; - - case ect is - when attente => - if (send='1') then - sended <= '0'; - load <= '1'; - ect <= serialize; - else - ect <= attente; - end if; - - when serialize => - load <= '0'; - if(CPT_ended='1')then - ect <= attente; - sended <= '1'; - end if; - - end case; - end if; - end process; - - process(sclk,load,raz) - begin - if (raz='0')then - vector_int <= (others=> '0'); - N <= 16; - elsif(load='1')then - vector_int <= vectin & '0'; - N <= 0; - elsif(sclk'event and sclk='0')then - if (CPT_ended='0') then - vector_int <= vector_int(15 downto 0) & '0'; - N <= N+1; - end if; - end if; - end process; - -CPT_ended <= '1' when N = 16 else '0'; - -with ect select - Data <= vector_int(16) when serialize, - '0' when others; - -end ar_Serialize; - diff --git a/lib/lpp/lpp_CNA_amba/clock.vhd b/lib/lpp/lpp_CNA_amba/clock.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/clock.vhd +++ /dev/null @@ -1,58 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - - -entity Clock_Serie is - -generic(N :integer := 695); - -port( - clk, raz : in std_logic ; - clock : out std_logic); - -end Clock_Serie; - - -architecture ar_Clock_Serie of Clock_Serie is - -signal clockint : std_logic; -signal countint : integer range 0 to N/2-1; - -begin - process (clk,raz) - begin - if(raz = '0') then - countint <= 0; - clockint <= '0'; - elsif (clk' event and clk='1') then - if (countint = N/2-1) then - countint <= 0; - clockint <= not clockint; - else - countint <= countint+1; - end if; - end if; - end process; - -clock <= clockint; - -end ar_Clock_Serie; diff --git a/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd b/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd deleted file mode 100644 --- a/lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd +++ /dev/null @@ -1,51 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; --- pragma translate_off -use std.textio.all; --- pragma translate_on -library lpp; -use lpp.lpp_amba.all; - - -package lpp_CNA_amba is - - -component APB_CNA is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - SYNC : out std_logic; - SCLK : out std_logic; - DATA : out std_logic - ); -end component; - -end;