diff --git a/designs/LFR_simu/Makefile b/designs/LFR_simu/Makefile --- a/designs/LFR_simu/Makefile +++ b/designs/LFR_simu/Makefile @@ -13,7 +13,7 @@ XSTOPT= SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd +VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd SIMTOP=testbench #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc diff --git a/designs/LFR_simu/run_tb_waveform.do b/designs/LFR_simu/run_tb_waveform.do --- a/designs/LFR_simu/run_tb_waveform.do +++ b/designs/LFR_simu/run_tb_waveform.do @@ -6,6 +6,11 @@ vcom -quiet -93 -work lpp ../../../grl vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_test.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd +vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd vcom -quiet -93 -work lpp testbench_package.vhd @@ -16,6 +21,6 @@ vsim work.testbench log -r * -do tb_waveform.do +do wave_ms.do run -all diff --git a/designs/LFR_simu/tb_waveform.vhd b/designs/LFR_simu/tb_waveform.vhd --- a/designs/LFR_simu/tb_waveform.vhd +++ b/designs/LFR_simu/tb_waveform.vhd @@ -44,13 +44,21 @@ USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; USE lpp.CY7C1061DV33_pkg.ALL; -ENTITY testbenc h IS +ENTITY testbench IS END; ARCHITECTURE behav OF testbench IS - -- REG ADDRESS - CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15; - CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; + CONSTANT INDEX_LFR : INTEGER := 15; + CONSTANT ADDR_LFR : INTEGER := 15; + -- REG MS + CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; + CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; + CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; + -- REG WAVEFORM CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; @@ -168,7 +176,7 @@ ARCHITECTURE behav OF testbench IS SIGNAL wpo : wprot_out_type; SIGNAL sdo : sdram_out_type; - SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL nSRAM_BE0 : STD_LOGIC; SIGNAL nSRAM_BE1 : STD_LOGIC; @@ -231,13 +239,13 @@ BEGIN nb_snapshot_param_size => 32, delta_vector_size => 32, delta_vector_size_f0_2 => 32, - pindex => INDEX_WAVEFORM_PICKER, - paddr => ADDR_WAVEFORM_PICKER, + pindex => INDEX_LFR, + paddr => ADDR_LFR, pmask => 16#fff#, pirq_ms => 6, pirq_wfp => 14, hindex => 0, - top_lfr_version => X"00000001") + top_lfr_version => X"000001") PORT MAP ( clk => clk25MHz, rstn => rstn, @@ -260,6 +268,8 @@ BEGIN ioen => 0, nahbm => 1, nahbs => 1) PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); + + --- AHB RAM ---------------------------------------------------------- --ahbram0 : ahbram -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) @@ -275,78 +285,78 @@ BEGIN -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); ----------------------------------------------------------------------------- ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + ---------------------------------------------------------------------- + --- Memory controllers --------------------------------------------- + ---------------------------------------------------------------------- + --memctrlr : mctrl GENERIC MAP ( + -- hindex => 0, + -- pindex => 0, + -- paddr => 0, + -- srbanks => 1 + -- ) + -- PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; + --memi.brdyn <= '1'; + --memi.bexcn <= '1'; + --memi.writen <= '1'; + --memi.wrn <= "1111"; + --memi.bwidth <= "10"; - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; + --bdr : FOR i IN 0 TO 3 GENERATE + -- data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + -- PORT MAP ( + -- data(31-i*8 DOWNTO 24-i*8), + -- memo.data(31-i*8 DOWNTO 24-i*8), + -- memo.bdrive(i), + -- memi.data(31-i*8 DOWNTO 24-i*8)); + --END GENERATE; - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); + --addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + -- PORT MAP (address, memo.address(21 DOWNTO 2)); - not_ramsn_0 <= NOT(memo.ramsn(0)); + --not_ramsn_0 <= NOT(memo.ramsn(0)); - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + --rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); + --oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + --nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + --nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + --nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + --nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + --nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - async_1Mx16_0: CY7C1061DV33 - GENERIC MAP ( - ADDR_BITS => 20, - DATA_BITS => 16, - depth => 1048576, - TimingInfo => TRUE, - TimingChecks => '1') - PORT MAP ( - CE1_b => '0', - CE2 => nSRAM_CE, - WE_b => nSRAM_WE, - OE_b => nSRAM_OE, - BHE_b => nSRAM_BE1, - BLE_b => nSRAM_BE0, - A => address, - DQ => data(15 DOWNTO 0)); + --async_1Mx16_0: CY7C1061DV33 + -- GENERIC MAP ( + -- ADDR_BITS => 20, + -- DATA_BITS => 16, + -- depth => 1048576, + -- TimingInfo => TRUE, + -- TimingChecks => '1') + -- PORT MAP ( + -- CE1_b => '0', + -- CE2 => nSRAM_CE, + -- WE_b => nSRAM_WE, + -- OE_b => nSRAM_OE, + -- BHE_b => nSRAM_BE1, + -- BLE_b => nSRAM_BE0, + -- A => address, + -- DQ => data(15 DOWNTO 0)); - async_1Mx16_1: CY7C1061DV33 - GENERIC MAP ( - ADDR_BITS => 20, - DATA_BITS => 16, - depth => 1048576, - TimingInfo => TRUE, - TimingChecks => '1') - PORT MAP ( - CE1_b => '0', - CE2 => nSRAM_CE, - WE_b => nSRAM_WE, - OE_b => nSRAM_OE, - BHE_b => nSRAM_BE3, - BLE_b => nSRAM_BE2, - A => address, - DQ => data(31 DOWNTO 16)); + --async_1Mx16_1: CY7C1061DV33 + -- GENERIC MAP ( + -- ADDR_BITS => 20, + -- DATA_BITS => 16, + -- depth => 1048576, + -- TimingInfo => TRUE, + -- TimingChecks => '1') + -- PORT MAP ( + -- CE1_b => '0', + -- CE2 => nSRAM_CE, + -- WE_b => nSRAM_WE, + -- OE_b => nSRAM_OE, + -- BHE_b => nSRAM_BE3, + -- BLE_b => nSRAM_BE2, + -- A => address, + -- DQ => data(31 DOWNTO 16)); ----------------------------------------------------------------------------- @@ -373,30 +383,40 @@ BEGIN WAIT UNTIL clk25MHz = '1'; rstn <= '1'; WAIT UNTIL clk25MHz = '1'; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); WAIT UNTIL clk25MHz = '1'; --------------------------------------------------------------------------- -- CONFIGURATION STEP - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" -- - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); WAIT UNTIL clk25MHz = '1'; WAIT UNTIL clk25MHz = '1'; - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); + + + --APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); WAIT UNTIL clk25MHz = '1'; WAIT UNTIL clk25MHz = '1'; WAIT UNTIL clk25MHz = '1'; @@ -408,18 +428,18 @@ BEGIN --------------------------------------------------------------------------- -- RUN STEP WAIT FOR 200 ms; - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); WAIT FOR 10 us; WAIT UNTIL clk25MHz = '1'; WAIT UNTIL clk25MHz = '1'; - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); WAIT UNTIL clk25MHz = '1'; coarse_time <= X"00000010"; WAIT FOR 100 ms; - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); WAIT FOR 10 us; - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); WAIT FOR 200 ms; REPORT "*** END simulation ***" SEVERITY failure; diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd --- a/lib/lpp/lpp_amba/apb_devices_list.vhd +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -40,6 +40,6 @@ PACKAGE apb_devices_list IS CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; - CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; + CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A1#; END; diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -1,424 +1,426 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY leon3_soc IS - GENERIC ( - fabtech : INTEGER := apa3e; - memtech : INTEGER := apa3e; - padtech : INTEGER := inferred; - clktech : INTEGER := inferred; - disas : INTEGER := 0; -- Enable disassembly to console - dbguart : INTEGER := 0; -- Print UART on console - pclow : INTEGER := 2; - -- - clk_freq : INTEGER := 25000; --kHz - -- - NB_CPU : INTEGER := 1; - ENABLE_FPU : INTEGER := 1; - FPU_NETLIST : INTEGER := 1; - ENABLE_DSU : INTEGER := 1; - ENABLE_AHB_UART : INTEGER := 1; - ENABLE_APB_UART : INTEGER := 1; - ENABLE_IRQMP : INTEGER := 1; - ENABLE_GPT : INTEGER := 1; - -- - NB_AHB_MASTER : INTEGER := 0; - NB_AHB_SLAVE : INTEGER := 0; - NB_APB_SLAVE : INTEGER := 0 - ); - PORT ( - clk : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- APB -------------------------------------------------------------------- - apbi_ext : OUT apb_slv_in_type; - apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); - -- AHB_Slave -------------------------------------------------------------- - ahbi_s_ext : OUT ahb_slv_in_type; - ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); - -- AHB_Master ------------------------------------------------------------- - ahbi_m_ext : OUT AHB_Mst_In_Type; - ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) - - ); -END; - -ARCHITECTURE Behavioral OF leon3_soc IS - - ----------------------------------------------------------------------------- - -- CONFIG ------------------------------------------------------------------- - ----------------------------------------------------------------------------- - - -- Clock generator - constant CFG_CLKMUL : integer := (1); - constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz - constant CFG_OCLKDIV : integer := (1); - constant CFG_CLK_NOFB : integer := 0; - -- LEON3 processor core - constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := NB_CPU; - constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC - constant CFG_V8 : integer := 0; - constant CFG_MAC : integer := 0; - constant CFG_SVT : integer := 0; - constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (1); - constant CFG_NWP : integer := (0); - constant CFG_PWD : integer := 1*2; - constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); - -- 1*(8 + 16 * 0) => grfpu-light - -- 1*(8 + 16 * 1) => netlist - -- 0*(8 + 16 * 0) => No FPU - -- 0*(8 + 16 * 1) => No FPU; - constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 0; - constant CFG_ILOCK : integer := 0; - constant CFG_ILRAMEN : integer := 0; - constant CFG_ILRAMADDR: integer := 16#8E#; - constant CFG_ILRAMSZ : integer := 1; - constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; - constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 0; - constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; - constant CFG_DLRAMEN : integer := 0; - constant CFG_DLRAMADDR: integer := 16#8F#; - constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; - - constant CFG_DSU : integer := ENABLE_DSU; - constant CFG_ITBSZ : integer := 0; - constant CFG_ATBSZ : integer := 0; - - -- AMBA settings - constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 1; - constant CFG_SPLIT : integer := 0; - constant CFG_AHBIO : integer := 16#FFF#; - constant CFG_APBADDR : integer := 16#800#; - - -- DSU UART - constant CFG_AHB_UART : integer := ENABLE_AHB_UART; - - -- LEON2 memory controller - constant CFG_MCTRL_SDEN : integer := 0; - - -- UART 1 - constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; - constant CFG_UART1_FIFO : integer := 1; - - -- LEON3 interrupt controller - constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; - - -- Modular timer - constant CFG_GPT_ENABLE : integer := ENABLE_GPT; - constant CFG_GPT_NTIM : integer := (2); - constant CFG_GPT_SW : integer := (8); - constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- SIGNALs - ----------------------------------------------------------------------------- - CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; - -- CLK & RST -- - SIGNAL clk2x : STD_ULOGIC; - SIGNAL clkmn : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - --- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - --UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; - --MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - --IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); - --Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; - --DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ----------------------------------------------------------------------------- -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) - PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3s -- LEON3 processor - GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, - 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) - PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i)); - END GENERATE; - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; - dsuo.tstop <= '0'; - dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => 0, nahbm => maxahbmsp, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) - PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- AMBA BUS ------------------------------------------------------------------- -------------------------------------------------------------------------------- - - -- APB -------------------------------------------------------------------- - apbi_ext <= apbi; - all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE - max_16_apb: IF I + 5 < 16 GENERATE - apbo(I+5)<= apbo_ext(I+5); - END GENERATE max_16_apb; - END GENERATE all_apb; - -- AHB_Slave -------------------------------------------------------------- - ahbi_s_ext <= ahbsi; - all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE - max_16_ahbs: IF I + 3 < 16 GENERATE - ahbso(I+3) <= ahbo_s_ext(I+3); - END GENERATE max_16_ahbs; - END GENERATE all_ahbs; - -- AHB_Master ------------------------------------------------------------- - ahbi_m_ext <= ahbmi; - all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE - max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE - ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); - END GENERATE max_16_ahbm; - END GENERATE all_ahbm; - - - -END Behavioral; +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY leon3_soc IS + GENERIC ( + fabtech : INTEGER := apa3e; + memtech : INTEGER := apa3e; + padtech : INTEGER := inferred; + clktech : INTEGER := inferred; + disas : INTEGER := 0; -- Enable disassembly to console + dbguart : INTEGER := 0; -- Print UART on console + pclow : INTEGER := 2; + -- + clk_freq : INTEGER := 25000; --kHz + -- + NB_CPU : INTEGER := 1; + ENABLE_FPU : INTEGER := 1; + FPU_NETLIST : INTEGER := 1; + ENABLE_DSU : INTEGER := 1; + ENABLE_AHB_UART : INTEGER := 1; + ENABLE_APB_UART : INTEGER := 1; + ENABLE_IRQMP : INTEGER := 1; + ENABLE_GPT : INTEGER := 1; + -- + NB_AHB_MASTER : INTEGER := 0; + NB_AHB_SLAVE : INTEGER := 0; + NB_APB_SLAVE : INTEGER := 0 + ); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- APB -------------------------------------------------------------------- + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) + + ); +END; + +ARCHITECTURE Behavioral OF leon3_soc IS + + ----------------------------------------------------------------------------- + -- CONFIG ------------------------------------------------------------------- + ----------------------------------------------------------------------------- + + -- Clock generator + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_CLK_NOFB : integer := 0; + -- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := NB_CPU; + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); + -- 1*(8 + 16 * 0) => grfpu-light + -- 1*(8 + 16 * 1) => netlist + -- 0*(8 + 16 * 0) => No FPU + -- 0*(8 + 16 * 1) => No FPU; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + + constant CFG_DSU : integer := ENABLE_DSU; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + + -- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + + -- DSU UART + constant CFG_AHB_UART : integer := ENABLE_AHB_UART; + + -- LEON2 memory controller + constant CFG_MCTRL_SDEN : integer := 0; + + -- UART 1 + constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; + constant CFG_UART1_FIFO : integer := 1; + + -- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; + + -- Modular timer + constant CFG_GPT_ENABLE : integer := ENABLE_GPT; + constant CFG_GPT_NTIM : integer := (2); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- SIGNALs + ----------------------------------------------------------------------------- + CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; + -- CLK & RST -- + SIGNAL clk2x : STD_ULOGIC; + SIGNAL clkmn : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; + --- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + --UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + --IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); + --Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; + --DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + ----------------------------------------------------------------------------- + + SIGNAL nSRAM_CE_s : STD_LOGIC; +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + cgi.pllctrl <= "00"; + cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) + PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; + dsuo.tstop <= '0'; + dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + nSRAM_CE_s <= NOT(memo.ramsn(0)); + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => 0, nahbm => maxahbmsp, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- AMBA BUS ------------------------------------------------------------------- +------------------------------------------------------------------------------- + + -- APB -------------------------------------------------------------------- + apbi_ext <= apbi; + all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE + max_16_apb: IF I + 5 < 16 GENERATE + apbo(I+5)<= apbo_ext(I+5); + END GENERATE max_16_apb; + END GENERATE all_apb; + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext <= ahbsi; + all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE + max_16_ahbs: IF I + 3 < 16 GENERATE + ahbso(I+3) <= ahbo_s_ext(I+3); + END GENERATE max_16_ahbs; + END GENERATE all_ahbs; + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext <= ahbmi; + all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE + max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE + ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); + END GENERATE max_16_ahbm; + END GENERATE all_ahbm; + + + +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -59,47 +59,47 @@ ENTITY lpp_lfr IS coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- - data_shaping_BW : OUT STD_LOGIC; + data_shaping_BW : OUT STD_LOGIC--; --debug - debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f0_data_valid : OUT STD_LOGIC; - debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f1_data_valid : OUT STD_LOGIC; - debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f2_data_valid : OUT STD_LOGIC; - debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC; + --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + --debug_f0_data_valid : OUT STD_LOGIC; + --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + --debug_f1_data_valid : OUT STD_LOGIC; + --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + --debug_f2_data_valid : OUT STD_LOGIC; + --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + --debug_f3_data_valid : OUT STD_LOGIC; - -- debug FIFO_IN - debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_fifo_in_valid : OUT STD_LOGIC; + ---- debug FIFO_IN + --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; + --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; - --debug FIFO OUT - debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_fifo_out_valid : OUT STD_LOGIC; - debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_fifo_out_valid : OUT STD_LOGIC; - debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_fifo_out_valid : OUT STD_LOGIC; - debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_fifo_out_valid : OUT STD_LOGIC; + ----debug FIFO OUT + --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; + --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; + --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; + --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; - --debug DMA IN - debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_dma_in_valid : OUT STD_LOGIC; - debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_dma_in_valid : OUT STD_LOGIC; - debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_dma_in_valid : OUT STD_LOGIC; - debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_dma_in_valid : OUT STD_LOGIC + ----debug DMA IN + --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f0_data_dma_in_valid : OUT STD_LOGIC; + --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f1_data_dma_in_valid : OUT STD_LOGIC; + --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f2_data_dma_in_valid : OUT STD_LOGIC; + --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --debug_f3_data_dma_in_valid : OUT STD_LOGIC ); END lpp_lfr; @@ -226,10 +226,14 @@ ARCHITECTURE beh OF lpp_lfr IS ----------------------------------------------------------------------------- -- DMA RR ----------------------------------------------------------------------------- - SIGNAL dma_sel_valid : STD_LOGIC; - SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_sel_valid : STD_LOGIC; + SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); ----------------------------------------------------------------------------- -- DMA_REG @@ -270,6 +274,17 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- MS + ----------------------------------------------------------------------------- + + SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_ms_valid : STD_LOGIC; + SIGNAL data_ms_valid_burst : STD_LOGIC; + SIGNAL data_ms_ren : STD_LOGIC; + SIGNAL data_ms_done : STD_LOGIC; BEGIN @@ -472,41 +487,41 @@ BEGIN data_f3_data_out => data_f3_data_out, data_f3_data_out_valid => data_f3_data_out_valid_s, data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, - data_f3_data_out_ren => data_f3_data_out_ren, + data_f3_data_out_ren => data_f3_data_out_ren --, - -- debug SNAPSHOT_OUT - debug_f0_data => debug_f0_data, - debug_f0_data_valid => debug_f0_data_valid , - debug_f1_data => debug_f1_data , - debug_f1_data_valid => debug_f1_data_valid, - debug_f2_data => debug_f2_data , - debug_f2_data_valid => debug_f2_data_valid , - debug_f3_data => debug_f3_data , - debug_f3_data_valid => debug_f3_data_valid, + ---- debug SNAPSHOT_OUT + --debug_f0_data => debug_f0_data, + --debug_f0_data_valid => debug_f0_data_valid , + --debug_f1_data => debug_f1_data , + --debug_f1_data_valid => debug_f1_data_valid, + --debug_f2_data => debug_f2_data , + --debug_f2_data_valid => debug_f2_data_valid , + --debug_f3_data => debug_f3_data , + --debug_f3_data_valid => debug_f3_data_valid, - -- debug FIFO_IN - debug_f0_data_fifo_in => debug_f0_data_fifo_in , - debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, - debug_f1_data_fifo_in => debug_f1_data_fifo_in , - debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, - debug_f2_data_fifo_in => debug_f2_data_fifo_in , - debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, - debug_f3_data_fifo_in => debug_f3_data_fifo_in , - debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid + ---- debug FIFO_IN + --debug_f0_data_fifo_in => debug_f0_data_fifo_in , + --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, + --debug_f1_data_fifo_in => debug_f1_data_fifo_in , + --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, + --debug_f2_data_fifo_in => debug_f2_data_fifo_in , + --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, + --debug_f3_data_fifo_in => debug_f3_data_fifo_in , + --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid ); ----------------------------------------------------------------------------- -- DEBUG -- WFP OUT - debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; - debug_f0_data_fifo_out <= data_f0_data_out; - debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; - debug_f1_data_fifo_out <= data_f1_data_out; - debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; - debug_f2_data_fifo_out <= data_f2_data_out; - debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; - debug_f3_data_fifo_out <= data_f3_data_out; + --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; + --debug_f0_data_fifo_out <= data_f0_data_out; + --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; + --debug_f1_data_fifo_out <= data_f1_data_out; + --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; + --debug_f2_data_fifo_out <= data_f2_data_out; + --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; + --debug_f3_data_fifo_out <= data_f3_data_out; ----------------------------------------------------------------------------- @@ -556,8 +571,22 @@ BEGIN clk => clk, rstn => rstn, in_valid => dma_rr_valid, - out_grant => dma_rr_grant); + out_grant => dma_rr_grant_s); + dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; + dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; + dma_rr_valid_ms(2) <= '0'; + dma_rr_valid_ms(3) <= '0'; + + RR_Arbiter_4_2 : RR_Arbiter_4 + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => dma_rr_valid_ms, + out_grant => dma_rr_grant_ms); + + dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; + ----------------------------------------------------------------------------- -- in : dma_rr_grant @@ -574,8 +603,7 @@ BEGIN dma_valid_burst <= '0'; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge IF run = '1' THEN --- IF dma_sel = "0000" OR dma_send = '1' THEN - IF dma_sel = "0000" OR dma_done = '1' THEN + IF dma_sel = "00000" OR dma_done = '1' THEN dma_sel <= dma_rr_grant; IF dma_rr_grant(0) = '1' THEN dma_send <= '1'; @@ -593,6 +621,14 @@ BEGIN dma_send <= '1'; dma_valid_burst <= data_f3_data_out_valid_burst; dma_sel_valid <= data_f3_data_out_valid; + ELSIF dma_rr_grant(4) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_ms_valid_burst; + dma_sel_valid <= data_ms_valid; + END IF; + + IF dma_sel(4) = '1' THEN + data_ms_done <= '1'; END IF; ELSE dma_sel <= dma_sel; @@ -610,17 +646,20 @@ BEGIN dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE data_f1_addr_out WHEN dma_sel(1) = '1' ELSE data_f2_addr_out WHEN dma_sel(2) = '1' ELSE - data_f3_addr_out; + data_f3_addr_out WHEN dma_sel(3) = '1' ELSE + data_ms_addr; dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE data_f1_data_out WHEN dma_sel(1) = '1' ELSE data_f2_data_out WHEN dma_sel(2) = '1' ELSE - data_f3_data_out; + data_f3_data_out WHEN dma_sel(3) = '1' ELSE + data_ms_data; data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; + data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; dma_data_2 <= dma_data; @@ -630,14 +669,14 @@ BEGIN ----------------------------------------------------------------------------- -- DEBUG -- DMA IN - debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; - debug_f0_data_dma_in <= dma_data; - debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; - debug_f1_data_dma_in <= dma_data; - debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; - debug_f2_data_dma_in <= dma_data; - debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; - debug_f3_data_dma_in <= dma_data; + --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; + --debug_f0_data_dma_in <= dma_data; + --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; + --debug_f1_data_dma_in <= dma_data; + --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; + --debug_f2_data_dma_in <= dma_data; + --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; + --debug_f3_data_dma_in <= dma_data; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- @@ -662,53 +701,58 @@ BEGIN data => dma_data_2); ----------------------------------------------------------------------------- - -- Matrix Spectral - TODO - ----------------------------------------------------------------------------- + -- Matrix Spectral ----------------------------------------------------------------------------- - --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & - -- NOT(sample_f0_val) & NOT(sample_f0_val) ; - --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & - -- NOT(sample_f1_val) & NOT(sample_f1_val) ; - --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & - -- NOT(sample_f3_val) & NOT(sample_f3_val) ; + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & + NOT(sample_f0_val) & NOT(sample_f0_val) ; + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & + NOT(sample_f1_val) & NOT(sample_f1_val) ; + sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & + NOT(sample_f3_val) & NOT(sample_f3_val) ; - --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) - --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); - --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); + sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) + sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); + sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); ------------------------------------------------------------------------------- - --lpp_lfr_ms_1: lpp_lfr_ms - -- GENERIC MAP ( - -- hindex => hindex_ms) - -- PORT MAP ( - -- clk => clk, - -- rstn => rstn, - -- sample_f0_wen => sample_f0_wen, - -- sample_f0_wdata => sample_f0_wdata, - -- sample_f1_wen => sample_f1_wen, - -- sample_f1_wdata => sample_f1_wdata, - -- sample_f3_wen => sample_f3_wen, - -- sample_f3_wdata => sample_f3_wdata, - -- AHB_Master_In => ahbi_ms, - -- AHB_Master_Out => ahbo_ms, + lpp_lfr_ms_1: lpp_lfr_ms + GENERIC MAP ( + Mem_use => Mem_use ) + PORT MAP ( + clk => clk, + rstn => rstn, + + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, - -- ready_matrix_f0_0 => ready_matrix_f0_0, - -- ready_matrix_f0_1 => ready_matrix_f0_1, - -- ready_matrix_f1 => ready_matrix_f1, - -- ready_matrix_f2 => ready_matrix_f2, - -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, - -- error_bad_component_error => error_bad_component_error, - -- debug_reg => debug_reg, - -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - -- status_ready_matrix_f1 => status_ready_matrix_f1, - -- status_ready_matrix_f2 => status_ready_matrix_f2, - -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - -- status_error_bad_component_error => status_error_bad_component_error, - -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - -- config_active_interruption_onError => config_active_interruption_onError, - -- addr_matrix_f0_0 => addr_matrix_f0_0, - -- addr_matrix_f0_1 => addr_matrix_f0_1, - -- addr_matrix_f1 => addr_matrix_f1, - -- addr_matrix_f2 => addr_matrix_f2); + dma_addr => data_ms_addr, -- + dma_data => data_ms_data, -- + dma_valid => data_ms_valid, -- + dma_valid_burst => data_ms_valid_burst, -- + dma_ren => data_ms_ren, -- + dma_done => data_ms_done, -- + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -17,6 +17,7 @@ USE lpp.lpp_demux.ALL; USE lpp.lpp_top_lfr_pkg.ALL; USE lpp.lpp_dma_pkg.ALL; USE lpp.lpp_Header.ALL; +USE lpp.lpp_lfr_pkg.ALL; LIBRARY grlib; USE grlib.amba.ALL; @@ -27,7 +28,7 @@ USE GRLIB.DMA2AHB_Package.ALL; ENTITY lpp_lfr_ms IS GENERIC ( - hindex : INTEGER := 2 + Mem_use : INTEGER ); PORT ( clk : IN STD_LOGIC; @@ -49,10 +50,12 @@ ENTITY lpp_lfr_ms IS --------------------------------------------------------------------------- -- DMA --------------------------------------------------------------------------- - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; -- Reg out ready_matrix_f0_0 : OUT STD_LOGIC; @@ -108,7 +111,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS ----------------------------------------------------------------------------- SIGNAL SM_FlagError : STD_LOGIC; - SIGNAL SM_Pong : STD_LOGIC; +-- SIGNAL SM_Pong : STD_LOGIC; SIGNAL SM_Wen : STD_LOGIC; SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); @@ -138,10 +141,10 @@ BEGIN ----------------------------------------------------------------------------- Memf0: lppFIFOxN GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, + tech => 0, Mem_use => Mem_use, Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, + rstn => rstn, wclk => clk, rclk => clk, ReUse => (OTHERS => '0'), wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), wdata => sample_f0_wdata, rdata => FifoF0_Data, @@ -149,10 +152,10 @@ BEGIN Memf1: lppFIFOxN GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, + tech => 0, Mem_use => Mem_use, Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, + rstn => rstn, wclk => clk, rclk => clk, ReUse => (OTHERS => '0'), wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), wdata => sample_f1_wdata, rdata => FifoF1_Data, @@ -161,10 +164,10 @@ BEGIN Memf2: lppFIFOxN GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, + tech => 0, Mem_use => Mem_use, Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, + rstn => rstn, wclk => clk, rclk => clk, ReUse => (OTHERS => '0'), wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), wdata => sample_f3_wdata, rdata => FifoF3_Data, @@ -217,13 +220,13 @@ BEGIN MemInt : lppFIFOxN GENERIC MAP ( tech => 0, - Mem_use => use_RAM, + Mem_use => Mem_use, Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') PORT MAP ( - rst => rstn, + rstn => rstn, wclk => clk, rclk => clk, ReUse => SM_ReUse, @@ -247,10 +250,10 @@ BEGIN SetReUse => FFT_ReUse, Valid => Head_Valid, Data_IN => FifoINT_Data, - ACQ => DMA_ack, + ACK => DMA_ack, SM_Write => SM_Wen, FlagError => SM_FlagError, - Pong => SM_Pong, +-- Pong => SM_Pong, Statu => SM_Param, Write => SM_Write, Read => SM_Read, @@ -262,13 +265,13 @@ BEGIN MemOut : lppFIFOxN GENERIC MAP ( tech => 0, - Mem_use => use_RAM, + Mem_use => Mem_use, Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') PORT MAP ( - rst => rstn, + rstn => rstn, wclk => clk, rclk => clk, ReUse => (OTHERS => '0'), @@ -287,7 +290,7 @@ BEGIN PORT MAP ( clkm => clk, rstn => rstn, - pong => SM_Pong, +-- pong => SM_Pong, Statu => SM_Param, Matrix_Type => DMUX_WorkFreq, Matrix_Write => SM_Wen, @@ -299,28 +302,30 @@ BEGIN emptyOUT => Head_Empty, RenIN => DMA_Read, header => Head_Header, - header_val => Head_Val, + header_val => Head_Val, header_ack => DMA_ack ); ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - lpp_dma_ip_1: lpp_dma_ip - GENERIC MAP ( - tech => 0, - hindex => hindex) + + lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma PORT MAP ( HCLK => clk, HRESETn => rstn, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, fifo_data => Head_Data, fifo_empty => Head_Empty, fifo_ren => DMA_Read, - header => Head_Header, - header_val => Head_Val, - header_ack => DMA_ack, + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack, + + dma_addr => dma_addr, + dma_data => dma_data, + dma_valid => dma_valid, + dma_valid_burst => dma_valid_burst, + dma_ren => dma_ren, + dma_done => dma_done, ready_matrix_f0_0 => ready_matrix_f0_0, ready_matrix_f0_1 => ready_matrix_f0_1, @@ -341,6 +346,48 @@ BEGIN addr_matrix_f0_1 => addr_matrix_f0_1, addr_matrix_f1 => addr_matrix_f1, addr_matrix_f2 => addr_matrix_f2); - ----------------------------------------------------------------------------- + + -END Behavioral; \ No newline at end of file + + ----------------------------------------------------------------------------- + --lpp_dma_ip_1: lpp_dma_ip + -- GENERIC MAP ( + -- tech => 0, + -- hindex => hindex) + -- PORT MAP ( + -- HCLK => clk, + -- HRESETn => rstn, + -- AHB_Master_In => AHB_Master_In, + -- AHB_Master_Out => AHB_Master_Out, + + -- fifo_data => Head_Data, + -- fifo_empty => Head_Empty, + -- fifo_ren => DMA_Read, + + -- header => Head_Header, + -- header_val => Head_Val, + -- header_ack => DMA_ack, + + -- ready_matrix_f0_0 => ready_matrix_f0_0, + -- ready_matrix_f0_1 => ready_matrix_f0_1, + -- ready_matrix_f1 => ready_matrix_f1, + -- ready_matrix_f2 => ready_matrix_f2, + -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, + -- error_bad_component_error => error_bad_component_error, + -- debug_reg => debug_reg, + -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + -- status_ready_matrix_f1 => status_ready_matrix_f1, + -- status_ready_matrix_f2 => status_ready_matrix_f2, + -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + -- status_error_bad_component_error => status_error_bad_component_error, + -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + -- config_active_interruption_onError => config_active_interruption_onError, + -- addr_matrix_f0_0 => addr_matrix_f0_0, + -- addr_matrix_f0_1 => addr_matrix_f0_1, + -- addr_matrix_f1 => addr_matrix_f1, + -- addr_matrix_f2 => addr_matrix_f2); + ------------------------------------------------------------------------------- + +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -16,7 +16,8 @@ PACKAGE lpp_lfr_pkg IS COMPONENT lpp_lfr_ms GENERIC ( - hindex : INTEGER); + Mem_use : INTEGER + ); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -26,8 +27,14 @@ PACKAGE lpp_lfr_pkg IS sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; + + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + ready_matrix_f0_0 : OUT STD_LOGIC; ready_matrix_f0_1 : OUT STD_LOGIC; ready_matrix_f1 : OUT STD_LOGIC; @@ -49,6 +56,44 @@ PACKAGE lpp_lfr_pkg IS addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; + COMPONENT lpp_lfr_ms_fsmdma + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fifo_empty : IN STD_LOGIC; + fifo_ren : OUT STD_LOGIC; + header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + header_val : IN STD_LOGIC; + header_ack : OUT STD_LOGIC; + dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dma_valid : OUT STD_LOGIC; + dma_valid_burst : OUT STD_LOGIC; + dma_ren : IN STD_LOGIC; + dma_done : IN STD_LOGIC; + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : IN STD_LOGIC; + status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + status_error_anticipating_empty_fifo : IN STD_LOGIC; + status_error_bad_component_error : IN STD_LOGIC; + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_filter GENERIC ( Mem_use : INTEGER); @@ -99,47 +144,7 @@ PACKAGE lpp_lfr_pkg IS ahbo : OUT AHB_Mst_Out_Type; coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data_shaping_BW : OUT STD_LOGIC; - - --debug - debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f0_data_valid : OUT STD_LOGIC; - debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f1_data_valid : OUT STD_LOGIC; - debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f2_data_valid : OUT STD_LOGIC; - debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - debug_f3_data_valid : OUT STD_LOGIC; - - -- debug FIFO_IN - debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_fifo_in_valid : OUT STD_LOGIC; - - --debug FIFO OUT - debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_fifo_out_valid : OUT STD_LOGIC; - debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_fifo_out_valid : OUT STD_LOGIC; - debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_fifo_out_valid : OUT STD_LOGIC; - debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_fifo_out_valid : OUT STD_LOGIC; - - --debug DMA IN - debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f0_data_dma_in_valid : OUT STD_LOGIC; - debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f1_data_dma_in_valid : OUT STD_LOGIC; - debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f2_data_dma_in_valid : OUT STD_LOGIC; - debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - debug_f3_data_dma_in_valid : OUT STD_LOGIC + data_shaping_BW : OUT STD_LOGIC ); END COMPONENT; diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -2,5 +2,6 @@ lpp_top_lfr_pkg.vhd lpp_lfr_pkg.vhd lpp_lfr_filter.vhd lpp_lfr_apbreg.vhd +lpp_lfr_ms_fsmdma.vhd lpp_lfr_ms.vhd lpp_lfr.vhd