diff --git a/boards/MiniSpartan6p/Makefile.inc b/boards/MiniSpartan6p/Makefile.inc new file mode 100644 --- /dev/null +++ b/boards/MiniSpartan6p/Makefile.inc @@ -0,0 +1,11 @@ +TECHNOLOGY=Spartan6 +ISETECH="Spartan6" +PACKAGE=ftg256 +PART=XC6SLX25 +SPEED=-3 +SYNFREQ=25 + +MANUFACTURER=Xilinx +MGCPART=XC6SLX25$(PACKAGE) +MGCTECHNOLOGY=SPARTAN-6 +MGCPACKAGE=$(PACKAGE) diff --git a/boards/MiniSpartan6p/default.ucf b/boards/MiniSpartan6p/default.ucf new file mode 100644 --- /dev/null +++ b/boards/MiniSpartan6p/default.ucf @@ -0,0 +1,64 @@ +# Clocks +NET "CLK50" PERIOD = 20 ns | LOC = "K3"; +#NET "CLK32" PERIOD = 31.25 ns | LOC = "J4"; + +# LEDs +NET "LEDS<0>" LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<1>" LOC="N9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<2>" LOC="M9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<3>" LOC="P9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<4>" LOC="T8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<5>" LOC="N8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<6>" LOC="P8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<7>" LOC="P7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; + +# DIP Switches +NET "SW<1>" LOC="L1" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<2>" LOC="L3" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<3>" LOC="L4" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<4>" LOC="L5" | IOSTANDARD=LVTTL | PULLUP; + +NET "uart_rxd" LOC="M7" | IOSTANDARD=LVTTL; +NET "uart_txd" LOC="N6" | IOSTANDARD=LVTTL; + +# SDRAM +NET "dram_udqm" LOC="F15" | IOSTANDARD=LVTTL; +NET "dram_clk" LOC="G16" | IOSTANDARD=LVTTL; +NET "dram_cke" LOC="H16" | IOSTANDARD=LVTTL; +NET "dram_ba_1" LOC="T14" | IOSTANDARD=LVTTL; +NET "dram_ba_0" LOC="R14" | IOSTANDARD=LVTTL; +NET "dram_cs_n" LOC="R1" | IOSTANDARD=LVTTL; +NET "dram_ras_n" LOC="R2" | IOSTANDARD=LVTTL; +NET "dram_cas_n" LOC="T4" | IOSTANDARD=LVTTL; +NET "dram_we_n" LOC="R5" | IOSTANDARD=LVTTL; +NET "dram_ldqm" LOC="T5" | IOSTANDARD=LVTTL; +NET "dram_addr<0>" LOC="T15" | IOSTANDARD=LVTTL; +NET "dram_addr<1>" LOC="R16" | IOSTANDARD=LVTTL; +NET "dram_addr<2>" LOC="P15" | IOSTANDARD=LVTTL; +NET "dram_addr<3>" LOC="P16" | IOSTANDARD=LVTTL; +NET "dram_addr<4>" LOC="N16" | IOSTANDARD=LVTTL; +NET "dram_addr<5>" LOC="M15" | IOSTANDARD=LVTTL; +NET "dram_addr<6>" LOC="M16" | IOSTANDARD=LVTTL; +NET "dram_addr<7>" LOC="L16" | IOSTANDARD=LVTTL; +NET "dram_addr<8>" LOC="K15" | IOSTANDARD=LVTTL; +NET "dram_addr<9>" LOC="K16" | IOSTANDARD=LVTTL; +NET "dram_addr<10>" LOC="R15" | IOSTANDARD=LVTTL; +NET "dram_addr<11>" LOC="J16" | IOSTANDARD=LVTTL; +NET "dram_addr<12>" LOC="H15" | IOSTANDARD=LVTTL; +NET "dram_dq<0>" LOC="T13" | IOSTANDARD=LVTTL; +NET "dram_dq<1>" LOC="T12" | IOSTANDARD=LVTTL; +NET "dram_dq<2>" LOC="R12" | IOSTANDARD=LVTTL; +NET "dram_dq<3>" LOC="T9" | IOSTANDARD=LVTTL; +NET "dram_dq<4>" LOC="R9" | IOSTANDARD=LVTTL; +NET "dram_dq<5>" LOC="T7" | IOSTANDARD=LVTTL; +NET "dram_dq<6>" LOC="R7" | IOSTANDARD=LVTTL; +NET "dram_dq<7>" LOC="T6" | IOSTANDARD=LVTTL; +NET "dram_dq<8>" LOC="F16" | IOSTANDARD=LVTTL; +NET "dram_dq<9>" LOC="E15" | IOSTANDARD=LVTTL; +NET "dram_dq<10>" LOC="E16" | IOSTANDARD=LVTTL; +NET "dram_dq<11>" LOC="D16" | IOSTANDARD=LVTTL; +NET "dram_dq<12>" LOC="B16" | IOSTANDARD=LVTTL; +NET "dram_dq<13>" LOC="B15" | IOSTANDARD=LVTTL; +NET "dram_dq<14>" LOC="C16" | IOSTANDARD=LVTTL; +NET "dram_dq<15>" LOC="C15" | IOSTANDARD=LVTTL; + diff --git a/boards/MiniSpartan6p/default.ut b/boards/MiniSpartan6p/default.ut new file mode 100644 --- /dev/null +++ b/boards/MiniSpartan6p/default.ut @@ -0,0 +1,24 @@ + +-g DebugBitstream:No +-g Binary:no +-b +-g CRC:Enable +-g ConfigRate:6 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g Persist:No +-g ReadBack +-g DonePipe:No +-g DriveDone:Yes diff --git a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd --- a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd +++ b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER.vhd @@ -35,15 +35,14 @@ use lpp.general_purpose.TimeGenAdvancedT entity APB_ADVANCED_TRIGGER is generic ( pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); + paddr : integer := 0 + ); port ( rstn : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; - + SPW_Tickout : IN STD_LOGIC; CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -59,7 +58,7 @@ constant REVISION : integer := 1; constant pconfig : apb_config_type := ( 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); + 1 => apb_iobar(paddr, 16#fff#)); @@ -116,19 +115,20 @@ adv_trig0: TimeGenAdvancedTrigger process(rstn,clk) begin if rstn = '0' then - r.CFG <= (others=>'0'); + r.CFG(31 DOWNTO 1) <= (others=>'0'); + r.CFG(0) <= '0'; r.Restart <= (others=>'0'); r.StartDate <= (others=>'0'); elsif clk'event and clk = '1' then --APB Write OP if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(3 downto 2) is - when "00" => + case apbi.paddr(8-1 downto 2) is + when "000000" => r.CFG <= apbi.pwdata; - when "01" => + when "000001" => r.Restart <= apbi.pwdata; - when "10" => + when "000010" => r.StartDate <= apbi.pwdata; when others => null; @@ -137,21 +137,23 @@ begin --APB READ OP if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(3 downto 2) is - when "00" => + case apbi.paddr(8-1 downto 2) is + when "000000" => Rdata <= r.CFG; - when "01" => + when "000001" => Rdata <= r.Restart; - when "10" => + when "000010" => Rdata <= r.StartDate; when others => Rdata <= r.Restart; end case; end if; - + end if; - apbo.pconfig <= pconfig; end process; +apbo.pconfig <= pconfig; apbo.prdata <= Rdata when apbi.penable = '1'; +apbo.pirq <= (OTHERS => '0'); +apbo.pindex <= pindex; end beh; diff --git a/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER_v.vhd b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER_v.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_amba/APB_ADVANCED_TRIGGER_v.vhd @@ -0,0 +1,168 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.apb_devices_list.all; +use lpp.lpp_amba.all; +use lpp.general_purpose.TimeGenAdvancedTrigger; + + +entity APB_ADVANCED_TRIGGER_v is + generic ( + pindex : integer; + paddr : integer; + count : integer range 1 to 16 := 1 + ); + port ( + rstn : in std_ulogic; + clk : in std_ulogic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + + SPW_Tickout : IN STD_LOGIC; + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + Trigger : OUT STD_LOGIC_VECTOR(count-1 DOWNTO 0) + ); +end; + + +architecture beh of APB_ADVANCED_TRIGGER_v is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER_v, 0, REVISION, 0), + 1 => apb_iobar(paddr, 16#fff#)); + + + +type adv_trig_type is record + TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15 + TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps + Restart : STD_LOGIC; + StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch + BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout +end record; + +type adv_trig_regs is record + CFG : STD_LOGIC_VECTOR(31 DOWNTO 0); + Restart : STD_LOGIC_VECTOR(31 DOWNTO 0); + StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); +end record; + +type adv_trig_regs_array is array(count-1 downto 0) of adv_trig_regs; +type adv_trig_type_array is array(count-1 downto 0) of adv_trig_type; + +signal r : adv_trig_regs_array; +signal adv_trig : adv_trig_type_array; +signal Rdata : std_logic_vector(31 downto 0); + + +begin + + +adv_trig_loop: FOR I IN 0 TO count-1 GENERATE + adv_trig_i: TimeGenAdvancedTrigger + PORT MAP( + clk => clk, + rstn => rstn, + + SPW_Tickout => SPW_Tickout, + + CoarseTime => CoarseTime, + FineTime => FineTime, + + TrigPeriod => adv_trig(i).TrigPeriod, + TrigShift => adv_trig(i).TrigShift, + Restart => adv_trig(i).Restart, + StartDate => adv_trig(i).StartDate, + + BypassTickout => adv_trig(i).BypassTickout, + Trigger => Trigger(i) + + ); + + adv_trig(i).BypassTickout <= r(i).CFG(0); + adv_trig(i).TrigPeriod <= r(i).CFG(7 downto 4); + adv_trig(i).TrigShift <= r(i).CFG(31 downto 16); + adv_trig(i).Restart <= r(i).Restart(0); + adv_trig(i).StartDate <= r(i).StartDate; +END GENERATE; + +process(rstn,clk) + Variable I : integer :=0; +begin + if rstn = '0' then + rst_loop: FOR I IN 0 TO count-1 LOOP + r(i).CFG(31 DOWNTO 1) <= (others=>'0'); + r(i).CFG(0) <= '0'; + r(i).Restart <= (others=>'0'); + r(i).StartDate <= (others=>'0'); + END LOOP; + elsif clk'event and clk = '1' then + I := to_integer(UNSIGNED(apbi.paddr(8-1 downto 4))); +--APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(3 downto 2) is + when "00" => + r(I).CFG <= apbi.pwdata; + when "01" => + r(I).Restart <= apbi.pwdata; + when "10" => + r(I).StartDate <= apbi.pwdata; + when others => + null; + end case; + end if; + +--APB READ OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(3 downto 2) is + when "00" => + Rdata <= r(I).CFG; + when "01" => + Rdata <= r(I).Restart; + when "10" => + Rdata <= r(I).StartDate; + when others => + Rdata <= std_logic_vector(to_unsigned(count,32)); + end case; + end if; + + end if; + +end process; +apbo.pconfig <= pconfig; +apbo.prdata <= Rdata when apbi.penable = '1'; +apbo.pirq <= (OTHERS => '0'); +apbo.pindex <= pindex; + +end beh; diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd --- a/lib/lpp/lpp_amba/apb_devices_list.vhd +++ b/lib/lpp/lpp_amba/apb_devices_list.vhd @@ -44,6 +44,7 @@ PACKAGE apb_devices_list IS CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; constant APB_ADC_READER : amba_device_type := 16#F1#; CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; - CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#; - + CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#; + CONSTANT LPP_APB_ADVANCED_TRIGGER_v : amba_device_type := 16#A4#; + END; diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd --- a/lib/lpp/lpp_amba/lpp_amba.vhd +++ b/lib/lpp/lpp_amba/lpp_amba.vhd @@ -32,9 +32,8 @@ package lpp_amba is component APB_ADVANCED_TRIGGER is generic ( pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); + paddr : integer := 0 + ); port ( rstn : in std_ulogic; clk : in std_ulogic; @@ -49,6 +48,26 @@ component APB_ADVANCED_TRIGGER is ); end component; +component APB_ADVANCED_TRIGGER_v is + generic ( + pindex : integer; + paddr : integer; + count : integer range 1 to 8 := 1 + ); + port ( + rstn : in std_ulogic; + clk : in std_ulogic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + + SPW_Tickout : IN STD_LOGIC; + CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + Trigger : OUT STD_LOGIC_VECTOR(count-1 DOWNTO 0) + ); +end component; + component APB_SIMPLE_DIODE is generic ( pindex : integer := 0; diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt --- a/lib/lpp/lpp_amba/vhdlsyn.txt +++ b/lib/lpp/lpp_amba/vhdlsyn.txt @@ -1,3 +1,4 @@ apb_devices_list.vhd lpp_amba.vhd APB_ADVANCED_TRIGGER.vhd +APB_ADVANCED_TRIGGER_v.vhd diff --git a/tests/Test_APB_ADVANCED_TRIGGER_v/Makefile b/tests/Test_APB_ADVANCED_TRIGGER_v/Makefile new file mode 100644 --- /dev/null +++ b/tests/Test_APB_ADVANCED_TRIGGER_v/Makefile @@ -0,0 +1,70 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=MiniSpartan6p +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=./default.ucf +UCF_PLANAHEAD=$(UCF) +QSF= +EFFORT=high +XSTOPT=-uc testbench.xcf +SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0" +VHDLSYNFILES= onboardTest.vhd +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = unisim + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi + +DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \ + grlfpc \ + ./dsp/lpp_fft_rtax \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_sim/CY7C1061DV33 \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft \ + ./lpp_leon3_soc \ + ./lpp_debug_lfr + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_ms_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd \ + lpp_lfr_ms.vhd \ + lpp_lfr_sim_pkg.vhd \ + mtie_maps.vhd \ + ftsrctrlc.vhd \ + ftsdctrl.vhd \ + ftsrctrl8.vhd \ + ftmctrl.vhd \ + ftsdctrl64.vhd \ + ftahbram.vhd \ + ftahbram2.vhd \ + sramft.vhd \ + nandfctrlx.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + + +test:ghdl-run + +flash: + xc3sprog -c ftdi -p0 testbench.bit diff --git a/tests/Test_APB_ADVANCED_TRIGGER_v/default.ucf b/tests/Test_APB_ADVANCED_TRIGGER_v/default.ucf new file mode 100644 --- /dev/null +++ b/tests/Test_APB_ADVANCED_TRIGGER_v/default.ucf @@ -0,0 +1,27 @@ +# Clocks +NET "CLK50" PERIOD = 20 ns | LOC = "K3"; +# LEDs +NET "LEDS<0>" LOC="P11" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<1>" LOC="N9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<2>" LOC="M9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<3>" LOC="P9" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<4>" LOC="T8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<5>" LOC="N8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<6>" LOC="P8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "LEDS<7>" LOC="P7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; + +# DIP Switches +NET "SW<1>" LOC="L1" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<2>" LOC="L3" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<3>" LOC="L4" | IOSTANDARD=LVTTL | PULLUP; +NET "SW<4>" LOC="L5" | IOSTANDARD=LVTTL | PULLUP; + +NET "uart_rxd" LOC="M7" | IOSTANDARD=LVTTL; +NET "uart_txd" LOC="N6" | IOSTANDARD=LVTTL; + + +NET "Trigger<0>" LOC="E7" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "Trigger<1>" LOC="C8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "Trigger<2>" LOC="D8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; +NET "Trigger<3>" LOC="E8" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; + diff --git a/tests/Test_APB_ADVANCED_TRIGGER_v/onboardTest.vhd b/tests/Test_APB_ADVANCED_TRIGGER_v/onboardTest.vhd new file mode 100644 --- /dev/null +++ b/tests/Test_APB_ADVANCED_TRIGGER_v/onboardTest.vhd @@ -0,0 +1,181 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; +use techmap.allclkgen.all; + +library gaisler; +use gaisler.uart.all; +use gaisler.misc.all; + +library grlib; +use grlib.stdlib.all; +use grlib.amba.all; +use grlib.devices.all; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY lpp; +USE lpp.general_purpose.ALL; +USE lpp.lpp_amba.all; +USE lpp.lpp_lfr_management.ALL; + +ENTITY testbench IS + port ( + CLK50 : in std_logic; + LEDS : inout std_logic_vector(7 downto 0); + SW : in std_logic_vector(4 downto 1); + Trigger : out STD_LOGIC_VECTOR(3 DOWNTO 0); + uart_txd : out std_logic; -- DSU tx data + uart_rxd : in std_logic -- DSU rx data + ); +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + SIGNAL clk_50 : STD_LOGIC := '0'; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + SIGNAL rst : STD_LOGIC; + SIGNAL resetn : STD_LOGIC; + SIGNAL rstraw : STD_LOGIC; + +--AMBA bus standard interface signals-- + signal apbi : apb_slv_in_type; + signal apbo : apb_slv_out_vector := (others => apb_none); + signal ahbsi : ahb_slv_in_type; + signal ahbso : ahb_slv_out_vector := (others => ahbs_none); + signal ahbmi : ahb_mst_in_type; + signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); + + + signal dui : uart_in_type; + signal duo : uart_out_type; + + SIGNAL SPW_Tickout : std_logic:='0'; + SIGNAL CoarseTime : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=>'0'); + SIGNAL FineTime : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0'); + SIGNAL SubFineTime : integer range 0 to 49999999:=0; + +BEGIN + + + clk_25:PROCESS(clk_50) + BEGIN + IF clk_50'EVENT AND clk_50 = '1' THEN + clk <= not clk; + END IF; + END PROCESS; + + resetn <= SW(1); + LEDS <= CoarseTime(7 downto 0); + + uart_txd <= duo.txd; + dui.rxd <= uart_rxd; + + clk_pad : clkpad generic map (tech => spartan6) port map (CLK50, clk_50); + + resetn_pad : inpad generic map (tech => spartan6) port map (resetn, rst); + rst0 : rstgen -- reset generator (reset is active LOW) + port map (rst, clk, '1', rstn, rstraw); +---------------------------------------------------------------------- +--- AHB CONTROLLER -------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => 0, split => 1, + rrobin => 1, ioaddr => 16#FFF#, + nahbm => 1, nahbs => 1) + + port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso); + + + dcom0: ahbuart -- Debug UART + generic map (hindex => 0, pindex => 0, paddr => 0) + port map (rstn, clk, dui, duo, apbi, apbo(0), ahbmi, ahbmo(0)); + +---------------------------------------------------------------------- +--- APB Bridge ------------------------------------------------------ +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 0, haddr => 16#800#) + port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo ); + + +spw_time:PROCESS(clk,rstn) +BEGIN +IF rstn = '0' THEN + SPW_Tickout <= '0'; + SubFineTime <= 0; +ELSIF clk'EVENT AND clk = '1' THEN + if SubFineTime = 24999999 then + SubFineTime <= 0; + SPW_Tickout <= '1'; + else + SPW_Tickout <= '0'; + SubFineTime <= SubFineTime + 1; + end if; +END IF; +END PROCESS; + + +---------------------------------------------------------------------- +--- APB_ADVANCED_TRIGGER_v -> Device Under Test --------------------- +---------------------------------------------------------------------- + +DUT: APB_ADVANCED_TRIGGER_v + generic map( + pindex => 1, + paddr => 1, + count => 4 + ) + port map( + rstn => rstn, + clk => clk, + apbi => apbi, + apbo => apbo(1), + + SPW_Tickout => SPW_Tickout, + CoarseTime => CoarseTime, + FineTime => FineTime, + + Trigger => Trigger + ); + +------------------------------------------------------------------------------- +-- APB_LFR_MANAGEMENT --------------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_management_1 : apb_lfr_management + GENERIC MAP ( + tech => spartan6, + pindex => 2, + paddr => 2, + pmask => 16#fff#, + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set + PORT MAP ( + clk25MHz => clk, + resetn_25MHz => rstn, + grspw_tick => SPW_Tickout, + apbi => apbi, + apbo => apbo(2), + HK_sample => (others=>'0'), + HK_val => '0', + HK_sel => open, + DAC_SDO => OPEN, + DAC_SCK => OPEN, + DAC_SYNC => OPEN, + DAC_CAL_EN => OPEN, + coarse_time => CoarseTime, + fine_time => FineTime, + LFR_soft_rstn => open + ); + + +END; diff --git a/tests/Test_APB_ADVANCED_TRIGGER_v/tb.vhd b/tests/Test_APB_ADVANCED_TRIGGER_v/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Test_APB_ADVANCED_TRIGGER_v/tb.vhd @@ -0,0 +1,235 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +library gaisler; +use gaisler.libdcom.all; +use gaisler.sim.all; +use gaisler.uart.all; + +library grlib; +use grlib.stdlib.all; +use grlib.amba.all; +use grlib.devices.all; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY lpp; +USE lpp.general_purpose.ALL; +USE lpp.lpp_amba.all; + +ENTITY testbench IS + +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + +--AMBA bus standard interface signals-- + signal apbi : apb_slv_in_type; + signal apbo : apb_slv_out_vector := (others => apb_none); + signal ahbsi : ahb_slv_in_type; + signal ahbso : ahb_slv_out_vector := (others => ahbs_none); + signal ahbmi : ahb_mst_in_type; + signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); + + + signal dui : uart_in_type; + signal duo : uart_out_type; + signal dsutx : STD_LOGIC; + signal dsurx : STD_LOGIC; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + constant lresp : boolean := false; + + SIGNAL SPW_Tickout : std_logic:='0'; + SIGNAL CoarseTime : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others=>'0'); + SIGNAL FineTime : STD_LOGIC_VECTOR(15 DOWNTO 0):=(others=>'0'); + SIGNAL Trigger : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rstn <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL end_of_simu = '1'; + WAIT UNTIL clk = '1'; + assert false report "end of test" severity note; + -- Wait forever; this will finish the simulation. + wait; + END PROCESS; + ----------------------------------------------------------------------------- + + clk_25M_gen:PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk <= NOT clk; + TSTAMP <= TSTAMP+20; + WAIT FOR 20 ns; + ELSE + assert false report "end of test" severity note; + WAIT; + END IF; + END PROCESS; + +----------------------------------------------------------------------------- +-- CoarseTime and FineTime +----------------------------------------------------------------------------- + +SpwFineTime:PROCESS +BEGIN + IF end_of_simu /= '1' THEN + IF SPW_Tickout = '1' then + FineTime <= (others=>'0'); + ELSE + FineTime <= std_logic_vector(UNSIGNED(FineTime) + 1); + END IF; + WAIT FOR 15 us; + ELSE + assert false report "end of test" severity note; + WAIT; + END IF; +END PROCESS; + +SpwCoarseTime:PROCESS +BEGIN + IF end_of_simu /= '1' THEN + wait until SPW_Tickout = '1'; + CoarseTime <= std_logic_vector(UNSIGNED(CoarseTime) + 1); + ELSE + assert false report "end of test" severity note; + WAIT; + END IF; +END PROCESS; + +SPWTickout:PROCESS +BEGIN + IF end_of_simu /= '1' THEN + wait for (1000 ms - 20 ns); + SPW_Tickout <= '1'; + wait for 20 ns; + SPW_Tickout <= '0'; + ELSE + assert false report "end of test" severity note; + WAIT; + END IF; +END PROCESS; + + + +---------------------------------------------------------------------- +--- AHB CONTROLLER -------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => 0, split => 1, + rrobin => 1, ioaddr => 16#FFF#, + nahbm => 1, nahbs => 1) + + port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso); + + + dcom0: ahbuart -- Debug UART + generic map (hindex => 0, pindex => 0, paddr => 0) + port map (rstn, clk, dui, duo, apbi, apbo(0), ahbmi, ahbmo(0)); + dsutx <= duo.txd; + dui.rxd <= dsurx; + +---------------------------------------------------------------------- +--- APB Bridge ------------------------------------------------------ +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 0, haddr => 16#800#) + port map (rstn, clk, ahbsi, ahbso(0), apbi, apbo ); + + +---------------------------------------------------------------------- +--- APB_ADVANCED_TRIGGER_v -> Device Under Test --------------------- +---------------------------------------------------------------------- + +DUT: APB_ADVANCED_TRIGGER_v + generic map( + pindex => 1, + paddr => 1, + count => 4 + ) + port map( + rstn => rstn, + clk => clk, + apbi => apbi, + apbo => apbo(1), + + SPW_Tickout => SPW_Tickout, + CoarseTime => CoarseTime, + FineTime => FineTime, + + Trigger => Trigger + ); + + + + dsucom : process + variable w32 : std_logic_vector(31 downto 0); + constant txp : time := 160 * 1 ns; + procedure writeReg(signal dsutx : out std_logic; address : integer; value : integer) is + begin + txc(dsutx, 16#c0#, txp); --control byte + txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress + txa(dsutx, (value / (256*256*256)) , (value / (256*256)), (value / (256)), value, txp); --write data + end; + + procedure readReg(signal dsurx : in std_logic; signal dsutx : out std_logic; address : integer; value: out std_logic_vector) is + + begin + txc(dsutx, 16#a0#, txp); --control byte + txa(dsutx, (address / (256*256*256)) , (address / (256*256)), (address / (256)), address, txp); --adress + rxi(dsurx, value, txp, lresp); --write data + end; + + procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is + variable c8 : std_logic_vector(7 downto 0); + begin + dsutx <= '1'; + wait for 5000 ns; + txc(dsutx, 16#55#, txp); + + writeReg(dsutx,16#8000100#,16#00#); + + end; + + begin + + dsucfg(dsutx, dsurx); + + wait for 1000 ms; + end_of_simu <= '1'; + wait; + end process; + + all_apbo : FOR I IN 0 TO 15 GENERATE + apbo_not_used : IF I /= 1 AND I /= 0 GENERATE + apbo(I) <= apb_none; + END GENERATE apbo_not_used; + END GENERATE all_apbo; + +END;