diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/FRAME_CLK.vhd +++ /dev/null @@ -1,87 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 09:21:03 10/19/2010 --- Design Name: --- Module Name: FRAME_CLK_GEN - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; - -entity FRAME_CLK_GEN is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - FRAME_CLK : out STD_LOGIC); -end FRAME_CLK_GEN; - -architecture Behavioral of FRAME_CLK_GEN is - -Constant Goal_FRAME_CLK_FREQ : integer := 20; - -Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; - -signal CPT : integer := 0; -signal FRAME_CLK_reg : std_logic :='0'; - -begin - -FRAME_CLK <= FRAME_CLK_reg; - -process(reset,clk) -begin - if reset = '0' then - CPT <= 0; - FRAME_CLK_reg <= '0'; - elsif clk'event and clk = '1' then - if CPT = FRAME_CLK_TRIG then - CPT <= 0; - FRAME_CLK_reg <= not FRAME_CLK_reg; - else - CPT <= CPT + 1; - end if; - end if; -end process; -end Behavioral; - - - - - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER b/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/GPL_HEADER +++ /dev/null @@ -1,18 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_CFG.vhd +++ /dev/null @@ -1,55 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.all; -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; - - - -package LCD_16x2_CFG is - - -constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01"; -constant FunctionSet : std_logic_vector(7 downto 0):= X"38"; -constant RetHome : std_logic_vector(7 downto 0):= X"02"; -constant SetEntryMode : std_logic_vector(7 downto 0):= X"06"; -constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C"; - -constant CursorON : std_logic_vector(7 downto 0):= X"0E"; -constant CursorOFF : std_logic_vector(7 downto 0):= X"0C"; - ---===========================================================| ---======L C D D R I V E R T I M I N G C O D E=====| ---===========================================================| - -constant Duration_4us : std_logic_vector(1 downto 0) := "00"; -constant Duration_100us : std_logic_vector(1 downto 0) := "01"; -constant Duration_4ms : std_logic_vector(1 downto 0) := "10"; -constant Duration_20ms : std_logic_vector(1 downto 0) := "11"; - - -end LCD_16x2_CFG; - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRIVER .vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRIVER .vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_DRIVER .vhd +++ /dev/null @@ -1,64 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:09:57 10/13/2010 --- Design Name: --- Module Name: LCD_2x16_DRIVER - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.all; -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; - - -entity LCD_16x2_DRIVER is - generic( - OSC_Freq_MHz : integer:=60 - ); - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - LCD_CTRL : out LCD_DRVR_CTRL_BUSS; - SYNCH : out LCD_DRVR_SYNCH_BUSS; - DRIVER_CMD : in LCD_DRVR_CMD_BUSS - ); -end LCD_16x2_DRIVER; - -architecture Behavioral of LCD_16x2_DRIVER is - -end Behavioral; - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_16x2_ENGINE.vhd +++ /dev/null @@ -1,228 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 08:32:21 10/19/2010 --- Design Name: --- Module Name: LCD_16x2_ENGINE - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; -use lpp.LCD_16x2_CFG.all; - - -entity LCD_16x2_ENGINE is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - DATA : in std_logic_vector(16*2*8-1 downto 0); - CMD : in std_logic_vector(10 downto 0); - Exec : in std_logic; - Ready : out std_logic; - LCD_CTRL : out LCD_DRVR_CTRL_BUSS - ); -end LCD_16x2_ENGINE; - -architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is - -constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome); - - - -signal SYNCH : LCD_DRVR_SYNCH_BUSS; -signal DRIVER_CMD : LCD_DRVR_CMD_BUSS; -signal FRAME_CLK : std_logic; - -signal FRAME_CLK_reg : std_logic; -signal RefreshFlag : std_logic; -signal CMD_Flag : std_logic; -signal Exec_Reg : std_logic; - -type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1); -signal state : state_t; -signal i : integer range 0 to 32 := 0; - - - -begin - -Driver0 : LCD_16x2_DRIVER - generic map(OSC_freqKHz) - Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD); - -FRAME_CLK_GEN0 : FRAME_CLK_GEN - generic map(OSC_freqKHz) - Port map( clk,reset,FRAME_CLK); - - - -process(reset,clk) -begin - if reset = '0' then - state <= INIT0; - Ready <= '0'; - RefreshFlag <= '0'; - i <= 0; - elsif clk'event and clk ='1' then - FRAME_CLK_reg <= FRAME_CLK; - Exec_Reg <= Exec; - - if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then - RefreshFlag <= '1'; - elsif state = Refresh or state = Refresh0 or state = Refresh1 then - RefreshFlag <= '0'; - end if; - - if Exec_Reg = '0' and Exec = '1' then - CMD_Flag <= '1'; - elsif state = ExecCMD0 or state = ExecCMD1 then - CMD_Flag <= '0'; - end if; - - case state is - when INIT0 => - if SYNCH.DRVR_READY = '1' then - DRIVER_CMD.Exec <= '1'; - DRIVER_CMD.Duration <= Duration_20ms; - DRIVER_CMD.CMD_Data <= '0'; - DRIVER_CMD.Word <= ConfigTbl(i); - i <= i + 1; - state <= INIT1; - else - DRIVER_CMD.Exec <= '0'; - end if; - when INIT1 => - state <= INIT2; - DRIVER_CMD.Exec <= '0'; - when INIT2 => - if SYNCH.DRVR_READY = '1' then - if i = 5 then - state <= Idle; - else - state <= INIT0; - end if; - end if; - when Idle=> - DRIVER_CMD.Exec <= '0'; - if RefreshFlag = '1' then - Ready <= '0'; - state <= Refresh; - elsif CMD_Flag = '1' then - Ready <= '0'; - state <= ExecCMD0; - else - Ready <= '1'; - end if; - i <= 0; - when Refresh=> - if SYNCH.DRVR_READY = '1' then - DRIVER_CMD.Exec <= '1'; - DRIVER_CMD.Duration <= Duration_100us; - DRIVER_CMD.CMD_Data <= '1'; - DRIVER_CMD.Word <= DATA(i*8+7 downto i*8); - i <= i + 1; - state <= Refresh0; - else - DRIVER_CMD.Exec <= '0'; - end if; - when Refresh0=> - state <= Refresh1; - DRIVER_CMD.Exec <= '0'; - when Refresh1=> - if SYNCH.DRVR_READY = '1' then - if i = 32 then - state <= ReturnHome; - elsif i = 16 then - state <= GoLine2; - else - state <= Refresh; - end if; - end if; - - when ExecCMD0=> - if SYNCH.DRVR_READY = '1' then - DRIVER_CMD.Exec <= '1'; - DRIVER_CMD.Duration <= CMD(9 downto 8); - DRIVER_CMD.CMD_Data <= '0'; - DRIVER_CMD.Word <= CMD(7 downto 0); - state <= ExecCMD1; - else - DRIVER_CMD.Exec <= '0'; - end if; - - when ExecCMD1=> - state <= Idle; - DRIVER_CMD.Exec <= '0'; - - when GoLine2=> - if SYNCH.DRVR_READY = '1' then - DRIVER_CMD.Exec <= '1'; - DRIVER_CMD.Duration <= Duration_100us; - DRIVER_CMD.CMD_Data <= '0'; - DRIVER_CMD.Word <= X"C0"; - state <= GoLine2_0; - else - DRIVER_CMD.Exec <= '0'; - end if; - when GoLine2_0=> - state <= Refresh; - DRIVER_CMD.Exec <= '0'; - when ReturnHome=> - if SYNCH.DRVR_READY = '1' then - DRIVER_CMD.Exec <= '1'; - DRIVER_CMD.Duration <= Duration_4ms; - DRIVER_CMD.CMD_Data <= '0'; - DRIVER_CMD.Word <= X"02"; - state <= Idle; - else - DRIVER_CMD.Exec <= '0'; - end if; - end case; - end if; -end process; - - -end ar_LCD_16x2_ENGINE; - - - - - - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_2x16_DRIVER.vhd +++ /dev/null @@ -1,175 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:09:57 10/13/2010 --- Design Name: --- Module Name: LCD_2x16_DRIVER - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.all; -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; - -entity LCD_2x16_DRIVER is - generic( - OSC_Freq_MHz : integer:=60; - Refresh_RateHz : integer:=5 - ); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - STATEOUT: out std_logic_vector(3 downto 0); - refreshPulse : out std_logic - ); -end LCD_2x16_DRIVER; - -architecture Behavioral of LCD_2x16_DRIVER is - -type stateT is(Rst,Configure,IDLE,RefreshScreen); -signal state : stateT; - -signal ShortTimePulse : std_logic; -signal MidleTimePulse : std_logic; -signal Refresh_RatePulse : std_logic; -signal Start : STD_LOGIC; - -signal CFGM_LCD_RS : std_logic; -signal CFGM_LCD_RW : std_logic; -signal CFGM_LCD_E : std_logic; -signal CFGM_LCD_DATA : std_logic_vector(7 downto 0); -signal CFGM_Enable : std_logic; -signal CFGM_completed : std_logic; - - -signal FRMW_LCD_RS : std_logic; -signal FRMW_LCD_RW : std_logic; -signal FRMW_LCD_E : std_logic; -signal FRMW_LCD_DATA : std_logic_vector(7 downto 0); -signal FRMW_Enable : std_logic; -signal FRMW_completed : std_logic; - -begin - - -Counter : LCD_Counter -generic map(OSC_Freq_MHz,Refresh_RateHz) -port map(reset,clk,ShortTimePulse,MidleTimePulse,Refresh_RatePulse,Start); - -ConfigModule : Config_Module -port map(reset,clk,CFGM_LCD_RS,CFGM_LCD_RW,CFGM_LCD_E,CFGM_LCD_DATA,CFGM_Enable,CFGM_completed,MidleTimePulse); - - -FrameWriter : FRAME_WRITER -port map(reset,clk,FramBUFF,FRMW_LCD_DATA,FRMW_LCD_RS,FRMW_LCD_RW,FRMW_LCD_E,FRMW_Enable,FRMW_Completed,ShortTimePulse,MidleTimePulse); - - -STATEOUT(0) <= '1' when state = Rst else '0'; -STATEOUT(1) <= '1' when state = Configure else '0'; -STATEOUT(2) <= '1' when state = IDLE else '0'; -STATEOUT(3) <= '1' when state = RefreshScreen else '0'; - - - -refreshPulse <= Refresh_RatePulse; - -Start <= '1'; - -process(reset,clk) -begin - if reset = '0' then - LCD_data <= (others=>'0'); - LCD_RS <= '0'; - LCD_RW <= '0'; - LCD_RET <= '0'; - LCD_CS1 <= '0'; - LCD_CS2 <= '0'; - LCD_E <= '0'; - state <= Rst; - CFGM_Enable <= '0'; - FRMW_Enable <= '0'; - elsif clk'event and clk ='1' then - case state is - when Rst => - LCD_data <= (others=>'0'); - LCD_RS <= '0'; - LCD_RW <= '0'; - LCD_E <= '0'; - CFGM_Enable <= '1'; - FRMW_Enable <= '0'; - if Refresh_RatePulse = '1' then - state <= Configure; - end if; - when Configure => - LCD_data <= CFGM_LCD_data; - LCD_RS <= CFGM_LCD_RS; - LCD_RW <= CFGM_LCD_RW; - LCD_E <= CFGM_LCD_E; - CFGM_Enable <= '0'; - if CFGM_completed = '1' then - state <= IDLE; - end if; - when IDLE => - if Refresh_RatePulse = '1' then - state <= RefreshScreen; - FRMW_Enable <= '1'; - end if; - LCD_RS <= '0'; - LCD_RW <= '0'; - LCD_E <= '0'; - LCD_data <= (others=>'0'); - when RefreshScreen => - LCD_data <= FRMW_LCD_data; - LCD_RS <= FRMW_LCD_RS; - LCD_RW <= FRMW_LCD_RW; - LCD_E <= FRMW_LCD_E; - FRMW_Enable <= '0'; - if FRMW_completed = '1' then - state <= IDLE; - end if; - end case; - end if; -end process; -end Behavioral; - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/LCD_CLK_GENERATOR.vhd +++ /dev/null @@ -1,91 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 08:52:25 10/18/2010 --- Design Name: --- Module Name: LCD_CLK_GENERATOR - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; - -entity LCD_CLK_GENERATOR is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - clk_1us : out STD_LOGIC); -end LCD_CLK_GENERATOR; - -architecture ar_LCD_CLK_GENERATOR of LCD_CLK_GENERATOR is - -Constant clk_1usTRIGER : integer := (OSC_freqKHz/2000)+1; - - -signal cpt1 : integer; - -signal clk_1us_int : std_logic := '0'; - - -begin - -clk_1us <= clk_1us_int; - - -process(reset,clk) -begin - if reset = '0' then - cpt1 <= 0; - clk_1us_int <= '0'; - elsif clk'event and clk = '1' then - if cpt1 = clk_1usTRIGER then - clk_1us_int <= not clk_1us_int; - cpt1 <= 0; - else - cpt1 <= cpt1 + 1; - end if; - end if; -end process; - - -end ar_LCD_CLK_GENERATOR; - - - - - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCD.vhd +++ /dev/null @@ -1,124 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 08:44:41 10/14/2010 --- Design Name: --- Module Name: Top_LCD - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -library lpp; -use lpp.amba_lcd_16x2_ctrlr.all; -use lpp.LCD_16x2_CFG.all; - - -entity AMBA_LCD_16x2_DRIVER is - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - Bp0 : in STD_LOGIC; - Bp1 : in STD_LOGIC; - Bp2 : in STD_LOGIC; - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - SF_CE0 : out std_logic - ); -end AMBA_LCD_16x2_DRIVER; - -architecture Behavioral of AMBA_LCD_16x2_DRIVER is - -signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0); -signal CMD : std_logic_vector(10 downto 0); -signal Exec : std_logic; -signal Ready : std_logic; -signal rst : std_logic; -signal LCD_CTRL : LCD_DRVR_CTRL_BUSS; - -begin - -LCD_data <= LCD_CTRL.LCD_DATA; -LCD_RS <= LCD_CTRL.LCD_RS; -LCD_RW <= LCD_CTRL.LCD_RW; -LCD_E <= LCD_CTRL.LCD_E; - - -LCD_RET <= '0'; -LCD_CS1 <= '0'; -LCD_CS2 <= '0'; - -SF_CE0 <= '1'; - -rst <= not reset; - - - -Driver0 : LCD_16x2_ENGINE - generic map(50000) - Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL); - -FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else - X"42" when Bp1 = '1' else - X"43" when Bp2 = '1' else - X"44"; - -FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else - X"47" when Bp1 = '1' else - X"48" when Bp2 = '1' else - X"49"; - - -CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else - Duration_100us & CursorOFF; - - -Exec <= Bp1; - -FramBUFF(2*8+7 downto 2*8) <= X"23"; -FramBUFF(3*8+7 downto 3*8) <= X"66"; -FramBUFF(4*8+7 downto 4*8) <= X"67"; -FramBUFF(5*8+7 downto 5*8) <= X"68"; -FramBUFF(17*8+7 downto 17*8) <= X"69"; ---FramBUFF(16*2*8-1 downto 16) <= (others => '0'); - -end Behavioral; - - - - - - diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf b/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/Top_LCDcst.ucf +++ /dev/null @@ -1,37 +0,0 @@ - -NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; - -NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; - -NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; - -NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; - -NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I; -NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I; -NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I; - -NET "LCD_data<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<1>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<2>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<3>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<4>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<5>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<6>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_data<7>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; - -NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; -NET "Bp0" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; -NET "Bp1" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; -NET "Bp2" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; - -net "clk" LOC = "C9" | IOSTANDARD = LVCMOS33; -net "clk" PERIOD = 20.0ns HIGH 40%; -#net "clkOUT" LOC = "N14" | IOSTANDARD = LVCMOS33; - -#net "STATEOUT<0>" LOC = "V5" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; -#net "STATEOUT<1>" LOC = "V6" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; -#net "STATEOUT<2>" LOC = "N12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; -#net "STATEOUT<3>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST ; - -#net "refreshPulse" LOC = "N15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; \ No newline at end of file diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd b/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/amba_lcd_16x2_ctrlr.vhd +++ /dev/null @@ -1,173 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - - - -package amba_lcd_16x2_ctrlr is - - -type LCD_DRVR_CTRL_BUSS is - record - LCD_RW : std_logic; - LCD_RS : std_logic; - LCD_E : std_logic; - LCD_DATA : std_logic_vector(7 downto 0); - end record; - - type LCD_DRVR_SYNCH_BUSS is - record - DRVR_READY : std_logic; - LCD_INITIALISED : std_logic; - end record; - - - type LCD_DRVR_CMD_BUSS is - record - Word : std_logic_vector(7 downto 0); - CMD_Data : std_logic; --CMD = '0' and data = '1' - Exec : std_logic; - Duration : std_logic_vector(1 downto 0); - end record; - type LCD_CFG_Tbl is array(0 to 4) of std_logic_vector(7 downto 0); - - - -component LCD_16x2_DRIVER is - generic( - OSC_Freq_MHz : integer:=60 - ); - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - LCD_CTRL : out LCD_DRVR_CTRL_BUSS; - SYNCH : out LCD_DRVR_SYNCH_BUSS; - DRIVER_CMD : in LCD_DRVR_CMD_BUSS - ); -end component; - - - -component amba_lcd_16x2_driver is - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - Bp0 : in STD_LOGIC; - Bp1 : in STD_LOGIC; - Bp2 : in STD_LOGIC; - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - SF_CE0 : out std_logic - ); -end component; - - - -component FRAME_CLK_GEN is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - FRAME_CLK : out STD_LOGIC); -end component; - - - -component LCD_2x16_DRIVER is - generic( - OSC_Freq_MHz : integer:=60; - Refresh_RateHz : integer:=5 - ); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - FramBUFF : in STD_LOGIC_VECTOR(16*2*8-1 downto 0); - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - STATEOUT: out std_logic_vector(3 downto 0); - refreshPulse : out std_logic - ); -end component; - - -component LCD_CLK_GENERATOR is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - clk_1us : out STD_LOGIC); -end component; - -component AMBA_LCD_16x2_DRIVER is - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - Bp0 : in STD_LOGIC; - Bp1 : in STD_LOGIC; - Bp2 : in STD_LOGIC; - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - SF_CE0 : out std_logic - ); -end component; - -component LCD_16x2_ENGINE is - generic(OSC_freqKHz : integer := 50000); - Port ( clk : in STD_LOGIC; - reset : in STD_LOGIC; - DATA : in std_logic_vector(16*2*8-1 downto 0); - CMD : in std_logic_vector(10 downto 0); - Exec : in std_logic; - Ready : out std_logic; - LCD_CTRL : out LCD_DRVR_CTRL_BUSS - ); -end component; - - -component AMBA_LCD_16x2_DRIVER is - Port ( reset : in STD_LOGIC; - clk : in STD_LOGIC; - Bp0 : in STD_LOGIC; - Bp1 : in STD_LOGIC; - Bp2 : in STD_LOGIC; - LCD_data : out STD_LOGIC_VECTOR (7 downto 0); - LCD_RS : out STD_LOGIC; - LCD_RW : out STD_LOGIC; - LCD_E : out STD_LOGIC; - LCD_RET : out STD_LOGIC; - LCD_CS1 : out STD_LOGIC; - LCD_CS2 : out STD_LOGIC; - SF_CE0 : out std_logic - ); -end component; - - - -end; diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh b/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/temp.sh +++ /dev/null @@ -1,1 +0,0 @@ -ls|grep .vhd|grep -i -v test>vhdlsyn.txt diff --git a/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt b/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt deleted file mode 100644 --- a/lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt +++ /dev/null @@ -1,9 +0,0 @@ -FRAME_CLK.vhd -LCD_16x2_CFG.vhd -LCD_16x2_DRIVER -.vhd -LCD_16x2_ENGINE.vhd -LCD_2x16_DRIVER.vhd -LCD_CLK_GENERATOR.vhd -Top_LCD.vhd -amba_lcd_16x2_ctrlr.vhd diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -1,4 +1,3 @@ -./amba_lcd_16x2_ctrlr ./dsp/iir_filter ./general_purpose ./lpp_amba diff --git a/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd b/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd @@ -0,0 +1,106 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- APB_MULTI_DIODE.vhd + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.numeric_std.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; + + +entity APB_MULTI_DIODE is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + LED : out std_logic_vector(2 downto 0) + ); +end; + + +architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + + + +type LEDregs is record + DATAin : std_logic_vector(31 downto 0); + DATAout : std_logic_vector(31 downto 0); +end record; + +signal r : LEDregs; + + +begin + +r.DATAout <= r.DATAin xor X"FFFFFFFF"; + +process(rst,clk) +begin + if rst = '0' then + LED <= "000"; + r.DATAin <= (others => '0'); + apbo.prdata <= (others => '0'); + elsif clk'event and clk = '1' then + + LED <= r.DATAin(2 downto 0); + +--APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + r.DATAin <= apbi.pwdata; + when others => + null; + end case; + end if; + +--APB READ OP + if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + apbo.prdata <= r.DATAin; + when others => + apbo.prdata <= r.DATAout; + end case; + end if; + + end if; + apbo.pconfig <= pconfig; +end process; + + +end ar_APB_MULTI_DIODE; \ No newline at end of file diff --git a/lib/lpp/lpp_amba/lpp_amba.vhd b/lib/lpp/lpp_amba/lpp_amba.vhd --- a/lib/lpp/lpp_amba/lpp_amba.vhd +++ b/lib/lpp/lpp_amba/lpp_amba.vhd @@ -24,9 +24,7 @@ use grlib.amba.all; -- pragma translate_off use std.textio.all; -- pragma translate_on - - - + package lpp_amba is @@ -38,6 +36,7 @@ constant VENDOR_LPP : amba_vendor constant ROCKET_TM : amba_device_type := 16#001#; constant otherCore : amba_device_type := 16#002#; constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#; +constant LPP_MULTI_DIODE : amba_device_type := 16#004#; component APB_SIMPLE_DIODE is @@ -57,4 +56,20 @@ component APB_SIMPLE_DIODE is end component; +component APB_MULTI_DIODE is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + LED : out std_logic_vector(2 downto 0) + ); +end component; + end; diff --git a/lib/lpp/lpp_amba/vhdlsyn.txt b/lib/lpp/lpp_amba/vhdlsyn.txt --- a/lib/lpp/lpp_amba/vhdlsyn.txt +++ b/lib/lpp/lpp_amba/vhdlsyn.txt @@ -1,2 +1,3 @@ +APB_MULTI_DIODE.vhd APB_SIMPLE_DIODE.vhd lpp_amba.vhd