diff --git a/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd b/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/ClkDivider.vhd
+++ /dev/null
@@ -1,36 +0,0 @@
--- ClkDivider.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-
-entity ClkDivider is 
-generic(N : integer := 16);
-port(
-    clk_in  :   in  std_logic;
-    clk_out :   out std_logic
-);
-end entity;
-
-
-
-architecture ar_ClkDivider of ClkDivider is
-signal  cpt     :   integer range 0 to N/2-1;
-signal  clk_int :   std_logic:='0';
-begin
-
-clk_out <=  clk_int;
-
-process(clk_in)
-begin
-    if clk_in'event and clk_in = '1' then
-        if cpt = N/2-1 then
-            clk_int <= not clk_int;
-            cpt       <=  0;
-        else
-            cpt       <=  cpt + 1;
-        end if;
-    end if;
-end process;
-end ar_ClkDivider;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Data.vhd b/designs/ICI4-Integ1/ICI4HDL/Data.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Data.vhd
+++ /dev/null
@@ -1,60 +0,0 @@
--- Data.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-use work.Convertisseur_config.all;
-
-entity Data is
-
-port(
-    clk,raz         : in std_logic;    
-    ADS_HF_In       : in IN_ADS;
-    ADS_LF_In       : in IN_ADS;
-    sclk            : out std_logic;    
-    ADS_HF_config   : out ADS_config;
-    ADS_LF_config   : out ADS_config;
-    ADS_HF_out      : out OUT_ADS;
-    ADS_LF_out      : out OUT_ADS;
-    Bit_fin_HF,Bit_fin_LF : out std_logic;
-    Vector_HF1,Vector_HF2,Vector_HF3 : out std_logic_vector(15 downto 0));
-
-end Data;
-
-architecture ar_Data of Data is
-
-constant ADS_HF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_power);
-constant ADS_LF_c : ADS_config :=('1','1',FSYNC_FORMAT,MODE_low_speed);
-
-signal Vect_1 : std_logic_vector(23 downto 0);
-signal Vect_2 : std_logic_vector(23 downto 0);
-signal Vect_3 : std_logic_vector(23 downto 0);
-signal sclk_int : std_logic;
-
-begin
-
-Clock_systeme : entity work.Sys_Clock
-    generic map (nb_compteur_sclk)
-    port map (clk,raz,sclk_int);
-    
-
-Data_LF : entity work.Vectorize
-    port map (clk,raz,sclk_int,ADS_LF_In.RDY,ADS_LF_In.Data_in(1),ADS_LF_In.Data_in(2),ADS_LF_In.Data_in(3),Bit_fin_LF,ADS_LF_out.Vector_out(1),ADS_LF_out.Vector_out(2),ADS_LF_out.Vector_out(3));
- 
-Data_HF : entity work.Vectorize
-    port map (clk,raz,sclk_int,ADS_HF_In.RDY,ADS_HF_In.Data_in(1),ADS_HF_In.Data_in(2),ADS_HF_In.Data_in(3),Bit_fin_HF,Vect_1,Vect_2,Vect_3);
-
-
-ADS_HF_config <= ADS_HF_c;
-ADS_LF_config <= ADS_LF_c;
-
-ADS_HF_out.Vector_out(1) <= Vect_1;
-ADS_HF_out.Vector_out(2) <= Vect_2;
-ADS_HF_out.Vector_out(3) <= Vect_3;
-
-Vector_HF1 <= Vect_1(23 downto 8);
-Vector_HF2 <= Vect_2(23 downto 8);
-Vector_HF3 <= Vect_3(23 downto 8);
-
-sclk <= sclk_int;
-
-end ar_Data;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Gene_17K36.vhd
+++ /dev/null
@@ -1,45 +0,0 @@
--- Gene_17K36.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity Gene_17K36 is 
-
-port(
-    clk,raz :   in  std_logic;
-    Pulse : in std_logic;
-    Clock_17K36 : out std_logic);
-
-end Gene_17K36;
-
-
-architecture ar_Gene_17K36 of Gene_17K36 is
-
-signal pulse_reg : std_logic;
-signal clk_int : std_logic;
-signal count : integer range 0 to 6;
-
-begin
-    process(clk, raz)
-        begin
-        if (raz='0')then            
-            clk_int <= '0';
-            pulse_reg <= '0'; 
-            count <= 0; 
-
-        elsif (clk'event and clk='1') then
-        pulse_reg <= Pulse;            
-            if(pulse_reg='0' and Pulse='1')then
-                if(count=5)then
-                    count <= 0;
-                    clk_int <= not clk_int;
-                else
-                    count <= count + 1;
-                end if;
-            end if;
-        end if;
-    end process;
-
-Clock_17K36 <= clk_int;
-
-end ar_Gene_17K36;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Gene_1K4.vhd
+++ /dev/null
@@ -1,45 +0,0 @@
--- Gene_1K4.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity Gene_1K4 is 
-
-port(
-    clk,raz :   in  std_logic;
-    Minor_Frame : in std_logic;
-    Clock_1K4 : out std_logic);
-
-end Gene_1K4;
-
-
-architecture ar_Gene_1K4 of Gene_1K4 is
-
-signal minor_reg : std_logic;
-signal clk_int : std_logic;
-
-begin
-    process(clk, raz)
-        begin
-        if (raz='0')then            
-            clk_int <= '0';
-            minor_reg <= '0';  
-
-        elsif (clk'event and clk='1') then
-        minor_reg <= Minor_Frame;            
-            if(minor_reg='0' and Minor_Frame='1')then    
-                clk_int <= not clk_int;
-            end if;
-        end if;
-    end process;
-
-Clock_1K4 <= clk_int;
-
-end ar_Gene_1K4;
-
-
-
-
-
-
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd b/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Gene_Freq.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
--- Gene_Freq.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity Gene_Freq is
-
-generic(nb_mots : integer :=144);
-
-port(
-    clk,raz     : in std_logic;
-    Minor_Frame : in std_logic;
-    Compt_mots  : in integer range 0 to nb_mots;
-    Clock_1k4   : out std_logic;
-    Clock_17K36 : out std_logic);
-
-end Gene_Freq;
-
-architecture ar_Gene_Freq of Gene_Freq is
-
-signal Pulse_mot : std_logic;
-
-begin
-    
-Gene_LF : entity work.Gene_1K4
-    port map (clk,raz,Minor_Frame,Clock_1K4);
-
- 
-Gene_HF : entity work.Gene_17K36 
-    port map(clk,raz,Pulse_mot,Clock_17K36);
-
-
-Pulsing : entity work.integer_to_clk
-    generic map(nb_mots)
-    port map(clk,raz,Compt_mots,Pulse_mot);
-
-end ar_Gene_Freq;
diff --git a/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd b/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/MinF_Cntr.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--- MinF_Cntr.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-
-
-entity MinF_Cntr is
-generic(MinFCount   :   integer := 64);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    Cnt_out :   out integer range 0 to MinFCount-1
-);
-end entity;
-
-
-
-architecture ar_MinF_Cntr of MinF_Cntr is
-
-signal  Cnt_int     :   integer range 0 to MinFCount-1 := 0;
-signal  MinF_reg    :   std_logic := '0';
-
-begin
-
-Cnt_out <=  Cnt_int;
-
-process(clk,reset)
-begin
-    if reset = '0' then
-        Cnt_int <= 0;
-    elsif clk'event and clk = '1' then
-        if Cnt_int = MinFCount -1 then
-            Cnt_int     <=  0;
-        else
-            Cnt_int     <=  Cnt_int + 1;
-        end if;
-    end if;
-end process;
-end ar_MinF_Cntr;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver.vhd
+++ /dev/null
@@ -1,44 +0,0 @@
--- Serial_Driver.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity Serial_Driver is
-generic(size    :   integer :=8);
-port(
-    sclk     :   in  std_logic;
-    inputDat:   in  std_logic_vector(size-1 downto 0);  
-    Gate    :   in  std_logic;
-    Data    :   out std_logic
-);
-end Serial_Driver;
-
-
-
-
-architecture ar_Serial_Driver of Serial_Driver is
-signal  Count   :   integer range 0 to size-1;
-signal    SR_internal :   std_logic_vector(size-1 downto 0):=std_logic_vector(TO_UNSIGNED(165,Size));
-begin
-process(sclk)
-begin
-    if SCLK'event and SCLK = '1' then
-        if gate = '1' then
-            if Count = size-1 then 
-                Count <= 0;
-                Data        <=  SR_internal(size-1);
-                SR_internal <=  inputDat;
-            else
-                Count <= Count+1;
-                Data    <=  SR_internal(size-1);
-                SR_internal <=  SR_internal(size-2 downto 0) & '0';
-            end if;
-        else
-            SR_internal <=  inputDat;
-            Data    <=  '0';
-            Count   <=  0;
-        end if;
-    end if;
-end process;
-end ar_Serial_Driver;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd b/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Serial_Driver_Multiplexor.vhd
+++ /dev/null
@@ -1,33 +0,0 @@
--- Serial_Driver_Multiplexor.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-
-entity Serial_Driver_Multiplexor is
-generic(InputCnt : integer := 2;inputSize : integer:=8);
-port(
-    clk     :   in  std_logic;
-    Sel     :   in  integer range 0 to InputCnt-1;
-    input   :   in  std_logic_vector(InputCnt*inputSize-1 downto 0);
-    output  :   out std_logic_vector(inputSize-1 downto 0)
-);
-end entity;
-
-
-
-architecture ar_Serial_Driver_Multiplexor of Serial_Driver_Multiplexor is
-begin
-
-
-process(clk)
-begin
-if clk'event and clk = '1' then
-    output  <=  input((Sel+1)*inputSize-1 downto (Sel)*inputSize);
-end if;
-end process;
-
-
-end ar_Serial_Driver_Multiplexor;
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd b/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Simple_Counter.vhd
+++ /dev/null
@@ -1,58 +0,0 @@
--- Simple_Counter.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity Simple_Counter is
-generic(N   :   integer := 8);
-port(
-    clk     :   in  std_logic;
-    sclk    :   in  std_logic;
-    Gate   :   in  std_logic;
-    OV      :   out std_logic
-
-);
-end entity;
-
-
-architecture ar_Simple_Counter of Simple_Counter is
-signal  Count   :   integer range 0 to N-1;
-signal  Gate_Reg    :   std_logic:='0';
-signal  sclk_Reg    :   std_logic := '0';
-begin
-
-process(clk)
-begin
-    if clk'event and clk = '1' then
-        Gate_Reg    <= Gate;
-        sclk_Reg     <=  sclk;
-        if Gate = '1' and Gate_reg = '0' then
-            Count <= 0;
-        else
-            if sclk = '1' and sclk_Reg = '0' then
-                if Count = N-1 then 
-                    Count <= 0;
-                else
-                    Count <= Count+1;
-                end if;
-            end if;
-        end if;
-    end if;
-end process;
-
-
-OV  <=  '1' when Count = N-1 and sclk_Reg = '0' and sclk = '1' else '0';
-
-end ar_Simple_Counter;
-
-
-
-
-
-
-
-
-
-
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/TOP_ICI3_INTEG1.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
--- TOP_ICI3_INTEG1.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
---library igloo;
---use igloo.all;
-use work.Convertisseur_config.all;
-
-entity TOP_ICI3_INTEG1 is 
-Generic(WordSize : integer := 8; WordCnt    :   integer := 144;MinFCount   :   integer := 64);
-port(
-    clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    sclk    :   in  std_logic;
-    Gate    :   in  std_logic;
-    MinF    :   in  std_logic;
-    MajF    :   in  std_logic;
-    Data    :   out std_logic;
-    DC_ADC_Sclk     :   out std_logic;
-    DC_ADC_IN       :   in  std_logic_vector(3 downto 0);
-    DC_ADC_FORMAT   :   out std_logic_vector(2 downto 0);
-    DC_ADC_Mode     :   out std_logic_vector(1 downto 0);
-    DC_ADC_ClkDiv   :   out std_logic;
-    DC_ADC_PWDOWN   :   out std_logic_vector(3 downto 0);
-    DC_ADC_FSynch   :   out std_logic;
-    DC_ADC_Synch    :   out std_logic;
---    DATA_out_Test   :   out std_logic;
---    Sclk_out_test   :   out std_logic;
---    Synch_out_test  :   out std_logic;  
-    test            :   out std_logic;  
-
-    LF_ADC_Sclk     :   out std_logic;
-    LF_ADC_IN       :   in  std_logic_vector(3 downto 0);
-    LF_ADC_FORMAT   :   out std_logic_vector(2 downto 0);
-    LF_ADC_Mode     :   out std_logic_vector(1 downto 0);
-    LF_ADC_ClkDiv   :   out std_logic;
-    LF_ADC_PWDOWN   :   out std_logic_vector(3 downto 0);
-    LF_ADC_FSynch   :   out std_logic;
-    LF_ADC_Synch    :   out std_logic
-
-);
-end entity;
-
-
-
-
-architecture ar_TOP_ICI3_INTEG1 of TOP_ICI3_INTEG1 is
-
---  component CLKINT
---    port( A : in    std_logic := 'U';
---          Y : out   std_logic
---        );
---  end component;
-
-signal  clk_buf,reset_buf   :   std_logic;
-
-Constant FramePlacerCount    :   integer := 2;
-
-signal  MinF_Inv    :   std_logic;
-signal  Gate_Inv    :   std_logic;
-signal  sclk_Inv    :   std_logic;
-signal  WordCount   :   integer range 0 to WordCnt-1;
-signal  WordClk     :   std_logic;
-
-signal  MuxOUT      :   std_logic_vector(WordSize-1 downto 0);
-signal  MuxIN       :   std_logic_vector((2*WordSize)-1 downto 0);
-signal  Sel         :   integer range 0 to 1;
-
-signal  DC1     :     std_logic_vector(23 downto 0);
-signal  DC2     :     std_logic_vector(23 downto 0);
-signal  DC3     :     std_logic_vector(23 downto 0);
-
-
-
-signal  LF1     :     std_logic_vector(15 downto 0);
-signal  LF2     :     std_logic_vector(15 downto 0);
-signal  LF3     :     std_logic_vector(15 downto 0);
-
-
-signal  LF1_int    :     std_logic_vector(23 downto 0);
-signal  LF2_int    :     std_logic_vector(23 downto 0);
-signal  LF3_int    :     std_logic_vector(23 downto 0);
-
---constant DC1cst :   std_logic_vector(23 downto 0) := X"FA5961";
---constant DC2cst :   std_logic_vector(23 downto 0) := X"123456";
---constant DC3cst :   std_logic_vector(23 downto 0) := X"789012";
---
---constant LF1cst :   std_logic_vector(15 downto 0) := X"3210";
---constant LF2cst :   std_logic_vector(15 downto 0) := X"6543";
---constant LF3cst :   std_logic_vector(15 downto 0) := X"3456";
---
-
-signal   DC_ADC_SmplClk  :    std_logic;
-signal   LF_ADC_SmplClk  :    std_logic;
-
-signal  MinFCnt   :   integer range 0 to MinFCount-1;
-
-signal  FramePlacerFlags    :   std_logic_vector(FramePlacerCount-1 downto 0);
-
-begin
-
---CLKINT0 : CLKINT
---    port map(clk,clk_buf);
---    
---CLKINT1 : CLKINT
---    port map(reset,reset_buf);
-
-clk_buf   <= clk;
-reset_buf <= reset;
---    
---DATA_out_Test   <=  DC_ADC_IN(0);
---Sclk_out_test   <=  DC_ADC_Sclk;
---Synch_out_test  <=  DC_ADC_FSynch;
-
-Gate_Inv    <=  not Gate;
-sclk_Inv    <=  not Sclk;
-MinF_Inv    <=  not MinF;
-
---DC1 <=  DC1cst;
---DC2 <=  DC2cst;
---DC3 <=  DC3cst;
-
---LF1 <=  LF1cst;
---LF2 <=  LF2cst;
---LF3 <=  LF3cst;
-
-SD0 : entity work.Serial_Driver 
-generic map(WordSize)
-port map(sclk_Inv,MuxOUT,Gate_inv,Data);
-
-WC0 :   entity work.Word_Cntr
-generic map(WordSize,WordCnt)
-port map(sclk_Inv,MinF,WordClk,WordCount);
-
-MFC0 : entity work.MinF_Cntr
-generic map(MinFCount)
-port map(
-    clk     =>  MinF_Inv,
-    reset   =>  MajF,
-    Cnt_out =>  MinFCnt
-);
-
-
-MUX0 : entity work.Serial_Driver_Multiplexor
-generic map(FramePlacerCount,WordSize)
-port map(sclk_Inv,Sel,MuxIN,MuxOUT);
-
-
-DCFP0 : entity work.DC_FRAME_PLACER 
-generic map(WordSize,WordCnt,MinFCount)
-port map(
-    clk     =>  Sclk,
-    Wcount  =>  WordCount,
-    MinFCnt =>  MinFCnt,
-    Flag    =>  FramePlacerFlags(0),
-    DC1     =>  DC1,
-    DC2     =>  DC2,
-    DC3     =>  DC3,
-    WordOut =>  MuxIN(7 downto 0));
-
-
-
-LFP0 : entity  work.LF_FRAME_PLACER
-generic map(WordSize,WordCnt,MinFCount)
-port map(
-    clk     =>  Sclk,
-    Wcount  =>  WordCount,
-    Flag    =>  FramePlacerFlags(1),
-    LF1     =>  LF1,
-    LF2     =>  LF2,
-    LF3     =>  LF3,
-    WordOut =>  MuxIN(15 downto 8));
-
-
-
-DC_SMPL_CLK0 : entity work.DC_SMPL_CLK 
-port map(MinF_Inv,DC_ADC_SmplClk);
-
-
-DC_ADC_Synch    <=  reset;
-LF_ADC_Synch    <=  reset;
-
-DC_ADC0 : entity work.ADS1274_DRIVER                      --With AMR down ! => 24bits DC TM -> SC high res on Spin
-generic map(MODE_low_power,FSYNC_FORMAT)
-port map(
-    Clk     =>  clk_buf,
-    reset   =>  reset_buf,
-    SpiClk  =>  DC_ADC_Sclk,
-    DIN     =>  DC_ADC_IN,
-    Ready   =>  '0',
-    Format  =>  DC_ADC_Format,
-    Mode    =>  DC_ADC_Mode,
-    ClkDiv  =>  DC_ADC_ClkDiv,
-    PWDOWN  =>  DC_ADC_PWDOWN,
-    SmplClk =>  DC_ADC_SmplClk,
-    OUT0    =>  DC1,
-    OUT1    =>  DC2,
-    OUT2    =>  DC3,
-    OUT3    =>  open,
-    FSynch  =>  DC_ADC_FSynch,
-    test    =>  test
-);
-
-
-LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
-port map(
-    Wclck    => WordClk,
-    MinF     => MinF,
-    SMPL_CLK => LF_ADC_SmplClk
-);
-
-LF_ADC0 : entity work.ADS1274_DRIVER 
-generic map(MODE_low_power,FSYNC_FORMAT)
-port map(
-    Clk     =>  clk_buf,
-    reset   =>  reset_buf,
-    SpiClk  =>  LF_ADC_Sclk,
-    DIN     =>  LF_ADC_IN,
-    Ready   =>  '0',
-    Format  =>  LF_ADC_Format,
-    Mode    =>  LF_ADC_Mode,
-    ClkDiv  =>  LF_ADC_ClkDiv,
-    PWDOWN  =>  LF_ADC_PWDOWN,
-    SmplClk =>  LF_ADC_SmplClk,
-    OUT0    =>  LF1_int,
-    OUT1    =>  LF2_int,
-    OUT2    =>  LF3_int,
-    OUT3    =>  open,
-    FSynch  =>  LF_ADC_FSynch
-);
-
-
-LF1     <=  LF1_int(23 downto 8);
-LF2     <=  LF2_int(23 downto 8);
-LF3     <=  LF3_int(23 downto 8);
---
---DC1     <=  LF1_int(23 downto 0);
---DC2     <=  LF2_int(23 downto 0);
---DC3     <=  LF3_int(23 downto 0);
-
---Input Word Selection Decoder
-
-process(clk)
-variable SelVar :   integer range 0 to 1;
-begin
-    if clk'event and clk ='1' then
-        Decoder: FOR i IN 0 to FramePlacerCount-1 loop
-            if FramePlacerFlags(i) = '1' then
-                SelVar := i;
-            end if;
-        END loop Decoder;
-        Sel <=  SelVar;
-    end if;
-end process;
-
-
-end ar_TOP_ICI3_INTEG1;
-
-
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diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver2.vhd
+++ /dev/null
@@ -1,65 +0,0 @@
--- TOP_Serial_Driver2.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity TOP_Serial_Driver2 is
-port(
-    clk     :   in  std_logic;
-    sclk    :   in  std_logic;
-    Gate    :   in  std_logic;
-    Data    :   out std_logic
-);
-end TOP_Serial_Driver2;
-
-
-
-
-architecture ar_TOP_Serial_Driver2 of TOP_Serial_Driver2 is
-constant Size   :   integer := 8;
-signal  MinF_Inv    :   std_logic;
-signal  Gate_Inv    :   std_logic;
-signal  sclk_Inv    :   std_logic;
-signal  OV          :   std_logic;
-signal  Word      :   std_logic_vector(Size-1 downto 0);
-constant  Word1      :   std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(36,Size));
-constant  Word2      :   std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(255,Size));
-signal  Flag        :   std_logic :='0';
-
-begin
-Gate_Inv    <=  not Gate;
-sclk_Inv    <=  not Sclk;
-
-
-SD0 : entity work.Serial_Driver 
-generic map(Size)
-port map(
-    sclk_Inv,
-    Word,
-    Gate_inv,
-    Data
-);
-
-cpt :   entity work.Simple_Counter
-generic map(8)
-port map(
-    clk,
-    sclk_Inv,
-    Gate_Inv,
-    OV);
-
-
-word    <=  Word1;-- when OV = '1' and Flag = '0' else Word2 when OV = '1' and Flag = '1';
-
-process(sclk)
-begin
-if sclk'event and sclk = '1' then
-    if OV = '1' then 
-        Flag    <=  not Flag;
-    end if;
-end if;
-end process;
-
-
-end ar_TOP_Serial_Driver2;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd b/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/TOP_Serial_Driver_Wcounter.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
--- TOP_Serial_Driver_Wcounter.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity TOP_Serial_Driver_Wcounter is 
-Generic(WordSize : integer := 8; WordCnt    :   integer := 144;MinFCount   :   integer := 64);
-port(
-    clk     :   in  std_logic;
-    sclk    :   in  std_logic;
-    Gate    :   in  std_logic;
-    MinF    :   in  std_logic;
-    MajF    :   in  std_logic;
-    Data    :   out std_logic
-);
-end entity;
-
-
-
-
-architecture ar_TOP_Serial_Driver_Wcounter of TOP_Serial_Driver_Wcounter is
-
-
-Constant FramePlacerCount    :   integer := 2;
-
-signal  MinF_Inv    :   std_logic;
-signal  Gate_Inv    :   std_logic;
-signal  sclk_Inv    :   std_logic;
-signal  WordCount   :   integer range 0 to WordCnt-1;
-signal  WordClk     :   std_logic;
-
-signal  MuxOUT      :   std_logic_vector(WordSize-1 downto 0);
-signal  MuxIN       :   std_logic_vector((2*WordSize)-1 downto 0);
-signal  Sel         :   integer range 0 to 1;
-
-signal  DC1     :     std_logic_vector(23 downto 0);
-signal  DC2     :     std_logic_vector(23 downto 0);
-signal  DC3     :     std_logic_vector(23 downto 0);
-
-
-
-signal  LF1     :     std_logic_vector(15 downto 0);
-signal  LF2     :     std_logic_vector(15 downto 0);
-signal  LF3     :     std_logic_vector(15 downto 0);
-
-constant DC1cst :   std_logic_vector(23 downto 0) := X"FA5961";
-constant DC2cst :   std_logic_vector(23 downto 0) := X"123456";
-constant DC3cst :   std_logic_vector(23 downto 0) := X"789012";
-
-constant LF1cst :   std_logic_vector(15 downto 0) := X"3210";
-constant LF2cst :   std_logic_vector(15 downto 0) := X"6543";
-constant LF3cst :   std_logic_vector(15 downto 0) := X"3456";
-
-
-signal  MinFCnt   :   integer range 0 to MinFCount-1;
-
-signal  FramePlacerFlags    :   std_logic_vector(FramePlacerCount-1 downto 0);
-
-begin
-
-Gate_Inv    <=  not Gate;
-sclk_Inv    <=  not Sclk;
-MinF_Inv    <=  not MinF;
-
-DC1 <=  DC1cst;
-DC2 <=  DC2cst;
-DC3 <=  DC3cst;
-
-LF1 <=  LF1cst;
-LF2 <=  LF2cst;
-LF3 <=  LF3cst;
-
-SD0 : entity work.Serial_Driver 
-generic map(WordSize)
-port map(sclk_Inv,MuxOUT,Gate_inv,Data);
-
-WC0 :   entity work.Word_Cntr
-generic map(WordSize,WordCnt)
-port map(sclk_Inv,MinF,WordClk,WordCount);
-
-MFC0 : entity work.MinF_Cntr
-generic map(MinFCount)
-port map(
-    clk     =>  MinF_Inv,
-    reset   =>  MajF,
-    Cnt_out =>  MinFCnt
-);
-
-
-MUX0 : entity work.Serial_Driver_Multiplexor
-generic map(FramePlacerCount,WordSize)
-port map(sclk_Inv,Sel,MuxIN,MuxOUT);
-
-
-DCFP0 : entity work.DC_FRAME_PLACER 
-generic map(WordSize,WordCnt,MinFCount)
-port map(
-    clk     =>  Sclk,
-    Wcount  =>  WordCount,
-    MinFCnt =>  MinFCnt,
-    Flag    =>  FramePlacerFlags(0),
-    DC1     =>  DC1,
-    DC2     =>  DC2,
-    DC3     =>  DC3,
-    WordOut =>  MuxIN(7 downto 0));
-
-
-
-LFP0 : entity  work.LF_FRAME_PLACER
-generic map(WordSize,WordCnt,MinFCount)
-port map(
-    clk     =>  Sclk,
-    Wcount  =>  WordCount,
-    Flag    =>  FramePlacerFlags(1),
-    LF1     =>  LF1,
-    LF2     =>  LF2,
-    LF3     =>  LF3,
-    WordOut =>  MuxIN(15 downto 8));
-
--- FramePlacerFlags(1) <= '0';
--- MuxIN(15 downto 8)  <= (others =>'0');
-
---Input Word Selection Decoder
-
-process(clk)
-variable SelVar :   integer range 0 to 1;
-begin
-    if clk'event and clk ='1' then
-        Decoder: FOR i IN 0 to FramePlacerCount-1 loop
-            if FramePlacerFlags(i) = '1' then
-                SelVar := i;
-            end if;
-        END loop Decoder;
-        Sel <=  SelVar;
-    end if;
-end process;
-
-
-end ar_TOP_Serial_Driver_Wcounter;
-
-
-
-
-
-
-
-
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-
-
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diff --git a/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd b/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Telemetry_config.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
--- Telemetry_config.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-package Telemetry_config is
-
---===========================================================|
---==================== Géné Signaux =========================|
---===========================================================|
-constant Fréq_clk_Hz        : integer := 40000000;
-constant Débit_Hz           : integer := 3300000;
-constant Débit_série_bauds  : integer := 57600;
-constant nb_bits_par_mot    : integer := 8;
-constant nb_mots_par_Minor  : integer := 144;
-constant nb_Minor_par_Major : integer := 64;
-constant nb_mots_total      : integer := nb_mots_par_Minor*nb_Minor_par_Major;
-constant nb_compteur_sclk   : integer := Fréq_clk_Hz / Débit_Hz;
-
-
---===========================================================|
---==================== Entêtes UART =========================|
---===========================================================|
-constant nb_bit_start       : integer := 1;
-constant nb_bit_stop        : integer := 1;
-constant nb_bit_pause       : integer := 3;
-
-
---===========================================================|
---=================== Signal Gate_HF ========================|
---===========================================================|
-constant nb_mots_lgt        : integer := 8;
-constant start_mot          : integer := 6;
-constant lrg_ON             : integer := 2;
-
-
---===========================================================|
---=================== Signal Gate_LF ========================|
---===========================================================|
-type Tbl is array(natural range <>) of integer ;
-constant Tablo : Tbl (0 to 7):= (16,17,20,21,24,25,28,29);
-
-
---===========================================================|
---====================== Pacquage ===========================|
---===========================================================|
-constant Start_1 : std_logic_vector(7 downto 0) := X"0F";
-constant Start_0 : std_logic_vector(7 downto 0) := X"A5";
-constant Stop_1  : std_logic_vector(7 downto 0) := X"5A";
-constant Stop_0  : std_logic_vector(7 downto 0) := X"F0";
-
-
-end;
diff --git a/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Top_Serial_Driver.vhd
+++ /dev/null
@@ -1,42 +0,0 @@
--- Top_Serial_Driver.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity Top_Serial_Driver is
-port(
-    sclk     :   in  std_logic;
-    Gate    :   in  std_logic;
-    MinF    :   in  std_logic;
-    Data    :   out std_logic
-);
-end Top_Serial_Driver;
-
-
-
-
-architecture ar_Top_Serial_Driver of Top_Serial_Driver is
-constant Size   :   integer := 8;
-signal  MinF_Inv    :   std_logic;
-signal  Gate_Inv    :   std_logic;
-signal  sclk_Inv    :   std_logic;
-constant  Word        :   std_logic_vector(Size-1 downto 0) := std_logic_vector(TO_UNSIGNED(165,Size));
-
-
-begin
-MinF_Inv    <=  not MinF;
-Gate_Inv    <=  not Gate;
-sclk_Inv    <=  not Sclk;
-
-
-SD0 : entity work.Serial_Driver 
-generic map(Size)
-port map(
-    sclk_Inv,
-    Word,
-    MinF_Inv,
-    Gate_Inv,
-    Data
-);
-end ar_Top_Serial_Driver;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd b/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Vectorize.vhd
+++ /dev/null
@@ -1,96 +0,0 @@
--- Vectorize.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-
-entity Vectorize is
-
-port(
-    clk,raz     : in std_logic;
-    sclk        : in std_logic;
-    RDY         : in std_logic;
-    In1,In2,In3 : in std_logic;
-    bit         : out std_logic;
-    Vector_1,Vector_2,Vector_3 : out std_logic_vector(23 downto 0));
-
-end Vectorize;
-
-
-architecture ar_Vectorize of Vectorize is
-
-type etat is (e0,e1,e2);
-signal ect      : etat;
-
-signal rdy_reg  : std_logic;
-signal sclk_reg : std_logic;
-signal cpt      : integer range 0 to 24;
-signal Vect_1   : std_logic_vector(23 downto 0);
-signal Vect_2   : std_logic_vector(23 downto 0);
-signal Vect_3   : std_logic_vector(23 downto 0);
-
-begin
-    process(clk,raz)
-    begin
-        if(raz='0')then
-            Vect_1      <= (others => '0');
-            Vect_2      <= (others => '0');
-            Vect_3      <= (others => '0');
-            rdy_reg     <= '1';
-            sclk_reg    <= '0';
-            ect         <= e0;
-            cpt         <= 0;
-            bit <= '0';
-                  
-        elsif(clk'event and clk='1')then
-        rdy_reg     <= RDY;
-        sclk_reg    <= sclk;
-
-            case ect is
-                when e0 =>
-                    if(rdy_reg='0' and RDY='1')then
-                        ect <= e1;
-                    else
-                        ect <= e0;
-                    end if;
-
-                when e1 =>
-                    bit <= '0';
-                    if(sclk_reg='0' and sclk='1')then
-                        Vect_1 <= Vect_1(22 downto 0) & In1;
-                        Vect_2 <= Vect_2(22 downto 0) & In2;
-                        Vect_3 <= Vect_3(22 downto 0) & In3;
-                        if(cpt=23)then
-                            cpt <= 0;
-                            bit  <= '1';
-                            ect <= e0;
-                        else
-                            cpt <= cpt + 1;
-                            ect <= e2;
-                        end if;
-                    end if;
-                
-                when e2 =>
-                    bit <= '0';
-                    if(sclk_reg='0' and sclk='1')then
-                        Vect_1 <= Vect_1(22 downto 0) & In1;
-                        Vect_2 <= Vect_2(22 downto 0) & In2;
-                        Vect_3 <= Vect_3(22 downto 0) & In3;
-                        if(cpt=23)then
-                            cpt <= 0;
-                            bit  <= '1';
-                            ect <= e0;
-                        else
-                            cpt <= cpt + 1;
-                            ect <= e1;
-                        end if;
-                    end if;
-            end case;
-        end if;
-    end process;
-
-Vector_1 <= Vect_1;
-Vector_2 <= Vect_2;
-Vector_3 <= Vect_3;
-
-end ar_Vectorize;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd b/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/Word_Cntr.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
--- Word_Cntr.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-
-
-entity Word_Cntr is
-generic(WordSize :integer := 8 ;N   :   integer := 144);
-port(
-    Sclk    :   in  std_logic;
-    reset   :   in  std_logic;
-    WordClk :   out std_logic;
-    Cnt_out :   out integer range 0 to N-1
-);
-end entity;
-
-
-
-architecture ar_Word_Cntr of Word_Cntr is
-
-signal  Cnt_int     :   integer range 0 to N-1 := 0;
-signal  Wcnt        :   integer range 0 to WordSize -1 ;
-
-begin
-
-Cnt_out <=  Cnt_int;
-
-process(Sclk,reset)
-begin
-    if reset = '0' then
-        Cnt_int <= 0;
-        Wcnt    <=  0;
-        WordClk <=  '0';
-    elsif Sclk'event and Sclk = '1' then
-        if Wcnt = WordSize - 1 then
-            Cnt_int <=  Cnt_int + 1;
-            Wcnt    <=  0;
-            WordClk <=  '1';
-        else
-            Wcnt    <=  Wcnt + 1;
-            WordClk <=  '0';
-        end if;
-    end if;
-end process;
-end ar_Word_Cntr;
-
-
-
-
-
-
-
-
-
-
-
-
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diff --git a/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd b/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/integer_to_clk.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
--- integer_to_clk.vhd
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity integer_to_clk is 
-
-generic(N : integer := 144);
-
-port(
-    clk,raz :   in  std_logic;
-    Compt : in integer range 0 to N;
-    Clock : out std_logic);
-
-end integer_to_clk;
-
-
-architecture ar_integer_to_clk of integer_to_clk is
-
-signal compt_reg : integer range 0 to N;
-signal Clock_int : std_logic;
-
-begin
-    process(clk, raz)
-        begin
-        if (raz='0')then            
-            Clock_int <= '0';
-            compt_reg <= 0;
-            
-        elsif (clk'event and clk='1') then
-        compt_reg <= Compt;
-            if(compt_reg/=Compt)then
-                Clock_int <= not Clock_int;
-            end if;
-        end if;
-    end process;
-
-Clock <= Clock_int;
-end ar_integer_to_clk;
-
-
-
-
-
-
-
-
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd b/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/sys_clock.vhd
+++ /dev/null
@@ -1,44 +0,0 @@
--- sys_clock.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity Sys_Clock is
-
-generic(N :integer := 22);
-
-port( 
-    clk, raz   : in std_logic ;
-    clock       : out std_logic);
-
-end Sys_Clock;
-
-
-architecture ar_Sys_Clock of Sys_Clock is
-
-signal clockint : std_logic;
-signal countint : integer range 0 to N/2-1;
-
-begin 
-    process (clk,raz)
-        begin
-        if(raz = '0') then
-            countint <= 0;
-            clockint <= '0';
-        elsif (clk' event and clk='1') then
-            if (countint = N/2-1) then 
-                countint <= 0;
-                clockint <= not clockint;
-            else 
-                countint <= countint+1;
-            end if;
-        end if;
-    end process;
-
-clock <= clockint;
-
-end ar_Sys_Clock;
-
-
-
diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
--- tb_Serial_Driver.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity tb_Serial_Driver is
-end entity;
-
-
-
-architecture ar_tb_Serial_Driver of tb_Serial_Driver is 
-
-constant Speed  :   integer :=  4*1000*1000;
-constant Tclk   :   time    :=  real(1000*1000*1000/Speed) * 1 ns;
-constant Size   :   integer := 8;
-
-
-signal  sclk        :   std_logic := '0';
-signal  inputDat    :   std_logic_vector(Size-1 downto 0);
-signal  load        :   std_logic:='0';
-signal  Gate        :   std_logic:='0';
-signal  Data        :   std_logic;
-
-begin
-
-SD0 : entity work.Serial_Driver 
-generic map(Size)
-port map(
-    sclk,
-    inputDat,
-    load,
-    Gate,
-    Data
-);
-
-sclk    <=  not sclk after Tclk/2;
-
-
-
-
-
-process
-begin
-
-inputDat    <=  std_logic_vector(TO_UNSIGNED(0,Size));
-wait for 1ns;
-load    <=  '1';
-wait for 1ns;
-load    <=  '0';
-gate    <=  '1';
-wait for Size * Tclk;
-gate    <=  '0';
-wait for 1ns;
-
-
-inputDat    <=  std_logic_vector(TO_UNSIGNED(165,Size));
-wait for 1ns;
-load    <=  '1';
-wait for 1ns;
-load    <=  '0';
-gate    <=  '1';
-wait for Size * Tclk;
-gate    <=  '0';
-wait for 1ns;
-
-
-wait;
-end process;
-
-
-
-end ar_tb_Serial_Driver;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak b/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/tb_Serial_Driver.vhd.bak
+++ /dev/null
@@ -1,73 +0,0 @@
--- tb_Serial_Driver.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity tb_Serial_Driver is
-end entity;
-
-
-
-architecture ar_tb_Serial_Driver of tb_Serial_Driver is 
-
-constant Speed  :   integer :=  4*1000*1000;
-constant Tclk   :   time    :=  real(1000*1000*1000/Speed) * 1 ns;
-constant Size   :   integer := 8;
-
-
-signal  sclk        :   std_logic := '0';
-signal  inputDat    :   std_logic_vector(Size-1 downto 0);
-signal  load        :   std_logic:='0';
-signal  Gate        :   std_logic:='0';
-signal  Data        :   std_logic;
-
-begin
-
-SD0 : entity work.Serial_Driver 
-generic map(Size)
-port map(
-    sclk,
-    inputDat,
-    load,
-    Gate,
-    Data
-);
-
-sclk    <=  not sclk after Tclk/2;
-
-
-
-
-
-process
-begin
-
-inputDat    <=  std_logic_vector(TO_UNSIGNED(0,Size));
-wait for 1ns;
-load    <=  '1';
-wait for 1ns;
-load    <=  '0';
-gate    <=  '1';
-wait for Size * Tclk/2;
-gate    <=  '0';
-wait for 1ns;
-
-
-inputDat    <=  std_logic_vector(TO_UNSIGNED(A5,Size));
-wait for 1ns;
-load    <=  '1';
-wait for 1ns;
-load    <=  '0';
-gate    <=  '1';
-wait for Size * Tclk/2;
-gate    <=  '0';
-wait for 1ns;
-
-
-wait;
-end process;
-
-
-
-end ar_tb_Serial_Driver;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver2.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
--- tb_TOP_Serial_Driver2.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity tb_TOP_Serial_Driver2 is
-end entity;
-
-
-
-architecture ar_tb_TOP_Serial_Driver2 of tb_TOP_Serial_Driver2 is 
-
-constant Speed  :   integer :=  4*1000*1000;
-constant Tclk   :   time    :=  real(1000*1000*1000/Speed) * 1 ns;
-constant Size   :   integer :=  8;
-
-signal  clk         :   std_logic:='0';
-signal  sclk        :   std_logic := '0';
-signal  Gate        :   std_logic:='1';
-signal  Data        :   std_logic;
-
-begin
-
-SD0 : entity work.TOP_Serial_Driver2
-port map(clk,sclk,Gate,Data);
-
-sclk    <=  not sclk after Tclk/2;
-clk     <=  not clk  after 10ns;
-
-
-
-
-process
-begin
-gate    <=  '1';
-wait for 1us;
-gate    <=  '0';
-wait for Size * Tclk;
-gate    <=  '1';
-wait for 1ns;
-
-wait for 1us;
-
-wait for 1ns;
-
-gate    <=  '0';
-wait for Size * Tclk;
-gate    <=  '1';
-wait for 1ns;
-
-gate    <=  '0';
-wait for Size *4* Tclk;
-gate    <=  '1';
-wait for 10us;
-
-
-gate    <=  '0';
-wait for Size *2* Tclk;
-gate    <=  '1';
-wait for 1ns;
-
-
-wait;
-end process;
-
-
-
-end ar_tb_TOP_Serial_Driver2;
\ No newline at end of file
diff --git a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd b/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd
deleted file mode 100644
--- a/designs/ICI4-Integ1/ICI4HDL/tb_TOP_Serial_Driver_Wcounter.vhd
+++ /dev/null
@@ -1,143 +0,0 @@
--- tb_TOP_Serial_Driver_Wcounter.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-
-entity tb_TOP_Serial_Driver_Wcounter is
-end entity;
-
-
-
-architecture ar_tb_TOP_Serial_Driver_Wcounter of tb_TOP_Serial_Driver_Wcounter is 
-
-constant Speed  :   integer :=  4*1000*1000;
-constant Tclk   :   time    :=  real(1000*1000*1000/Speed) * 1 ns;
-constant Size   :   integer :=  8;
-constant MinFCnt:   integer :=  144;
-constant MajFCnt:   integer :=  64;
-
-signal  clk         :   std_logic := '0';
-signal  sclk        :   std_logic := '0';
-signal  Gate        :   std_logic:='1';
-signal  Data        :   std_logic;
-signal  MinF        :   std_logic:='1';
-signal  MajF        :   std_logic:='1';
-signal  flag        :   std_logic;
-
-begin
-
-SD0 : entity work.TOP_Serial_Driver_Wcounter
---generic map(Size,MinFCnt)
-generic map(Size,MinFCnt,MajFCnt)
-port map(clk,sclk,Gate,MinF,MajF,Data);
-
-sclk    <=  not sclk after Tclk/2;
-
-clk    <=  not clk after 20ns;
-
-
-process
-begin
-
-gate <= '1';
-wait for (48)*Tclk;
-gate <= '0';                    --1 ADMLF1.1
-wait for (16)*Tclk;
-gate <= '1';
-wait for (48)*Tclk;
-gate <= '0';                    --2 ADMLF2.1
-wait for (32)*Tclk;
-gate <= '1';
-wait for (16)*Tclk;
-gate <= '0';                    --3 ADMDC1 LSB
-wait for (48)*Tclk;
-gate <= '1';
-wait for (16)*Tclk;
-gate <= '0';                    --4 ADMDC2 LSB
-wait for (32)*Tclk;
-gate <= '1';
-
-
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-wait for (48)*Tclk;
-gate <= '0';     
-wait for (16)*Tclk;
-gate <= '1';  
-end process;
-
-
-
-
-process
-begin
-MinF    <=  '0';
-wait for Tclk;
-MinF    <=  '1';
-wait for (MinFCnt)*(Size)*Tclk-Tclk;
-end process;
-
-
-
-process
-begin
-MajF    <=  '0';
-wait for Tclk;
-MajF    <=  '1';
-wait for (MajFCnt)*(MinFCnt)*(Size)*Tclk-Tclk;
-end process;
-
-
-
-end ar_tb_TOP_Serial_Driver_Wcounter;
\ No newline at end of file