diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
--- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
+++ b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd
@@ -1,93 +1,100 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
-----------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity RAM_CEL is 
-    port( WD : in std_logic_vector(15 downto 0); RD : out
-        std_logic_vector(15 downto 0);WEN, REN : in std_logic;
-        WADDR : in std_logic_vector(7 downto 0); RADDR : in 
-        std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
-        ) ;
-end RAM_CEL;
-
-
-
-architecture ar_RAM_CEL of RAM_CEL is
-type    RAMarrayT   is array (0 to 255) of std_logic_vector(15 downto 0);
-signal  RAMarray           :   RAMarrayT:=(others => X"0000");
-signal  RD_int       :   std_logic_vector(15 downto 0);
-
-begin
-
-RD_int  <=  RAMarray(to_integer(unsigned(RADDR)));
-
-
-process(RWclk,reset)
-begin
-if reset = '0' then
-	RD <= (X"0000");
-rst:for i in 0 to 255 loop
-        RAMarray(i)    <=  (others => '0');
-      end loop;
-
-elsif RWclk'event and RWclk = '1' then
-    if REN = '0' then
-        RD      <=  RD_int;
-    end if;
-
-    if WEN = '0' then
-        RAMarray(to_integer(unsigned(WADDR)))      <=  WD;
-    end if;
-
-end if;
-end process;
-end ar_RAM_CEL;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity RAM_CEL is 
+    generic(DataSz        :   integer range 1 to 32 := 8;
+            abits         :   integer range 2 to 12 := 8);
+    port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
+        std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
+        WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in 
+        std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
+        ) ;
+end RAM_CEL;
+
+
+
+architecture ar_RAM_CEL of RAM_CEL is
+
+constant VectInit : std_logic_vector(DataSz-1 downto 0):=(others => '0');
+constant MAX : integer := 2**(abits);
+
+type    RAMarrayT   is array (0 to MAX-1) of std_logic_vector(DataSz-1 downto 0);
+
+signal  RAMarray           :   RAMarrayT:=(others => VectInit);
+signal  RD_int       :   std_logic_vector(DataSz-1 downto 0);
+
+begin
+
+RD_int  <=  RAMarray(to_integer(unsigned(RADDR)));
+
+
+process(RWclk,reset)
+begin
+if reset = '0' then
+	RD <= VectInit;
+rst:for i in 0 to MAX-1 loop
+        RAMarray(i)    <=  (others => '0');
+      end loop;
+
+elsif RWclk'event and RWclk = '1' then
+    if REN = '0' then
+        RD      <=  RD_int;
+    end if;
+
+    if WEN = '0' then
+        RAMarray(to_integer(unsigned(WADDR)))      <=  WD;
+    end if;
+
+end if;
+end process;
+end ar_RAM_CEL;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd
--- a/lib/lpp/dsp/iir_filter/iir_filter.vhd
+++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd
@@ -203,17 +203,15 @@ PACKAGE iir_filter IS
           ) ;
   END COMPONENT;
 
-  COMPONENT RAM_CEL
-    GENERIC (
-      Sample_SZ : INTEGER);
-    PORT (
-      WD           : IN  STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
-      RD           : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
-      WEN, REN     : IN  STD_LOGIC;
-      WADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
-      RADDR        : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
-      RWCLK, RESET : IN  STD_LOGIC);
-  END COMPONENT;
+COMPONENT RAM_CEL is
+    generic(DataSz        :   integer range 1 to 32 := 8;
+            abits         :   integer range 2 to 12 := 8);
+    port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
+        std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
+        WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in 
+        std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
+        ) ;
+end COMPONENT;
 
   COMPONENT RAM_CEL_N
     GENERIC (
diff --git a/lib/lpp/lpp_Header/HeaderBuilder.vhd b/lib/lpp/lpp_Header/HeaderBuilder.vhd
--- a/lib/lpp/lpp_Header/HeaderBuilder.vhd
+++ b/lib/lpp/lpp_Header/HeaderBuilder.vhd
@@ -57,21 +57,29 @@ signal Matrix_Param     : std_logic_vect
 signal Write_reg : std_logic;
 signal Data_cpt : integer;
 signal MAX : integer;
+signal pong_reg : std_logic;
 
+type etat is (idle0,idle1,pong0,pong1);
+signal ect : etat;
 
 begin
 
  process (clkm,rstn)
     begin
         if(rstn='0')then
+            ect <= idle0;
             Valid <= '0';
+            pong_reg <= '0';
+            header_val <= '0';
+            header(5 downto 0) <= (others => '0');
             Write_reg    <= '0';
             Data_cpt <= 0;
-            MAX <= 0;
+            MAX <= 128;
 
             
         elsif(clkm' event and clkm='1')then
             Write_reg <= Matrix_Write;
+            pong_reg <= pong;
 
             if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
                 MAX <= 128;
@@ -79,33 +87,102 @@ begin
                 MAX <= 256;
             end if;
 
-            if(Write_reg = '0' and Matrix_Write = '1')then
-                if(Data_cpt = MAX)then
-                    Data_cpt <= 0;
-                    Valid <= '1';
-                    header_val <= '1';
-                else
-                    Data_cpt <= Data_cpt + 1;
-                    Valid <= '0';
-                end if;
+--            if(Write_reg = '0' and Matrix_Write = '1')then
+--                if(Data_cpt = MAX)then
+--                    Data_cpt <= 0;
+--                    Valid <= '1';
+--                    header_val <= '1';
+--                else
+--                    Data_cpt <= Data_cpt + 1;
+--                    Valid <= '0';
+--                end if;
+--            end if;
+
+            if(Write_reg = '0' and Matrix_Write = '1')then     
+                Data_cpt <= Data_cpt + 1;
+                Valid <= '0';
+            elsif(Data_cpt = MAX)then
+                Data_cpt <= 0;
+                Valid <= '1';
+                header_val <= '1';
+            else
+                Valid <= '0';
             end if;
 
-            if(header_ack = '1')then
-                header_val <= '0';
-            end if;
-              
+--            if(header_ack = '1')then
+--                header_val <= '0';
+--            end if;
+            
+--            if(emptyIN = "10")then
+--                ping <= '0';
+--            elsif(emptyIN = "01")then
+--                ping <= '1';
+--            else
+--                ping <= ping;
+--            end if;
+
+
+            case ect is
+
+                when idle0 =>
+                    if(header_ack = '1')then
+                        header_val <= '0';
+                        --if(pong = '1')then
+                            ect <= pong0;
+                        --elsif(pong = '0')then
+                            --ect <= pong1;
+                        --end if;
+                    end if;
+
+                when pong0 =>
+                    header(1 downto 0) <= Matrix_Type;
+                    header(5 downto 2) <= Matrix_Param;
+                    if(emptyIN(0) = '1')then
+                        ect <= idle1;
+                    end if;                  
+
+                when idle1 =>
+                     if(header_ack = '1')then
+                        header_val <= '0';
+                        ect <= pong1;
+                     end if;
+
+                when pong1 =>
+                    header(1 downto 0) <= Matrix_Type;
+                    header(5 downto 2) <= Matrix_Param;
+                    if(emptyIN(1) = '1')then
+                        ect <= idle0;
+                    end if;
+
+            end case;
         end if;
     end process;
 
 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
 
-header(1 downto 0) <= Matrix_Type;
-header(5 downto 2) <= Matrix_Param;
+--header(1 downto 0) <= Matrix_Type;
+--header(5 downto 2) <= Matrix_Param;
 header(31 downto 6) <= (others => '0');
 
-dataOUT <= dataIN(Data_sz-1 downto 0) when pong = '0' else dataIN((2*Data_sz)-1 downto Data_sz);
-emptyOUT <= emptyIN(0) when pong = '0' else emptyIN(1);
+with ect select
+    dataOUT <= dataIN(Data_sz-1 downto 0)           when pong0,
+               dataIN(Data_sz-1 downto 0)           when idle0,
+               dataIN((2*Data_sz)-1 downto Data_sz) when pong1,
+               dataIN((2*Data_sz)-1 downto Data_sz) when idle1,
+               (others => '0')                      when others;
 
-RenOUT <= '1' & RenIN when pong = '0' else RenIN & '1';
+with ect select
+    emptyOUT    <= emptyIN(0)   when pong0,
+                   emptyIN(0)   when idle0,
+                   emptyIN(1)   when pong1,
+                   emptyIN(1)   when idle1,
+                   '1'          when others;
+
+with ect select 
+    RenOUT  <= '1' & RenIN  when pong0,
+               '1' & RenIN  when idle0,
+               RenIN & '1'  when pong1,
+               RenIN & '1'  when idle1,
+               "11"         when others;
 
 end architecture;
diff --git a/lib/lpp/lpp_dma/lpp_dma_ip.vhd b/lib/lpp/lpp_dma/lpp_dma_ip.vhd
--- a/lib/lpp/lpp_dma/lpp_dma_ip.vhd
+++ b/lib/lpp/lpp_dma/lpp_dma_ip.vhd
@@ -103,6 +103,7 @@ ARCHITECTURE Behavioral OF lpp_dma_ip IS
   -----------------------------------------------------------------------------
   -----------------------------------------------------------------------------
   TYPE state_DMAWriteBurst IS (IDLE,
+                               CHECK_COMPONENT_TYPE,
                                TRASH_FIFO,
                                WAIT_HEADER_ACK,
                                SEND_DATA,
@@ -182,8 +183,7 @@ BEGIN
   END PROCESS debug_info;
     
   
-  matrix_type    <= header(1 DOWNTO 0);
-  component_type <= header(5 DOWNTO 2);
+
 
   send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
                  '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
@@ -191,8 +191,8 @@ BEGIN
                  '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0'   ELSE
                  '0';
   
-  header_check_ok <= '0' WHEN component_type = "1111" ELSE
-                     '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
+  header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
+                     '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
                      '1' WHEN component_type = component_type_pre + "0001"            ELSE
                      '0';
 
@@ -208,6 +208,8 @@ BEGIN
   DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
   BEGIN  -- PROCESS DMAWriteBurst_p
     IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
+      matrix_type    <= (others => '0');
+      component_type <= (others => '0');
       state                         <= IDLE;
       header_ack                    <= '0';
       ready_matrix_f0_0             <= '0';
@@ -216,7 +218,7 @@ BEGIN
       ready_matrix_f2               <= '0';
       error_anticipating_empty_fifo <= '0';
       error_bad_component_error     <= '0';
-      component_type_pre            <= "1110";
+      component_type_pre            <= "0000";
       fifo_ren_trash                <= '1';
       component_send                <= '0';
       address                       <= (OTHERS => '0');
@@ -226,7 +228,10 @@ BEGIN
     ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
 
       CASE state IS
-        WHEN IDLE =>
+        WHEN IDLE =>    
+          matrix_type    <= header(1 DOWNTO 0);
+          --component_type <= header(5 DOWNTO 2);
+
           ready_matrix_f0_0 <= '0';
           ready_matrix_f0_1 <= '0';
           ready_matrix_f1   <= '0';
@@ -234,9 +239,14 @@ BEGIN
           error_bad_component_error <= '0';
           header_select                    <= '1';
           IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
+              matrix_type        <= header(1 DOWNTO 0);
+              component_type     <= header(5 DOWNTO 2);
+              component_type_pre <= component_type;
+              state <= CHECK_COMPONENT_TYPE;
+          END IF;
+        
+        WHEN CHECK_COMPONENT_TYPE =>
             IF header_check_ok = '1' THEN
-              header_data        <= header;
-              component_type_pre <= header(5 DOWNTO 2);
               header_ack         <= '1';
               --
               header_send        <= '1';
@@ -247,14 +257,15 @@ BEGIN
               --
               state       <= WAIT_HEADER_ACK;
             ELSE
-              error_bad_component_error <= '1';
-              component_type_pre               <= "1110";
+              error_bad_component_error        <= '1';
+              component_type_pre               <= "0000";
               header_ack                       <= '1';
               state                            <= TRASH_FIFO;
             END IF;
-          END IF;
+
 
         WHEN TRASH_FIFO =>
+          header_ack  <= '0';
           error_bad_component_error <= '0';
           error_anticipating_empty_fifo <= '0';
           IF fifo_empty = '1' THEN
@@ -263,8 +274,9 @@ BEGIN
           ELSE
             fifo_ren_trash <= '0';
           END IF;
-          
+
         WHEN WAIT_HEADER_ACK =>
+          header_ack  <= '0';
           header_send <= '0';
           IF header_send_ko = '1' THEN
             state <= TRASH_FIFO;
@@ -279,7 +291,7 @@ BEGIN
         WHEN SEND_DATA =>
           IF fifo_empty = '1' THEN
             state <= IDLE;
-            IF component_type = "1110" THEN
+            IF component_type = "1110" THEN   --"1110" -- JC
               CASE matrix_type IS
                 WHEN "00"  => ready_matrix_f0_0 <= '1';
                 WHEN "01"  => ready_matrix_f0_1 <= '1';
@@ -287,6 +299,7 @@ BEGIN
                 WHEN "11"  => ready_matrix_f2   <= '1';
                 WHEN OTHERS => NULL;
               END CASE;
+
             END IF;
           ELSE
             component_send <= '1';
diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd
--- a/lib/lpp/lpp_memory/APB_FIFO.vhd
+++ b/lib/lpp/lpp_memory/APB_FIFO.vhd
@@ -1,263 +1,264 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-------------------------------------------------------------------------------
---                        Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
-------------------------------------------------------------------------------
--- APB_FIFO.vhd
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library techmap;
-use techmap.gencomp.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-use lpp.lpp_memory.all;
-
-
-entity APB_FIFO is
-generic (
-    tech           : integer := apa3;
-    pindex         : integer := 0;
-    paddr          : integer := 0;
-    pmask          : integer := 16#fff#;
-    pirq           : integer := 0;
-    abits          : integer := 8;
-    FifoCnt        : integer := 2;
-    Data_sz        : integer := 16;
-    Addr_sz        : integer := 9;
-    Enable_ReUse   : std_logic := '0';
-    R              : integer := 1;
-    W              : integer := 1
-    );
-  port (
-    clk          : in  std_logic;                              --! Horloge du composant
-    rst          : in  std_logic;                              --! Reset general du composant
-    rclk         : in  std_logic; 
-    wclk         : in  std_logic;
-    ReUse        : in  std_logic_vector(FifoCnt-1 downto 0);
-    REN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en mémoire
-    WEN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'écriture en mémoire
-    Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire vide
-    Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire pleine
-    RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de données en entrée
-    WDATA        : in  std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de données en sortie
-    WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (écriture)
-    RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
-    apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entrées du bus
-    apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
-    );
-end entity;
-
-architecture ar_APB_FIFO of APB_FIFO is
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-type FIFO_ctrlr_Reg is record
-     FIFO_Ctrl  : std_logic_vector(31 downto 0);
-     FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
-     FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
-end record;
-
-type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
-type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); 
-type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); 
-
-signal Rec           : FIFO_ctrlr_Reg_Vec;
-signal PRdata        : std_logic_vector(31 downto 0);
-signal FIFO_ID       : std_logic_vector(31 downto 0);
-signal autoloaded    : std_logic_vector(FifoCnt-1 downto 0);
-signal sFull         : std_logic_vector(FifoCnt-1 downto 0);
-signal sEmpty        : std_logic_vector(FifoCnt-1 downto 0);
-signal sEmpty_d      : std_logic_vector(FifoCnt-1 downto 0);
-signal sWen          : std_logic_vector(FifoCnt-1 downto 0);
-signal sRen          : std_logic_vector(FifoCnt-1 downto 0);
-signal sRclk         : std_logic;
-signal sWclk         : std_logic;
-signal sWen_APB      : std_logic_vector(FifoCnt-1 downto 0);
-signal sRen_APB      : std_logic_vector(FifoCnt-1 downto 0);
-signal sRDATA        : fifodatabus;
-signal sWDATA        : fifodatabus;
-signal sWADDR        : fifoaddressbus;
-signal sRADDR        : fifoaddressbus;
-signal sReUse        : std_logic_vector(FifoCnt-1 downto 0);
-signal sReUse_APB    : std_logic_vector(FifoCnt-1 downto 0);
-
-signal regDataValid  : std_logic_vector(FifoCnt-1 downto 0);
-signal regData       : fifodatabus;
-signal regREN        : std_logic_vector(FifoCnt-1 downto 0);
-
-type state_t is (idle,Read);
-signal fiforeadfsmst : state_t;
-
-begin
-
-FIFO_ID(3 downto 0)     <= std_logic_vector(to_unsigned(FifoCnt,4));
-FIFO_ID(15 downto 8)    <= std_logic_vector(to_unsigned(Data_sz,8));
-FIFO_ID(23 downto 16)   <= std_logic_vector(to_unsigned(Addr_sz,8));
-
-
-Writeint : if W /= 0 generate
-    FIFO_ID(4) <= '1';
-    sWen   <= sWen_APB;
-    sReUse <= sReUse_APB;
-    sWclk  <=  clk;
-    Wrapb: for i in 0 to FifoCnt-1 generate
-        sWDATA(i) <= Rec(i).FIFO_Wdata;
-    end generate;
-end generate;
-
-Writeext : if W = 0 generate 
-    FIFO_ID(4) <= '0';
-    sWen   <=  WEN;
-    sReUse <= ReUse;
-    sWclk  <=  Wclk;
-    Wrext: for i in 0 to FifoCnt-1 generate
-        sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
-    end generate;
-end generate;
-
-Readint : if R /= 0 generate 
- FIFO_ID(5) <= '1';
- sRen   <=  sRen_APB;
- srclk  <=  clk;
- Rdapb: for i in 0 to FifoCnt-1 generate
-        Rec(i).FIFO_Rdata  <= sRDATA(i);
- end generate;
-end generate;
-
-Readext : if R = 0 generate 
-    FIFO_ID(5) <= '0';
-    sRen   <=  REN;
-    srclk  <=  rclk;
-    Drext: for i in 0 to FifoCnt-1 generate
-        RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i)  <= sRDATA(i);
-    end generate;
-end generate;
-
-ctrlregs: for i in 0 to FifoCnt-1 generate
-    RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
-    WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
-    Rec(i).FIFO_Ctrl(16) <= sFull(i);
-    sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
-    Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
-    Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
-    Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
-    Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
-end generate;
-
-Empty <= sEmpty;
-Full <= sFull;
-
-fifos: for i in 0 to FifoCnt-1 generate
-    FIFO0 : lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
-        port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
-end generate;
-
-    process(rst,clk)
-    begin
-        if(rst='0')then
-        rstloop1: for i in 0 to FifoCnt-1 loop
-            Rec(i).FIFO_Wdata <=  (others => '0');
-            Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
-            sWen_APB(i) <= '1';
-        end loop;
-        elsif(clk'event and clk='1')then
-
-    --APB Write OP
-            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-                   writelp: for i in 0 to FifoCnt-1 loop
-                        if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
-                            Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
-                        elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
-                            Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
-                            sWen_APB(i) <= '0';
-                        end if;
-                   end loop; 
-            else
-                sWen_APB <= (others =>'1');
-            end if;
-
- --APB Read OP
-            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-               if(apbi.paddr(abits-1 downto 2)="000000") then
-                    PRdata   <= FIFO_ID;
-                else
-                   readlp: for i in 0 to FifoCnt-1 loop  
-                        if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
-                            PRdata   <= Rec(i).FIFO_Ctrl;
-                        elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
-                            PRdata(Data_sz-1 downto 0)  <= Rec(i).FIFO_rdata;
-                        end if;
-                   end loop;
-                end if;
-            end if;
-    end if;
-
-    apbo.pconfig <= pconfig;
-
-end process;
-apbo.prdata     <=   PRdata when apbi.penable = '1';
-
-process(rst,clk)
-    begin
-        if(rst='0')then
-            fiforeadfsmst   <= idle;
-            rstloop: for i in 0 to FifoCnt-1 loop
-                sRen_APB(i) <= '1';
-                autoloaded(i)  <= '1';
-                Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
-            end loop;
-        elsif clk'event and clk = '1' then
-            sEmpty_d    <= sEmpty;
-            case fiforeadfsmst is
-                when idle =>
-                    idlelp: for i in 0 to FifoCnt-1 loop
-                        if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
-                            if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
-                                 autoloaded(i)  <= '0';
-                            else 
-                                 autoloaded(i)  <= '1';
-                            end if;
-                            sRen_APB(i) <= '0';
-                            fiforeadfsmst   <= read;
-                            Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
-                        else
-                            sRen_APB(i) <= '1';
-                        end if;
-                    end loop;
-                when read =>
-                    sRen_APB        <= (others => '1');
-                    fiforeadfsmst   <= idle;
-                when others =>
-                    fiforeadfsmst <= idle;
-            end case;
-        end if;
-end process; 
-
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+------------------------------------------------------------------------------
+--                        Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+-- APB_FIFO.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library techmap;
+use techmap.gencomp.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library lpp;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+use lpp.lpp_memory.all;
+use lpp.iir_filter.all;
+
+entity APB_FIFO is
+generic (
+    tech           : integer := apa3;
+    pindex         : integer := 0;
+    paddr          : integer := 0;
+    pmask          : integer := 16#fff#;
+    pirq           : integer := 0;
+    abits          : integer := 8;
+    FifoCnt        : integer := 2;
+    Data_sz        : integer := 16;
+    Addr_sz        : integer := 9;
+    Enable_ReUse   : std_logic := '0';
+    Mem_use        : integer := use_RAM;
+    R              : integer := 1;
+    W              : integer := 1
+    );
+  port (
+    clk          : in  std_logic;                              --! Horloge du composant
+    rst          : in  std_logic;                              --! Reset general du composant
+    rclk         : in  std_logic; 
+    wclk         : in  std_logic;
+    ReUse        : in  std_logic_vector(FifoCnt-1 downto 0);
+    REN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en mémoire
+    WEN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'écriture en mémoire
+    Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire vide
+    Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire pleine
+    RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de données en entrée
+    WDATA        : in  std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de données en sortie
+    WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (écriture)
+    RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
+    apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entrées du bus
+    apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
+    );
+end entity;
+
+architecture ar_APB_FIFO of APB_FIFO is
+
+constant REVISION : integer := 1;
+
+constant pconfig : apb_config_type := (
+  0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
+  1 => apb_iobar(paddr, pmask));
+
+type FIFO_ctrlr_Reg is record
+     FIFO_Ctrl  : std_logic_vector(31 downto 0);
+     FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
+     FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
+end record;
+
+type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
+type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); 
+type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); 
+
+signal Rec           : FIFO_ctrlr_Reg_Vec;
+signal PRdata        : std_logic_vector(31 downto 0);
+signal FIFO_ID       : std_logic_vector(31 downto 0);
+signal autoloaded    : std_logic_vector(FifoCnt-1 downto 0);
+signal sFull         : std_logic_vector(FifoCnt-1 downto 0);
+signal sEmpty        : std_logic_vector(FifoCnt-1 downto 0);
+signal sEmpty_d      : std_logic_vector(FifoCnt-1 downto 0);
+signal sWen          : std_logic_vector(FifoCnt-1 downto 0);
+signal sRen          : std_logic_vector(FifoCnt-1 downto 0);
+signal sRclk         : std_logic;
+signal sWclk         : std_logic;
+signal sWen_APB      : std_logic_vector(FifoCnt-1 downto 0);
+signal sRen_APB      : std_logic_vector(FifoCnt-1 downto 0);
+signal sRDATA        : fifodatabus;
+signal sWDATA        : fifodatabus;
+signal sWADDR        : fifoaddressbus;
+signal sRADDR        : fifoaddressbus;
+signal sReUse        : std_logic_vector(FifoCnt-1 downto 0);
+signal sReUse_APB    : std_logic_vector(FifoCnt-1 downto 0);
+
+signal regDataValid  : std_logic_vector(FifoCnt-1 downto 0);
+signal regData       : fifodatabus;
+signal regREN        : std_logic_vector(FifoCnt-1 downto 0);
+
+type state_t is (idle,Read);
+signal fiforeadfsmst : state_t;
+
+begin
+
+FIFO_ID(3 downto 0)     <= std_logic_vector(to_unsigned(FifoCnt,4));
+FIFO_ID(15 downto 8)    <= std_logic_vector(to_unsigned(Data_sz,8));
+FIFO_ID(23 downto 16)   <= std_logic_vector(to_unsigned(Addr_sz,8));
+
+
+Writeint : if W /= 0 generate
+    FIFO_ID(4) <= '1';
+    sWen   <= sWen_APB;
+    sReUse <= sReUse_APB;
+    sWclk  <=  clk;
+    Wrapb: for i in 0 to FifoCnt-1 generate
+        sWDATA(i) <= Rec(i).FIFO_Wdata;
+    end generate;
+end generate;
+
+Writeext : if W = 0 generate 
+    FIFO_ID(4) <= '0';
+    sWen   <=  WEN;
+    sReUse <= ReUse;
+    sWclk  <=  Wclk;
+    Wrext: for i in 0 to FifoCnt-1 generate
+        sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
+    end generate;
+end generate;
+
+Readint : if R /= 0 generate 
+ FIFO_ID(5) <= '1';
+ sRen   <=  sRen_APB;
+ srclk  <=  clk;
+ Rdapb: for i in 0 to FifoCnt-1 generate
+        Rec(i).FIFO_Rdata  <= sRDATA(i);
+ end generate;
+end generate;
+
+Readext : if R = 0 generate 
+    FIFO_ID(5) <= '0';
+    sRen   <=  REN;
+    srclk  <=  rclk;
+    Drext: for i in 0 to FifoCnt-1 generate
+        RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i)  <= sRDATA(i);
+    end generate;
+end generate;
+
+ctrlregs: for i in 0 to FifoCnt-1 generate
+    RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
+    WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
+    Rec(i).FIFO_Ctrl(16) <= sFull(i);
+    sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
+    Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
+    Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
+    Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
+    Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
+end generate;
+
+Empty <= sEmpty;
+Full <= sFull;
+
+fifos: for i in 0 to FifoCnt-1 generate
+    FIFO0 : lpp_fifo
+        generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
+        port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
+end generate;
+
+    process(rst,clk)
+    begin
+        if(rst='0')then
+        rstloop1: for i in 0 to FifoCnt-1 loop
+            Rec(i).FIFO_Wdata <=  (others => '0');
+            Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
+            sWen_APB(i) <= '1';
+        end loop;
+        elsif(clk'event and clk='1')then
+
+    --APB Write OP
+            if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
+                   writelp: for i in 0 to FifoCnt-1 loop
+                        if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
+                            Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
+                        elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
+                            Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
+                            sWen_APB(i) <= '0';
+                        end if;
+                   end loop; 
+            else
+                sWen_APB <= (others =>'1');
+            end if;
+
+ --APB Read OP
+            if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
+               if(apbi.paddr(abits-1 downto 2)="000000") then
+                    PRdata   <= FIFO_ID;
+                else
+                   readlp: for i in 0 to FifoCnt-1 loop  
+                        if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
+                            PRdata   <= Rec(i).FIFO_Ctrl;
+                        elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
+                            PRdata(Data_sz-1 downto 0)  <= Rec(i).FIFO_rdata;
+                        end if;
+                   end loop;
+                end if;
+            end if;
+    end if;
+
+    apbo.pconfig <= pconfig;
+
+end process;
+apbo.prdata     <=   PRdata when apbi.penable = '1';
+
+process(rst,clk)
+    begin
+        if(rst='0')then
+            fiforeadfsmst   <= idle;
+            rstloop: for i in 0 to FifoCnt-1 loop
+                sRen_APB(i) <= '1';
+                autoloaded(i)  <= '1';
+                Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
+            end loop;
+        elsif clk'event and clk = '1' then
+            sEmpty_d    <= sEmpty;
+            case fiforeadfsmst is
+                when idle =>
+                    idlelp: for i in 0 to FifoCnt-1 loop
+                        if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
+                            if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
+                                 autoloaded(i)  <= '0';
+                            else 
+                                 autoloaded(i)  <= '1';
+                            end if;
+                            sRen_APB(i) <= '0';
+                            fiforeadfsmst   <= read;
+                            Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
+                        else
+                            sRen_APB(i) <= '1';
+                        end if;
+                    end loop;
+                when read =>
+                    sRen_APB        <= (others => '1');
+                    fiforeadfsmst   <= idle;
+                when others =>
+                    fiforeadfsmst <= idle;
+            end case;
+        end if;
+end process; 
+
 end ar_APB_FIFO;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/Bridge.vhd b/lib/lpp/lpp_memory/Bridge.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_memory/Bridge.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- Bridge.vhd
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Bridge is
-    port(
-        clk         : in std_logic;
-        raz        : in std_logic;
-        EmptyUp : in std_logic;
-        FullDwn : in std_logic;
-        WriteDwn : out std_logic;
-        ReadUp : out std_logic
-        );
-end entity;
-
-
-architecture ar_Bridge of Bridge is
-
-type etat is (e0,e1);
-signal ect : etat;
-
-begin
-
-    process(clk,raz)
-    begin
-        if(raz='0')then 
-            WriteDwn    <= '1';
-            ReadUp      <= '1';
-            ect         <= e0;
-
-        elsif(clk'event and clk='1')then
-
-            case ect is
-
-                when e0 =>
-                    WriteDwn    <= '1';
-                    if(EmptyUp='0' and FullDwn='0')then
-                        ReadUp      <= '0';
-                        ect         <= e1;
-                    end if;
-
-                when e1 =>
-                    ReadUp      <= '1';
-                    WriteDwn    <= '0';
-                    ect         <= e0; 
-                           
-            end case;                
-   
-        end if;
-    end process;
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/FillFifo.vhd b/lib/lpp/lpp_memory/FillFifo.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_memory/FillFifo.vhd
@@ -0,0 +1,90 @@
+-- FillFifo.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity FillFifo is
+generic(
+    Data_sz  : integer range 1 to 32 := 16;
+    Fifo_cnt : integer range 1 to 8 := 5
+    );
+port(
+    clk         : in std_logic;
+    raz        : in std_logic;
+    write : out std_logic_vector(Fifo_cnt-1 downto 0);
+    reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
+    data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
+);
+end entity;
+
+
+architecture ar_FillFifo of FillFifo is
+
+signal i : integer := 0;
+
+type etat is (eX,e0,e00);
+signal ect : etat;
+
+type Tbl is array(natural range <>) of std_logic_vector(Data_sz-1 downto 0);
+
+--constant TblA : Tbl (0 to 255) := (X"FFFF",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B",X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE",X"0000",X"0142",X"0282",X"03C2",X"04FF",X"0638",X"076E",X"08A0",X"09CC",X"0AF2",X"0C11",X"0D29",X"0E39",X"0F40",X"103E",X"1131",X"121A",X"12F8",X"13CA",X"1490",X"1549",X"15F5",X"1694",X"1724",X"17A7",X"181B",X"187F",X"18D5",X"191C",X"1953",X"197A",X"1992",X"199A",X"1992",X"197A",X"1953",X"191C",X"18D5",X"187F",X"181B",X"17A7",X"1724",X"1694",X"15F5",X"1549",X"1490",X"13CA",X"12F8",X"121A",X"1131",X"103E",X"0F40",X"0E39",X"0D29",X"0C11",X"0AF2",X"09CC",X"08A0",X"076E",X"0638",X"04FF",X"03C2",X"0282",X"0142",X"0000",X"FEBE",X"FD7E",X"FC3E",X"FB01",X"F9C8",X"F892",X"F760",X"F634",X"F50E",X"F3EF",X"F2D7",X"F1C7",X"F0C0",X"EFC2",X"EECF",X"EDE6",X"ED08",X"EC36",X"EB70",X"EAB7",X"EA0B",X"E96C",X"E8DC",X"E859",X"E7E5",X"E781",X"E72B", 
+--X"E6E4",X"E6AD",X"E686",X"E66E",X"E666",X"E66E",X"E686",X"E6AD",X"E6E4",X"E72B",X"E781",X"E7E5",X"E859",X"E8DC",X"E96C",X"EA0B",X"EAB7",X"EB70",X"EC36",X"ED08",X"EDE6",X"EECF",X"EFC2",X"F0C0",X"F1C7",X"F2D7",X"F3EF",X"F50E",X"F634",X"F760",X"F892",X"F9C8",X"FB01",X"FC3E",X"FD7E",X"FEBE");
+
+constant TblA : Tbl (0 to 255) := (X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
+
+constant TblB : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
+
+constant TblC : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
+
+constant TblD : Tbl (0 to 255) := (X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
+
+constant TblE : Tbl (0 to 255) := (X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",
+X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"1FFF",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001",X"0001");
+
+begin
+
+    process(clk,raz)
+    begin
+        if(raz='0')then 
+            i <= 0;
+            Write <= (others => '1');
+            Reuse <= (others => '0');
+            ect <= e00;
+            
+        elsif(clk'event and clk='1')then
+
+            case ect is
+
+                when e00 =>
+                    Write <= (others => '0');
+                    ect <= e0;                                  
+
+                when e0 =>                    
+                    if(i=255)then
+                        Write <= (others => '1');
+                        Reuse <= (others => '1');
+                        ect <= eX;
+                    else
+                        i <= i+1;
+                        ect <= e0;
+                    end if;
+
+                when eX =>
+                    null; 
+
+            end case;
+        end if;
+    end process;
+
+data <= TblE(i) & TblD(i) & TblC(i) & TblB(i) & TblA(i);
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/lppFIFOx5.vhd b/lib/lpp/lpp_memory/lppFIFOx5.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_memory/lppFIFOx5.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library lpp;
-use lpp.lpp_memory.all;
-library techmap;
-use techmap.gencomp.all;
-
-entity lppFIFOx5 is
-generic(
-    tech          :   integer := 0;
-    Data_sz       :   integer range 1 to 32 := 8;
-    Enable_ReUse  :   std_logic := '0'
-    );
-port(
-    rst     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(4 downto 0);
-    wen     :   in std_logic_vector(4 downto 0); 
-    ren     :   in std_logic_vector(4 downto 0);
-    wdata   :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((5*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(4 downto 0);
-    empty   :   out std_logic_vector(4 downto 0)    
-);
-end entity;
-
-
-architecture ar_lppFIFOx5 of lppFIFOx5 is
-
-begin
-
-    fifoB1 : entity work.lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
-        port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
-
-    fifoB2 : entity work.lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
-        port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
-
-    fifoB3 : entity work.lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
-        port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
-
-    fifoE1 : entity work.lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
-        port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
-
-    fifoE2 : entity work.lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,8)
-        port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
-
-
-end architecture;
-
diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd
--- a/lib/lpp/lpp_memory/lppFIFOxN.vhd
+++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd
@@ -1,64 +1,66 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-library lpp;
-use lpp.lpp_memory.all;
-library techmap;
-use techmap.gencomp.all;
-
-entity lppFIFOxN is
-generic(
-    tech          :   integer := 0;
-    Data_sz       :   integer range 1 to 32 := 8;
-    Addr_sz       :   integer range 1 to 32 := 8;
-    FifoCnt : integer := 1;
-    Enable_ReUse  :   std_logic := '0'
-    );
-port(
-    rst     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
-    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
-    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
-    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(FifoCnt-1 downto 0);
-    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
-);
-end entity;
-
-
-architecture ar_lppFIFOxN of lppFIFOxN is
-
-begin
-
-fifos: for i in 0 to FifoCnt-1 generate
-    FIFO0 : lpp_fifo
-        generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
-        port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
-end generate;
-
-end architecture;
-
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                     Mail : martin.morlot@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library lpp;
+use lpp.lpp_memory.all;
+use lpp.iir_filter.all;
+library techmap;
+use techmap.gencomp.all;
+
+entity lppFIFOxN is
+generic(
+    tech          :   integer := 0;
+    Mem_use       :   integer := use_RAM;
+    Data_sz       :   integer range 1 to 32 := 8;
+    Addr_sz       :   integer range 1 to 32 := 8;
+    FifoCnt : integer := 1;
+    Enable_ReUse  :   std_logic := '0'
+    );
+port(
+    rst     :   in std_logic;
+    wclk    :   in std_logic;    
+    rclk    :   in std_logic;
+    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
+    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
+    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
+    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
+    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
+    full    :   out std_logic_vector(FifoCnt-1 downto 0);
+    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
+);
+end entity;
+
+
+architecture ar_lppFIFOxN of lppFIFOxN is
+
+begin
+
+fifos: for i in 0 to FifoCnt-1 generate
+    FIFO0 : lpp_fifo
+        generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
+        port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
+end generate;
+
+end architecture;
+
diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd
--- a/lib/lpp/lpp_memory/lpp_FIFO.vhd
+++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd
@@ -31,6 +31,7 @@ use techmap.gencomp.all;
 entity lpp_fifo is
 generic(
     tech          :   integer := 0;
+    Mem_use       :   integer := use_RAM;
     Enable_ReUse  :   std_logic := '0';
     DataSz        :   integer range 1 to 32 := 8;
     abits         :   integer range 2 to 12 := 8
@@ -75,12 +76,17 @@ begin
 -- /!\ syncram_2p Write et Read actif a l'état haut /!\
 -- A l'inverse de RAM_CEL !!!
 --==================================================================================
-SRAM : syncram_2p
-    generic map(tech,abits,DataSz)
-    port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
+memRAM : IF Mem_use = use_RAM GENERATE
+  SRAM : syncram_2p
+      generic map(tech,abits,DataSz)
+      port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
+END GENERATE;
 --================================================================================== 
---RAM0: entity work.RAM_CEL
---    port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
+memCEL : IF Mem_use = use_CEL GENERATE
+  CRAM : RAM_CEL
+      generic map(DataSz,abits)
+      port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
+END GENERATE;
 --================================================================================== 
 
 --=============================
diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd
--- a/lib/lpp/lpp_memory/lpp_memory.vhd
+++ b/lib/lpp/lpp_memory/lpp_memory.vhd
@@ -1,177 +1,163 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-library gaisler;
-use gaisler.misc.all;
-use gaisler.memctrl.all;
-library techmap;
-use techmap.gencomp.all;
-
---! Package contenant tous les programmes qui forment le composant intégré dans le léon 
-
-package lpp_memory is
-
-component APB_FIFO is
-generic (
-    tech         : integer := apa3;
-    pindex       : integer := 0;
-    paddr        : integer := 0;
-    pmask        : integer := 16#fff#;
-    pirq         : integer := 0;
-    abits        : integer := 8;
-    FifoCnt      : integer := 2;
-    Data_sz      : integer := 16;
-    Addr_sz        : integer := 9;
-    Enable_ReUse   : std_logic := '0';
-    R            : integer := 1;
-    W            : integer := 1
-    );
-  port (
-    clk          : in  std_logic;                              --! Horloge du composant
-    rst          : in  std_logic;                              --! Reset general du composant
-    rclk         : in  std_logic; 
-    wclk         : in  std_logic;
-    ReUse        : in  std_logic_vector(FifoCnt-1 downto 0);
-    REN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en mémoire
-    WEN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'écriture en mémoire
-    Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire vide
-    Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire pleine
-    RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de données en entrée
-    WDATA        : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de données en sortie
-    WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (écriture)
-    RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
-    apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entrées du bus
-    apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
-    );
-end component;
-
-
-component lpp_fifo is
-generic(
-    tech          :   integer := 0;
-    Enable_ReUse  :   std_logic := '0';
-    DataSz        :   integer range 1 to 32 := 8;
-    abits         :   integer range 2 to 12 := 8
-    );
-port(
-    rstn    :   in std_logic;
-    ReUse   :   in std_logic;   --27/01/12
-    rclk    :   in std_logic;
-    ren     :   in std_logic;
-    rdata   :   out std_logic_vector(DataSz-1 downto 0);
-    empty   :   out std_logic;
-    raddr   :   out std_logic_vector(abits-1 downto 0);
-    wclk    :   in std_logic;
-    wen     :   in std_logic;
-    wdata   :   in std_logic_vector(DataSz-1 downto 0);
-    full    :   out std_logic;
-    waddr   :   out std_logic_vector(abits-1 downto 0)
-);
-end component;
-
-
-component lppFIFOxN is
-generic(
-    tech          :   integer := 0;
-    Data_sz       :   integer range 1 to 32 := 8;
-    Addr_sz       :   integer range 1 to 32 := 8;
-    FifoCnt : integer := 1;
-    Enable_ReUse  :   std_logic := '0'
-    );
-port(
-    rst     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
-    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
-    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
-    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(FifoCnt-1 downto 0);
-    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
-);
-end component;
-
-component lppFIFOx5 is
-generic(
-    tech          :   integer := 0;
-    Data_sz       :   integer range 1 to 32 := 16;
-    Addr_sz       :   integer range 2 to 12 := 8;
-    Enable_ReUse  :   std_logic := '0'
-    );
-port(
-    rst     :   in std_logic;
-    wclk    :   in std_logic;    
-    rclk    :   in std_logic;
-    ReUse   :   in std_logic_vector(4 downto 0);
-    wen     :   in std_logic_vector(4 downto 0); 
-    ren     :   in std_logic_vector(4 downto 0);
-    wdata   :   in std_logic_vector((5*Data_sz)-1 downto 0);
-    rdata   :   out std_logic_vector((5*Data_sz)-1 downto 0);
-    full    :   out std_logic_vector(4 downto 0);
-    empty   :   out std_logic_vector(4 downto 0)    
-);
-end component;
-
-component Bridge is
-    port(
-        clk         : in std_logic;
-        raz        : in std_logic;
-        EmptyUp : in std_logic;
-        FullDwn : in std_logic;
-        WriteDwn : out std_logic;
-        ReadUp : out std_logic
-        );
-end component;
-
-component ssram_plugin is
-generic (tech : integer := 0);
-port
-(
-    clk             : in  std_logic;
-    mem_ctrlr_o     : in  memory_out_type;
-    SSRAM_CLK       : out std_logic;
-    nBWa            : out std_logic;
-    nBWb            : out std_logic;
-    nBWc            : out std_logic;
-    nBWd            : out std_logic;
-    nBWE            : out std_logic;
-    nADSC           : out std_logic;
-    nADSP           : out std_logic;
-    nADV            : out std_logic;
-    nGW             : out std_logic;
-    nCE1            : out std_logic;
-    CE2             : out std_logic;
-    nCE3            : out std_logic;
-    nOE             : out std_logic;
-    MODE            : out std_logic;
-    ZZ              : out std_logic
-);
-end component;
-
-end;
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                     Mail : martin.morlot@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use std.textio.all;
+library lpp;
+use lpp.lpp_amba.all;
+use lpp.iir_filter.all;
+library gaisler;
+use gaisler.misc.all;
+use gaisler.memctrl.all;
+library techmap;
+use techmap.gencomp.all;
+
+--! Package contenant tous les programmes qui forment le composant intégré dans le léon 
+
+package lpp_memory is
+
+component APB_FIFO is
+generic (
+    tech         : integer := apa3;
+    pindex       : integer := 0;
+    paddr        : integer := 0;
+    pmask        : integer := 16#fff#;
+    pirq         : integer := 0;
+    abits        : integer := 8;
+    FifoCnt      : integer := 2;
+    Data_sz      : integer := 16;
+    Addr_sz        : integer := 9;
+    Enable_ReUse   : std_logic := '0';
+    Mem_use        : integer := use_RAM;
+    R            : integer := 1;
+    W            : integer := 1
+    );
+  port (
+    clk          : in  std_logic;                              --! Horloge du composant
+    rst          : in  std_logic;                              --! Reset general du composant
+    rclk         : in  std_logic; 
+    wclk         : in  std_logic;
+    ReUse        : in  std_logic_vector(FifoCnt-1 downto 0);
+    REN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en mémoire
+    WEN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'écriture en mémoire
+    Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire vide
+    Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, Mémoire pleine
+    RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de données en entrée
+    WDATA        : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de données en sortie
+    WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (écriture)
+    RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
+    apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entrées du bus
+    apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
+    );
+end component;
+
+
+component lpp_fifo is
+generic(
+    tech          :   integer := 0;
+    Mem_use       :   integer := use_RAM;
+    Enable_ReUse  :   std_logic := '0';
+    DataSz        :   integer range 1 to 32 := 8;
+    abits         :   integer range 2 to 12 := 8
+    );
+port(
+    rstn    :   in std_logic;
+    ReUse   :   in std_logic;   --27/01/12
+    rclk    :   in std_logic;
+    ren     :   in std_logic;
+    rdata   :   out std_logic_vector(DataSz-1 downto 0);
+    empty   :   out std_logic;
+    raddr   :   out std_logic_vector(abits-1 downto 0);
+    wclk    :   in std_logic;
+    wen     :   in std_logic;
+    wdata   :   in std_logic_vector(DataSz-1 downto 0);
+    full    :   out std_logic;
+    waddr   :   out std_logic_vector(abits-1 downto 0)
+);
+end component;
+
+
+component lppFIFOxN is
+generic(
+    tech          :   integer := 0;
+    Mem_use       :   integer := use_RAM;
+    Data_sz       :   integer range 1 to 32 := 8;
+    Addr_sz       :   integer range 1 to 32 := 8;
+    FifoCnt : integer := 1;
+    Enable_ReUse  :   std_logic := '0'
+    );
+port(
+    rst     :   in std_logic;
+    wclk    :   in std_logic;    
+    rclk    :   in std_logic;
+    ReUse   :   in std_logic_vector(FifoCnt-1 downto 0);
+    wen     :   in std_logic_vector(FifoCnt-1 downto 0);
+    ren     :   in std_logic_vector(FifoCnt-1 downto 0);
+    wdata   :   in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
+    rdata   :   out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
+    full    :   out std_logic_vector(FifoCnt-1 downto 0);
+    empty   :   out std_logic_vector(FifoCnt-1 downto 0)
+);
+end component;
+
+component FillFifo is
+generic(
+    Data_sz  : integer range 1 to 32 := 16;
+    Fifo_cnt : integer range 1 to 8 := 5
+    );
+port(
+    clk         : in std_logic;
+    raz        : in std_logic;
+    write : out std_logic_vector(Fifo_cnt-1 downto 0);
+    reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
+    data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
+);
+end component;
+
+component ssram_plugin is
+generic (tech : integer := 0);
+port
+(
+    clk             : in  std_logic;
+    mem_ctrlr_o     : in  memory_out_type;
+    SSRAM_CLK       : out std_logic;
+    nBWa            : out std_logic;
+    nBWb            : out std_logic;
+    nBWc            : out std_logic;
+    nBWd            : out std_logic;
+    nBWE            : out std_logic;
+    nADSC           : out std_logic;
+    nADSP           : out std_logic;
+    nADV            : out std_logic;
+    nGW             : out std_logic;
+    nCE1            : out std_logic;
+    CE2             : out std_logic;
+    nCE3            : out std_logic;
+    nOE             : out std_logic;
+    MODE            : out std_logic;
+    ZZ              : out std_logic
+);
+end component;
+
+end;
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
@@ -11,7 +11,8 @@ USE techmap.gencomp.ALL;
 
 ENTITY lpp_top_acq IS
   GENERIC(
-    tech : INTEGER := 0
+    tech : INTEGER := 0;
+    Mem_use : integer := use_RAM
     );
   PORT (
     -- ADS7886
@@ -143,7 +144,7 @@ BEGIN
   IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
     GENERIC MAP (
       tech         => 0,
-      Mem_use      => use_CEL, -- use_RAM
+      Mem_use      => Mem_use,
       Sample_SZ    => 18,
       Coef_SZ      => Coef_SZ,
       Coef_Nb      => 25,               -- TODO
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
@@ -16,7 +16,8 @@ PACKAGE lpp_top_lfr_pkg IS
 
   COMPONENT lpp_top_acq
   GENERIC(
-    tech : INTEGER := 0
+    tech : INTEGER := 0;
+    Mem_use : integer := use_RAM
     );
   PORT (
     -- ADS7886