diff --git a/designs/LFR-EQM-RTAX/LFR-EQM.vhd b/designs/LFR-EQM-RTAX/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-RTAX/LFR-EQM.vhd +++ /dev/null @@ -1,605 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -USE techmap.axcomp.ALL; - -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25_int : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL LFR_rstn_int : STD_LOGIC := '0'; - SIGNAL rstn_25_int : STD_LOGIC := '0'; - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 ); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - clk_25_int <= NOT clk_25_int; - --clk_25 <= NOT clk_25; - END IF; - END PROCESS; - clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int; - - rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn ); - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA, - RTL_DESIGN_LIGHT =>0, - WINDOWS_HAANNING_PARAM_SIZE => 15) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - --ahbrxd <= TAG(1); -- AHB UART - --TAG(3) <= ahbtxd; - - urxd1 <= TAG(2); -- APB UART - TAG(4) <= utxd1; - --TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-RTAX/Makefile b/designs/LFR-EQM-RTAX/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-RTAX/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) - -TOP=LFR_EQM -BOARD=LFR-EQM - -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc - -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= - -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd \ - sgmii.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd +++ /dev/null @@ -1,595 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 1, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 0, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/Makefile b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -VHDLIB=../../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) - -TOP=LFR_EQM -BOARD=LFR-EQM - -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc - -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= - -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/readme.txt +++ /dev/null @@ -1,13 +0,0 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 1 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/testbench.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/LFR-EQM.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/LFR-EQM.vhd +++ /dev/null @@ -1,595 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 0, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/Makefile b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -VHDLIB=../../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) - -TOP=LFR_EQM -BOARD=LFR-EQM - -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc - -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= - -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/readme.txt +++ /dev/null @@ -1,13 +0,0 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 0 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/testbench.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_1/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/LFR-EQM.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/LFR-EQM.vhd +++ /dev/null @@ -1,595 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 0, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/Makefile b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -VHDLIB=../../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) - -TOP=LFR_EQM -BOARD=LFR-EQM - -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc - -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= - -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/readme.txt +++ /dev/null @@ -1,16 +0,0 @@ -leon3_soc : - ENABLE_AHB_UART = 0 (disabled) - ENABLE_APB_UART = 0 (disabled) - FPU_NETLIST = 0 (enabled) - -apb_lfr_management : - lfr_cal_driver (enabled) - -top : - LFR_rstn <= LFR_soft_rstn AND rstn_25; - -GRSPW : - ft = 1 (enabled) - -Constraint file : - LFR_EQM_altran_syn_fanout.sdc diff --git a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/testbench.vhd b/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM-WFP_MS-RTAX_2/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/LFR-EQM.vhd b/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/LFR-EQM.vhd +++ /dev/null @@ -1,605 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -USE techmap.axcomp.ALL; - -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25_int : STD_LOGIC := '0'; - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL LFR_rstn_int : STD_LOGIC := '0'; - SIGNAL rstn_25_int : STD_LOGIC := '0'; - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25_int, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - rstn_pad_25 : clkint port map (A => rstn_25_int, Y => rstn_25 ); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - clk_25_int <= NOT clk_25_int; - --clk_25 <= NOT clk_25; - END IF; - END PROCESS; - clk_pad_25 : hclkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 0, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn_int <= LFR_soft_rstn AND rstn_25_int; - - rstn_pad_lfr : clkint port map (A => LFR_rstn_int, Y => LFR_rstn ); - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA, - RTL_DESIGN_LIGHT =>0, - WINDOWS_HAANNING_PARAM_SIZE => 15) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - --ahbrxd <= TAG(1); -- AHB UART - --TAG(3) <= ahbtxd; - - urxd1 <= TAG(2); -- APB UART - TAG(4) <= utxd1; - --TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/Makefile b/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-TEST/LFR-EQM2_RTAX_2/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -VHDLIB=../../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) - -TOP=LFR_EQM -BOARD=LFR-EQM - -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc - -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= - -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd - -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd \ - sgmii.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-EQM.vhd +++ /dev/null @@ -1,596 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 1, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-soc-subsystem.vhd b/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-soc-subsystem.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-soc-subsystem.vhd +++ /dev/null @@ -1,595 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_soc_subsystem IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_soc_subsystem; - - -ARCHITECTURE beh OF LFR_soc_subsystem IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 1, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management_nocal - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - --lpp_lfr_1 : lpp_lfr - -- GENERIC MAP ( - -- Mem_use => Mem_use, - -- tech => inferred,--tech, - -- nb_data_by_buffer_size => 32, - -- --nb_word_by_buffer_size => 30, - -- nb_snapshot_param_size => 32, - -- delta_vector_size => 32, - -- delta_vector_size_f0_2 => 7, -- log2(96) - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#, - -- pirq_ms => 6, - -- pirq_wfp => 14, - -- hindex => 2, - -- top_lfr_version => X"020153", -- aa.bb.cc version - -- -- AA : BOARD NUMBER - -- -- 0 => MINI_LFR - -- -- 1 => EM - -- -- 2 => EQM (with A3PE3000) - -- DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - -- PORT MAP ( - -- clk => clk_25, - -- rstn => LFR_rstn, - -- sample_B => sample_s(2 DOWNTO 0), - -- sample_E => sample_s(7 DOWNTO 3), - -- sample_val => sample_val, - -- apbi => apbi_ext, - -- apbo => apbo_ext(15), - -- ahbi => ahbi_m_ext, - -- ahbo => ahbo_m_ext(2), - -- coarse_time => coarse_time, - -- fine_time => fine_time, - -- data_shaping_BW => bias_fail_sw, - -- debug_vector => debug_vector, - -- debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-subsystem.vhd b/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-subsystem.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX-part/LFR-subsystem.vhd +++ /dev/null @@ -1,125 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - - -ENTITY lfr_subsystem IS - GENERIC ( - Mem_use : INTEGER := use_RAM - ); - PORT ( - clk_25 : IN STD_LOGIC; - LFR_soft_rstn : IN STD_LOGIC; - rstn_25 : IN STD_LOGIC; - -- SAMPLE - sample_s : IN Samples(7 DOWNTO 0); - sample_val : IN STD_LOGIC; - -- APB - apbi_ext : IN apb_slv_in_type; - apbo_ext : OUT apb_slv_out_type; - -- AHB - ahbi_m_ext : IN AHB_Mst_In_Type; - ahbo_m_ext : OUT AHB_Mst_Out_Type; - -- TIME - coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo - -- - bias_fail_sw : OUT STD_LOGIC; - -- - debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - ); -END lfr_subsystem; - - -ARCHITECTURE beh OF lfr_subsystem IS - SIGNAL LFR_rstn : STD_LOGIC; -BEGIN -- beh - - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => 0) - PORT MAP ( - clk => clk_25, - rstn => LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext, - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext, - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); - -END beh; \ No newline at end of file diff --git a/designs/LFR-EQM-WFP_MS-RTAX-part/Makefile b/designs/LFR-EQM-WFP_MS-RTAX-part/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX-part/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=LFR_EQM -BOARD=LFR-EQM -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -#SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -#VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc -##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc -##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-WFP_MS-RTAX-part/testbench.vhd b/designs/LFR-EQM-WFP_MS-RTAX-part/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX-part/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX/LFR-EQM.vhd +++ /dev/null @@ -1,597 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.sim.ALL; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib -USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - ---library proasic3l; ---use proasic3l.all; - -ENTITY LFR_EQM IS - GENERIC ( - Mem_use : INTEGER := use_RAM; - USE_BOOTLOADER : INTEGER := 0; - USE_ADCDRIVER : INTEGER := 1; - tech : INTEGER := inferred; - tech_leon : INTEGER := inferred; - DEBUG_FORCE_DATA_DMA : INTEGER := 0; - USE_DEBUG_VECTOR : INTEGER := 0 - ); - - PORT ( - clk50MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); - - -- TAG -------------------------------------------------------------------- - --TAG1 : IN STD_ULOGIC; -- DSU rx data - --TAG3 : OUT STD_ULOGIC; -- DSU tx data - -- UART APB --------------------------------------------------------------- - --TAG2 : IN STD_ULOGIC; -- UART1 rx data - --TAG4 : OUT STD_ULOGIC; -- UART1 tx data - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - nSRAM_MBE : INOUT STD_LOGIC; -- new - nSRAM_E1 : OUT STD_LOGIC; -- new - nSRAM_E2 : OUT STD_LOGIC; -- new --- nSRAM_SCRUB : OUT STD_LOGIC; -- new - nSRAM_W : OUT STD_LOGIC; -- new - nSRAM_G : OUT STD_LOGIC; -- new - nSRAM_BUSY : IN STD_LOGIC; -- new - -- SPW -------------------------------------------------------------------- - spw1_en : OUT STD_LOGIC; -- new - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_en : OUT STD_LOGIC; -- new - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - -- ADC -------------------------------------------------------------------- - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - -- DAC -------------------------------------------------------------------- - DAC_SDO : OUT STD_LOGIC; - DAC_SCK : OUT STD_LOGIC; - DAC_SYNC : OUT STD_LOGIC; - DAC_CAL_EN : OUT STD_LOGIC; - -- HK --------------------------------------------------------------------- - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; - --------------------------------------------------------------------------- --- TAG8 : OUT STD_LOGIC - ); - -END LFR_EQM; - - -ARCHITECTURE beh OF LFR_EQM IS - - SIGNAL clk_25 : STD_LOGIC := '0'; - SIGNAL clk_24 : STD_LOGIC := '0'; - ----------------------------------------------------------------------------- - SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); - - -- CONSTANTS - CONSTANT CFG_PADTECH : INTEGER := inferred; - CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f - CONSTANT NB_AHB_SLAVE : INTEGER := 1; - CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker - - SIGNAL apbi_ext : apb_slv_in_type; - SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - - SIGNAL rstn_50 : STD_LOGIC; - SIGNAL clk_lock : STD_LOGIC; - SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL nSRAM_BUSY_reg : STD_LOGIC; - - SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL ahbrxd: STD_LOGIC; - SIGNAL ahbtxd: STD_LOGIC; - SIGNAL urxd1 : STD_LOGIC; - SIGNAL utxd1 : STD_LOGIC; -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK_LOCK - ----------------------------------------------------------------------------- - rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); - - PROCESS (clk50MHz_int, rstn_50) - BEGIN -- PROCESS - IF rstn_50 = '0' THEN -- asynchronous reset (active low) - clk_lock <= '0'; - clk_busy_counter <= (OTHERS => '0'); - nSRAM_BUSY_reg <= '0'; - ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge - nSRAM_BUSY_reg <= nSRAM_BUSY; - IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN - IF clk_busy_counter = "1111" THEN - clk_lock <= '1'; - ELSE - clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); - END IF; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - --clk_25_int <= NOT clk_25_int; - clk_25 <= NOT clk_25; - END IF; - END PROCESS; - --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; --- clk_49 <= clk49_152MHz; - - ----------------------------------------------------------------------------- - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => axcel,--inferred,--axdsp, - memtech => axcel,--inferred,--tech_leon, - padtech => axcel,--inferred, - clktech => axcel,--inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 1, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 1, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1, - USES_MBE_PIN => 1, - BYPASS_EDAC_MEMCTRLR => '0', - SRBANKSZ => 8) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => ahbrxd, -- INPUT - ahbtxd => ahbtxd, -- OUTPUT - urxd1 => urxd1, -- INPUT - utxd1 => utxd1, -- OUTPUT - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - apb_lfr_management_1 : apb_lfr_management - GENERIC MAP ( - tech => tech, - pindex => 6, - paddr => 6, - pmask => 16#fff#, - --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - PORT MAP ( - clk25MHz => clk_25, - resetn_25MHz => rstn_25, -- TODO - --clk24_576MHz => clk_24, -- 49.152MHz/2 - --resetn_24_576MHz => rstn_24, -- TODO - - grspw_tick => swno.tickout, - apbi => apbi_ext, - apbo => apbo_ext(6), - - HK_sample => sample_s(8), - HK_val => sample_val, - HK_sel => HK_SEL, - - DAC_SDO => DAC_SDO, - DAC_SCK => DAC_SCK, - DAC_SYNC => DAC_SYNC, - DAC_CAL_EN => DAC_CAL_EN, - - coarse_time => coarse_time, - fine_time => fine_time, - LFR_soft_rstn => LFR_soft_rstn - ); - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => axcel,-- inferred,--axdsp,--tech_leon, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => axcel,--inferred,--axdsp,--tech_leon, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 1, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => axcel,--inferred,--tech_leon, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - --rst_domain25_lfr : rstgen PORT MAP (LFR_soft_rstn, clk_25, clk_lock, LFR_rstn, OPEN); - --LFR_rstn <= LFR_soft_rstn AND rstn_25; - - lpp_lfr_1 : lpp_lfr - GENERIC MAP ( - Mem_use => Mem_use, - tech => inferred,--tech, - nb_data_by_buffer_size => 32, - --nb_word_by_buffer_size => 30, - nb_snapshot_param_size => 32, - delta_vector_size => 32, - delta_vector_size_f0_2 => 7, -- log2(96) - pindex => 15, - paddr => 15, - pmask => 16#fff#, - pirq_ms => 6, - pirq_wfp => 14, - hindex => 2, - top_lfr_version => X"020153", -- aa.bb.cc version - -- AA : BOARD NUMBER - -- 0 => MINI_LFR - -- 1 => EM - -- 2 => EQM (with A3PE3000) - DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) - PORT MAP ( - clk => clk_25, - rstn => rstn_25,--LFR_rstn, - sample_B => sample_s(2 DOWNTO 0), - sample_E => sample_s(7 DOWNTO 3), - sample_val => sample_val, - apbi => apbi_ext, - apbo => apbo_ext(15), - ahbi => ahbi_m_ext, - ahbo => ahbo_m_ext(2), - coarse_time => coarse_time, - fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - debug_vector => debug_vector, - debug_vector_ms => OPEN); --, - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 12, - ncycle_cnv => 25, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => ADC_OEB_bar_CH_s, - sample => sample, - sample_val => sample_val); - - END GENERATE USE_ADCDRIVER_true; - - USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE - top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - GENERIC MAP ( - ChanelCount => 9, - ncycle_cnv_high => 25, - ncycle_cnv => 50, - FILTER_ENABLED => 16#FF#) - PORT MAP ( - cnv_clk => clk_24, - cnv_rstn => rstn_24, - cnv => ADC_smpclk_s, - clk => clk_25, - rstn => rstn_25, - ADC_data => ADC_data, - ADC_nOE => OPEN, - sample => OPEN, - sample_val => sample_val); - - ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); - - all_sample: FOR I IN 8 DOWNTO 0 GENERATE - ramp_generator_1: ramp_generator - GENERIC MAP ( - DATA_SIZE => 14, - VALUE_UNSIGNED_INIT => 2**I, - VALUE_UNSIGNED_INCR => 0, - VALUE_UNSIGNED_MASK => 16#3FFF#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - new_data => sample_val, - output_data => sample(I) ); - END GENERATE all_sample; - - - END GENERATE USE_ADCDRIVER_false; - - - - - ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - - ADC_smpclk <= ADC_smpclk_s; - HK_smpclk <= ADC_smpclk_s; - - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE - -- lpp_bootloader_1: lpp_bootloader - -- GENERIC MAP ( - -- pindex => 13, - -- paddr => 13, - -- pmask => 16#fff#, - -- hindex => 3, - -- haddr => 0, - -- hmask => 16#fff#) - -- PORT MAP ( - -- HCLK => clk_25, - -- HRESETn => rstn_25, - -- apbi => apbi_ext, - -- apbo => apbo_ext(13), - -- ahbsi => ahbi_s_ext, - -- ahbso => ahbo_s_ext(3)); - --END GENERATE inst_bootloader; - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE - PROCESS (clk_25, rstn_25) - BEGIN -- PROCESS - IF rstn_25 = '0' THEN -- asynchronous reset (active low) - TAG <= (OTHERS => '0'); - ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge - TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); - END IF; - END PROCESS; - - - END GENERATE USE_DEBUG_VECTOR_IF; - - USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE - ahbrxd <= TAG(1); - TAG(3) <= ahbtxd; - urxd1 <= TAG(2); - TAG(4) <= utxd1; - TAG(8) <= nSRAM_BUSY; - END GENERATE USE_DEBUG_VECTOR_IF2; - -END beh; diff --git a/designs/LFR-EQM-WFP_MS-RTAX/Makefile b/designs/LFR-EQM-WFP_MS-RTAX/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=LFR_EQM -BOARD=LFR-EQM -include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -#SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -#VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn.sdc -##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route_RTAX_ALTRAN.sdc -##SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = axcelerator - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-WFP_MS-RTAX/run.do b/designs/LFR-EQM-WFP_MS-RTAX/run.do deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX/run.do +++ /dev/null @@ -1,10 +0,0 @@ -vcom -quiet -93 -work work LFR-em.vhd -vcom -quiet -93 -work work testbench.vhd - -vsim work.testbench - -log -r * - -do wave.do - -run 65 ms diff --git a/designs/LFR-EQM-WFP_MS-RTAX/testbench.vhd b/designs/LFR-EQM-WFP_MS-RTAX/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-WFP_MS-RTAX/wave.do b/designs/LFR-EQM-WFP_MS-RTAX/wave.do deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-RTAX/wave.do +++ /dev/null @@ -1,28 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 -radix hexadecimal}} -expand -subitemconfig {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 {-radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 {-radix hexadecimal}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk -add wave -noupdate /testbench/LFR_em_1/ADC_data -add wave -noupdate /testbench/LFR_em_1/ADC_data -add wave -noupdate /testbench/LFR_em_1/HK_SEL -add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_HK -add wave -noupdate /testbench/LFR_em_1/HK_smpclk -add wave -noupdate /testbench/LFR_em_1/ADC_smpclk -add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_CH -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -quietly wave cursor active 0 -configure wave -namecolwidth 233 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {934646651 ps} {1003439650 ps} diff --git a/designs/LFR-EQM-WFP_MS-debug/Constraint_EQM.odt b/designs/LFR-EQM-WFP_MS-debug/Constraint_EQM.odt deleted file mode 100644 index 085d14d2fc345d53a0040c8de7bca480293f9426..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 GIT binary patch literal 0 Hc$@ apb_none); - SIGNAL ahbi_s_ext : ahb_slv_in_type; - SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); - SIGNAL ahbi_m_ext : AHB_Mst_In_Type; - SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); - --- Spacewire signals - SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL spw_rxtxclk : STD_ULOGIC; - SIGNAL spw_rxclkn : STD_ULOGIC; - SIGNAL spw_clk : STD_LOGIC; - SIGNAL swni : grspw_in_type; - SIGNAL swno : grspw_out_type; - ---GPIO - SIGNAL gpioi : gpio_in_type; - SIGNAL gpioo : gpio_out_type; - --- AD Converter ADS7886 - SIGNAL sample : Samples14v(8 DOWNTO 0); - SIGNAL sample_s : Samples(8 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL rstn_25 : STD_LOGIC; - SIGNAL rstn_24 : STD_LOGIC; - - SIGNAL LFR_soft_rstn : STD_LOGIC; - SIGNAL LFR_rstn : STD_LOGIC; - - SIGNAL ADC_smpclk_s : STD_LOGIC; - - SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL clk50MHz_int : STD_LOGIC := '0'; - - component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- CLK - ----------------------------------------------------------------------------- - rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); - rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); - - --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); - clk50MHz_int <= clk50MHz; - PROCESS(clk50MHz_int) - BEGIN - IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN - clk_25_int <= NOT clk_25_int; - END IF; - END PROCESS; - clk_pad : clkint port map (A => clk_25_int, Y => clk_25 ); - - PROCESS(clk49_152MHz) - BEGIN - IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN - clk_24 <= NOT clk_24; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- - leon3_soc_1 : leon3_soc - GENERIC MAP ( - fabtech => apa3e, - memtech => apa3e, - padtech => inferred, - clktech => inferred, - disas => 0, - dbguart => 0, - pclow => 2, - clk_freq => 25000, - IS_RADHARD => 0, - NB_CPU => 1, - ENABLE_FPU => 1, - FPU_NETLIST => 0, - ENABLE_DSU => 1, - ENABLE_AHB_UART => 1, - ENABLE_APB_UART => 1, - ENABLE_IRQMP => 1, - ENABLE_GPT => 1, - NB_AHB_MASTER => NB_AHB_MASTER, - NB_AHB_SLAVE => NB_AHB_SLAVE, - NB_APB_SLAVE => NB_APB_SLAVE, - ADDRESS_SIZE => 19, - USES_IAP_MEMCTRLR => 1) - PORT MAP ( - clk => clk_25, - reset => rstn_25, - errorn => OPEN, - - ahbrxd => TAG1, - ahbtxd => TAG3, - urxd1 => TAG2, - utxd1 => TAG4, - - address => address, - data => data, - nSRAM_BE0 => OPEN, - nSRAM_BE1 => OPEN, - nSRAM_BE2 => OPEN, - nSRAM_BE3 => OPEN, - nSRAM_WE => nSRAM_W, - nSRAM_CE => nSRAM_CE, - nSRAM_OE => nSRAM_G, - nSRAM_READY => nSRAM_BUSY, - SRAM_MBE => nSRAM_MBE, - - apbi_ext => apbi_ext, - apbo_ext => apbo_ext, - ahbi_s_ext => ahbi_s_ext, - ahbo_s_ext => ahbo_s_ext, - ahbi_m_ext => ahbi_m_ext, - ahbo_m_ext => ahbo_m_ext); - - - nSRAM_E1 <= nSRAM_CE(0); - nSRAM_E2 <= nSRAM_CE(1); - -------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- -------------------------------------------------------------------------------- - --apb_lfr_management_1 : apb_lfr_management - -- GENERIC MAP ( - -- tech => apa3e, - -- pindex => 6, - -- paddr => 6, - -- pmask => 16#fff#, - -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 - -- NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set - -- PORT MAP ( - -- clk25MHz => clk_25, - -- resetn_25MHz => rstn_25, -- TODO - -- clk24_576MHz => clk_24, -- 49.152MHz/2 - -- resetn_24_576MHz => rstn_24, -- TODO - - -- grspw_tick => swno.tickout, - -- apbi => apbi_ext, - -- apbo => apbo_ext(6), - - -- HK_sample => sample_s(8), - -- HK_val => sample_val, - -- HK_sel => HK_SEL, - - -- DAC_SDO => DAC_SDO, - -- DAC_SCK => DAC_SCK, - -- DAC_SYNC => DAC_SYNC, - -- DAC_CAL_EN => DAC_CAL_EN, - - -- coarse_time => coarse_time, - -- fine_time => fine_time, - -- LFR_soft_rstn => LFR_soft_rstn - -- ); - HK_sel <= "00"; - - DAC_SDO <= '1'; - DAC_SCK <= '0'; - DAC_SYNC <= '0'; - DAC_CAL_EN <= '0'; - ------------------------------------------------------------------------ ---- SpaceWire -------------------------------------------------------- ------------------------------------------------------------------------ - - ------------------------------------------------------------------------------ - -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ - ------------------------------------------------------------------------------ - spw1_en <= '1'; - spw2_en <= '1'; - ------------------------------------------------------------------------------ - -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ - ------------------------------------------------------------------------------ - - --spw_clk <= clk50MHz_int; - --spw_rxtxclk <= spw_clk; - --spw_rxclkn <= NOT spw_rxtxclk; - - -- PADS for SPW1 - spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_din, dtmp(0)); - spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sin, stmp(0)); - spw1_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_dout, swno.d(0)); - spw1_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw1_sout, swno.s(0)); - -- PADS FOR SPW2 - spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_din, dtmp(1)); - spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ - PORT MAP (spw2_sin, stmp(1)); - spw2_txd_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_dout, swno.d(1)); - spw2_txs_pad : outpad GENERIC MAP (tech => inferred) - PORT MAP (spw2_sout, swno.s(1)); - - -- GRSPW PHY - --spw1_input: if CFG_SPW_GRSPW = 1 generate - spw_inputloop : FOR j IN 0 TO 1 GENERATE - spw_phy0 : grspw_phy - GENERIC MAP( - tech => apa3e, - rxclkbuftype => 1, - scantest => 0) - PORT MAP( - rxrst => swno.rxrst, - di => dtmp(j), - si => stmp(j), - rxclko => spw_rxclk(j), - do => swni.d(j), - ndo => swni.nd(j*5+4 DOWNTO j*5), - dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); - END GENERATE spw_inputloop; - - -- SPW core - sw0 : grspwm GENERIC MAP( - tech => apa3e, - hindex => 1, - pindex => 5, - paddr => 5, - pirq => 11, - sysfreq => 25000, -- CPU_FREQ - rmap => 1, - rmapcrc => 1, - fifosize1 => 16, - fifosize2 => 16, - rxclkbuftype => 1, - rxunaligned => 0, - rmapbufs => 4, - ft => 0, - netlist => 0, - ports => 2, - --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 - memtech => apa3e, - destkey => 2, - spwcore => 1 - --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 - --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 - --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 - ) - PORT MAP(rstn_25, clk_25, - spw_rxclk(0), - spw_rxclk(1), - clk50MHz_int, - clk50MHz_int, --- spw_rxtxclk, spw_rxtxclk, - ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), - swni, swno); - - swni.tickin <= '0'; - swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz - swni.tickinraw <= '0'; - swni.timein <= (OTHERS => '0'); - swni.dcrstval <= (OTHERS => '0'); - swni.timerrstval <= (OTHERS => '0'); - -------------------------------------------------------------------------------- --- LFR ------------------------------------------------------------------------ -------------------------------------------------------------------------------- - LFR_rstn <= LFR_soft_rstn AND rstn_25; - - --lpp_lfr_1 : lpp_lfr - -- GENERIC MAP ( - -- Mem_use => use_RAM, - -- nb_data_by_buffer_size => 32, - -- --nb_word_by_buffer_size => 30, - -- nb_snapshot_param_size => 32, - -- delta_vector_size => 32, - -- delta_vector_size_f0_2 => 7, -- log2(96) - -- pindex => 15, - -- paddr => 15, - -- pmask => 16#fff#, - -- pirq_ms => 6, - -- pirq_wfp => 14, - -- hindex => 2, - -- top_lfr_version => X"020144") -- aa.bb.cc version - -- -- AA : BOARD NUMBER - -- -- 0 => MINI_LFR - -- -- 1 => EM - -- -- 2 => EQM (with A3PE3000) - -- PORT MAP ( - -- clk => clk_25, - -- rstn => LFR_rstn, - -- sample_B => sample_s(2 DOWNTO 0), - -- sample_E => sample_s(7 DOWNTO 3), - -- sample_val => sample_val, - -- apbi => apbi_ext, - -- apbo => apbo_ext(15), - -- ahbi => ahbi_m_ext, - -- ahbo => ahbo_m_ext(2), - -- coarse_time => coarse_time, - -- fine_time => fine_time, - -- data_shaping_BW => bias_fail_sw, - -- debug_vector => OPEN, - -- debug_vector_ms => OPEN); --, - - --observation_vector_0 => OPEN, - --observation_vector_1 => OPEN, - --observation_reg => observation_reg); - bias_fail_sw <= '0'; - - all_sample : FOR I IN 7 DOWNTO 0 GENERATE - sample_s(I) <= sample(I) & '0' & '0'; - END GENERATE all_sample; - sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - --top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter - -- GENERIC MAP ( - -- ChanelCount => 9, - -- ncycle_cnv_high => 13, - -- ncycle_cnv => 25, - -- FILTER_ENABLED => 16#FF#) - -- PORT MAP ( - -- cnv_clk => clk_24, - -- cnv_rstn => rstn_24, - -- cnv => ADC_smpclk_s, - -- clk => clk_25, - -- rstn => rstn_25, - -- ADC_data => ADC_data, - -- ADC_nOE => ADC_OEB_bar_CH_s, - -- sample => sample, - -- sample_val => sample_val); - - --ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); - ADC_OEB_bar_CH <= (OTHERS => '1'); - - --ADC_smpclk <= ADC_smpclk_s; - --HK_smpclk <= ADC_smpclk_s; - ADC_smpclk <= '0'; - HK_smpclk <= '0'; - - TAG8 <= '0'; - - ----------------------------------------------------------------------------- - -- HK - ----------------------------------------------------------------------------- - --ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - ADC_OEB_bar_HK <= '1'; - -END beh; diff --git a/designs/LFR-EQM-WFP_MS-debug/Makefile b/designs/LFR-EQM-WFP_MS-debug/Makefile deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-debug/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -#GRLIB=../.. -VHDLIB=../.. -SCRIPTSDIR=$(VHDLIB)/scripts/ -GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) -TOP=LFR_EQM -BOARD=LFR-EQM -include $(VHDLIB)/boards/$(BOARD)/Makefile.inc -DEVICE=$(PART)-$(PACKAGE)$(SPEED) -UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf -QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf -EFFORT=high -XSTOPT= -SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" -#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd -#VHDLSYNFILES=config.vhd leon3mp.vhd -VHDLSYNFILES=LFR-EQM.vhd -VHDLSIMFILES=testbench.vhd -#SIMTOP=testbench -PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_debug.pdc -#SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc -SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route-debug.sdc - -BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut -CLEAN=soft-clean - -TECHLIBS = proasic3e - -LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip hynix ihp gleichmann micron usbhc - -DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ - pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ - ./amba_lcd_16x2_ctrlr \ - ./general_purpose/lpp_AMR \ - ./general_purpose/lpp_balise \ - ./general_purpose/lpp_delay \ - ./lpp_bootloader \ - ./dsp/lpp_fft_rtax \ - ./lpp_uart \ - ./lpp_usb \ - ./lpp_sim/CY7C1061DV33 \ - -FILESKIP = i2cmst.vhd \ - APB_MULTI_DIODE.vhd \ - APB_MULTI_DIODE.vhd \ - Top_MatrixSpec.vhd \ - APB_FFT.vhd\ - CoreFFT_simu.vhd \ - lpp_lfr_apbreg_simu.vhd - -include $(GRLIB)/bin/Makefile -include $(GRLIB)/software/leon3/Makefile - -################## project specific targets ########################## - diff --git a/designs/LFR-EQM-WFP_MS-debug/run.do b/designs/LFR-EQM-WFP_MS-debug/run.do deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-debug/run.do +++ /dev/null @@ -1,10 +0,0 @@ -vcom -quiet -93 -work work LFR-em.vhd -vcom -quiet -93 -work work testbench.vhd - -vsim work.testbench - -log -r * - -do wave.do - -run 65 ms diff --git a/designs/LFR-EQM-WFP_MS-debug/testbench.vhd b/designs/LFR-EQM-WFP_MS-debug/testbench.vhd deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-debug/testbench.vhd +++ /dev/null @@ -1,382 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -use IEEE.std_logic_textio.all; -LIBRARY STD; -use std.textio.all; - -LIBRARY grlib; -USE grlib.stdlib.ALL; -LIBRARY gaisler; -USE gaisler.libdcom.ALL; -USE gaisler.sim.ALL; -USE gaisler.jtagtst.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY lpp; -USE lpp.lpp_sim_pkg.ALL; -USE lpp.lpp_lfr_sim_pkg.ALL; -USE lpp.lpp_lfr_apbreg_pkg.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; - - -ENTITY testbench IS -END; - -ARCHITECTURE behav OF testbench IS - - COMPONENT LFR_em - PORT ( - clk100MHz : IN STD_ULOGIC; - clk49_152MHz : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - TAG1 : IN STD_ULOGIC; - TAG3 : OUT STD_ULOGIC; - TAG2 : IN STD_ULOGIC; - TAG4 : OUT STD_ULOGIC; - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - spw1_din : IN STD_LOGIC; - spw1_sin : IN STD_LOGIC; - spw1_dout : OUT STD_LOGIC; - spw1_sout : OUT STD_LOGIC; - spw2_din : IN STD_LOGIC; - spw2_sin : IN STD_LOGIC; - spw2_dout : OUT STD_LOGIC; - spw2_sout : OUT STD_LOGIC; - bias_fail_sw : OUT STD_LOGIC; - ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - ADC_smpclk : OUT STD_LOGIC; - ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - HK_smpclk : OUT STD_LOGIC; - ADC_OEB_bar_HK : OUT STD_LOGIC; - HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - TAG8 : OUT STD_LOGIC; - led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); - END COMPONENT; - - - --COMPONENT MINI_LFR_top - -- PORT ( - -- clk_50 : IN STD_LOGIC; - -- clk_49 : IN STD_LOGIC; - -- reset : IN STD_LOGIC; - -- BP0 : IN STD_LOGIC; - -- BP1 : IN STD_LOGIC; - -- LED0 : OUT STD_LOGIC; - -- LED1 : OUT STD_LOGIC; - -- LED2 : OUT STD_LOGIC; - -- TXD1 : IN STD_LOGIC; - -- RXD1 : OUT STD_LOGIC; - -- nCTS1 : OUT STD_LOGIC; - -- nRTS1 : IN STD_LOGIC; - -- TXD2 : IN STD_LOGIC; - -- RXD2 : OUT STD_LOGIC; - -- nCTS2 : OUT STD_LOGIC; - -- nDTR2 : IN STD_LOGIC; - -- nRTS2 : IN STD_LOGIC; - -- nDCD2 : OUT STD_LOGIC; - -- IO0 : INOUT STD_LOGIC; - -- IO1 : INOUT STD_LOGIC; - -- IO2 : INOUT STD_LOGIC; - -- IO3 : INOUT STD_LOGIC; - -- IO4 : INOUT STD_LOGIC; - -- IO5 : INOUT STD_LOGIC; - -- IO6 : INOUT STD_LOGIC; - -- IO7 : INOUT STD_LOGIC; - -- IO8 : INOUT STD_LOGIC; - -- IO9 : INOUT STD_LOGIC; - -- IO10 : INOUT STD_LOGIC; - -- IO11 : INOUT STD_LOGIC; - -- SPW_EN : OUT STD_LOGIC; - -- SPW_NOM_DIN : IN STD_LOGIC; - -- SPW_NOM_SIN : IN STD_LOGIC; - -- SPW_NOM_DOUT : OUT STD_LOGIC; - -- SPW_NOM_SOUT : OUT STD_LOGIC; - -- SPW_RED_DIN : IN STD_LOGIC; - -- SPW_RED_SIN : IN STD_LOGIC; - -- SPW_RED_DOUT : OUT STD_LOGIC; - -- SPW_RED_SOUT : OUT STD_LOGIC; - -- ADC_nCS : OUT STD_LOGIC; - -- ADC_CLK : OUT STD_LOGIC; - -- ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- SRAM_nWE : OUT STD_LOGIC; - -- SRAM_CE : OUT STD_LOGIC; - -- SRAM_nOE : OUT STD_LOGIC; - -- SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - -- SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - -- SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - --END COMPONENT; - - ----------------------------------------------------------------------------- - SIGNAL clk_50 : STD_LOGIC := '0'; - SIGNAL clk_49 : STD_LOGIC := '0'; - SIGNAL reset : STD_LOGIC; - SIGNAL BP0 : STD_LOGIC; - SIGNAL BP1 : STD_LOGIC; - SIGNAL LED0 : STD_LOGIC; - SIGNAL LED1 : STD_LOGIC; - SIGNAL LED2 : STD_LOGIC; - SIGNAL TXD1 : STD_LOGIC; - SIGNAL RXD1 : STD_LOGIC; - SIGNAL nCTS1 : STD_LOGIC; - SIGNAL nRTS1 : STD_LOGIC; - SIGNAL TXD2 : STD_LOGIC; - SIGNAL RXD2 : STD_LOGIC; - SIGNAL nCTS2 : STD_LOGIC; - SIGNAL nDTR2 : STD_LOGIC; - SIGNAL nRTS2 : STD_LOGIC; - SIGNAL nDCD2 : STD_LOGIC; - SIGNAL IO0 : STD_LOGIC; - SIGNAL IO1 : STD_LOGIC; - SIGNAL IO2 : STD_LOGIC; - SIGNAL IO3 : STD_LOGIC; - SIGNAL IO4 : STD_LOGIC; - SIGNAL IO5 : STD_LOGIC; - SIGNAL IO6 : STD_LOGIC; - SIGNAL IO7 : STD_LOGIC; - SIGNAL IO8 : STD_LOGIC; - SIGNAL IO9 : STD_LOGIC; - SIGNAL IO10 : STD_LOGIC; - SIGNAL IO11 : STD_LOGIC; - SIGNAL SPW_EN : STD_LOGIC; - SIGNAL SPW_NOM_DIN : STD_LOGIC; - SIGNAL SPW_NOM_SIN : STD_LOGIC; - SIGNAL SPW_NOM_DOUT : STD_LOGIC; - SIGNAL SPW_NOM_SOUT : STD_LOGIC; - SIGNAL SPW_RED_DIN : STD_LOGIC; - SIGNAL SPW_RED_SIN : STD_LOGIC; - SIGNAL SPW_RED_DOUT : STD_LOGIC; - SIGNAL SPW_RED_SOUT : STD_LOGIC; - SIGNAL ADC_nCS : STD_LOGIC; - SIGNAL ADC_CLK : STD_LOGIC; - SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL SRAM_nWE : STD_LOGIC; - SIGNAL SRAM_CE : STD_LOGIC; - SIGNAL SRAM_nOE : STD_LOGIC; - SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); - SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); - - ----------------------------------------------------------------------------- - - SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL ADC_smpclk : STD_LOGIC; - SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); - SIGNAL HK_smpclk : STD_LOGIC; - SIGNAL ADC_OEB_bar_HK : STD_LOGIC; - SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL all_OEB_bar : STD_LOGIC_VECTOR(8 DOWNTO 0); - SIGNAL HK_SEL_DATA : STD_LOGIC_VECTOR(13 DOWNTO 0); - - ----------------------------------------------------------------------------- - - CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; - CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; - CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; - - - SIGNAL message_simu : STRING(1 TO 15) := "---------------"; - SIGNAL data_message : STRING(1 TO 15) := "---------------"; - SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); - -BEGIN - - ----------------------------------------------------------------------------- - -- TB - ----------------------------------------------------------------------------- - PROCESS - CONSTANT txp : TIME := 320 ns; - VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); - BEGIN -- PROCESS - TXD1 <= '1'; - reset <= '0'; - WAIT FOR 500 ns; - reset <= '1'; - WAIT FOR 10000 ns; - message_simu <= "0 - UART init "; - UART_INIT(TXD1,txp); - - message_simu <= "1 - UART test "; - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); - UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); - UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); - data_read <= data_read_v; - data_message <= "GPIO_data_write"; - - -- UNSET the LFR reset - message_simu <= "2 - LFR UNRESET"; - UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); - --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); - -- - message_simu <= "3 - LFR CONFIG "; - --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); - LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, - X"40000000", - X"40001000", - X"40002000", - X"40003000", - X"40004000", - X"40005000"); - - - LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, - LFR_MODE_SBM1, - X"7FFFFFFF", -- START DATE - - "00000",--DATA_SHAPING ( 4 DOWNTO 0) - X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) - X"0001280A",--DELTA_F0 (31 DOWNTO 0) - X"00000007",--DELTA_F0_2 (31 DOWNTO 0) - X"0001283F",--DELTA_F1 (31 DOWNTO 0) - X"000127FF",--DELTA_F2 (31 DOWNTO 0) - - ADDR_BASE_LFR, - X"40006000", - X"40007000", - X"40008000", - X"40009000", - X"4000A000", - X"4000B000", - X"4000C000", - X"4000D000"); - - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); - UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); - - message_simu <= "4 - GO GO GO !!"; - UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); - - READ_STATUS: LOOP - WAIT FOR 2 ms; - data_message <= "READ_NEW_STATUS"; - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); - - UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - data_read <= data_read_v; - UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v); - END LOOP READ_STATUS; - - WAIT; - END PROCESS; - - ----------------------------------------------------------------------------- - -- CLOCK - ----------------------------------------------------------------------------- - clk_50 <= NOT clk_50 AFTER 5 ns; - clk_49 <= NOT clk_49 AFTER 10172 ps; - - ----------------------------------------------------------------------------- - -- DON'T CARE - ----------------------------------------------------------------------------- - BP0 <= '0'; - BP1 <= '0'; - nRTS1 <= '0' ; - - TXD2 <= '1'; - nRTS2 <= '1'; - nDTR2 <= '1'; - - SPW_NOM_DIN <= '1'; - SPW_NOM_SIN <= '1'; - SPW_RED_DIN <= '1'; - SPW_RED_SIN <= '1'; - - ADC_SDO <= x"AA"; - - SRAM_DQ <= (OTHERS => 'Z'); - --IO0 <= 'Z'; - --IO1 <= 'Z'; - --IO2 <= 'Z'; - --IO3 <= 'Z'; - --IO4 <= 'Z'; - --IO5 <= 'Z'; - --IO6 <= 'Z'; - --IO7 <= 'Z'; - --IO8 <= 'Z'; - --IO9 <= 'Z'; - --IO10 <= 'Z'; - --IO11 <= 'Z'; - - ----------------------------------------------------------------------------- - -- DUT - ----------------------------------------------------------------------------- - - LFR_em_1: LFR_em - PORT MAP ( - clk100MHz => clk_50, - clk49_152MHz => clk_49, - reset => reset, - - TAG1 => TXD1, - TAG3 => RXD1, - TAG2 => TXD2, - TAG4 => RXD2, - - address => SRAM_A, - data => SRAM_DQ, - nSRAM_BE0 => SRAM_nBE(0), - nSRAM_BE1 => SRAM_nBE(1), - nSRAM_BE2 => SRAM_nBE(2), - nSRAM_BE3 => SRAM_nBE(3), - nSRAM_WE => SRAM_nWE, - nSRAM_CE => SRAM_CE, - nSRAM_OE => SRAM_nOE, - - spw1_din => SPW_NOM_DIN, - spw1_sin => SPW_NOM_SIN, - spw1_dout => SPW_NOM_DOUT, - spw1_sout => SPW_NOM_SOUT, - spw2_din => SPW_RED_DIN, - spw2_sin => SPW_RED_SIN, - spw2_dout => SPW_RED_DOUT, - spw2_sout => SPW_RED_SOUT, - - bias_fail_sw => OPEN, - - ADC_OEB_bar_CH => ADC_OEB_bar_CH, - ADC_smpclk => ADC_smpclk, - ADC_data => ADC_data, - HK_smpclk => HK_smpclk, - ADC_OEB_bar_HK => ADC_OEB_bar_HK, - HK_SEL => HK_SEL, - - TAG8 => OPEN, - led => OPEN); - - all_OEB_bar <= ADC_OEB_bar_HK & ADC_OEB_bar_CH; - - WITH HK_SEL SELECT - HK_SEL_DATA <= - "00"&X"00F" WHEN "00", - "00"&X"01F" WHEN "01", - "00"&X"02F" WHEN "10", - "XXXXXXXXXXXXXX" WHEN OTHERS; - - WITH all_OEB_bar SELECT - ADC_data <= - "00"&X"000" WHEN "111111110", - "00"&X"001" WHEN "111111101", - "00"&X"002" WHEN "111111011", - "00"&X"003" WHEN "111110111", - "00"&X"004" WHEN "111101111", - "00"&X"005" WHEN "111011111", - "00"&X"006" WHEN "110111111", - "00"&X"007" WHEN "101111111", - HK_SEL_DATA WHEN "011111111", - "XXXXXXXXXXXXXX" WHEN OTHERS; - -END; diff --git a/designs/LFR-EQM-WFP_MS-debug/wave.do b/designs/LFR-EQM-WFP_MS-debug/wave.do deleted file mode 100644 --- a/designs/LFR-EQM-WFP_MS-debug/wave.do +++ /dev/null @@ -1,28 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 -radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 -radix hexadecimal}} -expand -subitemconfig {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0 {-radix hexadecimal -childformat {{/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) -radix hexadecimal} {/testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) -radix hexadecimal}}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(15) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(14) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(13) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(12) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(11) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(10) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(9) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(8) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(7) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(6) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(5) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(4) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(3) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(2) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(1) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_0(0) {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_1 {-radix hexadecimal} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk.temp_2 {-radix hexadecimal}} /testbench/LFR_em_1/lpp_lfr_hk_1/reg_hk -add wave -noupdate /testbench/LFR_em_1/ADC_data -add wave -noupdate /testbench/LFR_em_1/ADC_data -add wave -noupdate /testbench/LFR_em_1/HK_SEL -add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_HK -add wave -noupdate /testbench/LFR_em_1/HK_smpclk -add wave -noupdate /testbench/LFR_em_1/ADC_smpclk -add wave -noupdate /testbench/LFR_em_1/ADC_OEB_bar_CH -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -quietly wave cursor active 0 -configure wave -namecolwidth 233 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {934646651 ps} {1003439650 ps}