diff --git a/lib/lpp/dsp/lpp_fft/FFT.vhd.bak b/lib/lpp/dsp/lpp_fft/FFT.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/FFT.vhd.bak @@ -0,0 +1,95 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ + +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_fft.all; +use lpp.fft_components.all; + +-- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "créneau" + +entity FFT is + generic( + Data_sz : integer := 16; + NbData : integer := 256); + port( + clkm : in std_logic; + rstn : in std_logic; + FifoIN_Empty : in std_logic_vector(4 downto 0); + FifoIN_Data : in std_logic_vector(79 downto 0); + FifoOUT_Full : in std_logic_vector(4 downto 0); + Load : out std_logic; + Read : out std_logic_vector(4 downto 0); + Write : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data : out std_logic_vector(79 downto 0) + ); +end entity; + + +architecture ar_FFT of FFT is + +signal Drive_Write : std_logic; +signal Drive_DataRE : std_logic_vector(15 downto 0); +signal Drive_DataIM : std_logic_vector(15 downto 0); + +signal Start : std_logic; +signal FFT_Load : std_logic; +signal FFT_Ready : std_logic; +signal FFT_Valid : std_logic; +signal FFT_DataRE : std_logic_vector(15 downto 0); +signal FFT_DataIM : std_logic_vector(15 downto 0); + +signal Link_Read : std_logic; + +begin + +Start <= '0'; +Load <= FFT_Load; + + DRIVE : Driver_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); + + FFT0 : CoreFFT + generic map( + LOGPTS => gLOGPTS, + LOGLOGPTS => gLOGLOGPTS, + WSIZE => gWSIZE, + TWIDTH => gTWIDTH, + DWIDTH => gDWIDTH, + TDWIDTH => gTDWIDTH, + RND_MODE => gRND_MODE, + SCALE_MODE => gSCALE_MODE, + PTS => gPTS, + HALFPTS => gHALFPTS, + inBuf_RWDLY => gInBuf_RWDLY) + port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); + + + LINK : Linker_FFT + generic map(Data_sz,NbData) + port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); + + +end architecture; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd.bak b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd.bak @@ -0,0 +1,73 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use work.FFT_config.all; + +--! Programme qui va permettre de générer des flags utilisés au niveau du driver C + +entity Flag_Extremum is + port( + clk,raz : in std_logic; --! Horloge et Reset général du composant + load : in std_logic; --! Signal en provenance de CoreFFT + y_rdy : in std_logic; --! Signal en provenance de CoreFFT + fill : out std_logic; --! Flag, Va permettre d'autoriser l'écriture (Driver C) + ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C) + ); +end Flag_Extremum; + +--! @details Flags générés a partir de signaux fourni par l'IP FFT d'actel + +architecture ar_Flag_Extremum of Flag_Extremum is + +begin + process (clk,raz) + begin + if(raz='0')then + fill <= '0'; + ready <= '0'; + + elsif(clk' event and clk='1')then + + if(load='1' and y_rdy='0')then + fill <= '1'; + ready <= '0'; + + elsif(y_rdy='1')then + fill <= '0'; + ready <= '1'; + + else + fill <= '0'; + ready <= '0'; + + end if; + end if; + end process; + +end ar_Flag_Extremum; + + + + diff --git a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt --- a/lib/lpp/dsp/lpp_fft/vhdlsyn.txt +++ b/lib/lpp/dsp/lpp_fft/vhdlsyn.txt @@ -1,4 +1,12 @@ lpp_fft.vhd +actar.vhd +actram.vhd +CoreFFT.vhd +fft_components.vhd +fftDp.vhd +fftSm.vhd +primitives.vhd +twiddle.vhd APB_FFT.vhd APB_FFT_half.vhd Driver_FFT.vhd diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd --- a/lib/lpp/leon3mp.vhd +++ b/lib/lpp/leon3mp.vhd @@ -47,6 +47,8 @@ use lpp.general_purpose.all; use lpp.Filtercfg.all; use lpp.lpp_demux.all; use lpp.lpp_top_lfr_pkg.all; +use lpp.lpp_dma_pkg.all; +use lpp.lpp_Header.all; entity leon3mp is generic ( @@ -124,7 +126,7 @@ end; architecture Behavioral of leon3mp is constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ - CFG_GRETH+CFG_AHB_JTAG; + CFG_GRETH+CFG_AHB_JTAG+1; -- +1 pour le DMA constant maxahbm : integer := maxahbmsp; --Clk & Rst géné @@ -188,17 +190,22 @@ signal FifoINT_Full : std_logic_vect signal FifoINT_Data : std_logic_vector(79 downto 0); signal FifoOUT_Full : std_logic_vector(1 downto 0); +signal FifoOUT_Empty : std_logic_vector(1 downto 0); +signal FifoOUT_Data : std_logic_vector(63 downto 0); + -- MATRICE SPECTRALE signal SM_FlagError : std_logic; signal SM_Pong : std_logic; +signal SM_Wen : std_logic; signal SM_Read : std_logic_vector(4 downto 0); signal SM_Write : std_logic_vector(1 downto 0); signal SM_ReUse : std_logic_vector(4 downto 0); signal SM_Param : std_logic_vector(3 downto 0); signal SM_Data : std_logic_vector(63 downto 0); -signal Dma_acq : std_logic; +--signal Dma_acq : std_logic; +--signal Head_Valid : std_logic; -- FFT signal FFT_Load : std_logic; @@ -208,20 +215,36 @@ signal FFT_ReUse : std_logic_vecto signal FFT_Data : std_logic_vector(79 downto 0); -- DEMUX -signal DEMU_Read : std_logic_vector(14 downto 0); -signal DEMU_Empty : std_logic_vector(4 downto 0); -signal DEMU_Data : std_logic_vector(79 downto 0); +signal DMUX_Read : std_logic_vector(14 downto 0); +signal DMUX_Empty : std_logic_vector(4 downto 0); +signal DMUX_Data : std_logic_vector(79 downto 0); +signal DMUX_WorkFreq : std_logic_vector(1 downto 0); -- ACQ signal sample_val : STD_LOGIC; signal sample : Samples(8-1 DOWNTO 0); -signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); -signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal ACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal ACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); +signal ACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0); +signal ACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + +-- Header +signal Head_Read : std_logic_vector(1 downto 0); +signal Head_Data : std_logic_vector(31 downto 0); +signal Head_Empty : std_logic; +signal Head_Header : std_logic_vector(31 DOWNTO 0); +signal Head_Valid : std_logic; +signal Head_Val : std_logic; + +--DMA +signal DMA_Read : std_logic; +signal DMA_ack : std_logic; +--signal AHB_Master_In : AHB_Mst_In_Type; +--signal AHB_Master_Out : AHB_Mst_Out_Type; + -- ADC --signal SmplClk : std_logic; @@ -351,74 +374,103 @@ led(1 downto 0) <= gpio(1 downto 0); -- end if; --end process; - TopACQ : lpp_top_acq - port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3); + ACQ0 : lpp_top_acq + port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,ACQ_WenF0,ACQ_DataF0,ACQ_WenF1,ACQ_DataF1,open,open,ACQ_WenF3,ACQ_DataF3); Bias_Fails <= '0'; ---- FIFO IN ------------------------------------------------------------- +--------- FIFO IN ------------------------------------------------------------- +---- +-- Memf0 : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF0,open,open,open,ACQ_DataF0,open,open,apbi,apbo(9)); +-- +-- Memf1 : APB_FIFO +-- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF1,open,open,open,ACQ_DataF1,open,open,apbi,apbo(8)); +-- +-- Memf3 : APB_FIFO +-- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),ACQ_WenF3,open,open,open,ACQ_DataF3,open,open,apbi,apbo(5)); --- MemOut : APB_FIFO --- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0) --- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9)); Memf0 : lppFIFOxN generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF0,DMUX_Read(4 downto 0),ACQ_DataF0,FifoF0_Data,open,FifoF0_Empty); Memf1 : lppFIFOxN generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF1,DMUX_Read(9 downto 5),ACQ_DataF1,FifoF1_Data,open,FifoF1_Empty); Memf3 : lppFIFOxN generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); - ---- DEMUX ------------------------------------------------------------- + port map(rstn,clkm,clkm,(others => '0'),ACQ_WenF3,DMUX_Read(14 downto 10),ACQ_DataF3,FifoF3_Data,open,FifoF3_Empty); +-- +----- DEMUX ------------------------------------------------------------- - DEMU0 : DEMUX + DMUX0 : DEMUX generic map(Data_sz => 16) - port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data); + port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DMUX_WorkFreq,DMUX_Read,DMUX_Empty,DMUX_Data); ---- FFT ------------------------------------------------------------- - +------- FFT ------------------------------------------------------------- + -- MemIn : APB_FIFO -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8)); +-- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),DMUX_Empty,open,DMUX_Data,(others => '0'),open,open,apbi,apbo(8)); FFT0 : FFT generic map(Data_sz => 16,NbData => 256) - port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); + port map(clkm,rstn,DMUX_Empty,DMUX_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data); ------ LINK MEMORY ------------------------------------------------------- +--------- LINK MEMORY ------------------------------------------------------- -- MemOut : APB_FIFO -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0) -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9)); MemInt : lppFIFOxN - generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1') + generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '1') port map(rstn,clkm,clkm,SM_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open); --- + -- MemIn : APB_FIFO -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1) --- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); +-- port map (clkm,rstn,clkm,clkm,(others => '0'),SM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8)); ----- MATRICE SPECTRALE ---------------------5 FIFO Input--------------- SM0 : MatriceSpectrale generic map(Input_SZ => 16,Result_SZ => 32) - port map(clkm,rstn,FifoINT_Full,FFT_ReUse,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); + port map(clkm,rstn,FifoINT_Full,FFT_ReUse,Head_Valid,FifoINT_Data,DMA_ack,SM_Wen,SM_FlagError,SM_Pong,SM_Param,SM_Write,SM_Read,SM_ReUse,SM_Data); + + +--DMA_ack <= '1'; +--Head_Valid <= '1'; -Dma_acq <= '1'; +-- MemOut : APB_FIFO +-- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); + + MemOut : lppFIFOxN + generic map(Data_sz => 32, Addr_sz => 8, FifoCnt => 2, Enable_ReUse => '0') + port map(rstn,clkm,clkm,(others => '0'),SM_Write,Head_Read,SM_Data,FifoOUT_Data,FifoOUT_Full,FifoOUT_Empty); - MemOut : APB_FIFO - generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9)); +----------- Header ------------------------------------------------------- + + Head0 : HeaderBuilder + generic map(Data_sz => 32) + port map(clkm,rstn,SM_Pong,SM_Param,DMUX_WorkFreq,SM_Wen,Head_Valid,FifoOUT_Data,FifoOUT_Empty,Head_Read,Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); + + +--- DMA ------------------------------------------------------- + + DMA0 : lpp_dma + generic map(hindex => 1,pindex => 9, paddr => 9,pirq => 14, pmask =>16#fff#,tech => CFG_FABTECH) + port map(clkm,rstn,apbi,apbo(9),ahbmi,ahbmo(1),Head_Data,Head_Empty,DMA_Read,Head_Header,Head_Val,DMA_ack); + ----- FIFO ------------------------------------------------------------- - Memtest : APB_FIFO - generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) - port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); +-- Memtest : APB_FIFO +-- generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) +-- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5)); --***************************************TEST DEMI-FIFO******************************************************************************** -- MemIn : APB_FIFO @@ -585,8 +637,8 @@ end process; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART - generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) - port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + generic map (hindex => 2, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(2)); dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; diff --git a/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd b/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_apbreg.vhd @@ -189,16 +189,16 @@ BEGIN -- beh END IF; END PROCESS lpp_dma_apbreg; - apbo.pirq <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR - ready_matrix_f0_1 OR + apbo.pirq(pirq) <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR ready_matrix_f1 OR ready_matrix_f2) ) OR (reg.config_active_interruption_onError AND (error_anticipating_empty_fifo OR - error_bad_component_error) - ); - + error_bad_component_error) + ); + @@ -208,4 +208,4 @@ BEGIN -- beh apbo.prdata <= prdata; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd.bak b/lib/lpp/lpp_matrix/ALU_Driver.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd.bak @@ -0,0 +1,216 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +use lpp.general_purpose.all; + +--! Driver de l'ALU + +entity ALU_Driver is + generic( + Input_SZ_1 : integer := 16; + Input_SZ_2 : integer := 16); + port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donnée d'entrée + IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donnée d'entrée + Take : in std_logic; --! Flag, opérande récupéré + Received : in std_logic; --! Flag, Résultat bien ressu + Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugué + Valid : out std_logic; --! Flag, Résultat disponible + Read : out std_logic; --! Flag, opérande disponible + CTRL : out std_logic_vector(2 downto 0); --! Permet de sélectionner la/les opération désirée + COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complémenter les opérandes + OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Opérande + OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Opérande +); +end ALU_Driver; + +--! @details Les opérandes sont issue des données d'entrées et associé aux bonnes valeurs sur CTRL, les différentes opérations sont effectuées + +architecture ar_ALU_Driver of ALU_Driver is + +signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0); +signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0); +signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0); +signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0); + +signal go_st : std_logic; +signal Take_reg : std_logic; +signal Received_reg : std_logic; + +type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW); +signal ect : etat; +signal st : etat; + +begin + process(clk,reset) + begin + + if(reset='0')then + ect <= eX; + st <= e0; + go_st <= '0'; + CTRL <= ctrl_CLRMAC; + COMP <= "00"; -- pas de complement + Read <= '0'; + Valid <= '0'; + Take_reg <= '0'; + Received_reg <= '0'; + + elsif(clk'event and clk='1')then + Take_reg <= Take; + Received_reg <= Received; + + case ect is + when eX => + go_st <= '0'; + Read <= '1'; + CTRL <= ctrl_CLRMAC; + ect <= e0; + + when e0 => + OP1re <= IN1; + if(Conjugate='1')then -- + OP2re <= IN1; -- + else -- + OP2re <= IN2; -- modif 23/06/11 + end if; -- + if(Take_reg='0' and Take='1')then + read <= '0'; + ect <= e1; + end if; + + when e1 => + OP1 <= OP1re; + OP2 <= OP2re; + CTRL <= ctrl_MAC; + Read <= '1'; + ect <= eY; + + when eY => + OP1im <= IN1; + if(Conjugate='1')then -- + OP2im <= IN1; -- + else -- + OP2im <= IN2; -- modif 23/06/11 + end if; -- + CTRL <= ctrl_IDLE; + if(Take_reg='1' and Take='0')then + Read <= '0'; + ect <= e2; + end if; + + when e2 => + OP1 <= OP1im; + OP2 <= OP2im; + CTRL <= ctrl_MAC; + ect <= eZ; + + when eZ => + CTRL <= ctrl_IDLE; + go_st <= '1'; + if(Received_reg='0' and Received='1')then + if(Conjugate='1')then + ect <= eX; + else + ect <= e3; + end if; + end if; + + when e3 => + CTRL <= ctrl_CLRMAC; + go_st <= '0'; + ect <= e4; + + when e4 => + OP1 <= OP1im; + OP2 <= OP2re; + CTRL <= ctrl_MAC; + ect <= e5; + + when e5 => + OP1 <= OP1re; + OP2 <= OP2im; + COMP <= "10"; + ect <= eW; + + when eW => + CTRL <= ctrl_IDLE; + COMP <= "00"; + go_st <= '1'; + if(Received_reg='1' and Received='0')then + ect <= eX; + end if; + end case; +--------------------------------------------------------------------------------- + case st is + when e0 => + if(go_st='1')then + st <= e1; + end if; + + when e1 => + Valid <= '1'; + st <= e2; + + when e2 => + if(Received_reg='0' and Received='1')then + Valid <= '0'; + if(Conjugate='1')then + st <= eY; + else + st <= eX; + end if; + end if; + + when eX => + st <= e3; + + when e3 => + if(go_st='1')then + st <= e4; + end if; + + when e4 => + Valid <= '1'; + st <= e5; + + when e5 => + if(Received_reg='1' and Received='0')then + Valid <= '0'; + st <= eY; + end if; + + when eY => + st <= e0; + + when others => + null; + end case; + + end if; + end process; + +end ar_ALU_Driver; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd.bak b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd.bak @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +--library lpp; +--use lpp.lpp_matrix.all; + +entity MatriceSpectrale is + generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); + port( + clkm : in std_logic; + rstn : in std_logic; + + FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); +-- FifoOUT_Full : in std_logic_vector(1 downto 0); + Valid : in std_logic; + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); + ACQ : in std_logic; + SM_Write : out std_logic; + FlagError : out std_logic; + Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); + Write : out std_logic_vector(1 downto 0); + Read : out std_logic_vector(4 downto 0); + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) + ); +end entity; + + +architecture ar_MatriceSpectrale of MatriceSpectrale is + +signal Matrix_Write : std_logic; +signal Matrix_Read : std_logic_vector(1 downto 0); +signal Matrix_Result : std_logic_vector(31 downto 0); + +signal TopSM_Start : std_logic; +signal TopSM_Statu : std_logic_vector(3 downto 0); +signal TopSM_Data1 : std_logic_vector(15 downto 0); +signal TopSM_Data2 : std_logic_vector(15 downto 0); + +begin + + CTRL0 : entity work.ReUse_CTRLR + port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); + + + TopSM : entity work.TopSpecMatrix + generic map (Input_SZ) + port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); + + SM : entity work.SpectralMatrix + generic map (Input_SZ,Result_SZ) + port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); + + DISP : entity work.Dispatch + generic map(Result_SZ) + port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); + +Statu <= TopSM_Statu; +SM_Write <= Matrix_Write; + +end architecture; + diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd.bak b/lib/lpp/lpp_matrix/SpectralMatrix.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd.bak @@ -0,0 +1,84 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +use lpp.lpp_matrix.all; + +entity SpectralMatrix is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + Start : in std_logic; + FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); + FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); + Statu : in std_logic_vector(3 downto 0); +-- FullFIFO : in std_logic; + ReadFIFO : out std_logic_vector(1 downto 0); + WriteFIFO : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end SpectralMatrix; + + +architecture ar_SpectralMatrix of SpectralMatrix is + +signal RaZ : std_logic; +signal Read_int : std_logic; +signal Take_int : std_logic; +signal Received_int : std_logic; +signal Valid_int : std_logic; +signal Conjugate_int : std_logic; + +signal Resultat : std_logic_vector(Result_SZ-1 downto 0); + + +begin + +RaZ <= reset and Start; + +IN1 : DriveInputs + port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO); + + +CALC0 : Matrix + generic map(Input_SZ) + port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); + + +RES0 : GetResult + generic map(Result_SZ) + port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO + + +With Statu select + Conjugate_int <= '1' when "0001", + '1' when "0011", + '1' when "0110", + '1' when "1010", + '1' when "1111", + '0' when others; + +end ar_SpectralMatrix; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/vhdlsyn.txt b/lib/lpp/lpp_matrix/vhdlsyn.txt --- a/lib/lpp/lpp_matrix/vhdlsyn.txt +++ b/lib/lpp/lpp_matrix/vhdlsyn.txt @@ -1,5 +1,6 @@ ALU_Driver.vhd APB_Matrix.vhd +ReUse_CTRLR.vhd Dispatch.vhd DriveInputs.vhd GetResult.vhd diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd.bak b/lib/lpp/lpp_memory/APB_FIFO.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/APB_FIFO.vhd.bak @@ -0,0 +1,264 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------ +-- APB_FIFO.vhd +library ieee; +use ieee.std_logic_1164.all; +use IEEE.numeric_std.all; +library techmap; +use techmap.gencomp.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.lpp_memory.all; + + +entity APB_FIFO is +generic ( + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + Mem_use : integer := use_RAM; + R : integer := 1; + W : integer := 1 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end entity; + +architecture ar_APB_FIFO of APB_FIFO is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type FIFO_ctrlr_Reg is record + FIFO_Ctrl : std_logic_vector(31 downto 0); + FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); + FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); +end record; + +type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; +type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); +type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); + +signal Rec : FIFO_ctrlr_Reg_Vec; +signal PRdata : std_logic_vector(31 downto 0); +signal FIFO_ID : std_logic_vector(31 downto 0); +signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); +signal sFull : std_logic_vector(FifoCnt-1 downto 0); +signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); +signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); +signal sWen : std_logic_vector(FifoCnt-1 downto 0); +signal sRen : std_logic_vector(FifoCnt-1 downto 0); +signal sRclk : std_logic; +signal sWclk : std_logic; +signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); +signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); +signal sRDATA : fifodatabus; +signal sWDATA : fifodatabus; +signal sWADDR : fifoaddressbus; +signal sRADDR : fifoaddressbus; +signal sReUse : std_logic_vector(FifoCnt-1 downto 0); +signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); + +signal regDataValid : std_logic_vector(FifoCnt-1 downto 0); +signal regData : fifodatabus; +signal regREN : std_logic_vector(FifoCnt-1 downto 0); + +type state_t is (idle,Read); +signal fiforeadfsmst : state_t; + +begin + +FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); +FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); +FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); + + +Writeint : if W /= 0 generate + FIFO_ID(4) <= '1'; + sWen <= sWen_APB; + sReUse <= sReUse_APB; + sWclk <= clk; + Wrapb: for i in 0 to FifoCnt-1 generate + sWDATA(i) <= Rec(i).FIFO_Wdata; + end generate; +end generate; + +Writeext : if W = 0 generate + FIFO_ID(4) <= '0'; + sWen <= WEN; + sReUse <= ReUse; + sWclk <= Wclk; + Wrext: for i in 0 to FifoCnt-1 generate + sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); + end generate; +end generate; + +Readint : if R /= 0 generate + FIFO_ID(5) <= '1'; + sRen <= sRen_APB; + srclk <= clk; + Rdapb: for i in 0 to FifoCnt-1 generate + Rec(i).FIFO_Rdata <= sRDATA(i); + end generate; +end generate; + +Readext : if R = 0 generate + FIFO_ID(5) <= '0'; + sRen <= REN; + srclk <= rclk; + Drext: for i in 0 to FifoCnt-1 generate + RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); + end generate; +end generate; + +ctrlregs: for i in 0 to FifoCnt-1 generate + RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); + WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); + Rec(i).FIFO_Ctrl(16) <= sFull(i); + sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); + Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; + Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; + Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); + Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); +end generate; + +Empty <= sEmpty; +Full <= sFull; + +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) + port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); +end generate; + + process(rst,clk) + begin + if(rst='0')then + rstloop1: for i in 0 to FifoCnt-1 loop + Rec(i).FIFO_Wdata <= (others => '0'); + Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse + sWen_APB(i) <= '1'; + end loop; + elsif(clk'event and clk='1')then + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + writelp: for i in 0 to FifoCnt-1 loop + if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then + Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1); + elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then + Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); + sWen_APB(i) <= '0'; + end if; + end loop; + else + sWen_APB <= (others =>'1'); + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + if(apbi.paddr(abits-1 downto 2)="000000") then + PRdata <= FIFO_ID; + else + readlp: for i in 0 to FifoCnt-1 loop + if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then + PRdata <= Rec(i).FIFO_Ctrl; + elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then + PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; + end if; + end loop; + end if; + end if; + end if; + + apbo.pconfig <= pconfig; + +end process; +apbo.prdata <= PRdata when apbi.penable = '1'; + +process(rst,clk) + begin + if(rst='0')then + fiforeadfsmst <= idle; + rstloop: for i in 0 to FifoCnt-1 loop + sRen_APB(i) <= '1'; + autoloaded(i) <= '1'; + Rec(i).FIFO_Ctrl(0) <= sEmpty(i); + end loop; + elsif clk'event and clk = '1' then + sEmpty_d <= sEmpty; + case fiforeadfsmst is + when idle => + idlelp: for i in 0 to FifoCnt-1 loop + if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then + if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then + autoloaded(i) <= '0'; + else + autoloaded(i) <= '1'; + end if; + sRen_APB(i) <= '0'; + fiforeadfsmst <= read; + Rec(i).FIFO_Ctrl(0) <= sEmpty(i); + else + sRen_APB(i) <= '1'; + end if; + end loop; + when read => + sRen_APB <= (others => '1'); + fiforeadfsmst <= idle; + when others => + fiforeadfsmst <= idle; + end case; + end if; +end process; + +end ar_APB_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd.bak b/lib/lpp/lpp_memory/lppFIFOxN.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd.bak @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; +library techmap; +use techmap.gencomp.all; + +entity lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rst : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end entity; + + +architecture ar_lppFIFOxN of lppFIFOxN is + +begin + +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) + port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); +end generate; + +end architecture; + diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd.bak b/lib/lpp/lpp_memory/lpp_memory.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_memory.vhd.bak @@ -0,0 +1,148 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_memory is + +component APB_FIFO is +generic ( + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + Mem_use : integer := use_RAM; + R : integer := 1; + W : integer := 1 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end component; + + +component lpp_fifo is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; --27/01/12 + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); +end component; + + +component lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rst : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end component; + +component ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); +end component; + +end; diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt --- a/lib/lpp/lpp_memory/vhdlsyn.txt +++ b/lib/lpp/lpp_memory/vhdlsyn.txt @@ -1,5 +1,6 @@ lpp_memory.vhd lpp_FIFO.vhd +FillFifo.vhd APB_FIFO.vhd Bridge.vhd SSRAM_plugin.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak @@ -0,0 +1,304 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_top_acq IS + GENERIC( + tech : INTEGER := 0, + Mem_use : integer := use_RAM + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) + ); +END lpp_top_acq; + +ARCHITECTURE tb OF lpp_top_acq IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + CONSTANT ncycle_cnv_high : INTEGER := 79; + CONSTANT ncycle_cnv : INTEGER := 500; + + ----------------------------------------------------------------------------- + SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; + SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sample_downsampling_out_val : STD_LOGIC; + SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + +BEGIN + + -- component instantiation + ----------------------------------------------------------------------------- + DIGITAL_acquisition : AD7688_drvr + GENERIC MAP ( + ChanelCount => ChanelCount, + ncycle_cnv_high => ncycle_cnv_high, + ncycle_cnv => ncycle_cnv) + PORT MAP ( + cnv_clk => cnv_clk, -- + cnv_rstn => cnv_rstn, -- + cnv_run => cnv_run, -- + cnv => cnv, -- + clk => clk, -- + rstn => rstn, -- + sck => sck, -- + sdo => sdo(ChanelCount-1 DOWNTO 0), -- + sample => sample, + sample_val => sample_val); + + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, -- TODO + Coef_sel_SZ => 5, -- TODO + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_filter_v2_out_r_val <= '0'; + rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP + rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP + sample_filter_v2_out_r(I, J) <= '0'; + END LOOP rst_all_bits; + END LOOP rst_all_chanel; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_filter_v2_out_r_val <= sample_filter_v2_out_val; + IF sample_filter_v2_out_val = '1' THEN + sample_filter_v2_out_r <= sample_filter_v2_out; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val , + sample_in => sample_filter_v2_out, + sample_out_val => sample_f0_val, + sample_out => sample_f0); + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata(I) <= sample_f0(0, I); + sample_f0_wdata(16*1+I) <= sample_f0(1, I); + sample_f0_wdata(16*2+I) <= sample_f0(2, I); + sample_f0_wdata(16*3+I) <= sample_f0(6, I); + sample_f0_wdata(16*4+I) <= sample_f0(7, I); + END GENERATE all_bit_sample_f0; + + sample_f0_wen <= NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val) & + NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f1_val, + sample_out => sample_f1); + + sample_f1_wen <= NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val) & + NOT(sample_f1_val); + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata(I) <= sample_f1(0, I); + sample_f1_wdata(16*1+I) <= sample_f1(1, I); + sample_f1_wdata(16*2+I) <= sample_f1(2, I); + sample_f1_wdata(16*3+I) <= sample_f1(6, I); + sample_f1_wdata(16*4+I) <= sample_f1(7, I); + END GENERATE all_bit_sample_f1; + + ----------------------------------------------------------------------------- + -- F2 -- @16 Hz + ----------------------------------------------------------------------------- + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val , + sample_in => sample_f1, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + sample_f2_wen <= NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val) & + NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata(I) <= sample_f2(0, I); + sample_f2_wdata(16*1+I) <= sample_f2(1, I); + sample_f2_wdata(16*2+I) <= sample_f2(2, I); + sample_f2_wdata(16*3+I) <= sample_f2(6, I); + sample_f2_wdata(16*4+I) <= sample_f2(7, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @256 Hz + ----------------------------------------------------------------------------- + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => ChanelCount, + SampleSize => 18, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val , + sample_in => sample_f0, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + sample_f3_wen <= (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val) & + (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata(I) <= sample_f3(0, I); + sample_f3_wdata(16*1+I) <= sample_f3(1, I); + sample_f3_wdata(16*2+I) <= sample_f3(2, I); + sample_f3_wdata(16*3+I) <= sample_f3(6, I); + sample_f3_wdata(16*4+I) <= sample_f3(7, I); + END GENERATE all_bit_sample_f3; + + + +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak @@ -0,0 +1,81 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_top_lfr_pkg IS + + COMPONENT lpp_top_acq + GENERIC( + tech : INTEGER := 0, + Mem_use : integer := use_RAM + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpp_top_apbreg + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + +END lpp_top_lfr_pkg; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -1,5 +1,6 @@ lpp_top_lfr_pkg.vhd lpp_top_apbreg.vhd +lpp_top_acq.vhd lpp_top_lfr_wf_picker.vhd lpp_top_lfr_wf_picker_ip.vhd lpp_top_lfr_wf_picker_ip_whitout_filter.vhd